aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorThomas Gleixner <tglx@linutronix.de>2014-06-19 17:34:40 -0400
committerJason Cooper <jason@lakedaemon.net>2014-06-24 08:37:42 -0400
commit03319a1a2966ec39be79182d6d529221c38fde72 (patch)
treef83eb0faf71112039968cd76366cbe8024a8878d
parentc5d1d857482b080875640bb68bc9d8b65ad29b6f (diff)
irqchip: spear_shirq: Reorder the spear320 ras blocks
Order the ras blocks in the order of interrupts not alphabetically. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20140619212713.310591579@linutronix.de Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r--drivers/irqchip/spear-shirq.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c
index f7c25a77845a..7ebb1a2fbfc7 100644
--- a/drivers/irqchip/spear-shirq.c
+++ b/drivers/irqchip/spear-shirq.c
@@ -138,20 +138,22 @@ static struct spear_shirq *spear310_shirq_blocks[] = {
138#define SPEAR320_INT_CLR_MASK_REG 0x04 138#define SPEAR320_INT_CLR_MASK_REG 0x04
139#define SPEAR320_INT_ENB_MASK_REG 0x08 139#define SPEAR320_INT_ENB_MASK_REG 0x08
140 140
141static struct spear_shirq spear320_shirq_ras1 = { 141static struct spear_shirq spear320_shirq_ras3 = {
142 .offset = 7, 142 .offset = 0,
143 .nr_irqs = 3, 143 .nr_irqs = 7,
144 .disabled = 1,
144 .regs = { 145 .regs = {
145 .enb_reg = -1, 146 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
147 .reset_to_enb = 1,
146 .status_reg = SPEAR320_INT_STS_MASK_REG, 148 .status_reg = SPEAR320_INT_STS_MASK_REG,
147 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 149 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
148 .reset_to_clear = 1, 150 .reset_to_clear = 1,
149 }, 151 },
150}; 152};
151 153
152static struct spear_shirq spear320_shirq_ras2 = { 154static struct spear_shirq spear320_shirq_ras1 = {
153 .offset = 10, 155 .offset = 7,
154 .nr_irqs = 1, 156 .nr_irqs = 3,
155 .regs = { 157 .regs = {
156 .enb_reg = -1, 158 .enb_reg = -1,
157 .status_reg = SPEAR320_INT_STS_MASK_REG, 159 .status_reg = SPEAR320_INT_STS_MASK_REG,
@@ -160,13 +162,11 @@ static struct spear_shirq spear320_shirq_ras2 = {
160 }, 162 },
161}; 163};
162 164
163static struct spear_shirq spear320_shirq_ras3 = { 165static struct spear_shirq spear320_shirq_ras2 = {
164 .offset = 0, 166 .offset = 10,
165 .nr_irqs = 7, 167 .nr_irqs = 1,
166 .disabled = 1,
167 .regs = { 168 .regs = {
168 .enb_reg = SPEAR320_INT_ENB_MASK_REG, 169 .enb_reg = -1,
169 .reset_to_enb = 1,
170 .status_reg = SPEAR320_INT_STS_MASK_REG, 170 .status_reg = SPEAR320_INT_STS_MASK_REG,
171 .clear_reg = SPEAR320_INT_CLR_MASK_REG, 171 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
172 .reset_to_clear = 1, 172 .reset_to_clear = 1,