diff options
author | Roger Quadros <rogerq@ti.com> | 2014-05-05 05:54:43 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-05-14 17:39:34 -0400 |
commit | 032d774575dfed145e4477b47579fd51d9c102b3 (patch) | |
tree | 09cf7b8a4a762d950b3c3e2c4025c999238d8818 | |
parent | c65d0ad51022b2fa250a3561cc370fcbfe23beda (diff) |
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
This clock gate description is missing in the older Reference manuals.
It is present on the SoC to provide 960MHz reference clock to the
internal USB PHYs.
Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL
Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
usb_otg_ss2_refclk960m.
CC: BenoƮt Cousson <bcousson@baylibre.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfb8fc753f50..c7676871d9c0 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi | |||
@@ -1386,6 +1386,14 @@ | |||
1386 | ti,dividers = <1>, <8>; | 1386 | ti,dividers = <1>, <8>; |
1387 | }; | 1387 | }; |
1388 | 1388 | ||
1389 | l3init_960m_gfclk: l3init_960m_gfclk { | ||
1390 | #clock-cells = <0>; | ||
1391 | compatible = "ti,gate-clock"; | ||
1392 | clocks = <&dpll_usb_clkdcoldo>; | ||
1393 | ti,bit-shift = <8>; | ||
1394 | reg = <0x06c0>; | ||
1395 | }; | ||
1396 | |||
1389 | dss_32khz_clk: dss_32khz_clk { | 1397 | dss_32khz_clk: dss_32khz_clk { |
1390 | #clock-cells = <0>; | 1398 | #clock-cells = <0>; |
1391 | compatible = "ti,gate-clock"; | 1399 | compatible = "ti,gate-clock"; |
@@ -1533,7 +1541,7 @@ | |||
1533 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { | 1541 | usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { |
1534 | #clock-cells = <0>; | 1542 | #clock-cells = <0>; |
1535 | compatible = "ti,gate-clock"; | 1543 | compatible = "ti,gate-clock"; |
1536 | clocks = <&dpll_usb_clkdcoldo>; | 1544 | clocks = <&l3init_960m_gfclk>; |
1537 | ti,bit-shift = <8>; | 1545 | ti,bit-shift = <8>; |
1538 | reg = <0x13f0>; | 1546 | reg = <0x13f0>; |
1539 | }; | 1547 | }; |
@@ -1541,7 +1549,7 @@ | |||
1541 | usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { | 1549 | usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { |
1542 | #clock-cells = <0>; | 1550 | #clock-cells = <0>; |
1543 | compatible = "ti,gate-clock"; | 1551 | compatible = "ti,gate-clock"; |
1544 | clocks = <&dpll_usb_clkdcoldo>; | 1552 | clocks = <&l3init_960m_gfclk>; |
1545 | ti,bit-shift = <8>; | 1553 | ti,bit-shift = <8>; |
1546 | reg = <0x1340>; | 1554 | reg = <0x1340>; |
1547 | }; | 1555 | }; |