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authorChon Ming Lee <chon.ming.lee@intel.com>2013-10-03 11:16:17 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-04 04:26:11 -0400
commit02f4c9e02a021c5608dde7ae0607946ab16ae00c (patch)
tree7d87faeccc015b2929a12af760b2962a18c9fe9d
parent40e9cf649a88abea96d5756aa6f86e89cfabde6e (diff)
drm/i915/vlv: Turn off power gate for BIOS-less system.
During system boot up, by default, the power gate for render, media and display well still power gated. Normally, BIOS will turn off the power gate. In the BIOS-less system, the driver need to turn off the power gate very early during driver load. v2: Move this to intel_uncore_sanitize to allow it to get call during resume path. (Daniel) v3: Remove redundant write 0 to DPIO_CTL, and use DPIO_RESET instead of just 0x1 (Ville) Add turn of power gate for display 2d/render well/media well. v4: Remove toggle cmnreset in intel_uncore_sanitize. Cmnreset should toggle after CRI clock source has been selected. Jesse DPIO reset patch which toggle the cmnreset in intel_modeset_init_hw() should handle it. (Ville) Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h9
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c16
2 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1017431fa5b..95385023e0ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -361,6 +361,15 @@
361#define PUNIT_OPCODE_REG_READ 6 361#define PUNIT_OPCODE_REG_READ 6
362#define PUNIT_OPCODE_REG_WRITE 7 362#define PUNIT_OPCODE_REG_WRITE 7
363 363
364#define PUNIT_REG_PWRGT_CTRL 0x60
365#define PUNIT_REG_PWRGT_STATUS 0x61
366#define PUNIT_CLK_GATE 1
367#define PUNIT_PWR_RESET 2
368#define PUNIT_PWR_GATE 3
369#define RENDER_PWRGT (PUNIT_PWR_GATE << 0)
370#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2)
371#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6)
372
364#define PUNIT_REG_GPU_LFM 0xd3 373#define PUNIT_REG_GPU_LFM 0xd3
365#define PUNIT_REG_GPU_FREQ_REQ 0xd4 374#define PUNIT_REG_GPU_FREQ_REQ 0xd4
366#define PUNIT_REG_GPU_FREQ_STS 0xd8 375#define PUNIT_REG_GPU_FREQ_STS 0xd8
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f2753d9fb098..288a3a654f06 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -301,10 +301,26 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev)
301 301
302void intel_uncore_sanitize(struct drm_device *dev) 302void intel_uncore_sanitize(struct drm_device *dev)
303{ 303{
304 struct drm_i915_private *dev_priv = dev->dev_private;
305 u32 reg_val;
306
304 intel_uncore_forcewake_reset(dev); 307 intel_uncore_forcewake_reset(dev);
305 308
306 /* BIOS often leaves RC6 enabled, but disable it for hw init */ 309 /* BIOS often leaves RC6 enabled, but disable it for hw init */
307 intel_disable_gt_powersave(dev); 310 intel_disable_gt_powersave(dev);
311
312 /* Turn off power gate, require especially for the BIOS less system */
313 if (IS_VALLEYVIEW(dev)) {
314
315 mutex_lock(&dev_priv->rps.hw_lock);
316 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
317
318 if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
319 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
320
321 mutex_unlock(&dev_priv->rps.hw_lock);
322
323 }
308} 324}
309 325
310/* 326/*