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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2015-01-02 09:17:24 -0500
committerVinod Koul <vinod.koul@intel.com>2015-01-13 13:16:00 -0500
commit029a40e97d0db269f4a7fc02b0f29f627f628309 (patch)
tree22a18f600ac6698c785e9d800b9ce655d27d6e82
parent3c20ba5fb5b9e3d5e266bfab316ee10b77da88e0 (diff)
dmaengine: dw: provide DMA capabilities
The new DMAEngine requirement is to provide what the DMA controller can do, such as directions, bus widths, and residue granularity. The patch sets those properties for the DesignWare DMA controller driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/dw/core.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 4bc307745ef1..fcb9a916e6f6 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -61,6 +61,13 @@
61 */ 61 */
62#define NR_DESCS_PER_CHANNEL 64 62#define NR_DESCS_PER_CHANNEL 64
63 63
64/* The set of bus widths supported by the DMA controller */
65#define DW_DMA_BUSWIDTHS \
66 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
67 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
68 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
69 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
70
64/*----------------------------------------------------------------------*/ 71/*----------------------------------------------------------------------*/
65 72
66static struct device *chan2dev(struct dma_chan *chan) 73static struct device *chan2dev(struct dma_chan *chan)
@@ -1660,8 +1667,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1660 dw->dma.device_free_chan_resources = dwc_free_chan_resources; 1667 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1661 1668
1662 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; 1669 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1663
1664 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; 1670 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1671
1665 dw->dma.device_config = dwc_config; 1672 dw->dma.device_config = dwc_config;
1666 dw->dma.device_pause = dwc_pause; 1673 dw->dma.device_pause = dwc_pause;
1667 dw->dma.device_resume = dwc_resume; 1674 dw->dma.device_resume = dwc_resume;
@@ -1670,6 +1677,13 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1670 dw->dma.device_tx_status = dwc_tx_status; 1677 dw->dma.device_tx_status = dwc_tx_status;
1671 dw->dma.device_issue_pending = dwc_issue_pending; 1678 dw->dma.device_issue_pending = dwc_issue_pending;
1672 1679
1680 /* DMA capabilities */
1681 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1682 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1683 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1684 BIT(DMA_MEM_TO_MEM);
1685 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1686
1673 err = dma_async_device_register(&dw->dma); 1687 err = dma_async_device_register(&dw->dma);
1674 if (err) 1688 if (err)
1675 goto err_dma_register; 1689 goto err_dma_register;