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authorArnd Bergmann <arnd@arndb.de>2014-03-11 12:41:33 -0400
committerArnd Bergmann <arnd@arndb.de>2014-03-26 21:49:24 -0400
commit027f3f96962df3a222c11dace0d1ff266d836371 (patch)
tree07d6cde248de0ed50b468fc637b58c13079278e8
parenta1b6b737def9d8bc1baec6d7046d90c7c136262a (diff)
ARM: cache-tauros2: remove ARMv6 code
When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode. Removing the ARMv6 code path reduces the code size and avoids the linker error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
-rw-r--r--arch/arm/mm/cache-tauros2.c29
1 files changed, 1 insertions, 28 deletions
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 1be0f4e5e6eb..b273739e6359 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -33,7 +33,7 @@
33 * outer cache operations into the kernel image if the kernel has been 33 * outer cache operations into the kernel image if the kernel has been
34 * configured to support a pre-v7 CPU. 34 * configured to support a pre-v7 CPU.
35 */ 35 */
36#if __LINUX_ARM_ARCH__ < 7 36#ifdef CONFIG_CPU_32v5
37/* 37/*
38 * Low-level cache maintenance operations. 38 * Low-level cache maintenance operations.
39 */ 39 */
@@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features)
229 } 229 }
230#endif 230#endif
231 231
232#ifdef CONFIG_CPU_32v6
233 /*
234 * Check whether this CPU lacks support for the v7 hierarchical
235 * cache ops. (PJ4 is in its v6 personality mode if the MMFR3
236 * register indicates no support for the v7 hierarchical cache
237 * ops.)
238 */
239 if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
240 /*
241 * When Tauros2 is used in an ARMv6 system, the L2
242 * enable bit is in the ARMv6 ARM-mandated position
243 * (bit [26] of the System Control Register).
244 */
245 if (!(get_cr() & 0x04000000)) {
246 printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
247 adjust_cr(0x04000000, 0x04000000);
248 }
249
250 mode = "ARMv6";
251 outer_cache.inv_range = tauros2_inv_range;
252 outer_cache.clean_range = tauros2_clean_range;
253 outer_cache.flush_range = tauros2_flush_range;
254 outer_cache.disable = tauros2_disable;
255 outer_cache.resume = tauros2_resume;
256 }
257#endif
258
259#ifdef CONFIG_CPU_32v7 232#ifdef CONFIG_CPU_32v7
260 /* 233 /*
261 * Check whether this CPU has support for the v7 hierarchical 234 * Check whether this CPU has support for the v7 hierarchical