Merge branch 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Just some minor fixes for VM reg check and a regression fix for dce3 plls

* 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/si: add some missing regs to the VM reg checker
  drm/radeon/cayman: add some missing regs to the VM reg checker
  drm/radeon/dce3: switch back to old pll allocation order for discrete

5 files changed, 40 insertions, 23 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 2e566e123e9e..3bce0299f64a 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1696,35 +1696,43 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
                         return ATOM_PPLL2;
                 DRM_ERROR("unable to allocate a PPLL\n");
                 return ATOM_PPLL_INVALID;
-        } else {
-                if (ASIC_IS_AVIVO(rdev)) {
-                        /* in DP mode, the DP ref clock can come from either PPLL
-                         * depending on the asic:
-                         * DCE3: PPLL1 or PPLL2
-                         */
-                        if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
-                                /* use the same PPLL for all DP monitors */
-                                pll = radeon_get_shared_dp_ppll(crtc);
-                                if (pll != ATOM_PPLL_INVALID)
-                                        return pll;
-                        } else {
-                                /* use the same PPLL for all monitors with the same clock */
-                                pll = radeon_get_shared_nondp_ppll(crtc);
-                                if (pll != ATOM_PPLL_INVALID)
-                                        return pll;
-                        }
-                        /* all other cases */
-                        pll_in_use = radeon_get_pll_use_mask(crtc);
+        } else if (ASIC_IS_AVIVO(rdev)) {
+                /* in DP mode, the DP ref clock can come from either PPLL
+                 * depending on the asic:
+                 * DCE3: PPLL1 or PPLL2
+                 */
+                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
+                        /* use the same PPLL for all DP monitors */
+                        pll = radeon_get_shared_dp_ppll(crtc);
+                        if (pll != ATOM_PPLL_INVALID)
+                                return pll;
+                } else {
+                        /* use the same PPLL for all monitors with the same clock */
+                        pll = radeon_get_shared_nondp_ppll(crtc);
+                        if (pll != ATOM_PPLL_INVALID)
+                                return pll;
+                }
+                /* all other cases */
+                pll_in_use = radeon_get_pll_use_mask(crtc);
+                /* the order shouldn't matter here, but we probably
+                 * need this until we have atomic modeset
+                 */
+                if (rdev->flags & RADEON_IS_IGP) {
                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
                                 return ATOM_PPLL1;
                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
                                 return ATOM_PPLL2;
-                        DRM_ERROR("unable to allocate a PPLL\n");
-                        return ATOM_PPLL_INVALID;
                 } else {
-                        /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
-                        return radeon_crtc->crtc_id;
+                        if (!(pll_in_use & (1 << ATOM_PPLL2)))
+                                return ATOM_PPLL2;
+                        if (!(pll_in_use & (1 << ATOM_PPLL1)))
+                                return ATOM_PPLL1;
                 }
+                DRM_ERROR("unable to allocate a PPLL\n");
+                return ATOM_PPLL_INVALID;
+        } else {
+                /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
+                return radeon_crtc->crtc_id;
         }
 }
 
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 95e6318b6268..c042e497e450 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -2725,6 +2725,9 @@ static bool evergreen_vm_reg_valid(u32 reg)
         /* check config regs */
         switch (reg) {
         case GRBM_GFX_INDEX:
+        case CP_STRMOUT_CNTL:
+        case CP_COHER_CNTL:
+        case CP_COHER_SIZE:
         case VGT_VTX_VECT_EJECT_REG:
         case VGT_CACHE_INVALIDATION:
         case VGT_GS_VERTEX_REUSE:
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index df542f1a5dfb..2bc0f6a1b428 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -91,6 +91,10 @@
 #define         FB_READ_EN                                      (1 << 0)
 #define         FB_WRITE_EN                                     (1 << 1)
 
+#define CP_STRMOUT_CNTL                                 0x84FC
+
+#define CP_COHER_CNTL                                   0x85F0
+#define CP_COHER_SIZE                                   0x85F4
 #define CP_COHER_BASE                                   0x85F8
 #define CP_STALLED_STAT1                        0x8674
 #define CP_STALLED_STAT2                        0x8678
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index b0db712060fb..4422d630b33b 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2474,6 +2474,7 @@ static bool si_vm_reg_valid(u32 reg)
         /* check config regs */
         switch (reg) {
         case GRBM_GFX_INDEX:
+        case CP_STRMOUT_CNTL:
         case VGT_VTX_VECT_EJECT_REG:
         case VGT_CACHE_INVALIDATION:
         case VGT_ESGS_RING_SIZE:
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 7d2a20e56577..a8871afc5b4e 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -424,6 +424,7 @@
 #       define RDERR_INT_ENABLE                         (1 << 0)
 #       define GUI_IDLE_INT_ENABLE                      (1 << 19)
 
+#define CP_STRMOUT_CNTL                                 0x84FC
 #define SCRATCH_REG0                                    0x8500
 #define SCRATCH_REG1                                    0x8504
 #define SCRATCH_REG2                                    0x8508