aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlex Deucher <alexander.deucher@amd.com>2013-08-13 15:57:32 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-14 18:03:40 -0400
commit022374c02e357ac82e98dd2689fb2efe05723d69 (patch)
tree166c8f88b03be842176bcc3c4983362470d053c1
parent112a6d0c071808f6d48354fc8834a574e5dcefc0 (diff)
drm/radeon/r7xx: fix copy paste typo in golden register setup
Uses the wrong array size for some asics which can lead to garbage getting written to registers. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=60674 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-rw-r--r--drivers/gpu/drm/radeon/rv770.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index bcc68ec204ad..f5e92cfcc140 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -744,10 +744,10 @@ static void rv770_init_golden_registers(struct radeon_device *rdev)
744 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 744 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
745 radeon_program_register_sequence(rdev, 745 radeon_program_register_sequence(rdev,
746 rv730_golden_registers, 746 rv730_golden_registers,
747 (const u32)ARRAY_SIZE(rv770_golden_registers)); 747 (const u32)ARRAY_SIZE(rv730_golden_registers));
748 radeon_program_register_sequence(rdev, 748 radeon_program_register_sequence(rdev,
749 rv730_mgcg_init, 749 rv730_mgcg_init,
750 (const u32)ARRAY_SIZE(rv770_mgcg_init)); 750 (const u32)ARRAY_SIZE(rv730_mgcg_init));
751 break; 751 break;
752 case CHIP_RV710: 752 case CHIP_RV710:
753 radeon_program_register_sequence(rdev, 753 radeon_program_register_sequence(rdev,
@@ -758,18 +758,18 @@ static void rv770_init_golden_registers(struct radeon_device *rdev)
758 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); 758 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
759 radeon_program_register_sequence(rdev, 759 radeon_program_register_sequence(rdev,
760 rv710_golden_registers, 760 rv710_golden_registers,
761 (const u32)ARRAY_SIZE(rv770_golden_registers)); 761 (const u32)ARRAY_SIZE(rv710_golden_registers));
762 radeon_program_register_sequence(rdev, 762 radeon_program_register_sequence(rdev,
763 rv710_mgcg_init, 763 rv710_mgcg_init,
764 (const u32)ARRAY_SIZE(rv770_mgcg_init)); 764 (const u32)ARRAY_SIZE(rv710_mgcg_init));
765 break; 765 break;
766 case CHIP_RV740: 766 case CHIP_RV740:
767 radeon_program_register_sequence(rdev, 767 radeon_program_register_sequence(rdev,
768 rv740_golden_registers, 768 rv740_golden_registers,
769 (const u32)ARRAY_SIZE(rv770_golden_registers)); 769 (const u32)ARRAY_SIZE(rv740_golden_registers));
770 radeon_program_register_sequence(rdev, 770 radeon_program_register_sequence(rdev,
771 rv740_mgcg_init, 771 rv740_mgcg_init,
772 (const u32)ARRAY_SIZE(rv770_mgcg_init)); 772 (const u32)ARRAY_SIZE(rv740_mgcg_init));
773 break; 773 break;
774 default: 774 default:
775 break; 775 break;