diff options
author | Rhyland Klein <rklein@nvidia.com> | 2015-02-11 12:55:51 -0500 |
---|---|---|
committer | Ulf Hansson <ulf.hansson@linaro.org> | 2015-03-23 09:13:44 -0400 |
commit | 01df7ecd90e94186f9a736a1c58b56e23830f061 (patch) | |
tree | 8df729a8df7b92b47aa17fa716879bfbac0314a5 | |
parent | dbb42d962c4149fe2e97f74bf1343b5229eefe5e (diff) |
mmc: tegra: Optimize write_w path for tegra114 and later
Setup a different set of sdhci_ops for tegra114 and later so that
the write_w callback is only used on tegra114. This allows us to
remove the NVQUIRK_SHADOW_XFER_MODE_REG and simply the logic
in tegra_sdhci_writew.
Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 47 |
1 files changed, 26 insertions, 21 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2489bb753708..93834ab6c3a3 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c | |||
@@ -41,7 +41,6 @@ | |||
41 | #define NVQUIRK_DISABLE_SDR50 BIT(3) | 41 | #define NVQUIRK_DISABLE_SDR50 BIT(3) |
42 | #define NVQUIRK_DISABLE_SDR104 BIT(4) | 42 | #define NVQUIRK_DISABLE_SDR104 BIT(4) |
43 | #define NVQUIRK_DISABLE_DDR50 BIT(5) | 43 | #define NVQUIRK_DISABLE_DDR50 BIT(5) |
44 | #define NVQUIRK_SHADOW_XFER_MODE_REG BIT(6) | ||
45 | 44 | ||
46 | struct sdhci_tegra_soc_data { | 45 | struct sdhci_tegra_soc_data { |
47 | const struct sdhci_pltfm_data *pdata; | 46 | const struct sdhci_pltfm_data *pdata; |
@@ -71,23 +70,19 @@ static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) | |||
71 | static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) | 70 | static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
72 | { | 71 | { |
73 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | 72 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
74 | struct sdhci_tegra *tegra_host = pltfm_host->priv; | ||
75 | const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; | ||
76 | 73 | ||
77 | if (soc_data->nvquirks & NVQUIRK_SHADOW_XFER_MODE_REG) { | 74 | switch (reg) { |
78 | switch (reg) { | 75 | case SDHCI_TRANSFER_MODE: |
79 | case SDHCI_TRANSFER_MODE: | 76 | /* |
80 | /* | 77 | * Postpone this write, we must do it together with a |
81 | * Postpone this write, we must do it together with a | 78 | * command write that is down below. |
82 | * command write that is down below. | 79 | */ |
83 | */ | 80 | pltfm_host->xfer_mode_shadow = val; |
84 | pltfm_host->xfer_mode_shadow = val; | 81 | return; |
85 | return; | 82 | case SDHCI_COMMAND: |
86 | case SDHCI_COMMAND: | 83 | writel((val << 16) | pltfm_host->xfer_mode_shadow, |
87 | writel((val << 16) | pltfm_host->xfer_mode_shadow, | 84 | host->ioaddr + SDHCI_TRANSFER_MODE); |
88 | host->ioaddr + SDHCI_TRANSFER_MODE); | 85 | return; |
89 | return; | ||
90 | } | ||
91 | } | 86 | } |
92 | 87 | ||
93 | writew(val, host->ioaddr + reg); | 88 | writew(val, host->ioaddr + reg); |
@@ -173,7 +168,6 @@ static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) | |||
173 | static const struct sdhci_ops tegra_sdhci_ops = { | 168 | static const struct sdhci_ops tegra_sdhci_ops = { |
174 | .get_ro = tegra_sdhci_get_ro, | 169 | .get_ro = tegra_sdhci_get_ro, |
175 | .read_w = tegra_sdhci_readw, | 170 | .read_w = tegra_sdhci_readw, |
176 | .write_w = tegra_sdhci_writew, | ||
177 | .write_l = tegra_sdhci_writel, | 171 | .write_l = tegra_sdhci_writel, |
178 | .set_clock = sdhci_set_clock, | 172 | .set_clock = sdhci_set_clock, |
179 | .set_bus_width = tegra_sdhci_set_bus_width, | 173 | .set_bus_width = tegra_sdhci_set_bus_width, |
@@ -214,6 +208,18 @@ static struct sdhci_tegra_soc_data soc_data_tegra30 = { | |||
214 | NVQUIRK_DISABLE_SDR104, | 208 | NVQUIRK_DISABLE_SDR104, |
215 | }; | 209 | }; |
216 | 210 | ||
211 | static const struct sdhci_ops tegra114_sdhci_ops = { | ||
212 | .get_ro = tegra_sdhci_get_ro, | ||
213 | .read_w = tegra_sdhci_readw, | ||
214 | .write_w = tegra_sdhci_writew, | ||
215 | .write_l = tegra_sdhci_writel, | ||
216 | .set_clock = sdhci_set_clock, | ||
217 | .set_bus_width = tegra_sdhci_set_bus_width, | ||
218 | .reset = tegra_sdhci_reset, | ||
219 | .set_uhs_signaling = sdhci_set_uhs_signaling, | ||
220 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, | ||
221 | }; | ||
222 | |||
217 | static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { | 223 | static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { |
218 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | | 224 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
219 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | | 225 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | |
@@ -221,15 +227,14 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { | |||
221 | SDHCI_QUIRK_NO_HISPD_BIT | | 227 | SDHCI_QUIRK_NO_HISPD_BIT | |
222 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | | 228 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
223 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | 229 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
224 | .ops = &tegra_sdhci_ops, | 230 | .ops = &tegra114_sdhci_ops, |
225 | }; | 231 | }; |
226 | 232 | ||
227 | static struct sdhci_tegra_soc_data soc_data_tegra114 = { | 233 | static struct sdhci_tegra_soc_data soc_data_tegra114 = { |
228 | .pdata = &sdhci_tegra114_pdata, | 234 | .pdata = &sdhci_tegra114_pdata, |
229 | .nvquirks = NVQUIRK_DISABLE_SDR50 | | 235 | .nvquirks = NVQUIRK_DISABLE_SDR50 | |
230 | NVQUIRK_DISABLE_DDR50 | | 236 | NVQUIRK_DISABLE_DDR50 | |
231 | NVQUIRK_DISABLE_SDR104 | | 237 | NVQUIRK_DISABLE_SDR104, |
232 | NVQUIRK_SHADOW_XFER_MODE_REG, | ||
233 | }; | 238 | }; |
234 | 239 | ||
235 | static const struct of_device_id sdhci_tegra_dt_match[] = { | 240 | static const struct of_device_id sdhci_tegra_dt_match[] = { |