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authorDave Airlie <airlied@redhat.com>2014-05-01 21:17:41 -0400
committerDave Airlie <airlied@redhat.com>2014-07-21 02:34:13 -0400
commit01b887c36e12845bb9162e65504de623f1a17f10 (patch)
treeed0527f5ed7e9ed79fff9890d70d5409446757d9
parente7c36347130fc3b9eec3572d00c53533f07a7347 (diff)
drm/i915: add some registers need for displayport MST support.
These are just from the Haswell spec. Reviewed-by: Todd Previte <tprevite@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d2c4deb3e87..b0036cd3fe19 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5815,6 +5815,7 @@ enum punit_power_well {
5815#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 5815#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5816#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 5816#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5817#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 5817#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
5818#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
5818#define TRANS_DDI_BFI_ENABLE (1<<4) 5819#define TRANS_DDI_BFI_ENABLE (1<<4)
5819 5820
5820/* DisplayPort Transport Control */ 5821/* DisplayPort Transport Control */
@@ -5824,6 +5825,7 @@ enum punit_power_well {
5824#define DP_TP_CTL_ENABLE (1<<31) 5825#define DP_TP_CTL_ENABLE (1<<31)
5825#define DP_TP_CTL_MODE_SST (0<<27) 5826#define DP_TP_CTL_MODE_SST (0<<27)
5826#define DP_TP_CTL_MODE_MST (1<<27) 5827#define DP_TP_CTL_MODE_MST (1<<27)
5828#define DP_TP_CTL_FORCE_ACT (1<<25)
5827#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 5829#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
5828#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 5830#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
5829#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 5831#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
@@ -5838,8 +5840,13 @@ enum punit_power_well {
5838#define DP_TP_STATUS_A 0x64044 5840#define DP_TP_STATUS_A 0x64044
5839#define DP_TP_STATUS_B 0x64144 5841#define DP_TP_STATUS_B 0x64144
5840#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) 5842#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
5841#define DP_TP_STATUS_IDLE_DONE (1<<25) 5843#define DP_TP_STATUS_IDLE_DONE (1<<25)
5842#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 5844#define DP_TP_STATUS_ACT_SENT (1<<24)
5845#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
5846#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5847#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
5848#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
5849#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
5843 5850
5844/* DDI Buffer Control */ 5851/* DDI Buffer Control */
5845#define DDI_BUF_CTL_A 0x64000 5852#define DDI_BUF_CTL_A 0x64000