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authorValentine Barshak <valentine.barshak@cogentembedded.com>2014-01-24 17:28:48 -0500
committerSimon Horman <horms+renesas@verge.net.au>2014-02-03 20:25:03 -0500
commit012a7069b5a10a0851584d71a1facdc40a972319 (patch)
treef52b2d5ac447a61e2bfce1eadbde42f127656ced
parent3440cb28627d7fbaf25c0d60cb9c6cf6d66d61ad (diff)
ARM: shmobile: r8a7790: Add PCI USB host clock support
This adds internal PCI USB host clock support. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index f25b43a1fd73..507073e9d455 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -201,7 +201,7 @@ enum {
201 MSTP811, MSTP810, MSTP809, MSTP808, 201 MSTP811, MSTP810, MSTP809, MSTP808,
202 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, 202 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
203 MSTP717, MSTP716, 203 MSTP717, MSTP716,
204 MSTP704, 204 MSTP704, MSTP703,
205 MSTP522, 205 MSTP522,
206 MSTP502, MSTP501, 206 MSTP502, MSTP501,
207 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 207 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
@@ -244,6 +244,7 @@ static struct clk mstp_clks[MSTP_NR] = {
244 [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */ 244 [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
245 [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */ 245 [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
246 [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */ 246 [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
247 [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
247 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */ 248 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
248 [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */ 249 [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
249 [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */ 250 [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
@@ -343,6 +344,9 @@ static struct clk_lookup lookups[] = {
343 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 344 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
344 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), 345 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
345 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), 346 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
347 CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
348 CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
349 CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
346 CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]), 350 CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
347 CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]), 351 CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
348 352