diff options
author | Benoit Cousson <b-cousson@ti.com> | 2011-07-09 21:14:28 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2011-07-09 21:14:28 -0400 |
commit | 00fe610b7a699780e956756be91ba60343302e49 (patch) | |
tree | c14795e179e9b9e56140a1421ccc88f8426ff0eb | |
parent | 7ecc5373fe5788b993820eb0bc0e4b7c282147e2 (diff) |
OMAP4: hwmod data: Fix bad alignement
Fix .prcm alignement and usb_otg_hs class and hwmod structures.
Add a couple of more potential hwmods in the comment.
Remove hsi, since it is already included in the data.
Remove one blank line.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 45 |
1 files changed, 23 insertions, 22 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index eb00c08b3481..0b73d8ee1de4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -632,7 +632,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |||
632 | * gpmc | 632 | * gpmc |
633 | * gpu | 633 | * gpu |
634 | * hdq1w | 634 | * hdq1w |
635 | * hsi | 635 | * mcasp |
636 | * mpu_c0 | ||
637 | * mpu_c1 | ||
636 | * ocmc_ram | 638 | * ocmc_ram |
637 | * ocp2scp_usb_phy | 639 | * ocp2scp_usb_phy |
638 | * ocp_wp_noc | 640 | * ocp_wp_noc |
@@ -739,7 +741,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = { | |||
739 | .mpu_irqs = omap44xx_aess_irqs, | 741 | .mpu_irqs = omap44xx_aess_irqs, |
740 | .sdma_reqs = omap44xx_aess_sdma_reqs, | 742 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
741 | .main_clk = "aess_fck", | 743 | .main_clk = "aess_fck", |
742 | .prcm = { | 744 | .prcm = { |
743 | .omap4 = { | 745 | .omap4 = { |
744 | .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | 746 | .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
745 | }, | 747 | }, |
@@ -768,7 +770,7 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { | |||
768 | static struct omap_hwmod omap44xx_bandgap_hwmod = { | 770 | static struct omap_hwmod omap44xx_bandgap_hwmod = { |
769 | .name = "bandgap", | 771 | .name = "bandgap", |
770 | .class = &omap44xx_bandgap_hwmod_class, | 772 | .class = &omap44xx_bandgap_hwmod_class, |
771 | .prcm = { | 773 | .prcm = { |
772 | .omap4 = { | 774 | .omap4 = { |
773 | .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | 775 | .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, |
774 | }, | 776 | }, |
@@ -827,7 +829,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { | |||
827 | .class = &omap44xx_counter_hwmod_class, | 829 | .class = &omap44xx_counter_hwmod_class, |
828 | .flags = HWMOD_SWSUP_SIDLE, | 830 | .flags = HWMOD_SWSUP_SIDLE, |
829 | .main_clk = "sys_32k_ck", | 831 | .main_clk = "sys_32k_ck", |
830 | .prcm = { | 832 | .prcm = { |
831 | .omap4 = { | 833 | .omap4 = { |
832 | .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, | 834 | .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, |
833 | }, | 835 | }, |
@@ -1003,7 +1005,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { | |||
1003 | .mpu_irqs = omap44xx_dmic_irqs, | 1005 | .mpu_irqs = omap44xx_dmic_irqs, |
1004 | .sdma_reqs = omap44xx_dmic_sdma_reqs, | 1006 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
1005 | .main_clk = "dmic_fck", | 1007 | .main_clk = "dmic_fck", |
1006 | .prcm = { | 1008 | .prcm = { |
1007 | .omap4 = { | 1009 | .omap4 = { |
1008 | .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | 1010 | .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
1009 | }, | 1011 | }, |
@@ -2093,7 +2095,7 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { | |||
2093 | .class = &omap44xx_hsi_hwmod_class, | 2095 | .class = &omap44xx_hsi_hwmod_class, |
2094 | .mpu_irqs = omap44xx_hsi_irqs, | 2096 | .mpu_irqs = omap44xx_hsi_irqs, |
2095 | .main_clk = "hsi_fck", | 2097 | .main_clk = "hsi_fck", |
2096 | .prcm = { | 2098 | .prcm = { |
2097 | .omap4 = { | 2099 | .omap4 = { |
2098 | .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, | 2100 | .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
2099 | }, | 2101 | }, |
@@ -2390,7 +2392,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = { | |||
2390 | .flags = HWMOD_INIT_NO_RESET, | 2392 | .flags = HWMOD_INIT_NO_RESET, |
2391 | .rst_lines = omap44xx_ipu_c0_resets, | 2393 | .rst_lines = omap44xx_ipu_c0_resets, |
2392 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), | 2394 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), |
2393 | .prcm = { | 2395 | .prcm = { |
2394 | .omap4 = { | 2396 | .omap4 = { |
2395 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, | 2397 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, |
2396 | }, | 2398 | }, |
@@ -2405,7 +2407,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = { | |||
2405 | .flags = HWMOD_INIT_NO_RESET, | 2407 | .flags = HWMOD_INIT_NO_RESET, |
2406 | .rst_lines = omap44xx_ipu_c1_resets, | 2408 | .rst_lines = omap44xx_ipu_c1_resets, |
2407 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), | 2409 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), |
2408 | .prcm = { | 2410 | .prcm = { |
2409 | .omap4 = { | 2411 | .omap4 = { |
2410 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, | 2412 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, |
2411 | }, | 2413 | }, |
@@ -2420,7 +2422,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { | |||
2420 | .rst_lines = omap44xx_ipu_resets, | 2422 | .rst_lines = omap44xx_ipu_resets, |
2421 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | 2423 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), |
2422 | .main_clk = "ipu_fck", | 2424 | .main_clk = "ipu_fck", |
2423 | .prcm = { | 2425 | .prcm = { |
2424 | .omap4 = { | 2426 | .omap4 = { |
2425 | .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | 2427 | .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, |
2426 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, | 2428 | .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, |
@@ -2506,7 +2508,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = { | |||
2506 | .mpu_irqs = omap44xx_iss_irqs, | 2508 | .mpu_irqs = omap44xx_iss_irqs, |
2507 | .sdma_reqs = omap44xx_iss_sdma_reqs, | 2509 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
2508 | .main_clk = "iss_fck", | 2510 | .main_clk = "iss_fck", |
2509 | .prcm = { | 2511 | .prcm = { |
2510 | .omap4 = { | 2512 | .omap4 = { |
2511 | .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | 2513 | .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, |
2512 | }, | 2514 | }, |
@@ -2686,7 +2688,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { | |||
2686 | .class = &omap44xx_kbd_hwmod_class, | 2688 | .class = &omap44xx_kbd_hwmod_class, |
2687 | .mpu_irqs = omap44xx_kbd_irqs, | 2689 | .mpu_irqs = omap44xx_kbd_irqs, |
2688 | .main_clk = "kbd_fck", | 2690 | .main_clk = "kbd_fck", |
2689 | .prcm = { | 2691 | .prcm = { |
2690 | .omap4 = { | 2692 | .omap4 = { |
2691 | .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | 2693 | .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, |
2692 | }, | 2694 | }, |
@@ -2750,7 +2752,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { | |||
2750 | .name = "mailbox", | 2752 | .name = "mailbox", |
2751 | .class = &omap44xx_mailbox_hwmod_class, | 2753 | .class = &omap44xx_mailbox_hwmod_class, |
2752 | .mpu_irqs = omap44xx_mailbox_irqs, | 2754 | .mpu_irqs = omap44xx_mailbox_irqs, |
2753 | .prcm = { | 2755 | .prcm = { |
2754 | .omap4 = { | 2756 | .omap4 = { |
2755 | .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, | 2757 | .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, |
2756 | }, | 2758 | }, |
@@ -3132,7 +3134,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |||
3132 | .mpu_irqs = omap44xx_mcpdm_irqs, | 3134 | .mpu_irqs = omap44xx_mcpdm_irqs, |
3133 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, | 3135 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
3134 | .main_clk = "mcpdm_fck", | 3136 | .main_clk = "mcpdm_fck", |
3135 | .prcm = { | 3137 | .prcm = { |
3136 | .omap4 = { | 3138 | .omap4 = { |
3137 | .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | 3139 | .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, |
3138 | }, | 3140 | }, |
@@ -3429,7 +3431,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |||
3429 | }; | 3431 | }; |
3430 | 3432 | ||
3431 | /* mmc1 */ | 3433 | /* mmc1 */ |
3432 | |||
3433 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | 3434 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { |
3434 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | 3435 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, |
3435 | { .irq = -1 } | 3436 | { .irq = -1 } |
@@ -3480,7 +3481,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { | |||
3480 | .mpu_irqs = omap44xx_mmc1_irqs, | 3481 | .mpu_irqs = omap44xx_mmc1_irqs, |
3481 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, | 3482 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
3482 | .main_clk = "mmc1_fck", | 3483 | .main_clk = "mmc1_fck", |
3483 | .prcm = { | 3484 | .prcm = { |
3484 | .omap4 = { | 3485 | .omap4 = { |
3485 | .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | 3486 | .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
3486 | }, | 3487 | }, |
@@ -3539,7 +3540,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { | |||
3539 | .mpu_irqs = omap44xx_mmc2_irqs, | 3540 | .mpu_irqs = omap44xx_mmc2_irqs, |
3540 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, | 3541 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
3541 | .main_clk = "mmc2_fck", | 3542 | .main_clk = "mmc2_fck", |
3542 | .prcm = { | 3543 | .prcm = { |
3543 | .omap4 = { | 3544 | .omap4 = { |
3544 | .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | 3545 | .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
3545 | }, | 3546 | }, |
@@ -3593,7 +3594,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { | |||
3593 | .mpu_irqs = omap44xx_mmc3_irqs, | 3594 | .mpu_irqs = omap44xx_mmc3_irqs, |
3594 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, | 3595 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
3595 | .main_clk = "mmc3_fck", | 3596 | .main_clk = "mmc3_fck", |
3596 | .prcm = { | 3597 | .prcm = { |
3597 | .omap4 = { | 3598 | .omap4 = { |
3598 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | 3599 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, |
3599 | }, | 3600 | }, |
@@ -3646,7 +3647,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { | |||
3646 | 3647 | ||
3647 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, | 3648 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
3648 | .main_clk = "mmc4_fck", | 3649 | .main_clk = "mmc4_fck", |
3649 | .prcm = { | 3650 | .prcm = { |
3650 | .omap4 = { | 3651 | .omap4 = { |
3651 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | 3652 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, |
3652 | }, | 3653 | }, |
@@ -3698,7 +3699,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { | |||
3698 | .mpu_irqs = omap44xx_mmc5_irqs, | 3699 | .mpu_irqs = omap44xx_mmc5_irqs, |
3699 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, | 3700 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
3700 | .main_clk = "mmc5_fck", | 3701 | .main_clk = "mmc5_fck", |
3701 | .prcm = { | 3702 | .prcm = { |
3702 | .omap4 = { | 3703 | .omap4 = { |
3703 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | 3704 | .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, |
3704 | }, | 3705 | }, |
@@ -4834,8 +4835,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |||
4834 | }; | 4835 | }; |
4835 | 4836 | ||
4836 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | 4837 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { |
4837 | .name = "usb_otg_hs", | 4838 | .name = "usb_otg_hs", |
4838 | .sysc = &omap44xx_usb_otg_hs_sysc, | 4839 | .sysc = &omap44xx_usb_otg_hs_sysc, |
4839 | }; | 4840 | }; |
4840 | 4841 | ||
4841 | /* usb_otg_hs */ | 4842 | /* usb_otg_hs */ |
@@ -4889,7 +4890,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |||
4889 | }, | 4890 | }, |
4890 | }, | 4891 | }, |
4891 | .opt_clks = usb_otg_hs_opt_clks, | 4892 | .opt_clks = usb_otg_hs_opt_clks, |
4892 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | 4893 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), |
4893 | .slaves = omap44xx_usb_otg_hs_slaves, | 4894 | .slaves = omap44xx_usb_otg_hs_slaves, |
4894 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), | 4895 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), |
4895 | .masters = omap44xx_usb_otg_hs_masters, | 4896 | .masters = omap44xx_usb_otg_hs_masters, |