diff options
author | Huang Shijie <b32955@freescale.com> | 2012-08-07 22:37:59 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-08-16 15:15:33 -0400 |
commit | 00592021010ad86d3b26bac7034034f6af145a2c (patch) | |
tree | ad64391844ab9a7cbfaf4a9b693ccd73586f75be | |
parent | 7d9739cd6b03575bc88c6ce3c60853dbc50a6ae2 (diff) |
serial: mxs-auart: fix the wrong RTS hardware flow control
Without checking if the auart supports the hardware flow control or not,
the old mxs_auart_set_mctrl() asserted the RTS pin blindly.
This will causes the auart receives wrong data in the following case:
The far-end has already started the write operation, and wait for
the auart asserts the RTS pin. Then the auart starts the read operation,
but mxs_auart_set_mctrl() may be called before we set the RTSCTS in the
mxs_auart_settermios(). So the RTS pin is asserted in a wrong situation,
and we get the wrong data in the end.
This bug has been catched when I connect the mx23(DTE) to the mx53(DCE).
This patch also replaces the AUART_CTRL2_RTS with AUART_CTRL2_RTSEN.
We should use the real the hardware flow control, not the software-controled
hardware flow control.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | drivers/tty/serial/mxs-auart.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c index 2e341b81ff89..3a667eed63d6 100644 --- a/drivers/tty/serial/mxs-auart.c +++ b/drivers/tty/serial/mxs-auart.c | |||
@@ -73,6 +73,7 @@ | |||
73 | #define AUART_CTRL0_CLKGATE (1 << 30) | 73 | #define AUART_CTRL0_CLKGATE (1 << 30) |
74 | 74 | ||
75 | #define AUART_CTRL2_CTSEN (1 << 15) | 75 | #define AUART_CTRL2_CTSEN (1 << 15) |
76 | #define AUART_CTRL2_RTSEN (1 << 14) | ||
76 | #define AUART_CTRL2_RTS (1 << 11) | 77 | #define AUART_CTRL2_RTS (1 << 11) |
77 | #define AUART_CTRL2_RXE (1 << 9) | 78 | #define AUART_CTRL2_RXE (1 << 9) |
78 | #define AUART_CTRL2_TXE (1 << 8) | 79 | #define AUART_CTRL2_TXE (1 << 8) |
@@ -259,9 +260,12 @@ static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) | |||
259 | 260 | ||
260 | u32 ctrl = readl(u->membase + AUART_CTRL2); | 261 | u32 ctrl = readl(u->membase + AUART_CTRL2); |
261 | 262 | ||
262 | ctrl &= ~AUART_CTRL2_RTS; | 263 | ctrl &= ~AUART_CTRL2_RTSEN; |
263 | if (mctrl & TIOCM_RTS) | 264 | if (mctrl & TIOCM_RTS) { |
264 | ctrl |= AUART_CTRL2_RTS; | 265 | if (u->state->port.flags & ASYNC_CTS_FLOW) |
266 | ctrl |= AUART_CTRL2_RTSEN; | ||
267 | } | ||
268 | |||
265 | s->ctrl = mctrl; | 269 | s->ctrl = mctrl; |
266 | writel(ctrl, u->membase + AUART_CTRL2); | 270 | writel(ctrl, u->membase + AUART_CTRL2); |
267 | } | 271 | } |
@@ -359,9 +363,9 @@ static void mxs_auart_settermios(struct uart_port *u, | |||
359 | 363 | ||
360 | /* figure out the hardware flow control settings */ | 364 | /* figure out the hardware flow control settings */ |
361 | if (cflag & CRTSCTS) | 365 | if (cflag & CRTSCTS) |
362 | ctrl2 |= AUART_CTRL2_CTSEN; | 366 | ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN; |
363 | else | 367 | else |
364 | ctrl2 &= ~AUART_CTRL2_CTSEN; | 368 | ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); |
365 | 369 | ||
366 | /* set baud rate */ | 370 | /* set baud rate */ |
367 | baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); | 371 | baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); |