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authorLinus Walleij <linus.walleij@linaro.org>2013-05-02 10:56:15 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-06-17 07:54:31 -0400
commit0004b017fe65eff60a9b403c52acc03521108c21 (patch)
tree23831006e3fc8c6621344065d8d9e5ad5ec22ab3
parent22f718efe61edffe30f9dc97292e5bbe66123843 (diff)
ARM: u300: push down syscon registers
Get rid of the <mach/syscon.h> header as a prerequisite for multiplatform support. Do this by pushing the registers down to their respective drivers and deleting the unused remainder. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--arch/arm/mach-u300/core.c26
-rw-r--r--arch/arm/mach-u300/include/mach/syscon.h592
-rw-r--r--arch/arm/mach-u300/regulator.c9
-rw-r--r--drivers/clk/clk-u300.c343
4 files changed, 373 insertions, 597 deletions
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 13d48125b89b..254fe922457d 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -22,7 +22,31 @@
22#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
23 23
24#include <mach/u300-regs.h> 24#include <mach/u300-regs.h>
25#include <mach/syscon.h> 25
26/*
27 * SYSCON addresses applicable to the core machine.
28 */
29
30/* Chip ID register 16bit (R/-) */
31#define U300_SYSCON_CIDR (0x400)
32/* SMCR */
33#define U300_SYSCON_SMCR (0x4d0)
34#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
35#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
36#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
37#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
38/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
39#define U300_SYSCON_CSDR (0x4f0)
40#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
41/* PRINT_CONTROL Print Control 16bit (R/-) */
42#define U300_SYSCON_PCR (0x4f8)
43#define U300_SYSCON_PCR_SERV_IND (0x0001)
44/* BOOT_CONTROL 16bit (R/-) */
45#define U300_SYSCON_BCR (0x4fc)
46#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
47#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
48#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
49#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
26 50
27/* 51/*
28 * Static I/O mappings that are needed for booting the U300 platforms. The 52 * Static I/O mappings that are needed for booting the U300 platforms. The
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0be9774..000000000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/syscon.h
4 *
5 *
6 * Copyright (C) 2008-2012 ST-Ericsson AB
7 *
8 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
9 */
10
11#ifndef __MACH_SYSCON_H
12#define __MACH_SYSCON_H
13
14/*
15 * All register defines for SYSCON registers that concerns individual
16 * block clocks and reset lines are registered here. This is because
17 * we don't want any other file to try to fool around with this stuff.
18 */
19
20/* APP side SYSCON registers */
21/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
22/* CLK Control Register 16bit (R/W) */
23#define U300_SYSCON_CCR (0x0000)
24#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
25#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
26#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
27#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
28#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
29#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
30#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
31#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
32#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
33/* CLK Status Register 16bit (R/W) */
34#define U300_SYSCON_CSR (0x0004)
35#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
36#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
37/* Reset lines for SLOW devices 16bit (R/W) */
38#define U300_SYSCON_RSR (0x0014)
39#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
40#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
41#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
42#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
43#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
44#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
45#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
46#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
47#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
48#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
49/* Reset lines for FAST devices 16bit (R/W) */
50#define U300_SYSCON_RFR (0x0018)
51#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
52#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
53#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
54#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
55#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
56#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
57#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
58#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
59/* Reset lines for the rest of the peripherals 16bit (R/W) */
60#define U300_SYSCON_RRR (0x001c)
61#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
62#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
63#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
64#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
65#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
66#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
67#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
68#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
69#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
70#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
71#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
72#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
73#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
74/* Clock enable for SLOW peripherals 16bit (R/W) */
75#define U300_SYSCON_CESR (0x0020)
76#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
77#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
78#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
79#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
80#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
81#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
82#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
83#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
84#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
85/* Clock enable for FAST peripherals 16bit (R/W) */
86#define U300_SYSCON_CEFR (0x0024)
87#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
88#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
89#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
90#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
91#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
92#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
93#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
94#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
95#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
96#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
97/* Clock enable for the rest of the peripherals 16bit (R/W) */
98#define U300_SYSCON_CERR (0x0028)
99#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
100#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
101#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
102#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
103#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
104#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
105#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
106#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
107#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
108#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
109#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
110#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
111#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
112#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
113/* Single block clock enable 16bit (-/W) */
114#define U300_SYSCON_SBCER (0x002c)
115#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
116#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
117#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
118#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
119#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
120#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
121#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
122#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
123#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
124#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
125#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
126#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
127#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
128#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
129#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
130#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
131#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
132#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
133#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
134#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
135#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
136#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
137#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
138#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
139#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
140#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
141#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
142#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
143#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
144#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
145#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
146#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
147#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
148/* Single block clock disable 16bit (-/W) */
149#define U300_SYSCON_SBCDR (0x0030)
150/* Same values as above for SBCER */
151/* Clock force SLOW peripherals 16bit (R/W) */
152#define U300_SYSCON_CFSR (0x003c)
153#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
154#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
155#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
156#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
157#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
158#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
159#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
160#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
161#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
162/* Clock force FAST peripherals 16bit (R/W) */
163#define U300_SYSCON_CFFR (0x40)
164/* Values not defined. Define if you want to use them. */
165/* Clock force the rest of the peripherals 16bit (R/W) */
166#define U300_SYSCON_CFRR (0x44)
167#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
168#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
169#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
170#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
171#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
172#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
173#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
174#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
175#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
176#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
177#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
178#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
179#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
180#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
181/* PLL208 Frequency Control 16bit (R/W) */
182#define U300_SYSCON_PFCR (0x48)
183#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
184/* Power Management Control 16bit (R/W) */
185#define U300_SYSCON_PMCR (0x50)
186#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
187#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
188/*
189 * All other clocking registers moved to clock.c!
190 */
191/* Reset Out 16bit (R/W) */
192#define U300_SYSCON_RCR (0x6c)
193#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
194/* EMIF Slew Rate Control 16bit (R/W) */
195#define U300_SYSCON_SRCLR (0x70)
196#define U300_SYSCON_SRCLR_MASK (0x03FF)
197#define U300_SYSCON_SRCLR_VALUE (0x03FF)
198#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
199#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
200#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
201#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
202#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
203#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
204#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
205#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
206#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
207#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
208/* EMIF Clock Control Register 16bit (R/W) */
209#define U300_SYSCON_ECCR (0x0078)
210#define U300_SYSCON_ECCR_MASK (0x000F)
211#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
212#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
213#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
214#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
215/* Step one for killing the applications system 16bit (-/W) */
216#define U300_SYSCON_KA1R (0x0080)
217#define U300_SYSCON_KA1R_MASK (0xFFFF)
218#define U300_SYSCON_KA1R_VALUE (0xFFFF)
219/* Step two for killing the application system 16bit (-/W) */
220#define U300_SYSCON_KA2R (0x0084)
221#define U300_SYSCON_KA2R_MASK (0xFFFF)
222#define U300_SYSCON_KA2R_VALUE (0xFFFF)
223/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
224#define U300_SYSCON_MMF0R (0x90)
225#define U300_SYSCON_MMF0R_MASK (0x00FF)
226#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
227#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
228/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
229#define U300_SYSCON_MMF1R (0x94)
230#define U300_SYSCON_MMF1R_MASK (0x00FF)
231#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
232#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
233/* AAIF control register 16 bit (R/W) */
234#define U300_SYSCON_AAIFCR (0x98)
235#define U300_SYSCON_AAIFCR_MASK (0x0003)
236#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003)
237#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000)
238#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001)
239#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002)
240#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003)
241/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
242#define U300_SYSCON_MMCR (0x9C)
243#define U300_SYSCON_MMCR_MASK (0x0003)
244#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
245#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
246/* Pull up/down control (R/W) */
247#define U300_SYSCON_PUCR (0x104)
248#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200)
249#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100)
250#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080)
251#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040)
252#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F)
253/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
254#define U300_SYSCON_S0CCR (0x120)
255#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
256#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
257#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
258#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
259#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
260#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
261#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
262#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
263#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
264#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
265#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
266#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
267#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
268#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
269#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
270#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
271/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
272#define U300_SYSCON_S1CCR (0x124)
273#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
274#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
275#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
276#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
277#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
278#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
279#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
280#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
281#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
282#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
283#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
284#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
285#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
286#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
287#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
288#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
289/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
290#define U300_SYSCON_S2CCR (0x128)
291#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
292#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
293#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
294#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
295#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
296#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
297#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
298#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
299#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
300#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
301#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
302#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
303#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
304#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
305#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
306#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
307#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
308/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
309#define U300_SYSCON_MCR (0x12c)
310#define U300_SYSCON_MCR_FIELD_MASK (0x00FF)
311#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0)
312#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000)
313#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040)
314#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0)
315#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030)
316#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000)
317#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010)
318#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020)
319#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030)
320#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C)
321#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000)
322#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004)
323#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008)
324#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C)
325#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002)
326#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001)
327/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
328#define U300_SYSCON_PICR (0x0130)
329#define U300_SYSCON_PICR_MASK (0x00FF)
330#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
331#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
332#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
333#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
334#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
335#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
336#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
337#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
338/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
339#define U300_SYSCON_PISR (0x0134)
340#define U300_SYSCON_PISR_MASK (0x000F)
341#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
342#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
343#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
344#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
345/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
346#define U300_SYSCON_PICLR (0x0138)
347#define U300_SYSCON_PICLR_MASK (0x000F)
348#define U300_SYSCON_PICLR_RWMASK (0x0000)
349#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
350#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
351#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
352#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
353/* CAMIF_CONTROL 16 bit (-/W) */
354#define U300_SYSCON_CICR (0x013C)
355#define U300_SYSCON_CICR_MASK (0x0FFF)
356#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00)
357#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00)
358#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300)
359#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0)
360#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0)
361#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030)
362#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F)
363#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C)
364#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003)
365/* Clock activity observability register 0 */
366#define U300_SYSCON_C0OAR (0x140)
367#define U300_SYSCON_C0OAR_MASK (0xFFFF)
368#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
369#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
370#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
371#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
372#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
373#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
374#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
375#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
376#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
377#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
378#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
379#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
380#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
381#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
382#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
383#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
384#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
385/* Clock activity observability register 1 */
386#define U300_SYSCON_C1OAR (0x144)
387#define U300_SYSCON_C1OAR_MASK (0x3FFE)
388#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
389#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
390#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
391#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
392#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
393#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
394#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
395#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
396#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
397#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
398#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
399#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
400#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
401#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
402/* Clock activity observability register 2 */
403#define U300_SYSCON_C2OAR (0x148)
404#define U300_SYSCON_C2OAR_MASK (0x0FFF)
405#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
406#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
407#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
408#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
409#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
410#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
411#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
412#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
413#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
414#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
415#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
416#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
417#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
418
419/* Chip ID register 16bit (R/-) */
420#define U300_SYSCON_CIDR (0x400)
421/* Video IRQ clear 16bit (R/W) */
422#define U300_SYSCON_VICR (0x404)
423#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
424#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
425/* SMCR */
426#define U300_SYSCON_SMCR (0x4d0)
427#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
428#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
429#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
430#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
431/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
432#define U300_SYSCON_CSDR (0x4f0)
433#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
434/* PRINT_CONTROL Print Control 16bit (R/-) */
435#define U300_SYSCON_PCR (0x4f8)
436#define U300_SYSCON_PCR_SERV_IND (0x0001)
437/* BOOT_CONTROL 16bit (R/-) */
438#define U300_SYSCON_BCR (0x4fc)
439#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
440#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
441#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
442#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
443
444
445/* CPU clock defines */
446/**
447 * CPU high frequency in MHz
448 */
449#define SYSCON_CPU_CLOCK_HIGH 208
450/**
451 * CPU medium frequency in MHz
452 */
453#define SYSCON_CPU_CLOCK_MEDIUM 52
454/**
455 * CPU low frequency in MHz
456 */
457#define SYSCON_CPU_CLOCK_LOW 13
458
459/* EMIF clock defines */
460/**
461 * EMIF high frequency in MHz
462 */
463#define SYSCON_EMIF_CLOCK_HIGH 104
464/**
465 * EMIF medium frequency in MHz
466 */
467#define SYSCON_EMIF_CLOCK_MEDIUM 52
468/**
469 * EMIF low frequency in MHz
470 */
471#define SYSCON_EMIF_CLOCK_LOW 13
472
473/* AHB clock defines */
474/**
475 * AHB high frequency in MHz
476 */
477#define SYSCON_AHB_CLOCK_HIGH 52
478/**
479 * AHB medium frequency in MHz
480 */
481#define SYSCON_AHB_CLOCK_MEDIUM 26
482/**
483 * AHB low frequency in MHz
484 */
485#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
486
487enum syscon_busmaster {
488 SYSCON_BM_DMAC,
489 SYSCON_BM_XGAM,
490 SYSCON_BM_VIDEO_ENC
491};
492
493/* Selectr a resistor or a set of resistors */
494enum syscon_pull_up_down {
495 SYSCON_PU_KEY_IN_EN,
496 SYSCON_PU_EMIF_1_8_BIT_EN,
497 SYSCON_PU_EMIF_1_16_BIT_EN,
498 SYSCON_PU_EMIF_1_NFIF_READY_EN,
499 SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
500};
501
502/*
503 * Note that this array must match the order of the array "clk_reg"
504 * in syscon.c
505 */
506enum syscon_clk {
507 SYSCON_CLKCONTROL_SLOW_BRIDGE,
508 SYSCON_CLKCONTROL_UART,
509 SYSCON_CLKCONTROL_BTR,
510 SYSCON_CLKCONTROL_EH,
511 SYSCON_CLKCONTROL_GPIO,
512 SYSCON_CLKCONTROL_KEYPAD,
513 SYSCON_CLKCONTROL_APP_TIMER,
514 SYSCON_CLKCONTROL_ACC_TIMER,
515 SYSCON_CLKCONTROL_FAST_BRIDGE,
516 SYSCON_CLKCONTROL_I2C0,
517 SYSCON_CLKCONTROL_I2C1,
518 SYSCON_CLKCONTROL_I2S0,
519 SYSCON_CLKCONTROL_I2S1,
520 SYSCON_CLKCONTROL_MMC,
521 SYSCON_CLKCONTROL_SPI,
522 SYSCON_CLKCONTROL_I2S0_CORE,
523 SYSCON_CLKCONTROL_I2S1_CORE,
524 SYSCON_CLKCONTROL_UART1,
525 SYSCON_CLKCONTROL_AAIF,
526 SYSCON_CLKCONTROL_AHB,
527 SYSCON_CLKCONTROL_APEX,
528 SYSCON_CLKCONTROL_CPU,
529 SYSCON_CLKCONTROL_DMA,
530 SYSCON_CLKCONTROL_EMIF,
531 SYSCON_CLKCONTROL_NAND_IF,
532 SYSCON_CLKCONTROL_VIDEO_ENC,
533 SYSCON_CLKCONTROL_XGAM,
534 SYSCON_CLKCONTROL_SEMI,
535 SYSCON_CLKCONTROL_AHB_SUBSYS,
536 SYSCON_CLKCONTROL_MSPRO
537};
538
539enum syscon_sysclk_mode {
540 SYSCON_SYSCLK_DISABLED,
541 SYSCON_SYSCLK_M_CLK,
542 SYSCON_SYSCLK_ACC_FSM,
543 SYSCON_SYSCLK_PLL60_48,
544 SYSCON_SYSCLK_PLL60_60,
545 SYSCON_SYSCLK_ACC_PLL208,
546 SYSCON_SYSCLK_APP_PLL13,
547 SYSCON_SYSCLK_APP_FSM,
548 SYSCON_SYSCLK_RTC,
549 SYSCON_SYSCLK_APP_PLL208
550};
551
552enum syscon_sysclk_req {
553 SYSCON_SYSCLKREQ_DISABLED,
554 SYSCON_SYSCLKREQ_ACTIVE_LOW,
555 SYSCON_SYSCLKREQ_MONITOR
556};
557
558enum syscon_clk_mode {
559 SYSCON_CLKMODE_OFF,
560 SYSCON_CLKMODE_DEFAULT,
561 SYSCON_CLKMODE_LOW,
562 SYSCON_CLKMODE_MEDIUM,
563 SYSCON_CLKMODE_HIGH,
564 SYSCON_CLKMODE_PERMANENT,
565 SYSCON_CLKMODE_ON,
566};
567
568enum syscon_call_mode {
569 SYSCON_CLKCALL_NOWAIT,
570 SYSCON_CLKCALL_WAIT,
571};
572
573int syscon_dc_on(bool keep_power_on);
574int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
575 bool active);
576bool syscon_get_busmaster_active_state(void);
577int syscon_set_sleep_mask(enum syscon_clk,
578 bool sleep_ctrl);
579int syscon_config_sysclk(u32 sysclk,
580 enum syscon_sysclk_mode sysclkmode,
581 bool inverse,
582 u32 divisor,
583 enum syscon_sysclk_req sysclkreq);
584bool syscon_can_turn_off_semi_clock(void);
585
586/* This function is restricted to core.c */
587int syscon_request_normal_power(bool req);
588
589/* This function is restricted to be used by platform_speed.c */
590int syscon_speed_request(enum syscon_call_mode wait_mode,
591 enum syscon_clk_mode req_clk_mode);
592#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index bbda954e00fd..ab7d7a519b2f 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -17,9 +17,12 @@
17#include <linux/regulator/consumer.h> 17#include <linux/regulator/consumer.h>
18/* Those are just for writing in syscon */ 18/* Those are just for writing in syscon */
19#include <linux/io.h> 19#include <linux/io.h>
20#include <asm/mach-types.h> 20#include <mach/u300-regs.h>
21#include <mach/hardware.h> 21
22#include <mach/syscon.h> 22/* Power Management Control 16bit (R/W) */
23#define U300_SYSCON_PMCR (0x50)
24#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
25#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
23 26
24/* 27/*
25 * Regulators that power the board and chip and which are 28 * Regulators that power the board and chip and which are
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a15f7928fb11..a41e42ec0916 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,7 +11,348 @@
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/spinlock.h> 13#include <linux/spinlock.h>
14#include <mach/syscon.h> 14
15/* APP side SYSCON registers */
16/* CLK Control Register 16bit (R/W) */
17#define U300_SYSCON_CCR (0x0000)
18#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
19#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
20#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
21#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
22#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
23#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
24#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
25#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
26#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
27/* CLK Status Register 16bit (R/W) */
28#define U300_SYSCON_CSR (0x0004)
29#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
30#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
31/* Reset lines for SLOW devices 16bit (R/W) */
32#define U300_SYSCON_RSR (0x0014)
33#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
34#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
35#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
36#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
37#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
38#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
39#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
40#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
41#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
42#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
43/* Reset lines for FAST devices 16bit (R/W) */
44#define U300_SYSCON_RFR (0x0018)
45#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
46#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
47#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
48#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
49#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
50#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
51#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
52#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
53/* Reset lines for the rest of the peripherals 16bit (R/W) */
54#define U300_SYSCON_RRR (0x001c)
55#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
56#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
57#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
58#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
59#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
60#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
61#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
62#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
63#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
64#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
65#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
66#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
67#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
68/* Clock enable for SLOW peripherals 16bit (R/W) */
69#define U300_SYSCON_CESR (0x0020)
70#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
71#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
72#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
73#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
74#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
75#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
76#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
77#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
78#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
79/* Clock enable for FAST peripherals 16bit (R/W) */
80#define U300_SYSCON_CEFR (0x0024)
81#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
82#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
83#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
84#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
85#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
86#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
87#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
88#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
89#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
90#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
91/* Clock enable for the rest of the peripherals 16bit (R/W) */
92#define U300_SYSCON_CERR (0x0028)
93#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
94#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
95#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
96#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
97#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
98#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
99#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
100#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
101#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
102#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
103#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
104#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
105#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
106#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
107/* Single block clock enable 16bit (-/W) */
108#define U300_SYSCON_SBCER (0x002c)
109#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
110#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
111#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
112#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
113#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
114#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
115#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
116#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
117#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
118#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
119#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
120#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
121#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
122#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
123#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
124#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
125#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
126#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
127#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
128#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
129#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
130#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
131#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
132#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
133#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
134#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
135#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
136#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
137#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
138#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
139#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
140#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
141#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
142/* Single block clock disable 16bit (-/W) */
143#define U300_SYSCON_SBCDR (0x0030)
144/* Same values as above for SBCER */
145/* Clock force SLOW peripherals 16bit (R/W) */
146#define U300_SYSCON_CFSR (0x003c)
147#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
148#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
149#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
150#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
151#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
152#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
153#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
154#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
155#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
156/* Clock force FAST peripherals 16bit (R/W) */
157#define U300_SYSCON_CFFR (0x40)
158/* Values not defined. Define if you want to use them. */
159/* Clock force the rest of the peripherals 16bit (R/W) */
160#define U300_SYSCON_CFRR (0x44)
161#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
162#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
163#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
164#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
165#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
166#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
167#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
168#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
169#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
170#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
171#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
172#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
173#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
174#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
175/* PLL208 Frequency Control 16bit (R/W) */
176#define U300_SYSCON_PFCR (0x48)
177#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
178/* Power Management Control 16bit (R/W) */
179#define U300_SYSCON_PMCR (0x50)
180#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
181#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
182/* Reset Out 16bit (R/W) */
183#define U300_SYSCON_RCR (0x6c)
184#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
185/* EMIF Slew Rate Control 16bit (R/W) */
186#define U300_SYSCON_SRCLR (0x70)
187#define U300_SYSCON_SRCLR_MASK (0x03FF)
188#define U300_SYSCON_SRCLR_VALUE (0x03FF)
189#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
190#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
191#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
192#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
193#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
194#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
195#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
196#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
197#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
198#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
199/* EMIF Clock Control Register 16bit (R/W) */
200#define U300_SYSCON_ECCR (0x0078)
201#define U300_SYSCON_ECCR_MASK (0x000F)
202#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
203#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
204#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
205#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
206/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
207#define U300_SYSCON_MMF0R (0x90)
208#define U300_SYSCON_MMF0R_MASK (0x00FF)
209#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
210#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
211/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
212#define U300_SYSCON_MMF1R (0x94)
213#define U300_SYSCON_MMF1R_MASK (0x00FF)
214#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
215#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
216/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
217#define U300_SYSCON_MMCR (0x9C)
218#define U300_SYSCON_MMCR_MASK (0x0003)
219#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
220#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
221/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
222#define U300_SYSCON_S0CCR (0x120)
223#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
224#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
225#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
226#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
227#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
228#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
229#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
230#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
231#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
232#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
233#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
234#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
235#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
236#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
237#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
238#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
239/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
240#define U300_SYSCON_S1CCR (0x124)
241#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
242#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
243#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
244#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
245#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
246#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
247#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
248#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
249#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
250#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
251#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
252#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
253#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
254#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
255#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
256#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
257/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
258#define U300_SYSCON_S2CCR (0x128)
259#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
260#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
261#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
262#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
263#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
264#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
265#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
266#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
267#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
268#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
269#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
270#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
271#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
272#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
273#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
274#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
275#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
276/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
277#define U300_SYSCON_PICR (0x0130)
278#define U300_SYSCON_PICR_MASK (0x00FF)
279#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
280#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
281#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
282#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
283#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
284#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
285#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
286#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
287/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
288#define U300_SYSCON_PISR (0x0134)
289#define U300_SYSCON_PISR_MASK (0x000F)
290#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
291#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
292#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
293#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
294/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
295#define U300_SYSCON_PICLR (0x0138)
296#define U300_SYSCON_PICLR_MASK (0x000F)
297#define U300_SYSCON_PICLR_RWMASK (0x0000)
298#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
299#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
300#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
301#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
302/* Clock activity observability register 0 */
303#define U300_SYSCON_C0OAR (0x140)
304#define U300_SYSCON_C0OAR_MASK (0xFFFF)
305#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
306#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
307#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
308#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
309#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
310#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
311#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
312#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
313#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
314#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
315#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
316#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
317#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
318#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
319#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
320#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
321#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
322/* Clock activity observability register 1 */
323#define U300_SYSCON_C1OAR (0x144)
324#define U300_SYSCON_C1OAR_MASK (0x3FFE)
325#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
326#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
327#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
328#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
329#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
330#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
331#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
332#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
333#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
334#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
335#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
336#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
337#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
338#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
339/* Clock activity observability register 2 */
340#define U300_SYSCON_C2OAR (0x148)
341#define U300_SYSCON_C2OAR_MASK (0x0FFF)
342#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
343#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
344#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
345#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
346#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
347#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
348#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
349#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
350#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
351#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
352#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
353#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
354#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
355
15 356
16/* 357/*
17 * The clocking hierarchy currently looks like this. 358 * The clocking hierarchy currently looks like this.
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 00:30:03 -0500