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authorDavid Gibson <david@gibson.dropbear.id.au>2007-06-13 00:52:59 -0400
committerPaul Mackerras <paulus@samba.org>2007-06-14 08:30:16 -0400
commitb2ba34f370a66d9ed4bbd440e45296ecf3e267d3 (patch)
tree9a743c7b356f5ceba15b3008588126fdced94fb8
parent11123346bfba8e65631957c6c25ed1a6ca1b4ffe (diff)
[POWERPC] Derive ebc ranges property from EBC registers
In the device tree for Ebony, the 'ranges' property in the node for the EBC bridge shows the mappings from the chip select / address lines actually used for the EBC peripherals into the address space of the OPB. At present, these mappings are hardcoded in ebony.dts for the mappings set up by the OpenBIOS firmware when it configures the EBC bridge. This replaces the hardcoded mappings with code in the zImage to read the EBC configuration registers and create an appropriate ranges property based on them. This should make the zImage and kernel more robust to changes in firmware configuration. In particular, some of the Ebony's DIP switches can change the effective address of the Flash and other peripherals in OPB space. With this patch, the kernel will be able to cope with at least some of the possible variations. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/boot/44x.c29
-rw-r--r--arch/powerpc/boot/44x.h1
-rw-r--r--arch/powerpc/boot/dcr.h37
-rw-r--r--arch/powerpc/boot/dts/ebony.dts8
-rw-r--r--arch/powerpc/boot/ebony.c1
5 files changed, 71 insertions, 5 deletions
diff --git a/arch/powerpc/boot/44x.c b/arch/powerpc/boot/44x.c
index bc3f570ff9ba..9f64e840bef6 100644
--- a/arch/powerpc/boot/44x.c
+++ b/arch/powerpc/boot/44x.c
@@ -54,3 +54,32 @@ void ibm44x_dbcr_reset(void)
54 ); 54 );
55 55
56} 56}
57
58/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
59 * banks into the OPB address space */
60void ibm4xx_fixup_ebc_ranges(const char *ebc)
61{
62 void *devp;
63 u32 bxcr;
64 u32 ranges[EBC_NUM_BANKS*4];
65 u32 *p = ranges;
66 int i;
67
68 for (i = 0; i < EBC_NUM_BANKS; i++) {
69 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
70 bxcr = mfdcr(DCRN_EBC0_CFGDATA);
71
72 if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
73 *p++ = i;
74 *p++ = 0;
75 *p++ = bxcr & EBC_BXCR_BAS;
76 *p++ = EBC_BXCR_BANK_SIZE(bxcr);
77 }
78 }
79
80 devp = finddevice(ebc);
81 if (! devp)
82 fatal("Couldn't locate EBC node %s\n\r", ebc);
83
84 setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
85}
diff --git a/arch/powerpc/boot/44x.h b/arch/powerpc/boot/44x.h
index 0da4abf390ad..577982c9a3cd 100644
--- a/arch/powerpc/boot/44x.h
+++ b/arch/powerpc/boot/44x.h
@@ -11,6 +11,7 @@
11#define _PPC_BOOT_44X_H_ 11#define _PPC_BOOT_44X_H_
12 12
13void ibm44x_fixup_memsize(void); 13void ibm44x_fixup_memsize(void);
14void ibm4xx_fixup_ebc_ranges(const char *ebc);
14 15
15void ibm44x_dbcr_reset(void); 16void ibm44x_dbcr_reset(void);
16void ebony_init(void *mac0, void *mac1); 17void ebony_init(void *mac0, void *mac1);
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 877bc97b1e97..14b44aa96fea 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -26,6 +26,43 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C
26#define SDRAM_CONFIG_BANK_SIZE(reg) \ 26#define SDRAM_CONFIG_BANK_SIZE(reg) \
27 (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)) 27 (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
28 28
29/* 440GP External Bus Controller (EBC) */
30#define DCRN_EBC0_CFGADDR 0x012
31#define DCRN_EBC0_CFGDATA 0x013
32#define EBC_NUM_BANKS 8
33#define EBC_B0CR 0x00
34#define EBC_B1CR 0x01
35#define EBC_B2CR 0x02
36#define EBC_B3CR 0x03
37#define EBC_B4CR 0x04
38#define EBC_B5CR 0x05
39#define EBC_B6CR 0x06
40#define EBC_B7CR 0x07
41#define EBC_BXCR(n) (n)
42#define EBC_BXCR_BAS 0xfff00000
43#define EBC_BXCR_BS 0x000e0000
44#define EBC_BXCR_BANK_SIZE(reg) \
45 (0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
46#define EBC_BXCR_BU 0x00018000
47#define EBC_BXCR_BU_OFF 0x00000000
48#define EBC_BXCR_BU_RO 0x00008000
49#define EBC_BXCR_BU_WO 0x00010000
50#define EBC_BXCR_BU_RW 0x00018000
51#define EBC_BXCR_BW 0x00006000
52#define EBC_B0AP 0x10
53#define EBC_B1AP 0x11
54#define EBC_B2AP 0x12
55#define EBC_B3AP 0x13
56#define EBC_B4AP 0x14
57#define EBC_B5AP 0x15
58#define EBC_B6AP 0x16
59#define EBC_B7AP 0x17
60#define EBC_BXAP(n) (0x10+(n))
61#define EBC_BEAR 0x20
62#define EBC_BESR 0x21
63#define EBC_CFG 0x23
64#define EBC_CID 0x24
65
29/* 440GP Clock, PM, chip control */ 66/* 440GP Clock, PM, chip control */
30#define DCRN_CPC0_SR 0x0b0 67#define DCRN_CPC0_SR 0x0b0
31#define DCRN_CPC0_ER 0x0b1 68#define DCRN_CPC0_ER 0x0b1
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index 0ec02f4726b5..586a2fc13c63 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -135,11 +135,9 @@
135 #address-cells = <2>; 135 #address-cells = <2>;
136 #size-cells = <1>; 136 #size-cells = <1>;
137 clock-frequency = <0>; // Filled in by zImage 137 clock-frequency = <0>; // Filled in by zImage
138 ranges = <0 00000000 fff00000 100000 138 // ranges property is supplied by zImage
139 1 00000000 48000000 100000 139 // based on firmware's configuration of the
140 2 00000000 ff800000 400000 140 // EBC bridge
141 3 00000000 48200000 100000
142 7 00000000 48300000 100000>;
143 interrupts = <5 4>; 141 interrupts = <5 4>;
144 interrupt-parent = <&UIC1>; 142 interrupt-parent = <&UIC1>;
145 143
diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c
index 634985802006..75daedafd0a4 100644
--- a/arch/powerpc/boot/ebony.c
+++ b/arch/powerpc/boot/ebony.c
@@ -100,6 +100,7 @@ static void ebony_fixups(void)
100 ibm440gp_fixup_clocks(sysclk, 6 * 1843200); 100 ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
101 ibm44x_fixup_memsize(); 101 ibm44x_fixup_memsize();
102 dt_fixup_mac_addresses(ebony_mac0, ebony_mac1); 102 dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
103 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
103} 104}
104 105
105void ebony_init(void *mac0, void *mac1) 106void ebony_init(void *mac0, void *mac1)