/*
* include/linux/fsl_devices.h
*
* Definitions for any platform device related flags or structures for
* Freescale processor devices
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2004,2012 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _FSL_DEVICE_H_
#define _FSL_DEVICE_H_
#define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
PHY CLK to become stable - 10ms*/
#define FSL_USB_VER_OLD 0
#define FSL_USB_VER_1_6 1
#define FSL_USB_VER_2_2 2
#include <linux/types.h>
/*
* Some conventions on how we handle peripherals on Freescale chips
*
* unique device: a platform_device entry in fsl_plat_devs[] plus
* associated device information in its platform_data structure.
*
* A chip is described by a set of unique devices.
*
* Each sub-arch has its own master list of unique devices and
* enumerates them by enum fsl_devices in a sub-arch specific header
*
* The platform data structure is broken into two parts. The
* first is device specific information that help identify any
* unique features of a peripheral. The second is any
* information that may be defined by the board or how the device
* is connected externally of the chip.
*
* naming conventions:
* - platform data structures: <driver>_platform_data
* - platform data device flags: FSL_<driver>_DEV_<FLAG>
* - platform data board flags: FSL_<driver>_BRD_<FLAG>
*
*/
enum fsl_usb2_operating_modes {
FSL_USB2_MPH_HOST,
FSL_USB2_DR_HOST,
FSL_USB2_DR_DEVICE,
FSL_USB2_DR_OTG,
};
enum fsl_usb2_phy_modes {
FSL_USB2_PHY_NONE,
FSL_USB2_PHY_ULPI,
FSL_USB2_PHY_UTMI,
FSL_USB2_PHY_UTMI_WIDE,
FSL_USB2_PHY_SERIAL,
};
struct clk;
struct platform_device;
struct fsl_usb2_platform_data {
/* board specific information */
int controller_ver;
enum fsl_usb2_operating_modes operating_mode;
enum fsl_usb2_phy_modes phy_mode;
unsigned int port_enables;
unsigned int workaround;
int (*init)(struct platform_device *);
void (*exit)(struct platform_device *);
void __iomem *regs; /* ioremap'd register base */
struct clk *clk;
unsigned power_budget; /* hcd->power_budget */
unsigned big_endian_mmio:1;
unsigned big_endian_desc:1;
unsigned es:1; /* need USBMODE:ES */
unsigned le_setup_buf:1;
unsigned have_sysif_regs:1;
unsigned invert_drvvbus:1;
unsigned invert_pwr_fault:1;
unsigned suspended:1;
unsigned already_suspended:1;
/* register save area for suspend/resume */
u32 pm_command;
u32 pm_status;
u32 pm_intr_enable;
u32 pm_frame_index;
u32 pm_segment;
u32 pm_frame_list;
u32 pm_async_next;
u32 pm_configured_flag;
u32 pm_portsc;
u32 pm_usbgenctrl;
};
/* Flags in fsl_usb2_mph_platform_data */
#define FSL_USB2_PORT0_ENABLED 0x00000001
#define FSL_USB2_PORT1_ENABLED 0x00000002
#define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0)
struct spi_device;
struct fsl_spi_platform_data {
u32 initial_spmode; /* initial SPMODE value */
s16 bus_num;
unsigned int flags;
#define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */
#define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */
#define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */
#define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */
#define SPI_QE (1 << 4) /* SPI unit is in QE block */
/* board specific information */
u16 max_chipselect;
void (*cs_control)(struct spi_device *spi, bool on);
u32 sysclk;
};
struct mpc8xx_pcmcia_ops {
void(*hw_ctrl)(int slot, int enable);
int(*voltage_set)(int slot, int vcc, int vpp);
};
/* Returns non-zero if the current suspend operation would
* lead to a deep sleep (i.e. power removed from the core,
* instead of just the clock).
*/
#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
int fsl_deep_sleep(void);
#else
static inline int fsl_deep_sleep(void) { return 0; }
#endif
#endif /* _FSL_DEVICE_H_ */
