aboutsummaryrefslogblamecommitdiffstats
path: root/drivers/scsi/aic7xxx/aic79xx.reg
blob: be14e2ecb8f796b6bdaebe3c4926481160a238bd (plain) (tree)
1
2
3
4
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537


                                                
                                                 




































                                                                             
                                                         
























                                                                               






































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































                                                                                
                              





































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































                                                                               





















                                                        


                                 


                                 














































































                                                                             










                                                            













                                                                         















































                                                                        


                                                    



























































                                                                              



















                                                    






























































































































































































                                                                                
                             




                            
/*
 * Aic79xx register and scratch ram definitions.
 *
 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
 * Copyright (c) 2000-2002 Adaptec Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    substantially similar to the "NO WARRANTY" disclaimer below
 *    ("Disclaimer") and any redistribution must be conditioned upon
 *    including a substantially similar Disclaimer requirement for further
 *    binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES.
 *
 * $FreeBSD$
 */
VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $"

/*
 * This file is processed by the aic7xxx_asm utility for use in assembling
 * firmware for the aic79xx family of SCSI host adapters as well as to generate
 * a C header file for use in the kernel portion of the Aic79xx driver.
 */

/* Register window Modes */
#define M_DFF0		0
#define M_DFF1		1
#define M_CCHAN		2
#define M_SCSI		3
#define M_CFG		4
#define M_DST_SHIFT	4

#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
#define SET_MODE(src, dst)						\
	SET_SRC_MODE	src;						\
	SET_DST_MODE	dst;						\
	if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {			\
		mvi	MK_MODE(src, dst) call set_mode_work_around;	\
	} else {							\
		mvi	MODE_PTR, MK_MODE(src, dst);			\
	}

#define RESTORE_MODE(mode)						\
	if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {			\
		mov	mode call set_mode_work_around;			\
	} else {							\
		mov	MODE_PTR, mode;					\
	}

#define SET_SEQINTCODE(code)						\
	if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {			\
		mvi	code call set_seqint_work_around;		\
	} else {							\
		mvi	SEQINTCODE, code;				\
	}

/*
 * Mode Pointer
 * Controls which of the 5, 512byte, address spaces should be used
 * as the source and destination of any register accesses in our
 * register window.
 */
register MODE_PTR {
	address			0x000
	access_mode	RW
	field	DST_MODE	0x70
	field	SRC_MODE	0x07
	mode_pointer
}

const SRC_MODE_SHIFT	0
const DST_MODE_SHIFT	4

/*
 * Host Interrupt Status
 */
register INTSTAT {
	address			0x001
	access_mode	RW
	field	HWERRINT	0x80
	field	BRKADRINT	0x40
	field	SWTMINT		0x20
	field	PCIINT		0x10
	field	SCSIINT		0x08
	field	SEQINT		0x04
	field	CMDCMPLT	0x02
	field	SPLTINT		0x01
	mask	INT_PEND 0xFF
}

/*
 * Sequencer Interrupt Code
 */
register SEQINTCODE {
	address			0x002
	access_mode	RW
	field {
		NO_SEQINT,			/* No seqint pending. */
		BAD_PHASE,			/* unknown scsi bus phase */
		SEND_REJECT,			/* sending a message reject */
		PROTO_VIOLATION, 		/* Protocol Violation */
		NO_MATCH,			/* no cmd match for reconnect */
		IGN_WIDE_RES,			/* Complex IGN Wide Res Msg */
		PDATA_REINIT,			/*
						 * Returned to data phase
						 * that requires data
						 * transfer pointers to be
						 * recalculated from the
						 * transfer residual.
						 */
		HOST_MSG_LOOP,			/*
						 * The bus is ready for the
						 * host to perform another
						 * message transaction.  This
						 * mechanism is used for things
						 * like sync/wide negotiation
						 * that require a kernel based
						 * message state engine.
						 */
		BAD_STATUS,			/* Bad status from target */
		DATA_OVERRUN,			/*
						 * Target attempted to write
						 * beyond the bounds of its
						 * command.
						 */
		MKMSG_FAILED,			/*
						 * Target completed command
						 * without honoring our ATN
						 * request to issue a message. 
						 */
		MISSED_BUSFREE,			/*
						 * The sequencer never saw
						 * the bus go free after
						 * either a command complete
						 * or disconnect message.
						 */
		DUMP_CARD_STATE,
		ILLEGAL_PHASE,
		INVALID_SEQINT,
		CFG4ISTAT_INTR,
		STATUS_OVERRUN,
		CFG4OVERRUN,
		ENTERING_NONPACK,
		TASKMGMT_FUNC_COMPLETE,		/*
						 * Task management function
						 * request completed with
						 * an expected busfree.
						 */
		TASKMGMT_CMD_CMPLT_OKAY,	/*
						 * A command with a non-zero
						 * task management function
						 * has completed via the normal
						 * command completion method
						 * for commands with a zero
						 * task management function.
						 * This happens when an attempt
						 * to abort a command loses
						 * the race for the command to
						 * complete normally.
						 */
		TRACEPOINT0,
		TRACEPOINT1,
		TRACEPOINT2,
		TRACEPOINT3,
		SAW_HWERR,
		BAD_SCB_STATUS
	}
}

/*
 * Clear Host Interrupt
 */
register CLRINT {
	address			0x003
	access_mode	WO
	field	CLRHWERRINT	0x80 /* Rev B or greater */
	field	CLRBRKADRINT	0x40
	field	CLRSWTMINT	0x20
	field	CLRPCIINT	0x10
	field	CLRSCSIINT	0x08
	field	CLRSEQINT	0x04
	field	CLRCMDINT	0x02
	field	CLRSPLTINT	0x01
}

/*
 * Error Register
 */
register ERROR {
	address			0x004
	access_mode	RO
	field	CIOPARERR	0x80
	field	CIOACCESFAIL	0x40 /* Rev B or greater */
	field	MPARERR		0x20
	field	DPARERR		0x10
	field	SQPARERR	0x08
	field	ILLOPCODE	0x04
	field	DSCTMOUT	0x02
}

/*
 * Clear Error
 */
register CLRERR {
	address			0x004
	access_mode 	WO
	field	CLRCIOPARERR	0x80
	field	CLRCIOACCESFAIL	0x40 /* Rev B or greater */
	field	CLRMPARERR	0x20
	field	CLRDPARERR	0x10
	field	CLRSQPARERR	0x08
	field	CLRILLOPCODE	0x04
	field	CLRDSCTMOUT	0x02
}

/*
 * Host Control Register
 * Overall host control of the device.
 */
register HCNTRL {
	address			0x005
	access_mode	RW
	field	SEQ_RESET	0x80 /* Rev B or greater */
	field	POWRDN		0x40
	field	SWINT		0x10
	field	SWTIMER_START_B	0x08 /* Rev B or greater */
	field	PAUSE		0x04
	field	INTEN		0x02
	field	CHIPRST		0x01
	field	CHIPRSTACK	0x01
}

/*
 * Host New SCB Queue Offset
 */
register HNSCB_QOFF {
	address			0x006
	access_mode	RW
	size		2
}

/*
 * Host Empty SCB Queue Offset
 */
register HESCB_QOFF {
	address			0x008
	access_mode	RW
}

/*
 * Host Mailbox
 */
register HS_MAILBOX {
	address			0x00B
	access_mode	RW
	mask	HOST_TQINPOS	0x80	/* Boundary at either 0 or 128 */
	mask	ENINT_COALESCE	0x40	/* Perform interrupt coalescing */
}

/*
 * Sequencer Interupt Status
 */
register SEQINTSTAT {
	address			0x00C
	access_mode	RO
	field	SEQ_SWTMRTO	0x10
	field	SEQ_SEQINT	0x08
	field	SEQ_SCSIINT	0x04
	field	SEQ_PCIINT	0x02
	field	SEQ_SPLTINT	0x01
}

/*
 * Clear SEQ Interrupt
 */
register CLRSEQINTSTAT {
	address			0x00C
	access_mode	WO
	field	CLRSEQ_SWTMRTO	0x10
	field	CLRSEQ_SEQINT	0x08
	field	CLRSEQ_SCSIINT	0x04
	field	CLRSEQ_PCIINT	0x02
	field	CLRSEQ_SPLTINT	0x01
}

/*
 * Software Timer
 */
register SWTIMER {
	address			0x00E
	access_mode	RW
	size		2
}

/*
 * SEQ New SCB Queue Offset
 */
register SNSCB_QOFF {
	address			0x010
	access_mode	RW
	size		2
	modes		M_CCHAN
}

/*
 * SEQ Empty SCB Queue Offset
 */
register SESCB_QOFF {
	address			0x012
	access_mode	RW
	modes		M_CCHAN
}

/*
 * SEQ Done SCB Queue Offset
 */
register SDSCB_QOFF {
	address			0x014
	access_mode	RW
	modes		M_CCHAN
	size		2
}

/*
 * Queue Offset Control & Status
 */
register QOFF_CTLSTA {
	address			0x016
	access_mode	RW
	modes		M_CCHAN
	field	EMPTY_SCB_AVAIL	0x80
	field	NEW_SCB_AVAIL	0x40
	field	SDSCB_ROLLOVR	0x20
	field	HS_MAILBOX_ACT	0x10
	field	SCB_QSIZE	0x0F {
		SCB_QSIZE_4,
		SCB_QSIZE_8,
		SCB_QSIZE_16,
		SCB_QSIZE_32,
		SCB_QSIZE_64,
		SCB_QSIZE_128,
		SCB_QSIZE_256,
		SCB_QSIZE_512,
		SCB_QSIZE_1024,
		SCB_QSIZE_2048,
		SCB_QSIZE_4096,
		SCB_QSIZE_8192,
		SCB_QSIZE_16384
	}
}

/*
 * Interrupt Control
 */
register INTCTL {
	address			0x018
	access_mode	RW
	field	SWTMINTMASK	0x80
	field	SWTMINTEN	0x40
	field	SWTIMER_START	0x20
	field	AUTOCLRCMDINT	0x10
	field	PCIINTEN	0x08
	field	SCSIINTEN	0x04
	field	SEQINTEN	0x02
	field	SPLTINTEN	0x01
}

/*
 * Data FIFO Control
 */
register DFCNTRL {
	address			0x019
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	PRELOADEN	0x80
	field	SCSIENWRDIS	0x40	/* Rev B only. */
	field	SCSIEN		0x20
	field	SCSIENACK	0x20
	field	HDMAEN		0x08
	field	HDMAENACK	0x08
	field	DIRECTION	0x04
	field	DIRECTIONACK	0x04
	field	FIFOFLUSH	0x02
	field	FIFOFLUSHACK	0x02
	field	DIRECTIONEN	0x01
}

/*
 * Device Space Command 0
 */
register DSCOMMAND0 {
	address			0x019
	access_mode	RW
	modes		M_CFG
	field	CACHETHEN	0x80	/* Cache Threshold enable */
	field	DPARCKEN	0x40	/* Data Parity Check Enable */
	field	MPARCKEN	0x20	/* Memory Parity Check Enable */
	field	EXTREQLCK	0x10	/* External Request Lock */
	field	DISABLE_TWATE	0x02	/* Rev B or greater */
	field	CIOPARCKEN	0x01	/* Internal bus parity error enable */
}

/*
 * Data FIFO Status
 */
register DFSTATUS {
	address			0x01A
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	PRELOAD_AVAIL		0x80
	field	PKT_PRELOAD_AVAIL	0x40
	field	MREQPEND		0x10
	field	HDONE			0x08
	field	DFTHRESH		0x04
	field	FIFOFULL		0x02
	field	FIFOEMP			0x01
}

/*
 * S/G Cache Pointer
 */
register SG_CACHE_PRE {
	address			0x01B
	access_mode	WO
	modes		M_DFF0, M_DFF1
	field	SG_ADDR_MASK	0xf8
	field	ODD_SEG		0x04
	field	LAST_SEG	0x02
}

register SG_CACHE_SHADOW {
	address			0x01B
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	SG_ADDR_MASK	0xf8
	field	ODD_SEG		0x04
	field	LAST_SEG	0x02
	field	LAST_SEG_DONE	0x01
}

/*
 * Arbiter Control
 */
register ARBCTL {
	address			0x01B
	access_mode	RW
	modes		M_CFG
	field	RESET_HARB	0x80
	field	RETRY_SWEN	0x08
	field	USE_TIME	0x07
}

/*
 * Data Channel Host Address
 */
register HADDR {
	address			0x070
	access_mode	RW
	size		8
	modes		M_DFF0, M_DFF1
}

/*
 * Host Overlay DMA Address
 */
register HODMAADR {
	address			0x070
	access_mode	RW
	size		8
	modes		M_SCSI
}

/*
 * PCI PLL Delay.
 */
register PLLDELAY {
	address			0x070
	access_mode	RW
	size		1
	modes		M_CFG
	field	SPLIT_DROP_REQ	0x80
}

/*
 * Data Channel Host Count
 */
register HCNT {
	address			0x078
	access_mode	RW
	size		3
	modes		M_DFF0, M_DFF1
}

/*
 * Host Overlay DMA Count
 */
register HODMACNT {
	address			0x078
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Host Overlay DMA Enable
 */
register HODMAEN {
	address			0x07A
	access_mode	RW
	modes		M_SCSI
}

/*
 * Scatter/Gather Host Address
 */
register SGHADDR {
	address			0x07C
	access_mode	RW
	size		8
	modes		M_DFF0, M_DFF1
}

/*
 * SCB Host Address
 */
register SCBHADDR {
	address			0x07C
	access_mode	RW
	size		8
	modes		M_CCHAN
}

/*
 * Scatter/Gather Host Count
 */
register SGHCNT {
	address			0x084
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * SCB Host Count
 */
register SCBHCNT {
	address			0x084
	access_mode	RW
	modes		M_CCHAN
}

/*
 * Data FIFO Threshold
 */
register DFF_THRSH {
	address			0x088
	access_mode	RW
	modes		M_CFG
	field	WR_DFTHRSH	0x70 {
		WR_DFTHRSH_MIN,
		WR_DFTHRSH_25,
		WR_DFTHRSH_50,
		WR_DFTHRSH_63,
		WR_DFTHRSH_75,
		WR_DFTHRSH_85,
		WR_DFTHRSH_90,
		WR_DFTHRSH_MAX
	}
	field	RD_DFTHRSH	0x07 {
		RD_DFTHRSH_MIN,
		RD_DFTHRSH_25,
		RD_DFTHRSH_50,
		RD_DFTHRSH_63,
		RD_DFTHRSH_75,
		RD_DFTHRSH_85,
		RD_DFTHRSH_90,
		RD_DFTHRSH_MAX
	}
}

/*
 * ROM Address
 */
register ROMADDR {
	address			0x08A
	access_mode	RW
	size		3
}

/*
 * ROM Control
 */
register ROMCNTRL {
	address			0x08D
	access_mode	RW
	field	ROMOP		0xE0
	field	ROMSPD		0x18
	field	REPEAT		0x02
	field	RDY		0x01
}

/*
 * ROM Data
 */
register ROMDATA {
	address			0x08E
	access_mode	RW
}

/*
 * Data Channel Receive Message 0
 */
register DCHRXMSG0 {
	address			0x090
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field		CDNUM	0xF8
	field		CFNUM	0x07
}

/*
 * CMC Recieve Message 0
 */
register CMCRXMSG0 {
	address			0x090
	access_mode	RO
	modes		M_CCHAN
	field		CDNUM	0xF8
	field		CFNUM	0x07
}

/*
 * Overlay Recieve Message 0
 */
register OVLYRXMSG0 {
	address			0x090
	access_mode	RO
	modes		M_SCSI
	field		CDNUM	0xF8
	field		CFNUM	0x07
}

/*
 * Relaxed Order Enable
 */
register ROENABLE {
	address			0x090
	access_mode	RW
	modes		M_CFG
	field	MSIROEN		0x20
	field	OVLYROEN	0x10
	field	CMCROEN		0x08
	field	SGROEN		0x04
	field	DCH1ROEN	0x02
	field	DCH0ROEN	0x01
}

/*
 * Data Channel Receive Message 1
 */
register DCHRXMSG1 {
	address			0x091
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	CBNUM		0xFF
}

/*
 * CMC Recieve Message 1
 */
register CMCRXMSG1 {
	address			0x091
	access_mode	RO
	modes		M_CCHAN
	field	CBNUM		0xFF
}

/*
 * Overlay Recieve Message 1
 */
register OVLYRXMSG1 {
	address			0x091
	access_mode	RO
	modes		M_SCSI
	field	CBNUM		0xFF
}

/*
 * No Snoop Enable
 */
register NSENABLE {
	address			0x091
	access_mode	RW
	modes		M_CFG
	field	MSINSEN		0x20
	field	OVLYNSEN	0x10
	field	CMCNSEN		0x08
	field	SGNSEN		0x04
	field	DCH1NSEN	0x02
	field	DCH0NSEN	0x01
}

/*
 * Data Channel Receive Message 2
 */
register DCHRXMSG2 {
	address			0x092
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	MINDEX		0xFF
}

/*
 * CMC Recieve Message 2
 */
register CMCRXMSG2 {
	address			0x092
	access_mode	RO
	modes		M_CCHAN
	field	MINDEX		0xFF
}

/*
 * Overlay Recieve Message 2
 */
register OVLYRXMSG2 {
	address			0x092
	access_mode	RO
	modes		M_SCSI
	field	MINDEX		0xFF
}

/*
 * Outstanding Split Transactions
 */
register OST {
	address			0x092
	access_mode	RW
	modes		M_CFG
}

/*
 * Data Channel Receive Message 3
 */
register DCHRXMSG3 {
	address			0x093
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	MCLASS		0x0F
}

/*
 * CMC Recieve Message 3
 */
register CMCRXMSG3 {
	address			0x093
	access_mode	RO
	modes		M_CCHAN
	field	MCLASS		0x0F
}

/*
 * Overlay Recieve Message 3
 */
register OVLYRXMSG3 {
	address			0x093
	access_mode	RO
	modes		M_SCSI
	field	MCLASS		0x0F
}

/*
 * PCI-X Control
 */
register PCIXCTL {
	address			0x093
	access_mode	RW
	modes		M_CFG
	field	SERRPULSE	0x80
	field	UNEXPSCIEN	0x20
	field	SPLTSMADIS	0x10
	field	SPLTSTADIS	0x08
	field	SRSPDPEEN	0x04
	field	TSCSERREN	0x02
	field	CMPABCDIS	0x01
}

/*
 * CMC Sequencer Byte Count
 */
register CMCSEQBCNT {
	address			0x094
	access_mode	RO
	modes		M_CCHAN
}

/*
 * Overlay Sequencer Byte Count
 */
register OVLYSEQBCNT {
	address			0x094
	access_mode	RO
	modes		M_SCSI
}

/*
 * Data Channel Sequencer Byte Count
 */
register DCHSEQBCNT {
	address			0x094
	access_mode	RO
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * Data Channel Split Status 0
 */
register DCHSPLTSTAT0 {
	address			0x096
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	STAETERM	0x80
	field	SCBCERR		0x40
	field	SCADERR		0x20
	field	SCDATBUCKET	0x10
	field	CNTNOTCMPLT	0x08
	field	RXOVRUN		0x04
	field	RXSCEMSG	0x02
	field	RXSPLTRSP	0x01
}

/*
 * CMC Split Status 0
 */
register CMCSPLTSTAT0 {
	address			0x096
	access_mode	RW
	modes		M_CCHAN
	field	STAETERM	0x80
	field	SCBCERR		0x40
	field	SCADERR		0x20
	field	SCDATBUCKET	0x10
	field	CNTNOTCMPLT	0x08
	field	RXOVRUN		0x04
	field	RXSCEMSG	0x02
	field	RXSPLTRSP	0x01
}

/*
 * Overlay Split Status 0
 */
register OVLYSPLTSTAT0 {
	address			0x096
	access_mode	RW
	modes		M_SCSI
	field	STAETERM	0x80
	field	SCBCERR		0x40
	field	SCADERR		0x20
	field	SCDATBUCKET	0x10
	field	CNTNOTCMPLT	0x08
	field	RXOVRUN		0x04
	field	RXSCEMSG	0x02
	field	RXSPLTRSP	0x01
}

/*
 * Data Channel Split Status 1
 */
register DCHSPLTSTAT1 {
	address			0x097
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	RXDATABUCKET	0x01
}

/*
 * CMC Split Status 1
 */
register CMCSPLTSTAT1 {
	address			0x097
	access_mode	RW
	modes		M_CCHAN
	field	RXDATABUCKET	0x01
}

/*
 * Overlay Split Status 1
 */
register OVLYSPLTSTAT1 {
	address			0x097
	access_mode	RW
	modes		M_SCSI
	field	RXDATABUCKET	0x01
}

/*
 * S/G Receive Message 0
 */
register SGRXMSG0 {
	address			0x098
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field		CDNUM	0xF8
	field		CFNUM	0x07
}

/*
 * S/G Receive Message 1
 */
register SGRXMSG1 {
	address			0x099
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	CBNUM		0xFF
}

/*
 * S/G Receive Message 2
 */
register SGRXMSG2 {
	address			0x09A
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	MINDEX		0xFF
}

/*
 * S/G Receive Message 3
 */
register SGRXMSG3 {
	address			0x09B
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	MCLASS		0x0F
}

/*
 * Slave Split Out Address 0
 */
register SLVSPLTOUTADR0 {
	address			0x098
	access_mode	RO
	modes		M_SCSI
	field	LOWER_ADDR	0x7F
}

/*
 * Slave Split Out Address 1
 */
register SLVSPLTOUTADR1 {
	address			0x099
	access_mode	RO
	modes		M_SCSI
	field	REQ_DNUM	0xF8
	field	REQ_FNUM	0x07
}

/*
 * Slave Split Out Address 2
 */
register SLVSPLTOUTADR2 {
	address			0x09A
	access_mode	RO
	modes		M_SCSI
	field	REQ_BNUM	0xFF
}

/*
 * Slave Split Out Address 3
 */
register SLVSPLTOUTADR3 {
	address			0x09B
	access_mode	RO
	modes		M_SCSI
	field	RLXORD		020
	field	TAG_NUM		0x1F
}

/*
 * SG Sequencer Byte Count
 */
register SGSEQBCNT {
	address			0x09C
	access_mode	RO
	modes		M_DFF0, M_DFF1
}

/*
 * Slave Split Out Attribute 0
 */
register SLVSPLTOUTATTR0 {
	address			0x09C
	access_mode	RO
	modes		M_SCSI
	field	LOWER_BCNT	0xFF
}

/*
 * Slave Split Out Attribute 1
 */
register SLVSPLTOUTATTR1 {
	address			0x09D
	access_mode	RO
	modes		M_SCSI
	field	CMPLT_DNUM	0xF8
	field	CMPLT_FNUM	0x07
}

/*
 * Slave Split Out Attribute 2
 */
register SLVSPLTOUTATTR2 {
	address			0x09E
	access_mode	RO
	size		2
	modes		M_SCSI
	field	CMPLT_BNUM	0xFF
}
/*
 * S/G Split Status 0
 */
register SGSPLTSTAT0 {
	address			0x09E
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	STAETERM	0x80
	field	SCBCERR		0x40
	field	SCADERR		0x20
	field	SCDATBUCKET	0x10
	field	CNTNOTCMPLT	0x08
	field	RXOVRUN		0x04
	field	RXSCEMSG	0x02
	field	RXSPLTRSP	0x01
}

/*
 * S/G Split Status 1
 */
register SGSPLTSTAT1 {
	address			0x09F
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	RXDATABUCKET	0x01
}

/*
 * Special Function
 */
register SFUNCT {
	address			0x09f
	access_mode	RW
	modes		M_CFG
	field	TEST_GROUP	0xF0
	field	TEST_NUM	0x0F
}

/*
 * Data FIFO 0 PCI Status 
 */
register DF0PCISTAT {
	address			0x0A0
	access_mode	RW
	modes		M_CFG
	field	DPE		0x80
	field	SSE		0x40
	field	RMA		0x20
	field	RTA		0x10
	field	SCAAPERR	0x08
	field	RDPERR		0x04
	field	TWATERR		0x02
	field	DPR		0x01
}

/*
 * Data FIFO 1 PCI Status 
 */
register DF1PCISTAT {
	address			0x0A1
	access_mode	RW
	modes		M_CFG
	field	DPE		0x80
	field	SSE		0x40
	field	RMA		0x20
	field	RTA		0x10
	field	SCAAPERR	0x08
	field	RDPERR		0x04
	field	TWATERR		0x02
	field	DPR		0x01
}

/*
 * S/G PCI Status 
 */
register SGPCISTAT {
	address			0x0A2
	access_mode	RW
	modes		M_CFG
	field	DPE		0x80
	field	SSE		0x40
	field	RMA		0x20
	field	RTA		0x10
	field	SCAAPERR	0x08
	field	RDPERR		0x04
	field	DPR		0x01
}

/*
 * CMC PCI Status 
 */
register CMCPCISTAT {
	address			0x0A3
	access_mode	RW
	modes		M_CFG
	field	DPE		0x80
	field	SSE		0x40
	field	RMA		0x20
	field	RTA		0x10
	field	SCAAPERR	0x08
	field	RDPERR		0x04
	field	TWATERR		0x02
	field	DPR		0x01
}

/*
 * Overlay PCI Status 
 */
register OVLYPCISTAT {
	address			0x0A4
	access_mode	RW
	modes		M_CFG
	field	DPE		0x80
	field	SSE		0x40
	field	RMA		0x20
	field	RTA		0x10
	field	SCAAPERR	0x08
	field	RDPERR		0x04
	field	DPR		0x01
}

/*
 * PCI Status for MSI Master DMA Transfer
 */
register MSIPCISTAT {
	address			0x0A6
	access_mode	RW
	modes		M_CFG
	field	SSE		0x40
	field	RMA		0x20
	field	RTA		0x10
	field	CLRPENDMSI	0x08
	field	TWATERR		0x02
	field	DPR		0x01
}

/*
 * PCI Status for Target
 */
register TARGPCISTAT {
	address			0x0A7
	access_mode	RW
	modes		M_CFG
	field	DPE		0x80
	field	SSE		0x40
	field	STA		0x08
	field	TWATERR		0x02
}

/*
 * LQ Packet In
 * The last LQ Packet recieved
 */
register LQIN {
	address			0x020
	access_mode	RW
	size		20
	modes		M_DFF0, M_DFF1, M_SCSI
}

/*
 * SCB Type Pointer
 * SCB offset for Target Mode SCB type information
 */
register TYPEPTR {
	address			0x020
	access_mode	RW
	modes		M_CFG
}

/*
 * Queue Tag Pointer
 * SCB offset to the Two Byte tag identifier used for target mode.
 */
register TAGPTR {
	address			0x021
	access_mode	RW
	modes		M_CFG
}

/*
 * Logical Unit Number Pointer
 * SCB offset to the LSB (little endian) of the lun field.
 */
register LUNPTR {
	address			0x022
	access_mode	RW
	modes		M_CFG
}

/*
 * Data Length Pointer
 * SCB offset for the 4 byte data length field in target mode.
 */
register DATALENPTR {
	address			0x023
	access_mode	RW
	modes		M_CFG
}

/*
 * Status Length Pointer
 * SCB offset to the two byte status field in target SCBs.
 */
register STATLENPTR {
	address			0x024
	access_mode	RW
	modes		M_CFG
}

/*
 * Command Length Pointer
 * Scb offset for the CDB length field in initiator SCBs.
 */
register CMDLENPTR {
	address			0x025
	access_mode	RW
	modes		M_CFG
}

/*
 * Task Attribute Pointer
 * Scb offset for the byte field specifying the attribute byte
 * to be used in command packets.
 */ 
register ATTRPTR {
	address			0x026
	access_mode	RW
	modes		M_CFG
}

/*
 * Task Management Flags Pointer
 * Scb offset for the byte field specifying the attribute flags
 * byte to be used in command packets.
 */ 
register FLAGPTR {
	address			0x027
	access_mode	RW
	modes		M_CFG
}

/*
 * Command Pointer
 * Scb offset for the first byte in the CDB for initiator SCBs.
 */
register CMDPTR {
	address			0x028
	access_mode	RW
	modes		M_CFG
}

/*
 * Queue Next Pointer
 * Scb offset for the 2 byte "next scb link".
 */
register QNEXTPTR {
	address			0x029
	access_mode	RW
	modes		M_CFG
}

/*
 * SCSI ID Pointer
 * Scb offset to the value to place in the SCSIID register
 * during target mode connections.
 */
register IDPTR {
	address			0x02A
	access_mode	RW
	modes		M_CFG
}

/*
 * Command Aborted Byte Pointer
 * Offset to the SCB flags field that includes the
 * "SCB aborted" status bit.
 */
register ABRTBYTEPTR {
	address			0x02B
	access_mode	RW
	modes		M_CFG
}

/*
 * Command Aborted Bit Pointer
 * Bit offset in the SCB flags field for "SCB aborted" status.
 */
register ABRTBITPTR {
	address			0x02C
	access_mode	RW
	modes		M_CFG
}

/*
 * Rev B or greater.
 */
register MAXCMDBYTES {
	address			0x02D
	access_mode	RW
	modes		M_CFG
}

/*
 * Rev B or greater.
 */
register MAXCMD2RCV {
	address			0x02E
	access_mode	RW
	modes		M_CFG
}

/*
 * Rev B or greater.
 */
register SHORTTHRESH {
	address			0x02F
	access_mode	RW
	modes		M_CFG
}

/*
 * Logical Unit Number Length
 * The length, in bytes, of the SCB lun field.
 */
register LUNLEN {
	address			0x030
	access_mode	RW
	modes		M_CFG
	mask		ILUNLEN	0x0F
	mask		TLUNLEN	0xF0
}
const LUNLEN_SINGLE_LEVEL_LUN 0xF

/*
 * CDB Limit
 * The size, in bytes, of the embedded CDB field in initator SCBs.
 */
register CDBLIMIT {
	address			0x031
	access_mode	RW
	modes		M_CFG
}

/*
 * Maximum Commands
 * The maximum number of commands to issue during a
 * single packetized connection.
 */
register MAXCMD {
	address			0x032
	access_mode	RW
	modes		M_CFG
}

/*
 * Maximum Command Counter
 * The number of commands already sent during this connection
 */
register MAXCMDCNT {
	address			0x033
	access_mode	RW
	modes		M_CFG
}

/*
 * LQ Packet Reserved Bytes
 * The bytes to be sent in the currently reserved fileds
 * of all LQ packets.
 */
register LQRSVD01 {
	address			0x034
	access_mode	RW
	modes		M_SCSI
}
register LQRSVD16 {
	address			0x035
	access_mode	RW
	modes		M_SCSI
}
register LQRSVD17 {
	address			0x036
	access_mode	RW
	modes		M_SCSI
}

/*
 * Command Reserved 0
 * The byte to be sent for the reserved byte 0 of
 * outgoing command packets.
 */
register CMDRSVD0 {
	address			0x037
	access_mode	RW
	modes		M_CFG
}

/*
 * LQ Manager Control 0
 */
register LQCTL0 {
	address			0x038
	access_mode	RW
	modes		M_CFG
	field	LQITARGCLT	0xC0
	field	LQIINITGCLT	0x30
	field	LQ0TARGCLT	0x0C
	field	LQ0INITGCLT	0x03
}

/*
 * LQ Manager Control 1
 */
register LQCTL1 {
	address			0x038
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	PCI2PCI		0x04
	field	SINGLECMD	0x02
	field	ABORTPENDING	0x01
}

/*
 * LQ Manager Control 2
 */
register LQCTL2 {
	address			0x039
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	LQIRETRY	0x80
	field	LQICONTINUE	0x40
	field	LQITOIDLE	0x20
	field	LQIPAUSE	0x10
	field	LQORETRY	0x08
	field	LQOCONTINUE	0x04
	field	LQOTOIDLE	0x02
	field	LQOPAUSE	0x01
}

/*
 * SCSI RAM BIST0
 */
register SCSBIST0 {
	address			0x039
	access_mode	RW
	modes		M_CFG
	field	GSBISTERR	0x40
	field	GSBISTDONE	0x20
	field	GSBISTRUN	0x10
	field	OSBISTERR	0x04
	field	OSBISTDONE	0x02
	field	OSBISTRUN	0x01
}

/*
 * SCSI Sequence Control0
 */
register SCSISEQ0 {
	address			0x03A
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	TEMODEO		0x80
	field	ENSELO		0x40
	field	ENARBO		0x20
	field	FORCEBUSFREE	0x10
	field	SCSIRSTO	0x01
}

/*
 * SCSI RAM BIST 1
 */
register SCSBIST1 {
	address			0x03A
	access_mode	RW
	modes		M_CFG
	field	NTBISTERR	0x04
	field	NTBISTDONE	0x02
	field	NTBISTRUN	0x01
}

/*
 * SCSI Sequence Control 1
 */
register SCSISEQ1 {
	address			0x03B
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	MANUALCTL	0x40
	field	ENSELI		0x20
	field	ENRSELI		0x10
	field	MANUALP		0x0C
	field	ENAUTOATNP	0x02
	field	ALTSTIM		0x01
}

/*
 * SCSI Transfer Control 0
 */
register SXFRCTL0 {
	address			0x03C
	access_mode	RW
	modes		M_SCSI
	field	DFON		0x80
	field	DFPEXP		0x40
	field	BIOSCANCELEN	0x10
	field	SPIOEN		0x08
}

/*
 * SCSI Transfer Control 1
 */
register SXFRCTL1 {
	address			0x03D
	access_mode	RW
	modes		M_SCSI
	field	BITBUCKET	0x80
	field	ENSACHK		0x40
	field	ENSPCHK		0x20
	field	STIMESEL	0x18
	field	ENSTIMER	0x04
	field	ACTNEGEN	0x02
	field	STPWEN		0x01
}

/*
 * SCSI Transfer Control 2
 */
register SXFRCTL2 {
	address			0x03E
	access_mode	RW
	modes		M_SCSI
	field	AUTORSTDIS	0x10
	field	CMDDMAEN	0x08
	field	ASU		0x07
}

/*
 * SCSI Bus Initiator IDs
 * Bitmask of observed initiators on the bus.
 */
register BUSINITID {
	address			0x03C
	access_mode	RW
	modes		M_CFG
	size		2
}

/*
 * Data Length Counters
 * Packet byte counter.
 */
register DLCOUNT {
	address			0x03C
	access_mode	RW
	modes		M_DFF0, M_DFF1
	size		3
}

/*
 * Data FIFO Status
 */
register DFFSTAT {
	address			0x03F
	access_mode	RW
	modes		M_SCSI
	field	FIFO1FREE	0x20
	field	FIFO0FREE	0x10
	/*
	 * On the B, this enum only works
	 * in the read direction.  For writes,
	 * you must use the B version of the
	 * CURRFIFO_0 definition which is defined
	 * as a constant outside of this register
	 * definition to avoid confusing the
	 * register pretty printing code.
	 */
	enum	CURRFIFO	0x03 {
		CURRFIFO_0,
		CURRFIFO_1,
		CURRFIFO_NONE	0x3
	}
}

const B_CURRFIFO_0 0x2

/*
 * SCSI Bus Target IDs
 * Bitmask of observed targets on the bus.
 */
register BUSTARGID {
	address			0x03E
	access_mode	RW
	modes		M_CFG
	size		2
}

/*
 * SCSI Control Signal Out
 */
register SCSISIGO {
	address			0x040
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CDO		0x80
	field	IOO		0x40
	field	MSGO		0x20
	field	ATNO		0x10
	field	SELO		0x08
	field	BSYO		0x04
	field	REQO		0x02
	field	ACKO		0x01
/*
 * Possible phases to write into SCSISIG0
 */
	enum	PHASE_MASK  CDO|IOO|MSGO {
		P_DATAOUT	0x0,
		P_DATAIN	IOO,
		P_DATAOUT_DT	P_DATAOUT|MSGO,
		P_DATAIN_DT	P_DATAIN|MSGO,
		P_COMMAND	CDO,
		P_MESGOUT	CDO|MSGO,
		P_STATUS	CDO|IOO,
		P_MESGIN	CDO|IOO|MSGO
	}
}

register SCSISIGI {
	address			0x041
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CDI		0x80
	field	IOI		0x40
	field	MSGI		0x20
	field	ATNI		0x10
	field	SELI		0x08
	field	BSYI		0x04
	field	REQI		0x02
	field	ACKI		0x01
/*
 * Possible phases in SCSISIGI
 */
	enum	PHASE_MASK  CDO|IOO|MSGO {
		P_DATAOUT	0x0,
		P_DATAIN	IOO,
		P_DATAOUT_DT	P_DATAOUT|MSGO,
		P_DATAIN_DT	P_DATAIN|MSGO,
		P_COMMAND	CDO,
		P_MESGOUT	CDO|MSGO,
		P_STATUS	CDO|IOO,
		P_MESGIN	CDO|IOO|MSGO
	}
}

/*
 * Multiple Target IDs
 * Bitmask of ids to respond as a target.
 */
register MULTARGID {
	address			0x040
	access_mode	RW
	modes		M_CFG
	size		2
}

/*
 * SCSI Phase
 */
register SCSIPHASE {
	address			0x042
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	STATUS_PHASE	0x20
	field	COMMAND_PHASE	0x10
	field	MSG_IN_PHASE	0x08
	field	MSG_OUT_PHASE	0x04
	field	DATA_PHASE_MASK	0x03 {
		DATA_OUT_PHASE	0x01,
		DATA_IN_PHASE	0x02
	}
}

/*
 * SCSI Data 0 Image
 */
register SCSIDAT0_IMG {
	address			0x043
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
}

/*
 * SCSI Latched Data
 */
register SCSIDAT {
	address			0x044
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	size		2
}

/*
 * SCSI Data Bus
 */
register SCSIBUS {
	address			0x046
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	size		2
}

/*
 * Target ID In
 */
register TARGIDIN {
	address			0x048
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLKOUT		0x80
	field	TARGID		0x0F
}

/*
 * Selection/Reselection ID
 * Upper four bits are the device id.  The ONEBIT is set when the re/selecting
 * device did not set its own ID.
 */
register SELID {
	address			0x049
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	SELID_MASK	0xf0
	field	ONEBIT		0x08
}

/*
 * SCSI Block Control
 * Controls Bus type and channel selection.  SELWIDE allows for the
 * coexistence of 8bit and 16bit devices on a wide bus.
 */
register SBLKCTL {
	address			0x04A
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	DIAGLEDEN	0x80
	field	DIAGLEDON	0x40
	field	ENAB40		0x08	/* LVD transceiver active */
	field	ENAB20		0x04	/* SE/HVD transceiver active */
	field	SELWIDE		0x02
}

/*
 * Option Mode
 */
register OPTIONMODE {
	address			0x04A
	access_mode	RW
	modes		M_CFG
	field	BIOSCANCTL		0x80
	field	AUTOACKEN		0x40
	field	BIASCANCTL		0x20
	field	BUSFREEREV		0x10
	field	ENDGFORMCHK		0x04
	field	AUTO_MSGOUT_DE		0x02
	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE
}

/*
 * SCSI Status 0
 */
register SSTAT0	{
	address			0x04B
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	TARGET		0x80	/* Board acting as target */
	field	SELDO		0x40	/* Selection Done */
	field	SELDI		0x20	/* Board has been selected */
	field	SELINGO		0x10	/* Selection In Progress */
	field	IOERR		0x08	/* LVD Tranceiver mode changed */
	field	OVERRUN		0x04	/* SCSI Offset overrun detected */
	field	SPIORDY		0x02	/* SCSI PIO Ready */
	field	ARBDO		0x01	/* Arbitration Done Out */
}

/*
 * Clear SCSI Interrupt 0
 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
 */
register CLRSINT0 {
	address			0x04B
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRSELDO	0x40
	field	CLRSELDI	0x20
	field	CLRSELINGO	0x10
	field	CLRIOERR	0x08
	field	CLROVERRUN	0x04
	field	CLRSPIORDY	0x02
	field	CLRARBDO	0x01
}

/*
 * SCSI Interrupt Mode 0
 * Setting any bit will enable the corresponding function
 * in SIMODE0 to interrupt via the IRQ pin.
 */
register SIMODE0 {
	address			0x04B
	access_mode	RW
	modes		M_CFG
	field	ENSELDO		0x40
	field	ENSELDI		0x20
	field	ENSELINGO	0x10
	field	ENIOERR		0x08
	field	ENOVERRUN	0x04
	field	ENSPIORDY	0x02
	field	ENARBDO		0x01
}

/*
 * SCSI Status 1
 */
register SSTAT1 {
	address			0x04C
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	SELTO		0x80
	field	ATNTARG 	0x40
	field	SCSIRSTI	0x20
	field	PHASEMIS	0x10
	field	BUSFREE		0x08
	field	SCSIPERR	0x04
	field	STRB2FAST	0x02
	field	REQINIT		0x01
}

/*
 * Clear SCSI Interrupt 1
 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 */
register CLRSINT1 {
	address			0x04C
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRSELTIMEO	0x80
	field	CLRATNO		0x40
	field	CLRSCSIRSTI	0x20
	field	CLRBUSFREE	0x08
	field	CLRSCSIPERR	0x04
	field	CLRSTRB2FAST	0x02
	field	CLRREQINIT	0x01
}

/*
 * SCSI Status 2
 */
register SSTAT2 {
	address			0x04d
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	BUSFREETIME	0xc0 {
		BUSFREE_LQO	0x40,
		BUSFREE_DFF0	0x80,
		BUSFREE_DFF1	0xC0
	}
	field	NONPACKREQ	0x20
	field	EXP_ACTIVE	0x10	/* SCSI Expander Active */
	field	BSYX		0x08	/* Busy Expander */
	field	WIDE_RES	0x04	/* Modes 0 and 1 only */
	field	SDONE		0x02	/* Modes 0 and 1 only */
	field	DMADONE		0x01	/* Modes 0 and 1 only */
}

/*
 * Clear SCSI Interrupt 2
 */
register CLRSINT2 {
	address			0x04D
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRNONPACKREQ	0x20
	field	CLRWIDE_RES	0x04	/* Modes 0 and 1 only */
	field	CLRSDONE	0x02	/* Modes 0 and 1 only */
	field	CLRDMADONE	0x01	/* Modes 0 and 1 only */
}

/*
 * SCSI Interrupt Mode 2
 */
register SIMODE2 {
	address			0x04D
	access_mode	RW
	modes		M_CFG
	field	ENWIDE_RES	0x04
	field	ENSDONE		0x02
	field	ENDMADONE	0x01
}

/*
 * Physical Error Diagnosis
 */
register PERRDIAG {
	address			0x04E
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	HIZERO		0x80
	field	HIPERR		0x40
	field	PREVPHASE	0x20
	field	PARITYERR	0x10
	field	AIPERR		0x08
	field	CRCERR		0x04
	field	DGFORMERR	0x02
	field	DTERR		0x01
}

/*
 * LQI Manager Current State
 */
register LQISTATE {
	address			0x04E
	access_mode	RO
	modes		M_CFG
}

/*
 * SCSI Offset Count
 */
register SOFFCNT {
	address			0x04F
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
}

/*
 * LQO Manager Current State
 */
register LQOSTATE {
	address			0x04F
	access_mode	RO
	modes		M_CFG
}

/*
 * LQI Manager Status
 */
register LQISTAT0 {
	address			0x050
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	LQIATNQAS	0x20
	field	LQICRCT1	0x10
	field	LQICRCT2	0x08
	field	LQIBADLQT	0x04
	field	LQIATNLQ	0x02
	field	LQIATNCMD	0x01
}

/*
 * Clear LQI Interrupts 0
 */
register CLRLQIINT0 {
	address			0x050
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRLQIATNQAS	0x20
	field	CLRLQICRCT1	0x10
	field	CLRLQICRCT2	0x08
	field	CLRLQIBADLQT	0x04
	field	CLRLQIATNLQ	0x02
	field	CLRLQIATNCMD	0x01
}

/*
 * LQI Manager Interrupt Mode 0
 */
register LQIMODE0 {
	address			0x050
	access_mode	RW
	modes		M_CFG
	field	ENLQIATNQASK	0x20
	field	ENLQICRCT1	0x10
	field	ENLQICRCT2	0x08
	field	ENLQIBADLQT	0x04
	field	ENLQIATNLQ	0x02
	field	ENLQIATNCMD	0x01
}

/*
 * LQI Manager Status 1
 */
register LQISTAT1 {
	address			0x051
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	LQIPHASE_LQ	0x80
	field	LQIPHASE_NLQ	0x40
	field	LQIABORT	0x20
	field	LQICRCI_LQ	0x10
	field	LQICRCI_NLQ	0x08
	field	LQIBADLQI	0x04
	field	LQIOVERI_LQ	0x02
	field	LQIOVERI_NLQ	0x01
}

/*
 * Clear LQI Manager Interrupts1
 */
register CLRLQIINT1 {
	address			0x051
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRLQIPHASE_LQ	0x80
	field	CLRLQIPHASE_NLQ	0x40
	field	CLRLIQABORT	0x20
	field	CLRLQICRCI_LQ	0x10
	field	CLRLQICRCI_NLQ	0x08
	field	CLRLQIBADLQI	0x04
	field	CLRLQIOVERI_LQ	0x02
	field	CLRLQIOVERI_NLQ	0x01
}

/*
 * LQI Manager Interrupt Mode 1
 */
register LQIMODE1 {
	address			0x051
	access_mode	RW
	modes		M_CFG
	field	ENLQIPHASE_LQ	0x80	/* LQIPHASE1 */
	field	ENLQIPHASE_NLQ	0x40	/* LQIPHASE2 */
	field	ENLIQABORT	0x20
	field	ENLQICRCI_LQ	0x10	/* LQICRCI1 */
	field	ENLQICRCI_NLQ	0x08	/* LQICRCI2 */
	field	ENLQIBADLQI	0x04
	field	ENLQIOVERI_LQ	0x02	/* LQIOVERI1 */
	field	ENLQIOVERI_NLQ	0x01	/* LQIOVERI2 */
}

/*
 * LQI Manager Status 2
 */
register LQISTAT2 {
	address			0x052
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	PACKETIZED	0x80
	field	LQIPHASE_OUTPKT	0x40
	field	LQIWORKONLQ	0x20
	field	LQIWAITFIFO	0x10
	field	LQISTOPPKT	0x08
	field	LQISTOPLQ	0x04
	field	LQISTOPCMD	0x02
	field	LQIGSAVAIL	0x01
}

/*
 * SCSI Status 3
 */
register SSTAT3 {
	address			0x053
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	NTRAMPERR	0x02
	field	OSRAMPERR	0x01
}

/*
 * Clear SCSI Status 3
 */
register CLRSINT3 {
	address			0x053
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRNTRAMPERR	0x02
	field	CLROSRAMPERR	0x01
}

/*
 * SCSI Interrupt Mode 3
 */
register SIMODE3 {
	address			0x053
	access_mode	RW
	modes		M_CFG
	field	ENNTRAMPERR	0x02
	field	ENOSRAMPERR	0x01
}

/*
 * LQO Manager Status 0
 */
register LQOSTAT0 {
	address			0x054
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	LQOTARGSCBPERR	0x10
	field	LQOSTOPT2	0x08
	field	LQOATNLQ	0x04
	field	LQOATNPKT	0x02
	field	LQOTCRC		0x01
}

/*
 * Clear LQO Manager interrupt 0
 */
register CLRLQOINT0 {
	address			0x054
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRLQOTARGSCBPERR	0x10
	field	CLRLQOSTOPT2		0x08
	field	CLRLQOATNLQ		0x04
	field	CLRLQOATNPKT		0x02
	field	CLRLQOTCRC		0x01
}

/*
 * LQO Manager Interrupt Mode 0
 */
register LQOMODE0 {
	address			0x054
	access_mode	RW
	modes		M_CFG
	field	ENLQOTARGSCBPERR	0x10
	field	ENLQOSTOPT2		0x08
	field	ENLQOATNLQ		0x04
	field	ENLQOATNPKT		0x02
	field	ENLQOTCRC		0x01
}

/*
 * LQO Manager Status 1
 */
register LQOSTAT1 {
	address			0x055
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	LQOINITSCBPERR	0x10
	field	LQOSTOPI2	0x08
	field	LQOBADQAS	0x04
	field	LQOBUSFREE	0x02
	field	LQOPHACHGINPKT	0x01
}

/*
 * Clear LOQ Interrupt 1
 */
register CLRLQOINT1 {
	address			0x055
	access_mode	WO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	CLRLQOINITSCBPERR	0x10
	field	CLRLQOSTOPI2		0x08
	field	CLRLQOBADQAS		0x04
	field	CLRLQOBUSFREE		0x02
	field	CLRLQOPHACHGINPKT	0x01
}

/*
 * LQO Manager Interrupt Mode 1
 */
register LQOMODE1 {
	address			0x055
	access_mode	RW
	modes		M_CFG
	field	ENLQOINITSCBPERR	0x10
	field	ENLQOSTOPI2		0x08
	field	ENLQOBADQAS		0x04
	field	ENLQOBUSFREE		0x02
	field	ENLQOPHACHGINPKT	0x01
}

/*
 * LQO Manager Status 2
 */
register LQOSTAT2 {
	address			0x056
	access_mode	RO
	modes		M_DFF0, M_DFF1, M_SCSI
	field	LQOPKT		0xE0
	field	LQOWAITFIFO	0x10
	field	LQOPHACHGOUTPKT	0x02	/* outside of packet boundaries. */
	field	LQOSTOP0	0x01	/* Stopped after sending all packets */
}

/*
 * Output Synchronizer Space Count
 */
register OS_SPACE_CNT {
	address			0x056
	access_mode	RO
	modes		M_CFG
}

/*
 * SCSI Interrupt Mode 1
 * Setting any bit will enable the corresponding function
 * in SIMODE1 to interrupt via the IRQ pin.
 */
register SIMODE1 {
	address			0x057
	access_mode	RW
	modes		M_DFF0, M_DFF1, M_SCSI
	field	ENSELTIMO	0x80
	field	ENATNTARG	0x40
	field	ENSCSIRST	0x20
	field	ENPHASEMIS	0x10
	field	ENBUSFREE	0x08
	field	ENSCSIPERR	0x04
	field	ENSTRB2FAST	0x02
	field	ENREQINIT	0x01
}

/*
 * Good Status FIFO
 */
register GSFIFO {
	address			0x058
	access_mode	RO
	size		2
	modes		M_DFF0, M_DFF1, M_SCSI
}

/*
 * Data FIFO SCSI Transfer Control
 */
register DFFSXFRCTL {
	address			0x05A
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	DFFBITBUCKET	0x08
	field	CLRSHCNT	0x04
	field	CLRCHN		0x02
	field	RSTCHN		0x01
}

/*
 * Next SCSI Control Block
 */
register NEXTSCB {
	address			0x05A
	access_mode	RW
	size		2
	modes		M_SCSI
}

/* Rev B only. */
register LQOSCSCTL {
	address			0x05A
	access_mode	RW
	size		1
	modes		M_CFG
	field		LQOH2A_VERSION	0x80
	field		LQONOCHKOVER	0x01
}

/*
 * SEQ Interrupts
 */
register SEQINTSRC {
	address			0x05B
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	CTXTDONE	0x40
	field	SAVEPTRS	0x20
	field	CFG4DATA	0x10
	field	CFG4ISTAT	0x08
	field	CFG4TSTAT	0x04
	field	CFG4ICMD	0x02
	field	CFG4TCMD	0x01
}

/*
 * Clear Arp Interrupts
 */
register CLRSEQINTSRC {
	address			0x05B
	access_mode	WO
	modes		M_DFF0, M_DFF1
	field	CLRCTXTDONE	0x40
	field	CLRSAVEPTRS	0x20
	field	CLRCFG4DATA	0x10
	field	CLRCFG4ISTAT	0x08
	field	CLRCFG4TSTAT	0x04
	field	CLRCFG4ICMD	0x02
	field	CLRCFG4TCMD	0x01
}

/*
 * SEQ Interrupt Enabled (Shared)
 */
register SEQIMODE {
	address			0x05C
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	ENCTXTDONE	0x40
	field	ENSAVEPTRS	0x20
	field	ENCFG4DATA	0x10
	field	ENCFG4ISTAT	0x08
	field	ENCFG4TSTAT	0x04
	field	ENCFG4ICMD	0x02
	field	ENCFG4TCMD	0x01
}

/*
 * Current SCSI Control Block
 */
register CURRSCB {
	address			0x05C
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Data FIFO Status
 */
register MDFFSTAT {
	address			0x05D
	access_mode	RO
	modes		M_DFF0, M_DFF1
	field	SHCNTNEGATIVE	0x40 /* Rev B or higher */
	field	SHCNTMINUS1	0x20 /* Rev B or higher */
	field	LASTSDONE	0x10
	field	SHVALID		0x08
	field	DLZERO		0x04 /* FIFO data ends on packet boundary. */
	field	DATAINFIFO	0x02
	field	FIFOFREE	0x01
}

/*
 * CRC Control
 */
register CRCCONTROL {
	address			0x05d
	access_mode	RW
	modes		M_CFG
	field	CRCVALCHKEN		0x40
}

/*
 * SCSI Test Control
 */
register SCSITEST {
	address			0x05E
	access_mode	RW
	modes		M_CFG
	field	CNTRTEST	0x08
	field	SEL_TXPLL_DEBUG	0x04
}

/*
 * Data FIFO Queue Tag
 */
register DFFTAG {
	address			0x05E
	access_mode	RW
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * Last SCSI Control Block
 */
register LASTSCB {
	address			0x05E
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * SCSI I/O Cell Power-down Control
 */
register IOPDNCTL {
	address			0x05F
	access_mode	RW
	modes		M_CFG
	field	DISABLE_OE	0x80
	field	PDN_IDIST	0x04
	field	PDN_DIFFSENSE	0x01
}

/*
 * Shaddow Host Address.
 */
register SHADDR {
	address			0x060
	access_mode	RO
	size		8
	modes		M_DFF0, M_DFF1
}

/*
 * Data Group CRC Interval.
 */
register DGRPCRCI {
	address			0x060
	access_mode	RW
	size		2
	modes		M_CFG
}

/*
 * Data Transfer Negotiation Address
 */
register NEGOADDR {
	address			0x060
	access_mode	RW
	modes		M_SCSI
}

/*
 * Data Transfer Negotiation Data - Period Byte
 */
register NEGPERIOD {
	address			0x061
	access_mode	RW
	modes		M_SCSI
}

/*
 * Packetized CRC Interval
 */
register PACKCRCI {
	address			0x062
	access_mode	RW
	size		2
	modes		M_CFG
}

/*
 * Data Transfer Negotiation Data - Offset Byte
 */
register NEGOFFSET {
	address			0x062
	access_mode	RW
	modes		M_SCSI
}

/*
 * Data Transfer Negotiation Data - PPR Options
 */
register NEGPPROPTS {
	address			0x063
	access_mode	RW
	modes		M_SCSI
	field	PPROPT_PACE	0x08
	field	PPROPT_QAS	0x04
	field	PPROPT_DT	0x02
	field	PPROPT_IUT	0x01
}

/*
 * Data Transfer Negotiation Data -  Connection Options
 */
register NEGCONOPTS {
	address			0x064
	access_mode	RW
	modes		M_SCSI
	field	ENSNAPSHOT	0x40
	field	RTI_WRTDIS	0x20
	field	RTI_OVRDTRN	0x10
	field	ENSLOWCRC	0x08
	field	ENAUTOATNI	0x04
	field	ENAUTOATNO	0x02
	field	WIDEXFER	0x01
}

/*
 * Negotiation Table Annex Column Index.
 */
register ANNEXCOL {
	address			0x065
	access_mode	RW
	modes		M_SCSI
}

register SCSCHKN {
	address			0x066
	access_mode	RW
	modes		M_CFG
	field	STSELSKIDDIS	0x40
	field	CURRFIFODEF	0x20
	field	WIDERESEN	0x10
	field	SDONEMSKDIS	0x08
	field	DFFACTCLR	0x04
	field	SHVALIDSTDIS	0x02
	field	LSTSGCLRDIS	0x01
}

const AHD_ANNEXCOL_PER_DEV0	4
const AHD_NUM_PER_DEV_ANNEXCOLS	4
const AHD_ANNEXCOL_PRECOMP_SLEW	4
const	AHD_PRECOMP_MASK	0x07
const	AHD_PRECOMP_SHIFT	0
const	AHD_PRECOMP_CUTBACK_17	0x04
const	AHD_PRECOMP_CUTBACK_29	0x06
const	AHD_PRECOMP_CUTBACK_37	0x07
const	AHD_SLEWRATE_MASK	0x78
const	AHD_SLEWRATE_SHIFT	3
/*
 * Rev A has only a single bit (high bit of field) of slew adjustment.
 * Rev B has 4 bits.  The current default happens to be the same for both.
 */
const	AHD_SLEWRATE_DEF_REVA	0x08
const	AHD_SLEWRATE_DEF_REVB	0x08

/* Rev A does not have any amplitude setting. */
const AHD_ANNEXCOL_AMPLITUDE	6
const	AHD_AMPLITUDE_MASK	0x7
const	AHD_AMPLITUDE_SHIFT	0
const	AHD_AMPLITUDE_DEF	0x7

/*
 * Negotiation Table Annex Data Port.
 */
register ANNEXDAT {
	address			0x066
	access_mode	RW
	modes		M_SCSI
}

/*
 * Initiator's Own Id.
 * The SCSI ID to use for Selection Out and seen during a reselection..
 */
register IOWNID {
	address			0x067
	access_mode	RW
	modes		M_SCSI
}

/*
 * 960MHz Phase-Locked Loop Control 0
 */
register PLL960CTL0 {
	address			0x068
	access_mode	RW
	modes		M_CFG
	field	PLL_VCOSEL	0x80
	field	PLL_PWDN	0x40
	field	PLL_NS		0x30
	field	PLL_ENLUD	0x08
	field	PLL_ENLPF	0x04
	field	PLL_DLPF	0x02
	field	PLL_ENFBM	0x01
}

/*
 * Target Own Id
 */
register TOWNID {
	address			0x069
	access_mode	RW
	modes		M_SCSI
}

/*
 * 960MHz Phase-Locked Loop Control 1
 */
register PLL960CTL1 {
	address			0x069
	access_mode	RW
	modes		M_CFG
	field	PLL_CNTEN	0x80
	field	PLL_CNTCLR	0x40
	field	PLL_RST		0x01
}

/*
 * Expander Signature
 */
register XSIG {
	address			0x06A
	access_mode	RW
	modes		M_SCSI
}

/*
 * Shadow Byte Count
 */
register SHCNT {
	address			0x068
	access_mode	RW
	size		3
	modes		M_DFF0, M_DFF1
}

/*
 * Selection Out ID
 */
register SELOID {
	address			0x06B
	access_mode	RW
	modes		M_SCSI
}

/*
 * 960-MHz Phase-Locked Loop Test Count
 */
register PLL960CNT0 {
	address			0x06A
	access_mode	RO
	size		2
	modes		M_CFG
}

/*
 * 400-MHz Phase-Locked Loop Control 0
 */
register PLL400CTL0 {
	address			0x06C
	access_mode	RW
	modes		M_CFG
	field	PLL_VCOSEL	0x80
	field	PLL_PWDN	0x40
	field	PLL_NS		0x30
	field	PLL_ENLUD	0x08
	field	PLL_ENLPF	0x04
	field	PLL_DLPF	0x02
	field	PLL_ENFBM	0x01
}

/*
 * Arbitration Fairness
 */
register FAIRNESS {
	address			0x06C
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * 400-MHz Phase-Locked Loop Control 1
 */
register PLL400CTL1 {
	address			0x06D
	access_mode	RW
	modes		M_CFG
	field	PLL_CNTEN	0x80
	field	PLL_CNTCLR	0x40
	field	PLL_RST		0x01
}

/*
 * Arbitration Unfairness
 */
register UNFAIRNESS {
	address			0x06E
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * 400-MHz Phase-Locked Loop Test Count
 */
register PLL400CNT0 {
	address			0x06E
	access_mode	RO
	size		2
	modes		M_CFG
}

/*
 * SCB Page Pointer
 */
register SCBPTR {
	address			0x0A8
	access_mode	RW
	size		2
	modes		M_DFF0, M_DFF1, M_CCHAN, M_SCSI
}

/*
 * CMC SCB Array Count
 * Number of bytes to transfer between CMC SCB memory and SCBRAM.
 * Transfers must be 8byte aligned and sized.
 */
register CCSCBACNT {
	address			0x0AB
	access_mode	RW
	modes		M_CCHAN
}

/*
 * SCB Autopointer
 * SCB-Next Address Snooping logic.  When an SCB is transferred to
 * the card, the next SCB address to be used by the CMC array can
 * be autoloaded from that transfer.
 */
register SCBAUTOPTR {
	address			0x0AB
	access_mode	RW
	modes		M_CFG
	field	AUSCBPTR_EN	0x80
	field	SCBPTR_ADDR	0x38
	field	SCBPTR_OFF	0x07
}

/*
 * CMC SG Ram Address Pointer
 */
register CCSGADDR {
	address			0x0AC
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * CMC SCB RAM Address Pointer
 */
register CCSCBADDR {
	address			0x0AC
	access_mode	RW
	modes		M_CCHAN
}

/*
 * CMC SCB Ram Back-up Address Pointer
 * Indicates the true stop location of transfers halted prior
 * to SCBHCNT going to 0.
 */
register CCSCBADR_BK {
	address			0x0AC
	access_mode	RO
	modes		M_CFG
}

/*
 * CMC SG Control
 */
register CCSGCTL {
	address			0x0AD
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	CCSGDONE	0x80
	field	SG_CACHE_AVAIL	0x10
	field	CCSGENACK	0x08
	mask	CCSGEN		0x0C
	field	SG_FETCH_REQ	0x02
	field	CCSGRESET	0x01
}

/*
 * CMD SCB Control
 */
register CCSCBCTL {
	address			0x0AD
	access_mode	RW
	modes		M_CCHAN
	field	CCSCBDONE	0x80
	field	ARRDONE		0x40
	field	CCARREN		0x10
	field	CCSCBEN		0x08
	field	CCSCBDIR	0x04
	field	CCSCBRESET	0x01
}

/*
 * CMC Ram BIST
 */
register CMC_RAMBIST {
	address			0x0AD
	access_mode	RW
	modes		M_CFG
	field	SG_ELEMENT_SIZE		0x80
	field	SCBRAMBIST_FAIL		0x40
	field	SG_BIST_FAIL		0x20
	field	SG_BIST_EN		0x10
	field	CMC_BUFFER_BIST_FAIL	0x02
	field	CMC_BUFFER_BIST_EN	0x01
}

/*
 * CMC SG RAM Data Port
 */
register CCSGRAM {
	address			0x0B0
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * CMC SCB RAM Data Port
 */
register CCSCBRAM {
	address			0x0B0
	access_mode	RW
	modes		M_CCHAN
}

/*
 * Flex DMA Address.
 */
register FLEXADR {
	address			0x0B0
	access_mode	RW
	size		3
	modes		M_SCSI
}

/*
 * Flex DMA Byte Count
 */
register FLEXCNT {
	address			0x0B3
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Flex DMA Status
 */
register FLEXDMASTAT {
	address			0x0B5
	access_mode	RW
	modes		M_SCSI
	field	FLEXDMAERR	0x02
	field	FLEXDMADONE	0x01
}

/*
 * Flex DMA Data Port
 */
register FLEXDATA {
	address			0x0B6
	access_mode	RW
	modes		M_SCSI
}

/*
 * Board Data
 */
register BRDDAT {
	address			0x0B8
	access_mode	RW
	modes		M_SCSI
}

/*
 * Board Control
 */
register BRDCTL {
	address			0x0B9
	access_mode	RW
	modes		M_SCSI
	field	FLXARBACK	0x80
	field	FLXARBREQ	0x40
	field	BRDADDR		0x38
	field	BRDEN		0x04
	field	BRDRW		0x02
	field	BRDSTB		0x01
}

/*
 * Serial EEPROM Address
 */
register SEEADR {
	address			0x0BA
	access_mode	RW
	modes		M_SCSI
}

/*
 * Serial EEPROM Data
 */
register SEEDAT {
	address			0x0BC
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Serial EEPROM Status
 */
register SEESTAT {
	address			0x0BE
	access_mode	RO
	modes		M_SCSI
	field	INIT_DONE	0x80
	field	SEEOPCODE	0x70
	field	LDALTID_L	0x08
	field	SEEARBACK	0x04
	field	SEEBUSY		0x02
	field	SEESTART	0x01
}

/*
 * Serial EEPROM Control
 */
register SEECTL {
	address			0x0BE
	access_mode	RW
	modes		M_SCSI
	field	SEEOPCODE	0x70 {
		SEEOP_ERASE	0x70,
		SEEOP_READ	0x60,
		SEEOP_WRITE	0x50,
	/*
	 * The following four commands use special
	 * addresses for differentiation.
	 */
		SEEOP_ERAL	0x40
	}
	mask	SEEOP_EWEN	0x40
	mask	SEEOP_WALL	0x40
	mask	SEEOP_EWDS	0x40
	field	SEERST		0x02
	field	SEESTART	0x01
}

const SEEOP_ERAL_ADDR	0x80
const SEEOP_EWEN_ADDR	0xC0
const SEEOP_WRAL_ADDR	0x40
const SEEOP_EWDS_ADDR	0x00

/*
 * SCB Counter
 */
register SCBCNT {
	address			0x0BF
	access_mode	RW
	modes		M_SCSI
}

/*
 * Data FIFO Write Address
 * Pointer to the next QWD location to be written to the data FIFO.
 */
register DFWADDR {
	address			0x0C0
	access_mode	RW
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * DSP Filter Control
 */
register DSPFLTRCTL {
	address			0x0C0
	access_mode	RW
	modes		M_CFG
	field	FLTRDISABLE	0x20
	field	EDGESENSE	0x10
	field	DSPFCNTSEL	0x0F
}

/*
 * DSP Data Channel Control
 */
register DSPDATACTL {
	address			0x0C1
	access_mode	RW
	modes		M_CFG
	field	BYPASSENAB	0x80
	field	DESQDIS		0x10
	field	RCVROFFSTDIS	0x04
	field	XMITOFFSTDIS	0x02
}

/*
 * Data FIFO Read Address
 * Pointer to the next QWD location to be read from the data FIFO.
 */
register DFRADDR {
	address			0x0C2
	access_mode	RW
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * DSP REQ Control
 */
register DSPREQCTL {
	address			0x0C2
	access_mode	RW
	modes		M_CFG
	field	MANREQCTL	0xC0
	field	MANREQDLY	0x3F
}

/*
 * DSP ACK Control
 */
register DSPACKCTL {
	address			0x0C3
	access_mode	RW
	modes		M_CFG
	field	MANACKCTL	0xC0
	field	MANACKDLY	0x3F
}

/*
 * Data FIFO Data
 * Read/Write byte port into the data FIFO.  The read and write
 * FIFO pointers increment with each read and write respectively
 * to this port.
 */
register DFDAT {
	address			0x0C4
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * DSP Channel Select
 */
register DSPSELECT {
	address			0x0C4
	access_mode	RW
	modes		M_CFG
	field	AUTOINCEN	0x80
	field	DSPSEL		0x1F
}

const NUMDSPS 0x14

/*
 * Write Bias Control
 */
register WRTBIASCTL {
	address			0x0C5
	access_mode	WO
	modes		M_CFG
	field	AUTOXBCDIS	0x80
	field	XMITMANVAL	0x3F
}

/*
 * Currently the WRTBIASCTL is the same as the default.
 */
const WRTBIASCTL_HP_DEFAULT 0x0

/*
 * Receiver Bias Control
 */
register RCVRBIOSCTL {
	address			0x0C6
	access_mode	WO
	modes		M_CFG
	field	AUTORBCDIS	0x80
	field	RCVRMANVAL	0x3F
}

/*
 * Write Bias Calculator
 */
register WRTBIASCALC {
	address			0x0C7
	access_mode	RO
	modes		M_CFG
}

/*
 * Data FIFO Pointers
 * Contains the byte offset from DFWADDR and DWRADDR to the current
 * FIFO write/read locations.
 */
register DFPTRS {
	address			0x0C8
	access_mode	RW
	modes		M_DFF0, M_DFF1
}

/*
 * Receiver Bias Calculator
 */
register RCVRBIASCALC {
	address			0x0C8
	access_mode	RO
	modes		M_CFG
}

/*
 * Data FIFO Backup Read Pointer
 * Contains the data FIFO address to be restored if the last
 * data accessed from the data FIFO was not transferred successfully.
 */
register DFBKPTR {
	address			0x0C9
	access_mode	RW
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * Skew Calculator
 */
register SKEWCALC {
	address			0x0C9
	access_mode	RO
	modes		M_CFG
}

/*
 * Data FIFO Debug Control
 */
register DFDBCTL {
	address				0x0CB
	access_mode	RW
	modes		M_DFF0, M_DFF1
	field	DFF_CIO_WR_RDY		0x20
	field	DFF_CIO_RD_RDY		0x10
	field	DFF_DIR_ERR		0x08
	field	DFF_RAMBIST_FAIL	0x04
	field	DFF_RAMBIST_DONE	0x02
	field	DFF_RAMBIST_EN		0x01
}

/*
 * Data FIFO Space Count
 * Number of FIFO locations that are free.
 */
register DFSCNT {
	address			0x0CC
	access_mode	RO
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * Data FIFO Byte Count
 * Number of filled FIFO locations.
 */
register DFBCNT {
	address			0x0CE
	access_mode	RO
	size		2
	modes		M_DFF0, M_DFF1
}

/*
 * Sequencer Program Overlay Address.
 * Low address must be written prior to high address.
 */
register OVLYADDR {
	address			0x0D4
	modes		M_SCSI
	size		2
	access_mode	RW
}

/*
 * Sequencer Control 0
 * Error detection mode, speed configuration,
 * single step, breakpoints and program load.
 */
register SEQCTL0 {
	address			0x0D6
	access_mode RW
	field	PERRORDIS	0x80
	field	PAUSEDIS	0x40
	field	FAILDIS		0x20
	field	FASTMODE	0x10
	field	BRKADRINTEN	0x08
	field	STEP		0x04
	field	SEQRESET	0x02
	field	LOADRAM		0x01
}

/*
 * Sequencer Control 1
 * Instruction RAM Diagnostics
 */
register SEQCTL1 {
	address			0x0D7
	access_mode RW
	field	OVRLAY_DATA_CHK	0x08
	field	RAMBIST_DONE	0x04
	field	RAMBIST_FAIL	0x02
	field	RAMBIST_EN	0x01
}

/*
 * Sequencer Flags
 * Zero and Carry state of the ALU.
 */
register FLAGS {
	address			0x0D8
	access_mode RO
	field	ZERO		0x02
	field	CARRY		0x01
}

/*
 * Sequencer Interrupt Control
 */ 
register SEQINTCTL {
	address			0x0D9
	access_mode RW
	field	INTVEC1DSL	0x80
	field	INT1_CONTEXT	0x20
	field	SCS_SEQ_INT1M1	0x10
	field	SCS_SEQ_INT1M0	0x08
	field	INTMASK2	0x04
	field	INTMASK1	0x02
	field	IRET		0x01
}

/*
 * Sequencer RAM Data Port
 * Single byte window into the Sequencer Instruction Ram area starting
 * at the address specified by OVLYADDR.  To write a full instruction word,
 * simply write four bytes in succession.  OVLYADDR will increment after the
 * most significant instrution byte (the byte with the parity bit) is written.
 */
register SEQRAM {
	address			0x0DA
	access_mode RW
}

/*
 * Sequencer Program Counter
 * Low byte must be written prior to high byte.
 */
register PRGMCNT {
	address			0x0DE
	access_mode	RW
	size		2
}

/*
 * Accumulator
 */
register ACCUM {
	address			0x0E0
	access_mode RW
	accumulator
}

/*
 * Source Index Register
 * Incrementing index for reads of SINDIR and the destination (low byte only)
 * for any immediate operands passed in jmp, jc, jnc, call instructions.
 * Example:
 *		mvi	0xFF	call some_routine;
 *
 *  Will set SINDEX[0] to 0xFF and call the routine "some_routine.
 */
register SINDEX	{
	address			0x0E2
	access_mode	RW
	size		2
	sindex
}

/*
 * Destination Index Register
 * Incrementing index for writes to DINDIR.  Can be used as a scratch register.
 */
register DINDEX {
	address			0x0E4
	access_mode	RW
	size		2
}

/*
 * Break Address
 * Sequencer instruction breakpoint address address.
 */
register BRKADDR0 {
	address			0x0E6
	access_mode	RW
}

register BRKADDR1 {
	address			0x0E6
	access_mode	RW
	field	BRKDIS		0x80	/* Disable Breakpoint */
}

/*
 * All Ones
 * All reads to this register return the value 0xFF.
 */
register ALLONES {
	address			0x0E8
	access_mode RO
	allones
}

/*
 * All Zeros
 * All reads to this register return the value 0.
 */
register ALLZEROS {
	address			0x0EA
	access_mode RO
	allzeros
}

/*
 * No Destination
 * Writes to this register have no effect.
 */
register NONE {
	address			0x0EA
	access_mode WO
	none
}

/*
 * Source Index Indirect
 * Reading this register is equivalent to reading (register_base + SINDEX) and
 * incrementing SINDEX by 1.
 */
register SINDIR	{
	address			0x0EC
	access_mode RO
}

/*
 * Destination Index Indirect
 * Writing this register is equivalent to writing to (register_base + DINDEX)
 * and incrementing DINDEX by 1.
 */
register DINDIR	 {
	address			0x0ED
	access_mode WO
}

/*
 * Function One
 * 2's complement to bit value conversion.  Write the 2's complement value
 * (0-7 only) to the top nibble and retrieve the bit indexed by that value
 * on the next read of this register. 
 * Example:
 *	Write	0x60
 *	Read	0x40
 */
register FUNCTION1 {
	address			0x0F0
	access_mode RW
}

/*
 * Stack
 * Window into the stack.  Each stack location is 10 bits wide reported
 * low byte followed by high byte.  There are 8 stack locations.
 */
register STACK {
	address			0x0F2
	access_mode RW
}

/*
 * Interrupt Vector 1 Address
 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
 */
register INTVEC1_ADDR {
	address			0x0F4
	access_mode	RW
	size		2
	modes		M_CFG
}

/*
 * Current Address
 * Address of the SEQRAM instruction currently executing instruction.
 */
register CURADDR {
	address			0x0F4
	access_mode	RW
	size		2
	modes		M_SCSI
}

/*
 * Interrupt Vector 2 Address
 * Interrupt branch address for HST_SEQ_INT2 interrupts.
 */
register INTVEC2_ADDR {
	address			0x0F6
	access_mode	RW
	size		2
	modes		M_CFG
}

/*
 * Last Address
 * Address of the SEQRAM instruction executed prior to the current instruction.
 */
register LASTADDR {
	address			0x0F6
	access_mode	RW
	size		2
	modes		M_SCSI
}

register AHD_PCI_CONFIG_BASE {
	address			0x100
	access_mode	RW
	size		256
	modes		M_CFG
}

/* ---------------------- Scratch RAM Offsets ------------------------- */
scratch_ram {
	/* Mode Specific */
	address			0x0A0
	size	8
	modes	0, 1, 2, 3
	REG0 {
		size		2
	}
	REG1 {
		size		2
	}
	REG_ISR {
		size		2
	}
	SG_STATE {
		size		1
		field	SEGS_AVAIL	0x01
		field	LOADING_NEEDED	0x02
		field	FETCH_INPROG	0x04
	}
	/*
	 * Track whether the transfer byte count for
	 * the current data phase is odd.
	 */
	DATA_COUNT_ODD {
		size		1
	}
}

scratch_ram {
	/* Mode Specific */
	address			0x0F8
	size	8
	modes	0, 1, 2, 3
	LONGJMP_ADDR {
		size		2
	}
	ACCUM_SAVE {
		size		1
	}
}


scratch_ram {
	address			0x100
	size	128
	modes	0, 1, 2, 3
	/*
	 * Per "other-id" execution queues.  We use an array of
	 * tail pointers into lists of SCBs sorted by "other-id".
	 * The execution head pointer threads the head SCBs for
	 * each list.
	 */
	WAITING_SCB_TAILS {
		size		32
	}
	WAITING_TID_HEAD {
		size		2
	}
	WAITING_TID_TAIL {
		size		2
	}
	/*
	 * SCBID of the next SCB in the new SCB queue.
	 */
	NEXT_QUEUED_SCB_ADDR {
		size		4
	}
	/*
	 * head of list of SCBs that have
	 * completed but have not been
	 * put into the qoutfifo.
	 */
	COMPLETE_SCB_HEAD {
		size		2
	}
	/*
	 * The list of completed SCBs in
	 * the active DMA.
	 */
	COMPLETE_SCB_DMAINPROG_HEAD {
		size		2
	}
	/*
	 * head of list of SCBs that have
	 * completed but need to be uploaded
	 * to the host prior to being completed.
	 */
	COMPLETE_DMA_SCB_HEAD {
		size		2
	}
	/*
	 * tail of list of SCBs that have
	 * completed but need to be uploaded
	 * to the host prior to being completed.
	 */
	COMPLETE_DMA_SCB_TAIL {
		size		2
	}
	/*
	 * head of list of SCBs that have
	 * been uploaded to the host, but cannot
	 * be completed until the QFREEZE is in
	 * full effect (i.e. no selections pending).
	 */
	COMPLETE_ON_QFREEZE_HEAD {
		size		2
	}
	/*
	 * Counting semaphore to prevent new select-outs
	 * The queue is frozen so long as the sequencer
	 * and kernel freeze counts differ.
	 */
	QFREEZE_COUNT {
		size		2
	}
	KERNEL_QFREEZE_COUNT {
		size		2
	}
	/*
	 * Mode to restore on legacy idle loop exit.
	 */
	SAVED_MODE {
		size		1
	}
	/*
	 * Single byte buffer used to designate the type or message
	 * to send to a target.
	 */
	MSG_OUT {
		size		1
	}
	/* Parameters for DMA Logic */
	DMAPARAMS {
		size		1
		field	PRELOADEN	0x80
		field	WIDEODD		0x40
		field	SCSIEN		0x20
		field	SDMAEN		0x10
		field	SDMAENACK	0x10
		field	HDMAEN		0x08
		field	HDMAENACK	0x08
		field	DIRECTION	0x04	/* Set indicates PCI->SCSI */
		field	FIFOFLUSH	0x02
		field	FIFORESET	0x01
	}
	SEQ_FLAGS {
		size		1
		field	NOT_IDENTIFIED		0x80
		field	NO_CDB_SENT		0x40
		field	TARGET_CMD_IS_TAGGED	0x40
		field	DPHASE			0x20
		/* Target flags */
		field	TARG_CMD_PENDING	0x10
		field	CMDPHASE_PENDING	0x08
		field	DPHASE_PENDING		0x04
		field	SPHASE_PENDING		0x02
		field	NO_DISCONNECT		0x01
	}
	/*
	 * Temporary storage for the
	 * target/channel/lun of a
	 * reconnecting target
	 */
	SAVED_SCSIID {
		size		1
	}
	SAVED_LUN {
		size		1
	}
	/*
	 * The last bus phase as seen by the sequencer. 
	 */
	LASTPHASE {
		size		1
		field	CDI		0x80
		field	IOI		0x40
		field	MSGI		0x20
		field	P_BUSFREE	0x01
		enum	PHASE_MASK  CDO|IOO|MSGO {
			P_DATAOUT	0x0,
			P_DATAIN	IOO,
			P_DATAOUT_DT	P_DATAOUT|MSGO,
			P_DATAIN_DT	P_DATAIN|MSGO,
			P_COMMAND	CDO,
			P_MESGOUT	CDO|MSGO,
			P_STATUS	CDO|IOO,
			P_MESGIN	CDO|IOO|MSGO
		}
	}
	/*
	 * Value to "or" into the SCBPTR[1] value to
	 * indicate that an entry in the QINFIFO is valid.
	 */
	QOUTFIFO_ENTRY_VALID_TAG {
		size		1
	}
	/*
	 * Kernel and sequencer offsets into the queue of
	 * incoming target mode command descriptors.  The
	 * queue is full when the KERNEL_TQINPOS == TQINPOS.
	 */
	KERNEL_TQINPOS {
		size		1
	}
	TQINPOS {                
		size		1
	}
	/*
	 * Base address of our shared data with the kernel driver in host
	 * memory.  This includes the qoutfifo and target mode
	 * incoming command queue.
	 */
	SHARED_DATA_ADDR {
		size		4
	}
	/*
	 * Pointer to location in host memory for next
	 * position in the qoutfifo.
	 */
	QOUTFIFO_NEXT_ADDR {
		size		4
	}
	ARG_1 {
		size		1
		mask	SEND_MSG		0x80
		mask	SEND_SENSE		0x40
		mask	SEND_REJ		0x20
		mask	MSGOUT_PHASEMIS		0x10
		mask	EXIT_MSG_LOOP		0x08
		mask	CONT_MSG_LOOP_WRITE	0x04
		mask	CONT_MSG_LOOP_READ	0x03
		mask	CONT_MSG_LOOP_TARG	0x02
		alias	RETURN_1
	}
	ARG_2 {
		size		1
		alias	RETURN_2
	}

	/*
	 * Snapshot of MSG_OUT taken after each message is sent.
	 */
	LAST_MSG {
		size		1
	}

	/*
	 * Sequences the kernel driver has okayed for us.  This allows
	 * the driver to do things like prevent initiator or target
	 * operations.
	 */
	SCSISEQ_TEMPLATE {
		size		1
		field	MANUALCTL	0x40
		field	ENSELI		0x20
		field	ENRSELI		0x10
		field	MANUALP		0x0C
		field	ENAUTOATNP	0x02
		field	ALTSTIM		0x01
	}

	/*
	 * The initiator specified tag for this target mode transaction.
	 */
	INITIATOR_TAG {
		size		1
	}

	SEQ_FLAGS2 {
		size		1
		field	PENDING_MK_MESSAGE	0x01
		field	TARGET_MSG_PENDING	0x02
		field	SELECTOUT_QFROZEN	0x04
	}

	ALLOCFIFO_SCBPTR {
		size		2
	}

	/*
	 * The maximum amount of time to wait, when interrupt coalescing
	 * is enabled, before issueing a CMDCMPLT interrupt for a completed
	 * command.
	 */
	INT_COALESCING_TIMER {
		size		2
	}

	/*
	 * The maximum number of commands to coalesce into a single interrupt.
	 * Actually the 2's complement of that value to simplify sequencer
	 * code.
	 */
	INT_COALESCING_MAXCMDS {
		size		1
	}

	/*
	 * The minimum number of commands still outstanding required
	 * to continue coalescing (2's complement of value).
	 */
	INT_COALESCING_MINCMDS {
		size		1
	}

	/*
	 * Number of commands "in-flight".
	 */
	CMDS_PENDING {
		size		2
	}

	/*
	 * The count of commands that have been coalesced.
	 */
	INT_COALESCING_CMDCOUNT {
		size		1
	}

	/*
	 * Since the HS_MAIBOX is self clearing, copy its contents to
	 * this position in scratch ram every time it changes.
	 */
	LOCAL_HS_MAILBOX {
		size		1
	}
	/*
	 * Target-mode CDB type to CDB length table used
	 * in non-packetized operation.
	 */
	CMDSIZE_TABLE {
		size		8
	}
	/*
	 * When an SCB with the MK_MESSAGE flag is
	 * queued to the controller, it cannot enter
	 * the waiting for selection list until the
	 * selections for any previously queued
	 * commands to that target complete.  During
	 * the wait, the MK_MESSAGE SCB is queued
	 * here.
	 */
	MK_MESSAGE_SCB {
		size		2
	}
	/*
	 * Saved SCSIID of MK_MESSAGE_SCB to avoid
	 * an extra SCBPTR operation when deciding
	 * if the MK_MESSAGE_SCB can be run.
	 */
	MK_MESSAGE_SCSIID {
		size		1
	}
}

/************************* Hardware SCB Definition ****************************/
scb {
	address			0x180
	size	64
	modes	0, 1, 2, 3
	SCB_RESIDUAL_DATACNT {
		size	4
		alias	SCB_CDB_STORE
		alias	SCB_HOST_CDB_PTR
	}
	SCB_RESIDUAL_SGPTR {
		size	4
		field	SG_ADDR_MASK		0xf8	/* In the last byte */
		field	SG_OVERRUN_RESID	0x02	/* In the first byte */
		field	SG_LIST_NULL		0x01	/* In the first byte */
	}
	SCB_SCSI_STATUS {
		size	1
		alias	SCB_HOST_CDB_LEN
	}
	SCB_TARGET_PHASES {
		size	1
	}
	SCB_TARGET_DATA_DIR {
		size	1
	}
	SCB_TARGET_ITAG {
		size	1
	}
	SCB_SENSE_BUSADDR {
		/*
		 * Only valid if CDB length is less than 13 bytes or
		 * we are using a CDB pointer.  Otherwise contains
		 * the last 4 bytes of embedded cdb information.
		 */
		size	4
		alias	SCB_NEXT_COMPLETE
	}
	SCB_TAG {
		alias	SCB_FIFO_USE_COUNT
		size	2
	}
	SCB_CONTROL {
		size	1
		field	TARGET_SCB	0x80
		field	DISCENB		0x40
		field	TAG_ENB		0x20
		field	MK_MESSAGE	0x10
		field	STATUS_RCVD	0x08
		field	DISCONNECTED	0x04
		field	SCB_TAG_TYPE	0x03
	}
	SCB_SCSIID {
		size	1
		field	TID	0xF0
		field	OID	0x0F
	}
	SCB_LUN {
		size	1
		field	LID	0xff
	}
	SCB_TASK_ATTRIBUTE {
		size	1
		/*
		 * Overloaded field for non-packetized 
		 * ignore wide residue message handling.
		 */
		field	SCB_XFERLEN_ODD	0x01
	}
	SCB_CDB_LEN {
		size	1
		field	SCB_CDB_LEN_PTR	0x80	/* CDB in host memory */
	}
	SCB_TASK_MANAGEMENT {
		size	1
	}
	SCB_DATAPTR {
		size	8
	}
	SCB_DATACNT {
		/*
		 * The last byte is really the high address bits for
		 * the data address.
		 */
		size	4
		field	SG_LAST_SEG		0x80	/* In the fourth byte */
		field	SG_HIGH_ADDR_BITS	0x7F	/* In the fourth byte */
	}
	SCB_SGPTR {
		size	4
		field	SG_STATUS_VALID	0x04	/* In the first byte */
		field	SG_FULL_RESID	0x02	/* In the first byte */
		field	SG_LIST_NULL	0x01	/* In the first byte */
	}
	SCB_BUSADDR {
		size	4
	}
	SCB_NEXT {
		alias	SCB_NEXT_SCB_BUSADDR
		size	2
	}
	SCB_NEXT2 {
		size	2
	}
	SCB_SPARE {
		size	8
		alias	SCB_PKT_LUN
	}
	SCB_DISCONNECTED_LISTS {
		size	8
	}
}

/*********************************** Constants ********************************/
const MK_MESSAGE_BIT_OFFSET	4
const TID_SHIFT		4
const TARGET_CMD_CMPLT	0xfe
const INVALID_ADDR	0x80
#define SCB_LIST_NULL	0xff
#define QOUTFIFO_ENTRY_VALID_TOGGLE	0x80

const CCSGADDR_MAX	0x80
const CCSCBADDR_MAX	0x80
const CCSGRAM_MAXSEGS	16

/* Selection Timeout Timer Constants */
const STIMESEL_SHIFT	3
const STIMESEL_MIN	0x18
const STIMESEL_BUG_ADJ	0x8

/* WDTR Message values */
const BUS_8_BIT			0x00
const BUS_16_BIT		0x01
const BUS_32_BIT		0x02

/* Offset maximums */
const MAX_OFFSET		0xfe
const MAX_OFFSET_PACED		0xfe
const MAX_OFFSET_PACED_BUG	0x7f
/*
 * Some 160 devices incorrectly accept 0xfe as a
 * sync offset, but will overrun this value.  Limit
 * to 0x7f for speed lower than U320 which will
 * avoid the persistent sync offset overruns.
 */
const MAX_OFFSET_NON_PACED	0x7f
const HOST_MSG			0xff

/*
 * The size of our sense buffers.
 * Sense buffer mapping can be handled in either of two ways.
 * The first is to allocate a dmamap for each transaction.
 * Depending on the architecture, dmamaps can be costly. The
 * alternative is to statically map the buffers in much the same
 * way we handle our scatter gather lists.  The driver implements
 * the later.
 */
const AHD_SENSE_BUFSIZE		256

/* Target mode command processing constants */
const CMD_GROUP_CODE_SHIFT	0x05

const STATUS_BUSY		0x08
const STATUS_QUEUE_FULL		0x28
const STATUS_PKT_SENSE		0xFF
const TARGET_DATA_IN		1

const SCB_TRANSFER_SIZE_FULL_LUN	56
const SCB_TRANSFER_SIZE_1BYTE_LUN	48
/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
const PKT_OVERRUN_BUFSIZE	512

/*
 * Timer parameters.
 */
const AHD_TIMER_US_PER_TICK	25
const AHD_TIMER_MAX_TICKS	0xFFFF
const AHD_TIMER_MAX_US		(AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)

/*
 * Downloaded (kernel inserted) constants
 */
const SG_PREFETCH_CNT download
const SG_PREFETCH_CNT_LIMIT download
const SG_PREFETCH_ALIGN_MASK download
const SG_PREFETCH_ADDR_MASK download
const SG_SIZEOF download
const PKT_OVERRUN_BUFOFFSET download
const SCB_TRANSFER_SIZE	download
const CACHELINE_MASK download

/*
 * BIOS SCB offsets
 */
const NVRAM_SCB_OFFSET	0x2C