/*
 * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <nvgpu/pmu.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include <nvgpu/gk20a.h>

#include "clk.h"
#include "ctrl/ctrlclk.h"
#include "ctrl/ctrlvolt.h"
#include "volt/volt.h"

#define BOOT_GPC2CLK_MHZ  2581
#define BOOT_MCLK_MHZ     3003

struct clkrpc_pmucmdhandler_params {
	struct nv_pmu_clk_rpc *prpccall;
	u32 success;
};

static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
				 void *param, u32 handle, u32 status)
{
	struct clkrpc_pmucmdhandler_params *phandlerparams =
		(struct clkrpc_pmucmdhandler_params *)param;

	nvgpu_log_info(g, " ");

	if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) {
		nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x",
			  msg->msg.clk.msg_type);
		return;
	}

	if (phandlerparams->prpccall->b_supported) {
		phandlerparams->success = 1;
	}
}


int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload)
{
	struct pmu_cmd cmd;
	struct pmu_payload payload;
	u32 status;
	u32 seqdesc;
	struct nv_pmu_clk_rpc rpccall;
	struct clkrpc_pmucmdhandler_params handler;
	struct nv_pmu_clk_load *clkload;

	memset(&payload, 0, sizeof(struct pmu_payload));
	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
	memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
	memset(&cmd, 0, sizeof(struct pmu_cmd));

	rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
	clkload = &rpccall.params.clk_load;
	clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_EFFECTIVE_AVG;
	clkload->action_mask = bload ?
		NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_YES :
		NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_NO;

	cmd.hdr.unit_id = PMU_UNIT_CLK;
	cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +
			(u32)sizeof(struct pmu_hdr);

	cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;

	payload.in.buf = (u8 *)&rpccall;
	payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;

	payload.out.buf = (u8 *)&rpccall;
	payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;

	handler.prpccall = &rpccall;
	handler.success = 0;

	status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
			PMU_COMMAND_QUEUE_LPQ,
			clkrpc_pmucmdhandler, (void *)&handler,
			&seqdesc, ~0);
	if (status) {
		nvgpu_err(g, "unable to post clk RPC cmd %x",
			cmd.cmd.clk.cmd_type);
		goto done;
	}

	pmu_wait_message_cond(&g->pmu,
			gk20a_get_gr_idle_timeout(g),
			&handler.success, 1);
	if (handler.success == 0) {
		nvgpu_err(g, "rpc call to load Effective avg clk domain freq failed");
		status = -EINVAL;
	}

done:
	return status;
}

u32 clk_freq_effective_avg(struct gk20a *g, u32  clkDomainMask) {

	struct pmu_cmd cmd;
	struct pmu_payload payload;
	u32 status;
	u32 seqdesc;
	struct nv_pmu_clk_rpc rpccall;
	struct clkrpc_pmucmdhandler_params handler;
	struct nv_pmu_clk_freq_effective_avg *clk_freq_effective_avg;

	memset(&payload, 0, sizeof(struct pmu_payload));
	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
	memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
	memset(&cmd, 0, sizeof(struct pmu_cmd));

	rpccall.function = NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG;
	clk_freq_effective_avg = &rpccall.params.clk_freq_effective_avg;
	clk_freq_effective_avg->clkDomainMask = clkDomainMask;

	cmd.hdr.unit_id = PMU_UNIT_CLK;
	cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +
			(u32)sizeof(struct pmu_hdr);

	cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;

	payload.in.buf = (u8 *)&rpccall;
	payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;

	payload.out.buf = (u8 *)&rpccall;
	payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;

	handler.prpccall = &rpccall;
	handler.success = 0;

	status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
			PMU_COMMAND_QUEUE_LPQ,
			clkrpc_pmucmdhandler, (void *)&handler,
			&seqdesc, ~0);
	if (status) {
		nvgpu_err(g, "unable to post clk RPC cmd %x",
			cmd.cmd.clk.cmd_type);
		goto done;
	}

	pmu_wait_message_cond(&g->pmu,
			gk20a_get_gr_idle_timeout(g),
			&handler.success, 1);
	if (handler.success == 0) {
		nvgpu_err(g, "rpc call to get clk frequency average failed");
		status = -EINVAL;
		goto done;
	}

	return rpccall.params.clk_freq_effective_avg.freqkHz[clkDomainMask];

done:
	return status;
}

int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
{
	struct pmu_cmd cmd;
	struct pmu_payload payload;
	u32 status;
	u32 seqdesc;
	struct nv_pmu_clk_rpc rpccall;
	struct clkrpc_pmucmdhandler_params handler;
	struct nv_pmu_clk_load *clkload;
	struct clk_freq_controllers *pclk_freq_controllers;
	struct ctrl_boardobjgrp_mask_e32 *load_mask;
	struct boardobjgrpmask_e32 isolate_cfc_mask;

	memset(&payload, 0, sizeof(struct pmu_payload));
	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
	memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));

	pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
	rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
	clkload = &rpccall.params.clk_load;
	clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER;
	clkload->action_mask = bload ?
		NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES :
		NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO;

	load_mask = &rpccall.params.clk_load.payload.freq_controllers.load_mask;

	status = boardobjgrpmask_e32_init(&isolate_cfc_mask, NULL);

	if (bit_idx == CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL) {
		status = boardobjgrpmask_export(
				&pclk_freq_controllers->
					freq_ctrl_load_mask.super,
				pclk_freq_controllers->
					freq_ctrl_load_mask.super.bitcount,
				&load_mask->super);


	} else {
		status = boardobjgrpmask_bitset(&isolate_cfc_mask.super,
						bit_idx);
		status = boardobjgrpmask_export(&isolate_cfc_mask.super,
					isolate_cfc_mask.super.bitcount,
					&load_mask->super);
		if (bload) {
			status = boardobjgrpmask_bitset(
					&pclk_freq_controllers->
						freq_ctrl_load_mask.super,
					bit_idx);
		} else {
			status = boardobjgrpmask_bitclr(
					&pclk_freq_controllers->
						freq_ctrl_load_mask.super,
					bit_idx);
		}
	}

	if (status) {
		nvgpu_err(g, "Error in generating mask used to select CFC");
		goto done;
	}

	cmd.hdr.unit_id = PMU_UNIT_CLK;
	cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +
			(u32)sizeof(struct pmu_hdr);

	cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;

	payload.in.buf = (u8 *)&rpccall;
	payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;

	payload.out.buf = (u8 *)&rpccall;
	payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;

	handler.prpccall = &rpccall;
	handler.success = 0;
	status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
			PMU_COMMAND_QUEUE_LPQ,
			clkrpc_pmucmdhandler, (void *)&handler,
			&seqdesc, ~0);

	if (status) {
		nvgpu_err(g, "unable to post clk RPC cmd %x",
			cmd.cmd.clk.cmd_type);
		goto done;
	}

	pmu_wait_message_cond(&g->pmu,
			gk20a_get_gr_idle_timeout(g),
			&handler.success, 1);

	if (handler.success == 0) {
		nvgpu_err(g, "rpc call to load freq cntlr cal failed");
		status = -EINVAL;
	}

done:
	return status;
}

u32 clk_pmu_vin_load(struct gk20a *g)
{
	struct pmu_cmd cmd;
	struct pmu_payload payload;
	u32 status;
	u32 seqdesc;
	struct nv_pmu_clk_rpc rpccall;
	struct clkrpc_pmucmdhandler_params handler;
	struct nv_pmu_clk_load *clkload;

	memset(&payload, 0, sizeof(struct pmu_payload));
	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
	memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));

	rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
	clkload = &rpccall.params.clk_load;
	clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN;
	clkload->action_mask = NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES << 4;

	cmd.hdr.unit_id = PMU_UNIT_CLK;
	cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +
			(u32)sizeof(struct pmu_hdr);

	cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
	cmd.cmd.clk.generic.b_perf_daemon_cmd =false;

	payload.in.buf = (u8 *)&rpccall;
	payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;

	payload.out.buf = (u8 *)&rpccall;
	payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
	payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
	payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;

	handler.prpccall = &rpccall;
	handler.success = 0;
	status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
			PMU_COMMAND_QUEUE_LPQ,
			clkrpc_pmucmdhandler, (void *)&handler,
			&seqdesc, ~0);

	if (status) {
		nvgpu_err(g, "unable to post clk RPC cmd %x",
			cmd.cmd.clk.cmd_type);
		goto done;
	}

	pmu_wait_message_cond(&g->pmu,
			gk20a_get_gr_idle_timeout(g),
			&handler.success, 1);

	if (handler.success == 0) {
		nvgpu_err(g, "rpc call to load vin cal failed");
		status = -EINVAL;
	}

done:
	return status;
}

u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
	struct nv_pmu_clk_rpc *rpccall,
	struct set_fll_clk *setfllclk)
{
	struct nv_pmu_clk_vf_change_inject *vfchange;

	vfchange = &rpccall->params.clk_vf_change_inject;
	vfchange->flags = 0;
	vfchange->clk_list.num_domains = 3;
	vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPC2CLK;
	vfchange->clk_list.clk_domains[0].clk_freq_khz =