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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915: Do not clobber the contents of TRANS_DP_CTL when enabling.Chris Wilson2010-08-09
| | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge remote branch 'origin/master' into drm-intel-nextEric Anholt2010-08-01
|\ | | | | | | | | | | | | | | This resolves the conflict in the EDP code, which has been rather popular to hack on recently. Conflicts: drivers/gpu/drm/i915/intel_dp.c
| * Merge branch 'for-linus' of ↵Linus Torvalds2010-07-26
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: add pipe A force quirks to i915 driver drm/i915: Fix panel fitting regression since 734b4157 drm/i915: fix deadlock in fb teardown drm/i915: don't free non-existent compressed llb on ILK+ agp/intel: Use the correct mask to detect i830 aperture size. drm/i915: disable FBC when more than one pipe is active drm/i915: Use the correct scanout alignment for fbcon. drm/i915: make sure eDP panel is turned on drm/i915: add PANEL_UNLOCK_REGS definition drm/i915: Make G4X-style PLL search more permissive drm/i915: Clear any existing dither mode prior to enabling spatial dithering drm/i915: handle shared framebuffers when flipping drm/i915: Explosion following OOM in do_execbuffer. gpu/drm/i915: Add a blacklist to omit modeset on LID open
| | * drm/i915: add PANEL_UNLOCK_REGS definitionJesse Barnes2010-07-26
| | | | | | | | | | | | | | | | | | | | | | | | In some cases, unlocking the panel regs is safe and can help us avoid a flickery, full mode set sequence. So define the unlock key and use it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: Typo in #defineNicolas Kaiser2010-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | checkpatch complains about this define: WARNING: space prohibited between function name and open parenthesis '(' +#define GEN6_RENDER TIMEOUT_COUNTER_EXPIRED (1 << 6) Signed-off-by: Nicolas Kaiser <nikai@nikai.net> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: Add frame buffer compression support on Ironlake mobileZhao Yakui2010-08-01
| | | | | | | | | | | | | | | | | | | | | | | | About 0.2W power can be saved on one HP laptop. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: Calculate cursor watermark under non-SR state for IronlakeZhao Yakui2010-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware team suggest that the "large buffer" method should be used to calculate the cursor watermark under non-SR state as well, which is to avoid the flicker when FBC is enabled on Ironlake. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: Apply self-refresh watermark calculation for cursor planeZhao Yakui2010-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | In SR mode cursor plane watermark calculation uses same formula like display plane. This one fixes the case for 965G and G45. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: Fix fifo size for self-refresh watermark on 965GZhao Yakui2010-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The total self-refresh fifo entry size for display plane is 512 instead of 128 for 965G. Also fix WM value mask for 965G. About 1.0W power can be saved on one T61 laptop after the self-refresh watermark is configured correctly. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | drm/i915: remove duplicate PIPE*STAT bit definitionsJesse Barnes2010-08-01
|/ / | | | | | | | | | | | | Having two sets has made me think I caught a bug more than once now. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* / drm/i915: Define MI_ARB_STATE bitsKeith Packard2010-07-20
|/ | | | | | | | | The i915 memory arbiter has a register full of configuration bits which are currently not defined in the driver header file. Signed-off-by: Keith Packard <keithp@keithp.com> cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/i915: Fix CRT hotplug regression in 2.6.35-rc1Andy Lutomirski2010-07-01
| | | | | | | | | | | | | | | | | | | | Commit 7a772c492fcfffae812ffca78a628e76fa57fe58 has two bugs which made the hotplug problems on my laptop worse instead of better. First, it did not, in fact, disable the CRT plug interrupt -- it disabled all the other hotplug interrupts. It seems rather doubtful that that bit of the patch fixed anything, so let's just remove it. (If you want to add it back, you probably meant ~CRT_HOTPLUG_INT_EN.) Second, on at least my GM45, setting CRT_HOTPLUG_ACTIVATION_PERIOD_64 and CRT_HOTPLUG_VOLTAGE_COMPARE_50 (when they were previously unset) causes a hotplug interrupt about three seconds later. The old code never restored PORT_HOTPLUG_EN so this could only happen once, but they new code restores those registers. So just set those bits when we set up the interrupt in the first place. Signed-off-by: Andy Lutomirski <luto@mit.edu> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: gen3 page flipping fixesJesse Barnes2010-06-18
| | | | | | | | | | | | | Gen3 chips have slightly different flip commands, and also contain a bit that indicates whether a "flip pending" interrupt means the flip has been queued or has been completed. So implement support for the gen3 flip command, and make sure we use the flip pending interrupt correctly depending on the value of ECOSKPD bit 0. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Unmask interrupt for render engine on SandybridgeZhenyu Wang2010-05-28
| | | | | | | | | With splitted engines on Sandybridge, each engine has its own interrupt control as well. This unmasks the interrupt to properly enable pipe control notify event for render engine. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add CxSR support on Pineview DDR3Li Peng2010-05-26
| | | | | | | | | | | | Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix HDMI mode select for Cougarpoint PCHZhenyu Wang2010-05-26
| | | | | | | | | | | | For real HDMI sink, CPT HDMI port has to set 'HDMI' mode flag in order to make HDMI audio work correctly. This is required patch for drm/i915 to enable HDMI audio on CPT PCH, ALSA patch is at http://mailman.alsa-project.org/pipermail/alsa-devel/2010-May/027601.html Tested-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add power monitoring supportJesse Barnes2010-05-26
| | | | | | | | | | | | Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: Fixed 32-bit compile. stupid obfuscating div_u64()] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915/gen4: Extra CRT hotplug paranoiaAdam Jackson2010-05-26
| | | | | | | | | Disable the CRT plug interrupt while doing the force cycle, explicitly clear any CRT interrupt we may have generated, and restore when done. Should mitigate interrupt storms from hotplug detection. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: implement BSD ring buffer V2Zou Nan hai2010-05-26
| | | | | | | | | | | The BSD (bit stream decoder) ring is used for accessing the BSD engine which decodes video bitstream for H.264 and VC1 on G45+. It is asynchronous with the render ring and has access to separate parts of the GPU from it, though the render cache is coherent between the two. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge remote branch 'origin/master' into drm-intel-nextEric Anholt2010-05-10
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/radeon/r300.c The BSD ringbuffer support that is landing in this branch significantly conflicts with the Ironlake PIPE_CONTROL fix on master, and requires it to be tested successfully anyway.
| * drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy BridgeJesse Barnes2010-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 965, the hardware has supported the PIPE_CONTROL command, which provides fine grained GPU cache flushing control. On recent chipsets, this instruction is required for reliable interrupt and sequence number reporting in the driver. So add support for this instruction, including workarounds, on Ironlake and Sandy Bridge hardware. https://bugs.freedesktop.org/show_bug.cgi?id=27108 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: fix tiling limits for i915 class hw v2Daniel Vetter2010-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code is definitely crap: Largest pitch allowed spills into the TILING_Y bit of the fence registers ... :( I've rewritten the limits check under the assumption that 3rd gen hw has a 3d pitch limit of 8kb (like 2nd gen). This is supported by an otherwise totally misleading XXX comment. This bug mostly resulted in tiling-corrupted pixmaps because the kernel allowed too wide buffers to be tiled. Bug brought to the light by the xf86-video-intel 2.11 release because that unconditionally enabled tiling for pixmaps, relying on the kernel to check things. Tiling for the framebuffer was not affected because the ddx does some additional checks there ensure the buffer is within hw-limits. v2: Instead of computing the value that would be written into the hw fence registers and then checking the limits simply check whether the stride is above the 8kb limit. To better document the hw, add some WARN_ONs in i915_write_fence_reg like I've done for the i830 case (using the right limits). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27449 Tested-by: Alexander Lam <lambchop468@gmail.com> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Use spatio-temporal dithering on PCHAdam Jackson2010-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spatial dither is better than nothing, but ST is even better. (from ajax's followup message:) I noticed this with: http://ajax.fedorapeople.org/YellowFlower.jpg set as my desktop background in Gnome on a 1280x800 machine (in particular, a Sony Vaio VPCB1 with 6-bit panel and a rather bright black level). Easiest way to test this is by poking at PIPEACONF with intel_reg_write directly: % sudo intel_reg_write 0x70008 0xc0000040 # no dither % sudo intel_reg_write 0x70008 0xc0000050 # spatial % sudo intel_reg_write 0x70008 0xc0000054 # ST I notice it especially strongly in the relatively flat dark area in the top left. Closer than about 18" I can see a noticeable checkerboard pattern with plain spatial dithering. ST smooths that out; I can still tell that it's lacking color precision, but it's not offensive. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Add the support of memory self-refresh on IronlakeZhenyu Wang2010-04-12
| | | | | | | | | | | | | | | | | | | | | | | | Update the self-refresh watermark for display plane/cursor and enable the memory self-refresh on Ironlake. The watermark is also updated for the active display plane. More than 1W idle power is saved on one Ironlake laptop after enabling memory self-refresh. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
* | drm/i915: Move Pineview CxSR and watermark code into update_wm hook.Zhao Yakui2010-04-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, after setting up the Pineview CxSR state, i9xx_update_wm would get called and overwrite our state. BTW: We will disable the self-refresh and never enable it any more if we can't find the appropriate the latency on pineview plaftorm. In such case the update_wm callback will be NULL. The bitmask macro is also defined to access the corresponding fifo watermark register. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
* | drm/i915: Add support of SDVO on Ibexpeak PCHZhao Yakui2010-04-12
| | | | | | | | | | | | | | | | SDVO on Ibexpeak PCH with Ironlake is multiplexed with HDMIB port, and only has SDVOB port. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
* | drm/i915: Support for Cougarpoint PCH display pipelineZhenyu Wang2010-04-12
|/ | | | | | | | | | | | | | | | Cougarpoint is the new PCH for Sandybridge CPU. This one resolves the chipset change for display pipeline compared to previous Ibexpeak PCH. Sandybridge/Cougarpoint has different FDI training parameters, so this also makes seperate FDI training functions for IBX and CPT. Other change includes new transcoder DPLL select function to set which DPLL for transcoder to pick up. And with another new transcoder C introduced in Cougarpoint, each connector has new transcoder select bits. This one adds that change to light up VGA. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.Eric Anholt2010-03-18
| | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Enable VS timer dispatch.Eric Anholt2010-03-17
| | | | | | | | | | | This could resolve HW deadlocks where a unit downstream of the VS is waiting for more input, the VS has one vertex queued up but not dispatched because it hopes to get one more vertex for 2x4 dispatch, and software isn't handing more vertices down because it's waiting for rendering to complete. The B-Spec says you should always have this bit set. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Rename FBC_C3_IDLE to FBC_CTL_C3_IDLE to match other registersPriit Laes2010-03-17
| | | | | Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915, agp/intel: Fix stolen memory size on SandybridgeZhenyu Wang2010-02-26
| | | | | | | | New memory control config reg at 0x50 should be used for stolen memory size detection on Sandybridge. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix sandybridge status page setup.Eric Anholt2010-02-26
| | | | | | The register's moved to the same location as the one for the BCS, it seems. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Set up fence registers on sandybridge.Eric Anholt2010-02-26
| | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Record batch buffer following GPU errorChris Wilson2010-02-22
| | | | | | | | | | | | | | | | | | | | | | In order to improve our diagnostic capabilities following a GPU hang and subsequent reset, we need to record the batch buffer that triggered the error. We assume that the current batch buffer, plus a few details about what else is on the active list, will be sufficient -- at the very least an improvement over nothing. The extra information is stored in /debug/dri/.../i915_error_state following an error, and may be decoded using intel_gpu_tools/tools/intel_error_decode. v2: Avoid excessive work under spinlocks. v3: Include ringbuffer for later analysis. v4: Use kunmap correctly and record more buffer state. v5: Search ringbuffer for current batch buffer v6: Use a work fn for the impossible IRQ error case. v7: Avoid non-atomic paths whilst in IRQ context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Deobfuscate the render p-state obfuscationMatthew Garrett2010-02-22
| | | | | | | | The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add dynamic performance control support for IronlakeJesse Barnes2010-02-22
| | | | | | | | | | | | | | | | | Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: ykzhao <yakui.zhao@intel.com> [anholt: Resolved against the irq handler loop removal] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: enable memory self refresh on 9xxLi Peng2010-02-22
| | | | | | | | | | | | | | | | | | | Enabling memory self refresh (SR) on 9xx needs to set additional register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the write to self refresh bit and bit 16 to enable the write of self refresh watermark. On 915, bit 12 of INSTPM is used to enable SR. SR will take effect when CPU enters C3+ state and its entry/exit should be automatically controlled by H/W, driver only needs to set SR enable bits in wm update. But this isn't safe in my test on 945 because GPU is hung. So this patch explicitly enables SR when GPU is idle, and disables SR when it is busy. In my test on a netbook of 945GSE chipset, it saves about 0.8W idle power. Signed-off-by: Li Peng <peng.li@intel.com> [anholt: rebased against 33c5fd121eabbccc9103daf6cda36941eb3c349f by adding disable of INSTPM SR bit on 915GM for two pipe setup] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: handle FBC and self-refresh betterJesse Barnes2010-02-10
| | | | | | | | | | | | | On 945, we need to avoid entering self-refresh if the compressor is busy, or we may cause display FIFO underruns leading to ugly flicker. Fixes fdo bug #24314, kernel bug #15043. Tested-by: Alexander Lam <lambchop468@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Julien Cristau <jcristau@debian.org> (fd.o #25371) Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix the incorrect cursor A bit definition in DSPFW2 registerZhao Yakui2010-01-15
| | | | | | Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Enable/disable the dithering for LVDS based on VBT settingZhao Yakui2010-01-06
| | | | | | | | | Enable/disable the dithering for LVDS based on VBT setting. On the 965/g4x platform the dithering flag is defined in LVDS register. And on the ironlake the dithering flag is defined in pipeconf register. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: only enable hotplug for detected outputsJesse Barnes2009-12-16
| | | | | | | | | | | | This patch changes around our hotplug enable code a bit to only enable it for ports we actually detect and initialize. This prevents problems with stuck or spurious interrupts on outputs that aren't actually wired up, and is generally more correct. Fixes FDO bug #23183. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix product names and #definesAdam Jackson2009-12-07
| | | | | | | | | IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.Eric Anholt2009-12-01
| | | | | | | | This is a sync of a fix I made in the old UMS code. If the BIOS uses the GMBUS and doesn't clear that setup, then our bit-banging I2C can fail, leading to monitors not being detected. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: disable the interrupt hotplug for integrated TV outputAdam Jackson2009-12-01
| | | | | | | | | | | | | Otherwise, I'd get stuck in a loop where (afaict) output scan would trigger a TV interrupt, which would trigger a scan, etc. TV load detection not being the fastest thing in the world, X would process requests very slowly. https://bugs.freedesktop.org/show_bug.cgi?id=24404 Signed-off-by: Adam Jackson <ajax@redhat.com> Acked-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add intel implementation of the pageflip ioctlKristian Høgsberg2009-12-01
| | | | | | | | | Acked-by: Jakob Bornecrantz <jakob@vmware.com> Acked-by: Thomas Hellström <thomas@shipmail.org> Review-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse "Orange Smoothie" Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: remove Pineview EOS protection supportShaohua Li2009-11-30
| | | | | | | | | | | | | HW guys have an evaluation about the impact about EOS, and say the impact is quite small, so they have removed EOS detection support. This patch removes EOS feature. revert commit 043029655816ed4cfc2ed247020ef97e5d637392 directly reverting it gives a hunk error, so please use this one. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net> [anholt: fixed up commit message for update that the feature's really gone]
* drm/i915: Add display hotplug event on IronlakeZhenyu Wang2009-11-05
| | | | | | | Enable display hotplug irqs from Ibex Peak (PCH). Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Support 30 bit depth modesKristian Høgsberg2009-11-05
| | | | | Signed-off-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: implement drmmode overlay support v4Daniel Vetter2009-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements intel overlay support for kms via a device-specific ioctl. Thomas Hellstrom brought up the idea of a general ioctl (on dri-devel). We've reached the conclusion that such an infrastructure only makes sense when multiple kms overlay implementations exists, which atm don't (and it doesn't look like this is gonna change). Open issues: - Runs in sync with the gpu, i.e. unnecessary waiting. I've decided to wait on this because the hw tends to hang when changing something in this area. I left some dummy functions as infrastructure. - polyphase filtering uses a static table. - uses uninterruptible sleeps. Unfortunately the alternatives may unnecessarily wedged the hw if/when we timeout too early (and userspace only overloaded the batch buffers with stuff worth a few secs of gpu time). Changes since v1: - fix off-by-one misconception on my side. This fixes fullscreen playback. Changes since v2: - add underrun detection as spec'ed for i965. - flush caches properly, fixing visual corruptions. Changes since v4: - fix up cache flushing of overlay memory regs. - killed require_pipe_a logic - it hangs the chip. Tested-By: diego.abelenda@gmail.com (on a 865G) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [anholt: Resolved against the MADVISE ioctl going in before this one] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add render standby supportJesse Barnes2009-11-05
| | | | | | | | | | Render standy allows the GPU to power down the render unit when idle. In order for this to work, it needs a page of graphics memory to save state. This patch allocates that page and enables the feature on supported chipsets. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
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