diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-05-20 17:28:11 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-05-26 17:10:01 -0400 |
commit | 7648fa99eb77a2e1a90b7beaa420e07d819b9c11 (patch) | |
tree | 29991eba782a22922441813dcc3a5cbde8377119 /drivers/gpu/drm/i915/i915_reg.h | |
parent | 7a772c492fcfffae812ffca78a628e76fa57fe58 (diff) |
drm/i915: add power monitoring support
Add power monitoring support to the i915 driver for use by the IPS
driver. Export the available power info to the IPS driver through a few
new inter-driver hooks. When used together, the IPS driver and this
patch can significantly increase graphics performance on Ironlake class
chips.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Fixed 32-bit compile. stupid obfuscating div_u64()]
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7a726840efa..df7224de0ae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -838,6 +838,12 @@ | |||
838 | #define CLKCFG_MEM_800 (3 << 4) | 838 | #define CLKCFG_MEM_800 (3 << 4) |
839 | #define CLKCFG_MEM_MASK (7 << 4) | 839 | #define CLKCFG_MEM_MASK (7 << 4) |
840 | 840 | ||
841 | #define TR1 0x11006 | ||
842 | #define TSFS 0x11020 | ||
843 | #define TSFS_SLOPE_MASK 0x0000ff00 | ||
844 | #define TSFS_SLOPE_SHIFT 8 | ||
845 | #define TSFS_INTR_MASK 0x000000ff | ||
846 | |||
841 | #define CRSTANDVID 0x11100 | 847 | #define CRSTANDVID 0x11100 |
842 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ | 848 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ |
843 | #define PXVFREQ_PX_MASK 0x7f000000 | 849 | #define PXVFREQ_PX_MASK 0x7f000000 |
@@ -976,6 +982,41 @@ | |||
976 | #define MEMSTAT_SRC_CTL_STDBY 3 | 982 | #define MEMSTAT_SRC_CTL_STDBY 3 |
977 | #define RCPREVBSYTUPAVG 0x113b8 | 983 | #define RCPREVBSYTUPAVG 0x113b8 |
978 | #define RCPREVBSYTDNAVG 0x113bc | 984 | #define RCPREVBSYTDNAVG 0x113bc |
985 | #define SDEW 0x1124c | ||
986 | #define CSIEW0 0x11250 | ||
987 | #define CSIEW1 0x11254 | ||
988 | #define CSIEW2 0x11258 | ||
989 | #define PEW 0x1125c | ||
990 | #define DEW 0x11270 | ||
991 | #define MCHAFE 0x112c0 | ||
992 | #define CSIEC 0x112e0 | ||
993 | #define DMIEC 0x112e4 | ||
994 | #define DDREC 0x112e8 | ||
995 | #define PEG0EC 0x112ec | ||
996 | #define PEG1EC 0x112f0 | ||
997 | #define GFXEC 0x112f4 | ||
998 | #define RPPREVBSYTUPAVG 0x113b8 | ||
999 | #define RPPREVBSYTDNAVG 0x113bc | ||
1000 | #define ECR 0x11600 | ||
1001 | #define ECR_GPFE (1<<31) | ||
1002 | #define ECR_IMONE (1<<30) | ||
1003 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ | ||
1004 | #define OGW0 0x11608 | ||
1005 | #define OGW1 0x1160c | ||
1006 | #define EG0 0x11610 | ||
1007 | #define EG1 0x11614 | ||
1008 | #define EG2 0x11618 | ||
1009 | #define EG3 0x1161c | ||
1010 | #define EG4 0x11620 | ||
1011 | #define EG5 0x11624 | ||
1012 | #define EG6 0x11628 | ||
1013 | #define EG7 0x1162c | ||
1014 | #define PXW 0x11664 | ||
1015 | #define PXWL 0x11680 | ||
1016 | #define LCFUSE02 0x116c0 | ||
1017 | #define LCFUSE_HIV_MASK 0x000000ff | ||
1018 | #define CSIPLL0 0x12c10 | ||
1019 | #define DDRMPLL1 0X12c20 | ||
979 | #define PEG_BAND_GAP_DATA 0x14d68 | 1020 | #define PEG_BAND_GAP_DATA 0x14d68 |
980 | 1021 | ||
981 | /* | 1022 | /* |