61 files changed, 49525 insertions, 0 deletions

diff --git a/sound/soc/atmel/playpaq_wm8510.c b/sound/soc/atmel/playpaq_wm8510.c
new file mode 100644
index 00000000000..1aac2f4dbcf
--- /dev/null
+++ b/sound/soc/atmel/playpaq_wm8510.c
@@ -0,0 +1,471 @@
+/* sound/soc/at32/playpaq_wm8510.c
+ * ASoC machine driver for PlayPaq using WM8510 codec
+ *
+ * Copyright (C) 2008 Long Range Systems
+ *    Geoffrey Wossum <gwossum@acm.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
+ *
+ * NOTE: If you don't have the AT32 enhanced portmux configured (which
+ * isn't currently in the mainline or Atmel patched kernel), you will
+ * need to set the MCLK pin (PA30) to peripheral A in your board initialization
+ * code.  Something like:
+ *      at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
+ *
+ */
+
+/* #define DEBUG */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/at32ap700x.h>
+#include <mach/portmux.h>
+
+#include "../codecs/wm8510.h"
+#include "atmel-pcm.h"
+#include "atmel_ssc_dai.h"
+
+
+/*-------------------------------------------------------------------------*\
+ * constants
+\*-------------------------------------------------------------------------*/
+#define MCLK_PIN                GPIO_PIN_PA(30)
+#define MCLK_PERIPH             GPIO_PERIPH_A
+
+
+/*-------------------------------------------------------------------------*\
+ * data types
+\*-------------------------------------------------------------------------*/
+/* SSC clocking data */
+struct ssc_clock_data {
+        /* CMR div */
+        unsigned int cmr_div;
+
+        /* Frame period (as needed by xCMR.PERIOD) */
+        unsigned int period;
+
+        /* The SSC clock rate these settings where calculated for */
+        unsigned long ssc_rate;
+};
+
+
+/*-------------------------------------------------------------------------*\
+ * module data
+\*-------------------------------------------------------------------------*/
+static struct clk *_gclk0;
+static struct clk *_pll0;
+
+#define CODEC_CLK (_gclk0)
+
+
+/*-------------------------------------------------------------------------*\
+ * Sound SOC operations
+\*-------------------------------------------------------------------------*/
+#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
+static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
+        struct snd_pcm_hw_params *params,
+        struct snd_soc_dai *cpu_dai)
+{
+        struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
+        struct ssc_device *ssc = ssc_p->ssc;
+        struct ssc_clock_data cd;
+        unsigned int rate, width_bits, channels;
+        unsigned int bitrate, ssc_div;
+        unsigned actual_rate;
+
+
+        /*
+         * Figure out required bitrate
+         */
+        rate = params_rate(params);
+        channels = params_channels(params);
+        width_bits = snd_pcm_format_physical_width(params_format(params));
+        bitrate = rate * width_bits * channels;
+
+
+        /*
+         * Figure out required SSC divider and period for required bitrate
+         */
+        cd.ssc_rate = clk_get_rate(ssc->clk);
+        ssc_div = cd.ssc_rate / bitrate;
+        cd.cmr_div = ssc_div / 2;
+        if (ssc_div & 1) {
+                /* round cmr_div up */
+                cd.cmr_div++;
+        }
+        cd.period = width_bits - 1;
+
+
+        /*
+         * Find actual rate, compare to requested rate
+         */
+        actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
+        pr_debug("playpaq_wm8510: Request rate = %u, actual rate = %u\n",
+                 rate, actual_rate);
+
+
+        return cd;
+}
+#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
+
+
+
+static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
+                                    struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
+        struct ssc_device *ssc = ssc_p->ssc;
+        unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
+        int ret;
+
+
+        /* Due to difficulties with getting the correct clocks from the AT32's
+         * PLL0, we're going to let the CODEC be in charge of all the clocks
+         */
+#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
+        const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+#else
+        struct ssc_clock_data cd;
+        const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBS_CFS);
+#endif
+
+        if (ssc == NULL) {
+                pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
+                return -EINVAL;
+        }
+
+
+        /*
+         * Figure out PLL and BCLK dividers for WM8510
+         */
+        switch (params_rate(params)) {
+        case 48000:
+                pll_out = 24576000;
+                mclk_div = WM8510_MCLKDIV_2;
+                bclk = WM8510_BCLKDIV_8;
+                break;
+
+        case 44100:
+                pll_out = 22579200;
+                mclk_div = WM8510_MCLKDIV_2;
+                bclk = WM8510_BCLKDIV_8;
+                break;
+
+        case 22050:
+                pll_out = 22579200;
+                mclk_div = WM8510_MCLKDIV_4;
+                bclk = WM8510_BCLKDIV_8;
+                break;
+
+        case 16000:
+                pll_out = 24576000;
+                mclk_div = WM8510_MCLKDIV_6;
+                bclk = WM8510_BCLKDIV_8;
+                break;
+
+        case 11025:
+                pll_out = 22579200;
+                mclk_div = WM8510_MCLKDIV_8;
+                bclk = WM8510_BCLKDIV_8;
+                break;
+
+        case 8000:
+                pll_out = 24576000;
+                mclk_div = WM8510_MCLKDIV_12;
+                bclk = WM8510_BCLKDIV_8;
+                break;
+
+        default:
+                pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
+                           params_rate(params));
+                return -EINVAL;
+        }
+
+
+        /*
+         * set CPU and CODEC DAI configuration
+         */
+        ret = snd_soc_dai_set_fmt(codec_dai, fmt);
+        if (ret < 0) {
+                pr_warning("playpaq_wm8510: "
+                           "Failed to set CODEC DAI format (%d)\n",
+                           ret);
+                return ret;
+        }
+        ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
+        if (ret < 0) {
+                pr_warning("playpaq_wm8510: "
+                           "Failed to set CPU DAI format (%d)\n",
+                           ret);
+                return ret;
+        }
+
+
+        /*
+         * Set CPU clock configuration
+         */
+#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
+        cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
+        pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
+                 cd.cmr_div, cd.period);
+        ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
+        if (ret < 0) {
+                pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
+                           ret);
+                return ret;
+        }
+        ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
+                                          cd.period);
+        if (ret < 0) {
+                pr_warning("playpaq_wm8510: "
+                           "Failed to set CPU transmit period (%d)\n",
+                           ret);
+                return ret;
+        }
+#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
+
+
+        /*
+         * Set CODEC clock configuration
+         */
+        pr_debug("playpaq_wm8510: "
+                 "pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
+                 clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);
+
+
+#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
+        ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
+        if (ret < 0) {
+                pr_warning
+                    ("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
+                     ret);
+                return ret;
+        }
+#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
+
+
+        ret = snd_soc_dai_set_pll(codec_dai, 0, 0,
+                                         clk_get_rate(CODEC_CLK), pll_out);
+        if (ret < 0) {
+                pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
+                           ret);
+                return ret;
+        }
+
+
+        ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
+        if (ret < 0) {
+                pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
+                           ret);
+                return ret;
+        }
+
+
+        return 0;
+}
+
+
+
+static struct snd_soc_ops playpaq_wm8510_ops = {
+        .hw_params = playpaq_wm8510_hw_params,
+};
+
+
+
+static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
+        SND_SOC_DAPM_MIC("Int Mic", NULL),
+        SND_SOC_DAPM_SPK("Ext Spk", NULL),
+};
+
+
+
+static const struct snd_soc_dapm_route intercon[] = {
+        /* speaker connected to SPKOUT */
+        {"Ext Spk", NULL, "SPKOUTP"},
+        {"Ext Spk", NULL, "SPKOUTN"},
+
+        {"Mic Bias", NULL, "Int Mic"},
+        {"MICN", NULL, "Mic Bias"},
+        {"MICP", NULL, "Mic Bias"},
+};
+
+
+
+static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int i;
+
+        /*
+         * Add DAPM widgets
+         */
+        for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
+                snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]);
+
+
+
+        /*
+         * Setup audio path interconnects
+         */
+        snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
+
+
+
+        /* always connected pins */
+        snd_soc_dapm_enable_pin(dapm, "Int Mic");
+        snd_soc_dapm_enable_pin(dapm, "Ext Spk");
+        snd_soc_dapm_sync(dapm);
+
+
+
+        /* Make CSB show PLL rate */
+        snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV,
+                                       WM8510_OPCLKDIV_1 | 4);
+
+        return 0;
+}
+
+
+
+static struct snd_soc_dai_link playpaq_wm8510_dai = {
+        .name = "WM8510",
+        .stream_name = "WM8510 PCM",
+        .cpu_dai_name= "atmel-ssc-dai.0",
+        .platform_name = "atmel-pcm-audio",
+        .codec_name = "wm8510-codec.0-0x1a",
+        .codec_dai_name = "wm8510-hifi",
+        .init = playpaq_wm8510_init,
+        .ops = &playpaq_wm8510_ops,
+};
+
+
+
+static struct snd_soc_card snd_soc_playpaq = {
+        .name = "LRS_PlayPaq_WM8510",
+        .dai_link = &playpaq_wm8510_dai,
+        .num_links = 1,
+};
+
+static struct platform_device *playpaq_snd_device;
+
+
+static int __init playpaq_asoc_init(void)
+{
+        int ret = 0;
+
+        /*
+         * Configure MCLK for WM8510
+         */
+        _gclk0 = clk_get(NULL, "gclk0");
+        if (IS_ERR(_gclk0)) {
+                _gclk0 = NULL;
+                goto err_gclk0;
+        }
+        _pll0 = clk_get(NULL, "pll0");
+        if (IS_ERR(_pll0)) {
+                _pll0 = NULL;
+                goto err_pll0;
+        }
+        if (clk_set_parent(_gclk0, _pll0)) {
+                pr_warning("snd-soc-playpaq: "
+                           "Failed to set PLL0 as parent for DAC clock\n");
+                goto err_set_clk;
+        }
+        clk_set_rate(CODEC_CLK, 12000000);
+        clk_enable(CODEC_CLK);
+
+#if defined CONFIG_AT32_ENHANCED_PORTMUX
+        at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
+#endif
+
+
+        /*
+         * Create and register platform device
+         */
+        playpaq_snd_device = platform_device_alloc("soc-audio", 0);
+        if (playpaq_snd_device == NULL) {
+                ret = -ENOMEM;
+                goto err_device_alloc;
+        }
+
+        platform_set_drvdata(playpaq_snd_device, &snd_soc_playpaq);
+
+        ret = platform_device_add(playpaq_snd_device);
+        if (ret) {
+                pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
+                           ret);
+                goto err_device_add;
+        }
+
+        return 0;
+
+
+err_device_add:
+        if (playpaq_snd_device != NULL) {
+                platform_device_put(playpaq_snd_device);
+                playpaq_snd_device = NULL;
+        }
+err_device_alloc:
+err_set_clk:
+        if (_pll0 != NULL) {
+                clk_put(_pll0);
+                _pll0 = NULL;
+        }
+err_pll0:
+        if (_gclk0 != NULL) {
+                clk_put(_gclk0);
+                _gclk0 = NULL;
+        }
+        return ret;
+}
+
+
+static void __exit playpaq_asoc_exit(void)
+{
+        if (_gclk0 != NULL) {
+                clk_put(_gclk0);
+                _gclk0 = NULL;
+        }
+        if (_pll0 != NULL) {
+                clk_put(_pll0);
+                _pll0 = NULL;
+        }
+
+#if defined CONFIG_AT32_ENHANCED_PORTMUX
+        at32_free_pin(MCLK_PIN);
+#endif
+
+        platform_device_unregister(playpaq_snd_device);
+        playpaq_snd_device = NULL;
+}
+
+module_init(playpaq_asoc_init);
+module_exit(playpaq_asoc_exit);
+
+MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
+MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h
new file mode 100644
index 00000000000..bbea174e3d2
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
+/*
+ * linux/sound/soc/codecs/Patch_base_jazz_Rate48_pps_driver.h
+ *
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+*/
+
+reg_value jazz_A_reg_values[] = {
+};
+#define miniDSP_A_reg_values_COEFF_START   0
+#define miniDSP_A_reg_values_COEFF_SIZE    0
+#define miniDSP_A_reg_values_INST_START    0
+#define miniDSP_A_reg_values_INST_SIZE     0
+
+reg_value jazz_D_reg_values[] = {
+        {0, 0x0},
+        {0x7F, 0x50},
+        { 0, 0x01},
+        { 36, 0xB0},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0xE0},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+        { 44, 0x08},
+        { 45, 0x00},
+        { 46, 0x00},
+        { 47, 0x00},
+        { 48, 0x40},
+        { 49, 0x00},
+        { 50, 0x00},
+        { 51, 0x00},
+        { 52, 0x58},
+        { 53, 0x00},
+        { 54, 0x00},
+        { 55, 0x00},
+        {  0, 0x09},
+        {100, 0xB0},
+        {101, 0x00},
+        {102, 0x00},
+        {103, 0x00},
+        {104, 0xE0},
+        {105, 0x00},
+        {106, 0x00},
+        {107, 0x00},
+        {108, 0x08},
+        {109, 0x00},
+        {110, 0x00},
+        {111, 0x00},
+        {112, 0x40},
+        {113, 0x00},
+        {114, 0x00},
+        {115, 0x00},
+        {116, 0x58},
+        {117, 0x00},
+        {118, 0x00},
+        {119, 0x00},
+        {  0, 0x0},
+        { 0x7F, 0x3C},
+        {  0, 0x01},
+        { 24, 0xB0},
+        { 25, 0x00},
+        { 26, 0x00},
+        { 27, 0x00},
+        { 28, 0xE0},
+        { 29, 0x00},
+        { 30, 0x00},
+        { 31, 0x00},
+        { 32, 0x08},
+        { 33, 0x00},
+        { 34, 0x00},
+        { 35, 0x00},
+        { 36, 0x40},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0x58},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+};
+#define miniDSP_D_reg_values_COEFF_START   0
+#define miniDSP_D_reg_values_COEFF_SIZE    67
+#define miniDSP_D_reg_values_INST_START    67
+#define miniDSP_D_reg_values_INST_SIZE     0
diff --git a/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h
new file mode 100644
index 00000000000..80cc3416c34
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
+/*
+ * linux/sound/soc/codecs/Patch_base_main_Rate48_pps_driver.h
+ *
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+*/
+
+reg_value main_A_reg_values[] = {
+};
+#define miniDSP_A_reg_values_COEFF_START   0
+#define miniDSP_A_reg_values_COEFF_SIZE    0
+#define miniDSP_A_reg_values_INST_START    0
+#define miniDSP_A_reg_values_INST_SIZE     0
+
+reg_value main_D_reg_values[] = {
+        {  0, 0x0},
+        {  0x7F, 0x50},
+        {  0, 0x01},
+        { 36, 0x00},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0x00},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+        { 44, 0x00},
+        { 45, 0x00},
+        { 46, 0x00},
+        { 47, 0x00},
+        { 48, 0x00},
+        { 49, 0x00},
+        { 50, 0x00},
+        { 51, 0x00},
+        { 52, 0x00},
+        { 53, 0x00},
+        { 54, 0x00},
+        { 55, 0x00},
+        {  0, 0x09},
+        {100, 0x00},
+        {101, 0x00},
+        {102, 0x00},
+        {103, 0x00},
+        {104, 0x00},
+        {105, 0x00},
+        {106, 0x00},
+        {107, 0x00},
+        {108, 0x00},
+        {109, 0x00},
+        {110, 0x00},
+        {111, 0x00},
+        {112, 0x00},
+        {113, 0x00},
+        {114, 0x00},
+        {115, 0x00},
+        {116, 0x00},
+        {117, 0x00},
+        {118, 0x00},
+        {119, 0x00},
+        {  0, 0x0},
+        {  0x7F, 0x3C},
+        {  0, 0x01},
+        { 24, 0x00},
+        { 25, 0x00},
+        { 26, 0x00},
+        { 27, 0x00},
+        { 28, 0x00},
+        { 29, 0x00},
+        { 30, 0x00},
+        { 31, 0x00},
+        { 32, 0x00},
+        { 33, 0x00},
+        { 34, 0x00},
+        { 35, 0x00},
+        { 36, 0x00},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0x00},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+};
+#define miniDSP_D_reg_values_COEFF_START   0
+#define miniDSP_D_reg_values_COEFF_SIZE    67
+#define miniDSP_D_reg_values_INST_START    67
+#define miniDSP_D_reg_values_INST_SIZE     0
diff --git a/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h
new file mode 100644
index 00000000000..c2c3d0a1df8
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
+/*
+ * linux/sound/soc/codecs/Patch_base_pop_Rate48_pps_driver.h
+ *
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+*/
+
+reg_value pop_A_reg_values[] = {
+};
+#define miniDSP_A_reg_values_COEFF_START   0
+#define miniDSP_A_reg_values_COEFF_SIZE    0
+#define miniDSP_A_reg_values_INST_START    0
+#define miniDSP_A_reg_values_INST_SIZE     0
+
+reg_value pop_D_reg_values[] = {
+        {  0, 0x0},
+        {  0x7F, 0x50},
+        {  0, 0x01},
+        { 36, 0x40},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0x20},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+        { 44, 0x00},
+        { 45, 0x00},
+        { 46, 0x00},
+        { 47, 0x00},
+        { 48, 0xD8},
+        { 49, 0x00},
+        { 50, 0x00},
+        { 51, 0x00},
+        { 52, 0xB0},
+        { 53, 0x00},
+        { 54, 0x00},
+        { 55, 0x00},
+        {  0, 0x09},
+        {100, 0x40},
+        {101, 0x00},
+        {102, 0x00},
+        {103, 0x00},
+        {104, 0x20},
+        {105, 0x00},
+        {106, 0x00},
+        {107, 0x00},
+        {108, 0x00},
+        {109, 0x00},
+        {110, 0x00},
+        {111, 0x00},
+        {112, 0xD8},
+        {113, 0x00},
+        {114, 0x00},
+        {115, 0x00},
+        {116, 0xB0},
+        {117, 0x00},
+        {118, 0x00},
+        {119, 0x00},
+        {  0, 0x0},
+        {  0x7F, 0x3C},
+        {  0, 0x01},
+        { 24, 0x40},
+        { 25, 0x00},
+        { 26, 0x00},
+        { 27, 0x00},
+        { 28, 0x20},
+        { 29, 0x00},
+        { 30, 0x00},
+        { 31, 0x00},
+        { 32, 0x00},
+        { 33, 0x00},
+        { 34, 0x00},
+        { 35, 0x00},
+        { 36, 0xD8},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0xB0},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+};
+#define miniDSP_D_reg_values_COEFF_START   0
+#define miniDSP_D_reg_values_COEFF_SIZE    67
+#define miniDSP_D_reg_values_INST_START    67
+#define miniDSP_D_reg_values_INST_SIZE     0
diff --git a/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h b/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h
new file mode 100644
index 00000000000..954c7c37478
--- /dev/null
+++ b/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h
@@ -0,0 +1,96 @@
+/*
+ * linux/sound/soc/codecs/Patch_base_rock_Rate48_pps_driver.h
+ *
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+*/
+
+reg_value rock_A_reg_values[] = {
+};
+#define miniDSP_A_reg_values_COEFF_START   0
+#define miniDSP_A_reg_values_COEFF_SIZE    0
+#define miniDSP_A_reg_values_INST_START    0
+#define miniDSP_A_reg_values_INST_SIZE     0
+
+reg_value rock_D_reg_values[] = {
+        {  0, 0x0},
+        {  0x7F, 0x50},
+        {  0, 0x01},
+        { 36, 0x58},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0x30},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+        { 44, 0xD8},
+        { 45, 0x00},
+        { 46, 0x00},
+        { 47, 0x00},
+        { 48, 0xF0},
+        { 49, 0x00},
+        { 50, 0x00},
+        { 51, 0x00},
+        { 52, 0x60},
+        { 53, 0x00},
+        { 54, 0x00},
+        { 55, 0x00},
+        {  0, 0x09},
+        {100, 0x58},
+        {101, 0x00},
+        {102, 0x00},
+        {103, 0x00},
+        {104, 0x30},
+        {105, 0x00},
+        {106, 0x00},
+        {107, 0x00},
+        {108, 0xD8},
+        {109, 0x00},
+        {110, 0x00},
+        {111, 0x00},
+        {112, 0xF0},
+        {113, 0x00},
+        {114, 0x00},
+        {115, 0x00},
+        {116, 0x60},
+        {117, 0x00},
+        {118, 0x00},
+        {119, 0x00},
+        {  0, 0x0},
+        {  0x7F, 0x3C},
+        {  0, 0x01},
+        { 24, 0x58},
+        { 25, 0x00},
+        { 26, 0x00},
+        { 27, 0x00},
+        { 28, 0x30},
+        { 29, 0x00},
+        { 30, 0x00},
+        { 31, 0x00},
+        { 32, 0xD8},
+        { 33, 0x00},
+        { 34, 0x00},
+        { 35, 0x00},
+        { 36, 0xF0},
+        { 37, 0x00},
+        { 38, 0x00},
+        { 39, 0x00},
+        { 40, 0x60},
+        { 41, 0x00},
+        { 42, 0x00},
+        { 43, 0x00},
+};
+#define miniDSP_D_reg_values_COEFF_START   0
+#define miniDSP_D_reg_values_COEFF_SIZE    67
+#define miniDSP_D_reg_values_INST_START    67
+#define miniDSP_D_reg_values_INST_SIZE     0
diff --git a/sound/soc/codecs/ads117x.h b/sound/soc/codecs/ads117x.h
new file mode 100644
index 00000000000..3ce02861400
--- /dev/null
+++ b/sound/soc/codecs/ads117x.h
@@ -0,0 +1,13 @@
+/*
+ * ads117x.h  --  Driver for ads1174/8 ADC chips
+ *
+ * Copyright 2009 ShotSpotter Inc.
+ * Author: Graeme Gregory <gg@slimlogic.co.uk>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+extern struct snd_soc_dai_driver ads117x_dai;
+extern struct snd_soc_codec_driver soc_codec_dev_ads117x;
diff --git a/sound/soc/codecs/aic326x_tiload.c b/sound/soc/codecs/aic326x_tiload.c
new file mode 100644
index 00000000000..00aa4d4ce7d
--- /dev/null
+++ b/sound/soc/codecs/aic326x_tiload.c
@@ -0,0 +1,312 @@
+/*
+ * linux/sound/soc/codecs/AIC3262_tiload.c
+ *
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ *
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * History:
+ *
+ * Rev 0.1       Tiload support          16-09-2010
+ *
+ *          The Tiload programming support is added to AIC3262.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/types.h>
+#include <linux/kdev_t.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <sound/soc.h>
+#include <sound/control.h>
+
+#include "tlv320aic326x.h"
+#include "aic326x_tiload.h"
+
+/* enable debug prints in the driver */
+#define DEBUG
+//#undef DEBUG
+
+#ifdef DEBUG
+#define dprintk(x...)   printk(x)
+#else
+#define dprintk(x...)
+#endif
+
+#ifdef AIC3262_TiLoad
+
+/* Function prototypes */
+#ifdef REG_DUMP_aic3262
+static void aic3262_dump_page(struct i2c_client *i2c, u8 page);
+#endif
+
+/* externs */
+extern int aic3262_change_page(struct snd_soc_codec *codec, u8 new_page);
+extern int aic3262_change_book(struct snd_soc_codec *codec, u8 new_book);
+extern int aic3262_write(struct snd_soc_codec *codec, u16 reg, u8 value);
+int aic3262_driver_init(struct snd_soc_codec *codec);
+/************** Dynamic aic3262 driver, TI LOAD support  ***************/
+
+static struct cdev *aic3262_cdev;
+static int aic3262_major = 0;   /* Dynamic allocation of Mjr No. */
+static int aic3262_opened = 0;  /* Dynamic allocation of Mjr No. */
+static struct snd_soc_codec *aic3262_codec;
+struct class *tiload_class;
+static unsigned int magic_num = 0xE0;
+
+/******************************** Debug section *****************************/
+
+#ifdef REG_DUMP_aic3262
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_dump_page
+ * Purpose  : Read and display one codec register page, for debugging purpose
+ *----------------------------------------------------------------------------
+ */
+static void aic3262_dump_page(struct i2c_client *i2c, u8 page)
+{
+        int i;
+        u8 data;
+        u8 test_page_array[8];
+
+        dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
+        aic3262_change_page(codec, page);
+
+        data = 0x0;
+
+        i2c_master_send(i2c, data, 1);
+        i2c_master_recv(i2c, test_page_array, 8);
+
+        printk("\n------- aic3262 PAGE %d DUMP --------\n", page);
+        for (i = 0; i < 8; i++) {
+                printk(" [ %d ] = 0x%x\n", i, test_page_array[i]);
+        }
+}
+#endif
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : tiload_open
+ *
+ * Purpose  : open method for aic3262-tiload programming interface
+ *----------------------------------------------------------------------------
+ */
+static int tiload_open(struct inode *in, struct file *filp)
+{
+        dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
+        if (aic3262_opened) {
+                printk("%s device is already opened\n", "aic3262");
+                printk("%s: only one instance of driver is allowed\n",
+                       "aic3262");
+                return -1;
+        }
+        aic3262_opened++;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : tiload_release
+ *
+ * Purpose  : close method for aic3262_tilaod programming interface
+ *----------------------------------------------------------------------------
+ */
+static int tiload_release(struct inode *in, struct file *filp)
+{
+        dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
+        aic3262_opened--;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : tiload_read
+ *
+ * Purpose  : read method for mini dsp programming interface
+ *----------------------------------------------------------------------------
+ */
+static ssize_t tiload_read(struct file *file, char __user * buf,
+                           size_t count, loff_t * offset)
+{
+        static char rd_data[8];
+        char reg_addr;
+        size_t size;
+        #ifdef DEBUG
+        int i;
+        #endif
+        struct i2c_client *i2c = aic3262_codec->control_data;
+
+        dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
+        if (count > 128) {
+                printk("Max 128 bytes can be read\n");
+                count = 128;
+        }
+
+        /* copy register address from user space  */
+        size = copy_from_user(&reg_addr, buf, 1);
+        if (size != 0) {
+                printk("read: copy_from_user failure\n");
+                return -1;
+        }
+        /* Send the address to device thats is to be read */
+
+        if (i2c_master_send(i2c, &reg_addr, 1) != 1) {
+                dprintk("Can not write register address\n");
+                return -1;
+        }
+        /* read the codec device registers */
+        size = i2c_master_recv(i2c, rd_data, count);
+#ifdef DEBUG
+        printk(KERN_ERR "read size = %d, reg_addr= %x , count = %d\n",
+               (int)size, reg_addr, (int)count);
+        for (i = 0; i < (int)size; i++) {
+                printk(KERN_ERR "rd_data[%d]=%x\n", i, rd_data[i]);
+        }
+#endif
+        if (size != count) {
+                printk("read %d registers from the codec\n", size);
+        }
+
+        if (copy_to_user(buf, rd_data, size) != 0) {
+                dprintk("copy_to_user failed\n");
+                return -1;
+        }
+
+        return size;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : tiload_write
+ *
+ * Purpose  : write method for aic3262_tiload programming interface
+ *----------------------------------------------------------------------------
+ */
+static ssize_t tiload_write(struct file *file, const char __user * buf,
+                            size_t count, loff_t * offset)
+{
+        static char wr_data[8];
+        u8 pg_no;
+        #ifdef DEBUG
+        int i;
+        #endif
+        struct i2c_client *i2c = aic3262_codec->control_data;
+        struct aic3262_priv *aic3262_private = snd_soc_codec_get_drvdata(aic3262_codec);
+
+        dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
+        /* copy buffer from user space  */
+        if (copy_from_user(wr_data, buf, count)) {
+                printk("copy_from_user failure\n");
+                return -1;
+        }
+#ifdef DEBUG
+        printk(KERN_ERR "write size = %d\n", (int)count);
+        for (i = 0; i < (int)count; i++) {
+                printk(KERN_INFO "\nwr_data[%d]=%x\n", i, wr_data[i]);
+        }
+#endif
+        if (wr_data[0] == 0) {
+                aic3262_change_page(aic3262_codec, wr_data[1]);
+                return count;
+        }
+        pg_no = aic3262_private->page_no;
+
+        if ((wr_data[0] == 127) && (pg_no == 0)) {
+                aic3262_change_book(aic3262_codec, wr_data[1]);
+                return count;
+        }
+        return i2c_master_send(i2c, wr_data, count);
+}
+
+static int tiload_ioctl( struct file *filp,
+                        unsigned int cmd, unsigned long arg)
+{
+        int num = 0;
+        void __user *argp = (void __user *)arg;
+        if (_IOC_TYPE(cmd) != aic3262_IOC_MAGIC)
+                return -ENOTTY;
+
+        dprintk("TiLoad DRIVER : %s\n", __FUNCTION__);
+        switch (cmd) {
+        case aic3262_IOMAGICNUM_GET:
+                num = copy_to_user(argp, &magic_num, sizeof(int));
+                break;
+        case aic3262_IOMAGICNUM_SET:
+                num = copy_from_user(&magic_num, argp, sizeof(int));
+                break;
+        }
+        return num;
+}
+
+/*********** File operations structure for aic3262-tiload programming *************/
+static struct file_operations aic3262_fops = {
+        .owner = THIS_MODULE,
+        .open = tiload_open,
+        .release = tiload_release,
+        .read = tiload_read,
+        .write = tiload_write,
+        .unlocked_ioctl = tiload_ioctl,
+};
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_driver_init
+ *
+ * Purpose  : Register a char driver for dynamic aic3262-tiload programming
+ *----------------------------------------------------------------------------
+ */
+int aic3262_driver_init(struct snd_soc_codec *codec)
+{
+        int result;
+
+        dev_t dev = MKDEV(aic3262_major, 0);
+        printk("TiLoad DRIVER : %s\n", __FUNCTION__);
+        aic3262_codec = codec;
+
+        printk("allocating dynamic major number\n");
+
+        result = alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME);
+        if (result < 0) {
+                printk("cannot allocate major number %d\n", aic3262_major);
+                return result;
+        }
+        tiload_class = class_create(THIS_MODULE, DEVICE_NAME);
+        aic3262_major = MAJOR(dev);
+        printk("allocated Major Number: %d\n", aic3262_major);
+
+        aic3262_cdev = cdev_alloc();
+        cdev_init(aic3262_cdev, &aic3262_fops);
+        aic3262_cdev->owner = THIS_MODULE;
+        aic3262_cdev->ops = &aic3262_fops;
+
+        if (cdev_add(aic3262_cdev, dev, 1) < 0) {
+                dprintk("aic3262_driver: cdev_add failed \n");
+                unregister_chrdev_region(dev, 1);
+                aic3262_cdev = NULL;
+                return 1;
+        }
+        printk("Registered aic3262 TiLoad driver, Major number: %d \n",
+               aic3262_major);
+        //class_device_create(tiload_class, NULL, dev, NULL, DEVICE_NAME, 0);
+        return 0;
+}
+
+#endif
diff --git a/sound/soc/codecs/aic326x_tiload.h b/sound/soc/codecs/aic326x_tiload.h
new file mode 100644
index 00000000000..6621a4127b1
--- /dev/null
+++ b/sound/soc/codecs/aic326x_tiload.h
@@ -0,0 +1,36 @@
+/*
+ * linux/sound/soc/codecs/aic3262_tiload.h
+ *
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ *
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * History:
+ *
+ *
+ *
+ *
+ */
+
+#ifndef _AIC3262_TILOAD_H
+#define _AIC3262_TILOAD_H
+
+/* typedefs required for the included header files */
+typedef char *string;
+
+/* defines */
+#define DEVICE_NAME             "tiload_node"
+#define aic3262_IOC_MAGIC       0xE0
+#define aic3262_IOMAGICNUM_GET  _IOR(aic3262_IOC_MAGIC, 1, int)
+#define aic3262_IOMAGICNUM_SET  _IOW(aic3262_IOC_MAGIC, 2, int)
+
+#endif
diff --git a/sound/soc/codecs/base_main_Rate48_pps_driver.h b/sound/soc/codecs/base_main_Rate48_pps_driver.h
new file mode 100644
index 00000000000..4d6f227cc42
--- /dev/null
+++ b/sound/soc/codecs/base_main_Rate48_pps_driver.h
@@ -0,0 +1,5979 @@
+static control base_speaker_SRS_MUX_controls[] = {

+/*{4,28,1,0},

+{4,36,1,1},

+{4,112,1,2}*/

+};

+

+static char * base_speaker_SRS_MUX_control_names[] = {

+/*"Stereo_Mux_1",

+"Stereo_Mux_3",

+"Stereo_Mux_4"*/

+};

+

+static control base_speaker_SRS_VOLUME_controls[] = {

+};

+

+static char * base_speaker_SRS_VOLUME_control_names[] = {

+};

+

+/*//INSTRUCTIONS & COEFFICIENTS

+typedef struct {

+    u8 reg_off;

+    u8 reg_val;

+} reg_value;*/

+

+static char * base_speaker_SRS_REG_Section_names[] = {

+    "miniDSP_A_reg_values",

+    "miniDSP_D_reg_values",

+};

+

+reg_value base_speaker_SRS_REG_init_Section_program[] = {

+    {  0,0x0},

+    {  0x7F,0x00},

+//                      # Set AutoINC

+    {121,0x01},

+    {  0x7F,0x78},

+//                      # reg[120][0][50] = 0x88                     ; Interpolation Ratio is 8, FIFO = Enabled

+    { 50,0x88},

+    {  0x7F,0x64},

+//                      # reg[100][0][50] = 0xa4                     ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled

+    { 50,0xA4},

+    {  0x7F,0x78},

+//                      # reg[120][0][24]=0x80

+    { 24,0x80},

+};

+    

+reg_value base_speaker_SRS_REG_post_Section_program[] = {

+    {  0,0x0},

+    {  0x7F,0x28},

+//                      # reg[40][0][1] = 0x04                        ; adaptive mode for ADC

+    {  1,0x04},

+    {  0x7F,0x50},

+//                      # reg[80][0][1] = 0x04                        ; adaptive mode for DAC

+    {  1,0x04},

+    {  0x7F,0x64},

+//                      # reg[100][0][48] = 4

+    { 48,0x04},

+//                      # reg[100][0][49] = 0

+    { 49,0x00},

+    {  0x7F,0x78},

+//                      # reg[120][0][48] = 4

+    { 48,0x04},

+//                      # reg[120][0][49] = 0

+    { 49,0x00},

+    {  0x7F,0x64},

+//                      # reg[100][0][20] = 0x00 ; Disable ADC double buffer mode

+    { 20,0x00},

+    {  0x7F,0x78},

+//                      # reg[120][0][20] = 0x00 ; Disable DAC double buffer mode

+    { 20,0x00},

+

+};

+

+reg_value base_speaker_SRS_miniDSP_A_reg_values[] = {

+    {  0,0x0},

+    {  0x7F,0x28},

+    {  0,0x01},

+    {  8,0x00},

+    {  9,0xA7},

+    { 10,0xF8},

+    { 11,0x00},

+    { 12,0x7E},

+    { 13,0xB0},

+    { 14,0x10},

+    { 15,0x00},

+    { 16,0x7F},

+    { 17,0xFF},

+    { 18,0xFF},

+    { 19,0x00},

+    { 20,0x00},

+    { 21,0x00},

+    { 22,0x00},

+    { 23,0x00},

+    { 24,0x00},

+    { 25,0x00},

+    { 26,0x00},

+    { 27,0x00},

+    { 28,0xFF},

+    { 29,0xFF},

+    { 30,0xFF},

+    { 31,0x00},

+    { 32,0x80},

+    { 33,0x00},

+    { 34,0x00},

+    { 35,0x00},

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+    {115,0x13},

+    {116,0x1C},

+    {117,0x05},

+    {118,0x40},

+    {119,0x46},

+    {120,0x1C},

+    {121,0x05},

+    {122,0x60},

+    {123,0x2E},

+    {124,0x1C},

+    {125,0x05},

+    {126,0x60},

+    {127,0x2B},

+    {  0,0x04},

+    {  8,0x1C},

+    {  9,0x05},

+    { 10,0x80},

+    { 11,0x10},

+    { 12,0x1C},

+    { 13,0x05},

+    { 14,0x80},

+    { 15,0x49},

+    { 16,0x1C},

+    { 17,0x05},

+    { 18,0xA0},

+    { 19,0x17},

+    { 20,0x1C},

+    { 21,0x05},

+    { 22,0xA0},

+    { 23,0x42},

+    { 24,0x1C},

+    { 25,0x05},

+    { 26,0xC0},

+    { 27,0x1D},

+    { 28,0x1C},

+    { 29,0x05},

+    { 30,0xC0},

+    { 31,0x3C},

+    { 32,0x1C},

+    { 33,0x05},

+    { 34,0xE0},

+    { 35,0x1B},

+    { 36,0x1C},

+    { 37,0x05},

+    { 38,0xE0},

+    { 39,0x3E},

+    { 40,0x1C},

+    { 41,0x06},

+    { 42,0x00},

+    { 43,0x39},

+    { 44,0x1C},

+    { 45,0x06},

+    { 46,0x00},

+    { 47,0x20},

+    { 48,0x00},

+    { 49,0x00},

+    { 50,0x00},

+    { 51,0x00},

+    { 52,0x5C},

+    { 53,0x90},

+    { 54,0x40},

+    { 55,0x00},

+    { 56,0x00},

+    { 57,0x00},

+    { 58,0x00},

+    { 59,0x00},

+    { 60,0x5C},

+    { 61,0x90},

+    { 62,0x20},

+    { 63,0x00},

+    { 64,0x00},

+    { 65,0x00},

+    { 66,0x00},

+    { 67,0x00},

+    { 68,0x00},

+    { 69,0x00},

+    { 70,0x00},

+    { 71,0x00},

+    { 72,0x00},

+    { 73,0x00},

+    { 74,0x00},

+    { 75,0x00},

+    { 76,0x10},

+    { 77,0x00},

+    { 78,0x00},

+    { 79,0x49},

+    { 80,0x18},

+    { 81,0x00},

+    { 82,0x60},

+    { 83,0x4A},

+    { 84,0x1C},

+    { 85,0x00},

+    { 86,0x80},

+    { 87,0x4C},

+    { 88,0x1C},

+    { 89,0x00},

+    { 90,0x40},

+    { 91,0x49},

+    { 92,0x30},

+    { 93,0x00},

+    { 94,0x00},

+    { 95,0x4C},

+    { 96,0x1C},

+    { 97,0x00},

+    { 98,0x20},

+    { 99,0x4E},

+    {100,0x00},

+    {101,0x00},

+    {102,0x00},

+    {103,0x00},

+    {104,0x10},

+    {105,0x30},

+    {106,0x00},

+    {107,0x4B},

+    {108,0x34},

+    {109,0x00},

+    {110,0x00},

+    {111,0x4B},

+    {112,0x5C},

+    {113,0x60},

+    {114,0xA0},

+    {115,0x4B},

+    {116,0x0C},

+    {117,0x00},

+    {118,0x40},

+    {119,0x00},

+    {120,0x00},

+    {121,0x00},

+    {122,0x00},

+    {123,0x00},

+    {124,0x10},

+    {125,0x30},

+    {126,0x00},

+    {127,0x4D},

+    {  0,0x05},

+    {  8,0x10},

+    {  9,0x13},

+    { 10,0xE0},

+    { 11,0x50},

+    { 12,0x18},

+    { 13,0x01},

+    { 14,0x00},

+    { 15,0x50},

+    { 16,0x18},

+    { 17,0x03},

+    { 18,0x60},

+    { 19,0x53},

+    { 20,0x6C},

+    { 21,0x03},

+    { 22,0x40},

+    { 23,0x52},

+    { 24,0x6C},

+    { 25,0x03},

+    { 26,0x80},

+    { 27,0x55},

+    { 28,0x10},

+    { 29,0x00},

+    { 30,0x20},

+    { 31,0x51},

+    { 32,0x1C},

+    { 33,0x03},

+    { 34,0x20},

+    { 35,0x51},

+    { 36,0x1C},

+    { 37,0x03},

+    { 38,0xA0},

+    { 39,0x56},

+    { 40,0x00},

+    { 41,0x00},

+    { 42,0x00},

+    { 43,0x00},

+    { 44,0x00},

+    { 45,0x00},

+    { 46,0x00},

+    { 47,0x00},

+    { 48,0x00},

+    { 49,0x00},

+    { 50,0x00},

+    { 51,0x00},

+    { 52,0x10},

+    { 53,0x00},

+    { 54,0x00},

+    { 55,0x54},

+    { 56,0x18},

+    { 57,0x01},

+    { 58,0x00},

+    { 59,0x54},

+    { 60,0x00},

+    { 61,0x00},

+    { 62,0x00},

+    { 63,0x00},

+    { 64,0x0C},

+    { 65,0x00},

+    { 66,0x00},

+    { 67,0x03},

+    { 68,0x00},

+    { 69,0x00},

+    { 70,0x00},

+    { 71,0x00},

+    { 72,0x00},

+    { 73,0x00},

+    { 74,0x00},

+    { 75,0x00},

+    { 76,0x00},

+    { 77,0x00},

+    { 78,0x00},

+    { 79,0x00},

+    { 80,0x02},

+    { 81,0x00},

+    { 82,0x00},

+    { 83,0x00},

+    { 84,0x00},

+    { 85,0x00},

+    { 86,0x00},

+    { 87,0x00},

+};

+

+

+reg_value base_speaker_SRS_miniDSP_D_reg_values[] = {

+    {  0,0x0},

+    {  0x7F,0x50},

+    {  0,0x01},

+    {  8,0xFF},

+    {  9,0xFF},

+    { 10,0xFF},

+    { 11,0x00},

+    { 12,0x80},

+    { 13,0x00},

+    { 14,0x00},

+    { 15,0x00},

+    { 16,0x7F},

+    { 17,0xF7},

+    { 18,0x00},

+    { 19,0x00},

+    { 20,0x80},

+    { 21,0x09},

+    { 22,0x00},

+    { 23,0x00},

+    { 24,0x7F},

+    { 25,0xEF},

+    { 26,0x00},

+    { 27,0x00},

+    { 28,0x66},

+    { 29,0x66},

+    { 30,0x60},

+    { 31,0x00},

+    { 32,0x1B},

+    { 33,0x33},

+    { 34,0x20},

+    { 35,0x00},

+    { 36,0x66},

+    { 37,0x66},

+    { 38,0x60},

+    { 39,0x00},

+    { 40,0x33},

+    { 41,0x33},

+    { 42,0x30},

+    { 43,0x00},

+    { 44,0x4C},

+    { 45,0xCC},

+    { 46,0xCD},

+    { 47,0x00},

+    { 48,0x00},

+    { 49,0x00},

+    { 50,0x01},

+    { 51,0x00},

+    { 52,0x33},

+    { 53,0x33},

+    { 54,0x30},

+    { 55,0x00},

+    { 56,0x33},

+    { 57,0x33},

+    { 58,0x30},

+    { 59,0x00},

+    { 60,0x7F},

+    { 61,0xFF},

+    { 62,0xAC},

+    { 63,0x00},

+    { 64,0x80},

+    { 65,0x00},

+    { 66,0x00},

+    { 67,0x00},

+    { 68,0x40},

+    { 69,0x00},

+    { 70,0x00},

+    { 71,0x00},

+    { 72,0x40},

+    { 73,0x00},

+    { 74,0x00},

+    { 75,0x00},

+    { 76,0xC0},

+    { 77,0x00},

+    { 78,0x00},

+    { 79,0x00},

+    { 80,0x50},

+    { 81,0xC3},

+    { 82,0x36},

+    { 83,0x00},

+    { 84,0x02},

+    { 85,0x8F},

+    { 86,0x5C},

+    { 87,0x00},

+    { 88,0x02},

+    { 89,0xD7},

+    { 90,0x0A},

+    { 91,0x00},

+    { 92,0x00},

+    { 93,0x00},

+    { 94,0x00},

+    { 95,0x00},

+    { 96,0x00},

+    { 97,0x00},

+    { 98,0x00},

+    { 99,0x00},

+    {100,0x00},

+    {101,0x00},

+    {102,0x00},

+    {103,0x00},

+    {104,0x00},

+    {105,0x00},

+    {106,0x00},

+    {107,0x00},

+    {108,0x00},

+    {109,0x00},

+    {110,0x00},

+    {111,0x00},

+    {112,0x40},

+    {113,0x00},

+    {114,0x00},

+    {115,0x00},

+    {116,0xFF},

+    {117,0xFF},

+    {118,0xFF},

+    {119,0x00},

+    {120,0xFF},

+    {121,0xFF},

+    {122,0xFE},

+    {123,0x00},

+    {124,0xFF},

+    {125,0xFF},

+    {126,0xFD},

+    {127,0x00},

+    {  0,0x02},

+    {  8,0xFF},

+    {  9,0xFF},

+    { 10,0xFC},

+    { 11,0x00},

+    { 12,0x00},

+    { 13,0x00},

+    { 14,0x00},

+    { 15,0x00},

+    { 16,0x73},

+    { 17,0x56},

+    { 18,0x6E},

+    { 19,0x00},

+    { 20,0x7F},

+    { 21,0xF4},

+    { 22,0xA0},

+    { 23,0x00},

+    { 24,0x00},

+    { 25,0x80},

+    { 26,0x2D},

+    { 27,0x00},

+    { 28,0x7E},

+    { 29,0xFF},

+    { 30,0xA5},

+    { 31,0x00},

+    { 32,0x00},

+    { 33,0x2E},

+    { 34,0x73},

+    { 35,0x00},

+    { 36,0xFF},

+    { 37,0xD1},

+    { 38,0x8D},

+    { 39,0x00},

+    { 40,0x7F},

+    { 41,0xC1},

+    { 42,0x2F},

+    { 43,0x00},

+    { 44,0x80},

+    { 45,0x7B},

+    { 46,0x94},

+    { 47,0x00},

+    { 48,0x01},

+    { 49,0x50},

+    { 50,0xC1},

+    { 51,0x00},

+    { 52,0xFE},

+    { 53,0xAF},

+    { 54,0x3F},

+    { 55,0x00},

+    { 56,0x7F},

+    { 57,0x55},

+    { 58,0xC1},

+    { 59,0x00},

+    { 60,0x81},

+    { 61,0x4E},

+    { 62,0x4E},

+    { 63,0x00},

+    { 64,0x7F},

+    { 65,0xFF},

+    { 66,0xFF},

+    { 67,0x00},

+    { 68,0x00},

+    { 69,0x00},

+    { 70,0x00},

+    { 71,0x00},

+    { 72,0xC7},

+    { 73,0x2E},

+    { 74,0x8D},

+    { 75,0x00},

+    { 76,0x31},

+    { 77,0x91},

+    { 78,0x54},

+    { 79,0x00},

+    { 80,0xD1},

+    { 81,0xFC},

+    { 82,0xF4},

+    { 83,0x00},

+    { 84,0x2A},

+    { 85,0x09},

+    { 86,0x1A},

+    { 87,0x00},

+    { 88,0xEA},

+    { 89,0xD6},

+    { 90,0x1C},

+    { 91,0x00},

+    { 92,0xC5},

+    { 93,0x28},

+    { 94,0xA2},

+    { 95,0x00},

+    { 96,0x32},

+    { 97,0xD7},

+    { 98,0x53},

+    { 99,0x00},

+    {100,0xD3},

+    {101,0x74},

+    {102,0x4B},

+    {103,0x00},

+    {104,0x15},

+    {105,0x04},

+    {106,0x8D},

+    {107,0x00},

+    {108,0xF5},

+    {109,0x6B},

+    {110,0x0E},

+    {111,0x00},

+    {112,0xC0},

+    {113,0x0C},

+    {114,0x47},

+    {115,0x00},

+    {116,0x3F},

+    {117,0x99},

+    {118,0x61},

+    {119,0x00},

+    {120,0x3E},

+    {121,0xE2},

+    {122,0x1D},

+    {123,0x00},

+    {124,0x3E},

+    {125,0xE2},

+    {126,0x1D},

+    {127,0x00},

+    {  0,0x03},

+    {  8,0x0A},

+    {  9,0x57},

+    { 10,0x0D},

+    { 11,0x00},

+    { 12,0xF5},

+    { 13,0xA8},

+    { 14,0xF3},

+    { 15,0x00},

+    { 16,0x6E},

+    { 17,0x1B},

+    { 18,0xC0},

+    { 19,0x00},

+    { 20,0x89},

+    { 21,0x90},

+    { 22,0x65},

+    { 23,0x00},

+    { 24,0x1B},

+    { 25,0x6E},

+    { 26,0xFE},

+    { 27,0x00},

+    { 28,0xE4},

+    { 29,0x91},

+    { 30,0x02},

+    { 31,0x00},

+    { 32,0x5B},

+    { 33,0x45},

+    { 34,0x9C},

+    { 35,0x00},

+    { 36,0x99},

+    { 37,0x5F},

+    { 38,0xEC},

+    { 39,0x00},

+    { 40,0x15},

+    { 41,0x3D},

+    { 42,0xC9},

+    { 43,0x00},

+    { 44,0xEA},

+    { 45,0xC2},

+    { 46,0x37},

+    { 47,0x00},

+    { 48,0x40},

+    { 49,0x53},

+    { 50,0x16},

+    { 51,0x00},

+    { 52,0x93},

+    { 53,0xA5},

+    { 54,0xAE},

+    { 55,0x00},

+    { 56,0x9B},

+    { 57,0x77},

+    { 58,0x00},

+    { 59,0x00},

+    { 60,0x64},

+    { 61,0x88},

+    { 62,0xF0},

+    { 63,0x00},

+    { 64,0x45},

+    { 65,0x84},

+    { 66,0x40},

+    { 67,0x00},

+    { 68,0xBA},

+    { 69,0x7B},

+    { 70,0xB0},

+    { 71,0x00},

+    { 72,0xC3},

+    { 73,0xE0},

+    { 74,0x00},

+    { 75,0x00},

+    { 76,0x3C},

+    { 77,0x1F},

+    { 78,0xF0},

+    { 79,0x00},

+    { 80,0x68},

+    { 81,0x76},

+    { 82,0x1D},

+    { 83,0x00},

+    { 84,0x97},

+    { 85,0x89},

+    { 86,0xE3},

+    { 87,0x00},

+    { 88,0x67},

+    { 89,0xEA},

+    { 90,0x3A},

+    { 91,0x00},

+    { 92,0xAD},

+    { 93,0xFC},

+    { 94,0x02},

+    { 95,0x00},

+    { 96,0x79},

+    { 97,0xEC},

+    { 98,0x4D},

+    { 99,0x00},

+    {100,0x86},

+    {101,0x13},

+    {102,0xB3},

+    {103,0x00},

+    {104,0x3A},

+    {105,0x36},

+    {106,0x6A},

+    {107,0x00},

+    {108,0x7F},

+    {109,0xFF},

+    {110,0xFF},

+    {111,0x00},

+    {112,0x00},

+    {113,0x00},

+    {114,0x00},

+    {115,0x00},

+    {116,0x00},

+    {117,0x00},

+    {118,0x00},

+    {119,0x00},

+    {120,0x00},

+    {121,0x00},

+    {122,0x00},

+    {123,0x00},

+    {124,0x00},

+    {125,0x00},

+    {126,0x00},

+    {127,0x00},

+    {  0,0x04},

+    {  8,0x7F},

+    {  9,0xFF},

+    { 10,0xFF},

+    { 11,0x00},

+    { 12,0x00},

+    { 13,0x00},

+    { 14,0x00},

+    { 15,0x00},

+    { 16,0x00},

+    { 17,0x00},

+    { 18,0x00},

+    { 19,0x00},

+    { 20,0x00},

+    { 21,0x00},

+    { 22,0x00},

+    { 23,0x00},

+    { 24,0x00},

+    { 25,0x00},

+    { 26,0x00},

+    { 27,0x00},

+    { 28,0x00},

+    { 29,0x00},

+    { 30,0x01},

+    { 31,0x00},

+    { 32,0xC0},

+    { 33,0x00},

+    { 34,0x00},

+    { 35,0x00},

+    { 36,0x00},

+    { 37,0x00},

+    { 38,0x01},

+    { 39,0x00},

+    { 40,0x00},

+    { 41,0x00},

+    { 42,0xAF},

+    { 43,0x00},

+    { 44,0x7F},

+    { 45,0xFF},

+    { 46,0x51},

+    { 47,0x00},

+    { 48,0x00},

+    { 49,0x00},

+    { 50,0x00},

+    { 51,0x00},

+    { 52,0xF0},

+    { 53,0x00},

+    { 54,0x00},

+    { 55,0x00},

+    { 56,0xE4},

+    { 57,0x00},

+    { 58,0x00},

+    { 59,0x00},

+    { 60,0x32},

+    { 61,0x00},

+    { 62,0x00},

+    { 63,0x00},

+    { 64,0x14},

+    { 65,0x00},

+    { 66,0x00},

+    { 67,0x00},

+    { 68,0xFF},

+    { 69,0x00},

+    { 70,0x00},

+    { 71,0x00},

+    { 72,0xF0},

+    { 73,0x00},

+    { 74,0x00},

+    { 75,0x00},

+    { 76,0x00},

+    { 77,0x02},

+    { 78,0xBB},

+    { 79,0x00},

+    { 80,0x7F},

+    { 81,0xFD},

+    { 82,0x45},

+    { 83,0x00},

+    { 84,0x00},

+    { 85,0x00},

+    { 86,0x57},

+    { 87,0x00},

+    { 88,0x7F},

+    { 89,0xFF},

+    { 90,0xA9},

+    { 91,0x00},

+    { 92,0x20},

+    { 93,0x00},

+    { 94,0x00},

+    { 95,0x00},

+    { 96,0x00},

+    { 97,0x00},

+    { 98,0x00},

+    { 99,0x00},

+    {100,0xD7},

+    {101,0x41},

+    {102,0xA0},

+    {103,0x00},

+    {104,0xFF},

+    {105,0xF0},

+    {106,0x00},

+    {107,0x00},

+    {108,0x88},

+    {109,0x00},

+    {110,0x00},

+    {111,0x00},

+    {112,0x18},

+    {113,0x00},

+    {114,0x00},

+    {115,0x00},

+    {116,0x00},

+    {117,0x00},

+    {118,0x00},

+    {119,0x00},

+    {120,0x0C},

+    {121,0x00},

+    {122,0x00},

+    {123,0x00},

+    {124,0xF4},

+    {125,0x00},

+    {126,0x00},

+    {127,0x00},

+    {  0,0x05},

+    {  8,0x15},

+    {  9,0x42},

+    { 10,0xA6},

+    { 11,0x00},

+    { 12,0x7F},

+    { 13,0xFF},

+    { 14,0xFF},

+    { 15,0x00},

+    { 16,0x0B},

+    { 17,0xF9},

+    { 18,0x13},

+    { 19,0x00},

+    { 20,0x18},

+    { 21,0xEC},

+    { 22,0xF7},

+    { 23,0x00},

+    { 24,0x5B},

+    { 25,0x9E},

+    { 26,0xC4},

+    { 27,0x00},

+    { 28,0x7F},

+    { 29,0x7B},

+    { 30,0x30},

+    { 31,0x00},

+    { 32,0x00},

+    { 33,0x00},

+    { 34,0x00},

+    { 35,0x00},

+    { 36,0x00},

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+    {111,0xD3},

+    {112,0x1C},

+    {113,0x11},

+    {114,0x20},

+    {115,0xD8},

+    {116,0x1C},

+    {117,0x11},

+    {118,0x40},

+    {119,0xC4},

+    {120,0x1C},

+    {121,0x11},

+    {122,0x40},

+    {123,0xE7},

+    {124,0x1C},

+    {125,0x11},

+    {126,0x60},

+    {127,0xCC},

+    {  0,0x19},

+    {  8,0x1C},

+    {  9,0x11},

+    { 10,0x60},

+    { 11,0xDF},

+    { 12,0x1C},

+    { 13,0x11},

+    { 14,0x80},

+    { 15,0xC8},

+    { 16,0x1C},

+    { 17,0x11},

+    { 18,0x80},

+    { 19,0xE3},

+    { 20,0x1C},

+    { 21,0x11},

+    { 22,0xA0},

+    { 23,0xD0},

+    { 24,0x1C},

+    { 25,0x11},

+    { 26,0xA0},

+    { 27,0xDB},

+    { 28,0x1C},

+    { 29,0x11},

+    { 30,0xC0},

+    { 31,0xCA},

+    { 32,0x1C},

+    { 33,0x11},

+    { 34,0xC0},

+    { 35,0xE1},

+    { 36,0x1C},

+    { 37,0x11},

+    { 38,0xE0},

+    { 39,0xC6},

+    { 40,0x1C},

+    { 41,0x11},

+    { 42,0xE0},

+    { 43,0xE5},

+    { 44,0x1C},

+    { 45,0x12},

+    { 46,0x00},

+    { 47,0xCE},

+    { 48,0x1C},

+    { 49,0x12},

+    { 50,0x00},

+    { 51,0xDD},

+    { 52,0x1C},

+    { 53,0x12},

+    { 54,0x20},

+    { 55,0xD2},

+    { 56,0x1C},

+    { 57,0x12},

+    { 58,0x20},

+    { 59,0xD9},

+    { 60,0x1C},

+    { 61,0x12},

+    { 62,0x40},

+    { 63,0xD4},

+    { 64,0x1C},

+    { 65,0x12},

+    { 66,0x40},

+    { 67,0xD7},

+    { 68,0x1C},

+    { 69,0x12},

+    { 70,0x60},

+    { 71,0xD5},

+    { 72,0x1C},

+    { 73,0x12},

+    { 74,0x60},

+    { 75,0xD6},

+    { 76,0x00},

+    { 77,0x00},

+    { 78,0x00},

+    { 79,0x00},

+    { 80,0x00},

+    { 81,0x00},

+    { 82,0x00},

+    { 83,0x00},

+    { 84,0x00},

+    { 85,0x00},

+    { 86,0x00},

+    { 87,0x00},

+    { 88,0x10},

+    { 89,0x00},

+    { 90,0x00},

+    { 91,0xED},

+    { 92,0x18},

+    { 93,0x12},

+    { 94,0xA0},

+    { 95,0xEC},

+    { 96,0x1C},

+    { 97,0x12},

+    { 98,0xC0},

+    { 99,0xEE},

+    {100,0x1C},

+    {101,0x12},

+    {102,0xC0},

+    {103,0xEB},

+    {104,0x1C},

+    {105,0x12},

+    {106,0xA0},

+    {107,0xED},

+    {108,0x1C},

+    {109,0x12},

+    {110,0xE0},

+    {111,0xEA},

+    {112,0x1C},

+    {113,0x12},

+    {114,0xE0},

+    {115,0xEF},

+    {116,0x1C},

+    {117,0x13},

+    {118,0x00},

+    {119,0xE9},

+    {120,0x1C},

+    {121,0x13},

+    {122,0x00},

+    {123,0xF0},

+    {124,0x18},

+    {125,0x13},

+    {126,0x60},

+    {127,0xF1},

+    {  0,0x1A},

+    {  8,0x1C},

+    {  9,0x13},

+    { 10,0x60},

+    { 11,0xF3},

+    { 12,0x1C},

+    { 13,0x13},

+    { 14,0x40},

+    { 15,0xF6},

+    { 16,0x4C},

+    { 17,0x13},

+    { 18,0x40},

+    { 19,0xF4},

+    { 20,0x00},

+    { 21,0x00},

+    { 22,0x00},

+    { 23,0x00},

+    { 24,0x5C},

+    { 25,0x90},

+    { 26,0x60},

+    { 27,0x03},

+    { 28,0x18},

+    { 29,0x12},

+    { 30,0xA0},

+    { 31,0xAC},

+    { 32,0x1C},

+    { 33,0x12},

+    { 34,0xA0},

+    { 35,0xAD},

+    { 36,0x1C},

+    { 37,0x12},

+    { 38,0xC0},

+    { 39,0xAE},

+    { 40,0x10},

+    { 41,0x00},

+    { 42,0x40},

+    { 43,0xFD},

+    { 44,0x1C},

+    { 45,0x12},

+    { 46,0xC0},

+    { 47,0xAB},

+    { 48,0x1C},

+    { 49,0x12},

+    { 50,0xE0},

+    { 51,0xAA},

+    { 52,0x1C},

+    { 53,0x12},

+    { 54,0xE0},

+    { 55,0xAF},

+    { 56,0x1C},

+    { 57,0x13},

+    { 58,0x00},

+    { 59,0xA9},

+    { 60,0x1C},

+    { 61,0x13},

+    { 62,0x00},

+    { 63,0xB0},

+    { 64,0x18},

+    { 65,0x13},

+    { 66,0x60},

+    { 67,0xB1},

+    { 68,0x1C},

+    { 69,0x13},

+    { 70,0x60},

+    { 71,0xB3},

+    { 72,0x1C},

+    { 73,0x13},

+    { 74,0x40},

+    { 75,0xB6},

+    { 76,0x4C},

+    { 77,0x13},

+    { 78,0x40},

+    { 79,0xB4},

+    { 80,0x00},

+    { 81,0x00},

+    { 82,0x00},

+    { 83,0x00},

+    { 84,0x5C},

+    { 85,0x90},

+    { 86,0x40},

+    { 87,0x03},

+    { 88,0x00},

+    { 89,0x00},

+    { 90,0x00},

+    { 91,0x00},

+    { 92,0x00},

+    { 93,0x00},

+    { 94,0x00},

+    { 95,0x00},

+    { 96,0x00},

+    { 97,0x00},

+    { 98,0x00},

+    { 99,0x00},

+    {100,0x10},

+    {101,0x00},

+    {102,0x40},

+    {103,0xBD},

+    {104,0x18},

+    {105,0x13},

+    {106,0x80},

+    {107,0xF4},

+    {108,0x1C},

+    {109,0x13},

+    {110,0x80},

+    {111,0xF3},

+    {112,0x1C},

+    {113,0x13},

+    {114,0xA0},

+    {115,0xF1},

+    {116,0x00},

+    {117,0x00},

+    {118,0x00},

+    {119,0x00},

+    {120,0x5C},

+    {121,0x90},

+    {122,0x60},

+    {123,0x03},

+    {124,0x18},

+    {125,0x13},

+    {126,0x80},

+    {127,0xB4},

+    {  0,0x1B},

+    {  8,0x1C},

+    {  9,0x13},

+    { 10,0x80},

+    { 11,0xB3},

+    { 12,0x1C},

+    { 13,0x13},

+    { 14,0xA0},

+    { 15,0xB1},

+    { 16,0x10},

+    { 17,0x00},

+    { 18,0x40},

+    { 19,0xFC},

+    { 20,0x18},

+    { 21,0x13},

+    { 22,0x20},

+    { 23,0xEA},

+    { 24,0x5C},

+    { 25,0x90},

+    { 26,0x40},

+    { 27,0x03},

+    { 28,0x18},

+    { 29,0x13},

+    { 30,0x40},

+    { 31,0xF3},

+    { 32,0x1C},

+    { 33,0x13},

+    { 34,0x60},

+    { 35,0xF4},

+    { 36,0x4C},

+    { 37,0x13},

+    { 38,0x40},

+    { 39,0xF5},

+    { 40,0x10},

+    { 41,0x00},

+    { 42,0x40},

+    { 43,0xBC},

+    { 44,0x1C},

+    { 45,0x13},

+    { 46,0x60},

+    { 47,0xF1},

+    { 48,0x18},

+    { 49,0x13},

+    { 50,0x20},

+    { 51,0xAA},

+    { 52,0x5C},

+    { 53,0x90},

+    { 54,0x60},

+    { 55,0x03},

+    { 56,0x18},

+    { 57,0x13},

+    { 58,0x40},

+    { 59,0xB3},

+    { 60,0x1C},

+    { 61,0x13},

+    { 62,0x60},

+    { 63,0xB4},

+    { 64,0x4C},

+    { 65,0x13},

+    { 66,0x40},

+    { 67,0xB5},

+    { 68,0x10},

+    { 69,0x00},

+    { 70,0x40},

+    { 71,0xFB},

+    { 72,0x1C},

+    { 73,0x13},

+    { 74,0x60},

+    { 75,0xB1},

+    { 76,0x00},

+    { 77,0x00},

+    { 78,0x00},

+    { 79,0x00},

+    { 80,0x5C},

+    { 81,0x90},

+    { 82,0x40},

+    { 83,0x03},

+    { 84,0x18},

+    { 85,0x13},

+    { 86,0x80},

+    { 87,0xF5},

+    { 88,0x1C},

+    { 89,0x13},

+    { 90,0x80},

+    { 91,0xF1},

+    { 92,0x1C},

+    { 93,0x13},

+    { 94,0xA0},

+    { 95,0xF4},

+    { 96,0x10},

+    { 97,0x00},

+    { 98,0x40},

+    { 99,0xBB},

+    {100,0x5C},

+    {101,0x90},

+    {102,0x60},

+    {103,0x03},

+    {104,0x00},

+    {105,0x00},

+    {106,0x00},

+    {107,0x00},

+    {108,0x00},

+    {109,0x00},

+    {110,0x00},

+    {111,0x00},

+    {112,0x00},

+    {113,0x00},

+    {114,0x00},

+    {115,0x00},

+    {116,0x10},

+    {117,0x00},

+    {118,0x40},

+    {119,0xFA},

+    {120,0x18},

+    {121,0x13},

+    {122,0x80},

+    {123,0xB5},

+    {124,0x1C},

+    {125,0x13},

+    {126,0x80},

+    {127,0xB1},

+    {  0,0x1C},

+    {  8,0x1C},

+    {  9,0x13},

+    { 10,0xA0},

+    { 11,0xB4},

+    { 12,0x18},

+    { 13,0x12},

+    { 14,0x80},

+    { 15,0xD5},

+    { 16,0x5C},

+    { 17,0x90},

+    { 18,0x40},

+    { 19,0x03},

+    { 20,0x18},

+    { 21,0x12},

+    { 22,0xA0},

+    { 23,0xF0},

+    { 24,0x1C},

+    { 25,0x12},

+    { 26,0xC0},

+    { 27,0xE9},

+    { 28,0x4C},

+    { 29,0x12},

+    { 30,0xA0},

+    { 31,0xE8},

+    { 32,0x10},

+    { 33,0x00},

+    { 34,0x40},

+    { 35,0xBA},

+    { 36,0x1C},

+    { 37,0x12},

+    { 38,0xC0},

+    { 39,0xEF},

+    { 40,0x1C},

+    { 41,0x12},

+    { 42,0xE0},

+    { 43,0xEE},

+    { 44,0x1C},

+    { 45,0x12},

+    { 46,0xE0},

+    { 47,0xEA},

+    { 48,0x1C},

+    { 49,0x13},

+    { 50,0x00},

+    { 51,0xED},

+    { 52,0x1C},

+    { 53,0x13},

+    { 54,0x00},

+    { 55,0xEB},

+    { 56,0x18},

+    { 57,0x13},

+    { 58,0x60},

+    { 59,0xF5},

+    { 60,0x1C},

+    { 61,0x13},

+    { 62,0x60},

+    { 63,0xF4},

+    { 64,0x1C},

+    { 65,0x13},

+    { 66,0x40},

+    { 67,0xF1},

+    { 68,0x4C},

+    { 69,0x13},

+    { 70,0x40},

+    { 71,0xF2},

+    { 72,0x18},

+    { 73,0x12},

+    { 74,0x80},

+    { 75,0x95},

+    { 76,0x5C},

+    { 77,0x90},

+    { 78,0x60},

+    { 79,0x03},

+    { 80,0x18},

+    { 81,0x12},

+    { 82,0xA0},

+    { 83,0xB0},

+    { 84,0x1C},

+    { 85,0x12},

+    { 86,0xC0},

+    { 87,0xA9},

+    { 88,0x4C},

+    { 89,0x12},

+    { 90,0xA0},

+    { 91,0xA8},

+    { 92,0x10},

+    { 93,0x00},

+    { 94,0x40},

+    { 95,0xF9},

+    { 96,0x1C},

+    { 97,0x12},

+    { 98,0xC0},

+    { 99,0xAF},

+    {100,0x1C},

+    {101,0x12},

+    {102,0xE0},

+    {103,0xAE},

+    {104,0x1C},

+    {105,0x12},

+    {106,0xE0},

+    {107,0xAA},

+    {108,0x1C},

+    {109,0x13},

+    {110,0x00},

+    {111,0xAD},

+    {112,0x1C},

+    {113,0x13},

+    {114,0x00},

+    {115,0xAB},

+    {116,0x18},

+    {117,0x13},

+    {118,0x60},

+    {119,0xB5},

+    {120,0x1C},

+    {121,0x13},

+    {122,0x60},

+    {123,0xB4},

+    {124,0x1C},

+    {125,0x13},

+    {126,0x40},

+    {127,0xB1},

+    {  0,0x1D},

+    {  8,0x4C},

+    {  9,0x13},

+    { 10,0x40},

+    { 11,0xB2},

+    { 12,0x00},

+    { 13,0x00},

+    { 14,0x00},

+    { 15,0x00},

+    { 16,0x5C},

+    { 17,0x90},

+    { 18,0x40},

+    { 19,0x03},

+    { 20,0x00},

+    { 21,0x00},

+    { 22,0x00},

+    { 23,0x00},

+    { 24,0x00},

+    { 25,0x00},

+    { 26,0x00},

+    { 27,0x00},

+    { 28,0x00},

+    { 29,0x00},

+    { 30,0x00},

+    { 31,0x00},

+    { 32,0x10},

+    { 33,0x00},

+    { 34,0x40},

+    { 35,0xB8},

+    { 36,0x18},

+    { 37,0x13},

+    { 38,0x80},

+    { 39,0xF2},

+    { 40,0x1C},

+    { 41,0x13},

+    { 42,0x80},

+    { 43,0xF4},

+    { 44,0x1C},

+    { 45,0x13},

+    { 46,0xA0},

+    { 47,0xF5},

+    { 48,0x10},

+    { 49,0x00},

+    { 50,0x40},

+    { 51,0xB9},

+    { 52,0x00},

+    { 53,0x00},

+    { 54,0x00},

+    { 55,0x00},

+    { 56,0x5C},

+    { 57,0x90},

+    { 58,0x60},

+    { 59,0x03},

+    { 60,0x18},

+    { 61,0x13},

+    { 62,0x80},

+    { 63,0xB2},

+    { 64,0x1C},

+    { 65,0x13},

+    { 66,0x80},

+    { 67,0xB4},

+    { 68,0x1C},

+    { 69,0x13},

+    { 70,0xA0},

+    { 71,0xB5},

+    { 72,0x10},

+    { 73,0x00},

+    { 74,0x40},

+    { 75,0xF8},

+    { 76,0x18},

+    { 77,0x13},

+    { 78,0x20},

+    { 79,0xEE},

+    { 80,0x5C},

+    { 81,0x90},

+    { 82,0x40},

+    { 83,0x03},

+    { 84,0x18},

+    { 85,0x13},

+    { 86,0x40},

+    { 87,0xF4},

+    { 88,0x1C},

+    { 89,0x13},

+    { 90,0x60},

+    { 91,0xF2},

+    { 92,0x4C},

+    { 93,0x13},

+    { 94,0x40},

+    { 95,0xF0},

+    { 96,0x10},

+    { 97,0x00},

+    { 98,0x40},

+    { 99,0xB8},

+    {100,0x1C},

+    {101,0x13},

+    {102,0x60},

+    {103,0xF5},

+    {104,0x18},

+    {105,0x13},

+    {106,0x20},

+    {107,0xAE},

+    {108,0x5C},

+    {109,0x90},

+    {110,0x60},

+    {111,0x03},

+    {112,0x18},

+    {113,0x13},

+    {114,0x40},

+    {115,0xB4},

+    {116,0x1C},

+    {117,0x13},

+    {118,0x60},

+    {119,0xB2},

+    {120,0x4C},

+    {121,0x13},

+    {122,0x40},

+    {123,0xB0},

+    {124,0x10},

+    {125,0x00},

+    {126,0x40},

+    {127,0xF7},

+    {  0,0x1E},

+    {  8,0x1C},

+    {  9,0x13},

+    { 10,0x60},

+    { 11,0xB5},

+    { 12,0x00},

+    { 13,0x00},

+    { 14,0x00},

+    { 15,0x00},

+    { 16,0x5C},

+    { 17,0x90},

+    { 18,0x40},

+    { 19,0x03},

+    { 20,0x18},

+    { 21,0x13},

+    { 22,0x80},

+    { 23,0xF0},

+    { 24,0x1C},

+    { 25,0x13},

+    { 26,0x80},

+    { 27,0xF5},

+    { 28,0x1C},

+    { 29,0x13},

+    { 30,0xA0},

+    { 31,0xF2},

+    { 32,0x10},

+    { 33,0x00},

+    { 34,0x40},

+    { 35,0xB7},

+    { 36,0x00},

+    { 37,0x00},

+    { 38,0x00},

+    { 39,0x00},

+    { 40,0x5C},

+    { 41,0x90},

+    { 42,0x60},

+    { 43,0x03},

+    { 44,0x18},

+    { 45,0x13},

+    { 46,0x80},

+    { 47,0xB0},

+    { 48,0x1C},

+    { 49,0x13},

+    { 50,0x80},

+    { 51,0xB5},

+    { 52,0x1C},

+    { 53,0x13},

+    { 54,0xA0},

+    { 55,0xB2},

+    { 56,0x10},

+    { 57,0x00},

+    { 58,0x40},

+    { 59,0xF6},

+    { 60,0x5C},

+    { 61,0x90},

+    { 62,0x40},

+    { 63,0x03},

+    { 64,0x00},

+    { 65,0x00},

+    { 66,0x00},

+    { 67,0x00},

+    { 68,0x00},

+    { 69,0x00},

+    { 70,0x00},

+    { 71,0x00},

+    { 72,0x00},

+    { 73,0x00},

+    { 74,0x00},

+    { 75,0x00},

+    { 76,0x10},

+    { 77,0x00},

+    { 78,0x40},

+    { 79,0xB6},

+    { 80,0x00},

+    { 81,0x00},

+    { 82,0x00},

+    { 83,0x00},

+    { 84,0x00},

+    { 85,0x00},

+    { 86,0x00},

+    { 87,0x00},

+    { 88,0x00},

+    { 89,0x00},

+    { 90,0x00},

+    { 91,0x00},

+    { 92,0x02},

+    { 93,0x00},

+    { 94,0x00},

+    { 95,0x00},

+    { 96,0x00},

+    { 97,0x00},

+    { 98,0x00},

+    { 99,0x00},

+};

+

+reg_value SRS_OFF_miniDSP_D_reg_values[] = {

+    {  0,0x0},

+    {  0x7F,0x50},

+    {  0,0x04},

+    { 36,0x00},

+    { 37,0x00},

+    { 38,0x01},

+    { 39,0x00},

+    {  0,0x0C},

+    {100,0x00},

+    {101,0x00},

+    {102,0x01},

+    {103,0x00},

+};

+

+reg_value SRS_ON_miniDSP_D_reg_values[] = {

+    {  0,0x0},

+    {  0x7F,0x50},

+    {  0,0x04},

+    { 36,0x00},

+    { 37,0x00},

+    { 38,0x02},

+    { 39,0x00},

+    {  0,0x0C},

+    {100,0x00},

+    {101,0x00},

+    {102,0x02},

+    {103,0x00},

+};

diff --git a/sound/soc/codecs/first_rate_pps_driver.h b/sound/soc/codecs/first_rate_pps_driver.h
new file mode 100644
index 00000000000..95d1996b742
--- /dev/null
+++ b/sound/soc/codecs/first_rate_pps_driver.h
@@ -0,0 +1,5959 @@
+static control main44_MUX_controls[] = {
+/*{4,28,1,0},
+{4,36,1,1},
+{4,112,1,2}*/
+};
+
+static char * main44_MUX_control_names[] = {
+/*"Stereo_Mux_1",
+"Stereo_Mux_3",
+"Stereo_Mux_4"*/
+};
+
+static control main44_VOLUME_controls[] = {
+};
+
+static char * main44_VOLUME_control_names[] = {
+};
+
+/*//INSTRUCTIONS & COEFFICIENTS
+typedef struct {
+    u8 reg_off;
+    u8 reg_val;
+} reg_value;*/
+
+static char * main44_REG_Section_names[] = {
+    "main44_miniDSP_A_reg_values",
+    "main44_miniDSP_D_reg_values",
+};
+
+reg_value main44_REG_Section_init_program[] = {
+    {  0,0x0},
+    {  0x7F,0x00},
+//                      # Set AutoINC
+    {121,0x01},
+    {  0x7F,0x78},
+//                      # reg[120][0][50] = 0x88                     ; Interpolation Ratio is 8, FIFO = Enabled
+    { 50,0x88},
+    {  0x7F,0x64},
+//                      # reg[100][0][50] = 0xa4                     ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled
+    { 50,0xA4},
+    {  0x7F,0x78},
+//                      # reg[120][0][24]=0x80
+    { 24,0x80},
+};
+
+reg_value main44_REG_Section_post_program[] = {
+    {  0,0x0},
+    {  0x7F,0x28},
+//                      # reg[40][0][1] = 0x04                        ; adaptive mode for ADC
+    {  1,0x04},
+    {  0x7F,0x50},
+//                      # reg[80][0][1] = 0x04                        ; adaptive mode for DAC
+    {  1,0x04},
+    {  0x7F,0x64},
+//                      # reg[100][0][48] = 4
+    { 48,0x04},
+//                      # reg[100][0][49] = 0
+    { 49,0x00},
+    {  0x7F,0x78},
+//                      # reg[120][0][48] = 4
+    { 48,0x04},
+//                      # reg[120][0][49] = 0
+    { 49,0x00},
+    {  0x7F,0x64},
+//                      # reg[100][0][20] = 0x00 ; Disable ADC double buffer mode
+    { 20,0x00},
+    {  0x7F,0x78},
+//                      # reg[120][0][20] = 0x00 ; Disable DAC double buffer mode
+    { 20,0x00},
+
+};
+
+reg_value main44_miniDSP_A_reg_values[] = {
+    {  0,0x0},
+    {  0x7F,0x28},
+    {  0,0x01},
+    {  8,0x00},
+    {  9,0xA7},
+    { 10,0xF8},
+    { 11,0x00},
+    { 12,0x7E},
+    { 13,0xB0},
+    { 14,0x10},
+    { 15,0x00},
+    { 16,0x7F},
+    { 17,0xFF},
+    { 18,0xFF},
+    { 19,0x00},
+    { 20,0x00},
+    { 21,0x00},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x00},
+    { 25,0x00},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0xFF},
+    { 29,0xFF},
+    { 30,0xFF},
+    { 31,0x00},
+    { 32,0x80},
+    { 33,0x00},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0x7F},
+    { 37,0xFF},
+    { 38,0xFF},
+    { 39,0x00},
+    { 40,0x40},
+    { 41,0x00},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0xFF},
+    { 49,0x9E},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0xF7},
+    { 53,0x10},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0x26},
+    { 57,0xF0},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x02},
+    { 61,0x61},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0x40},
+    { 65,0x02},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0xFF},
+    { 69,0xFC},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0xFF},
+    { 73,0xFD},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0xFF},
+    { 77,0xE5},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0xFF},
+    { 81,0xA7},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0xFF},
+    { 85,0xC7},
+    { 86,0x00},
+    { 87,0x00},
+    { 88,0xFF},
+    { 89,0xCE},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0xFF},
+    { 93,0xFE},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0xFE},
+    { 97,0xF7},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0xFF},
+    {101,0x46},
+    {102,0x00},
+    {103,0x00},
+    {104,0xFF},
+    {105,0x22},
+    {106,0x00},
+    {107,0x00},
+    {108,0x7F},
+    {109,0xFF},
+    {110,0xFF},
+    {111,0x00},
+    {112,0x00},
+    {113,0x00},
+    {114,0x00},
+    {115,0x00},
+    {116,0x00},
+    {117,0x00},
+    {118,0x00},
+    {119,0x00},
+    {120,0x00},
+    {121,0x00},
+    {122,0x00},
+    {123,0x00},
+    {124,0x00},
+    {125,0x00},
+    {126,0x00},
+    {127,0x00},
+    {  0,0x02},
+    {  8,0xFF},
+    {  9,0x0F},
+    { 10,0x00},
+    { 11,0x00},
+    { 12,0xFA},
+    { 13,0x8C},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0xF5},
+    { 17,0x08},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0xFD},
+    { 21,0x92},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0xF3},
+    { 25,0xA3},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0x03},
+    { 29,0xB3},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0x00},
+    { 33,0x33},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0x00},
+    { 37,0x71},
+    { 38,0x00},
+    { 39,0x00},
+    { 40,0x40},
+    { 41,0x60},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0x00},
+    { 45,0xE2},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x00},
+    { 49,0xC6},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x00},
+    { 53,0x87},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0x00},
+    { 57,0x0F},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x00},
+    { 61,0x0A},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0x00},
+    { 65,0x02},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x01},
+    { 69,0x81},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x18},
+    { 73,0x89},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0x07},
+    { 77,0xFB},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x03},
+    { 81,0xBE},
+    { 82,0x00},
+    { 83,0x00},
+    {  0,0x09},
+    { 72,0x00},
+    { 73,0xA7},
+    { 74,0xF8},
+    { 75,0x00},
+    { 76,0x7E},
+    { 77,0xB0},
+    { 78,0x10},
+    { 79,0x00},
+    { 80,0x7F},
+    { 81,0xFF},
+    { 82,0xFF},
+    { 83,0x00},
+    { 84,0x00},
+    { 85,0x00},
+    { 86,0x00},
+    { 87,0x00},
+    { 88,0x00},
+    { 89,0x00},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0xFF},
+    { 93,0xFF},
+    { 94,0xFF},
+    { 95,0x00},
+    { 96,0x80},
+    { 97,0x00},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0x7F},
+    {101,0xFF},
+    {102,0xFF},
+    {103,0x00},
+    {104,0x40},
+    {105,0x00},
+    {106,0x00},
+    {107,0x00},
+    {108,0x00},
+    {109,0x00},
+    {110,0x00},
+    {111,0x00},
+    {112,0xFF},
+    {113,0x9E},
+    {114,0x00},
+    {115,0x00},
+    {116,0xF7},
+    {117,0x10},
+    {118,0x00},
+    {119,0x00},
+    {120,0x26},
+    {121,0xF0},
+    {122,0x00},
+    {123,0x00},
+    {124,0x02},
+    {125,0x61},
+    {126,0x00},
+    {127,0x00},
+    {  0,0x0A},
+    {  8,0x40},
+    {  9,0x02},
+    { 10,0x00},
+    { 11,0x00},
+    { 12,0xFF},
+    { 13,0xFC},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0xFF},
+    { 17,0xFD},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0xFF},
+    { 21,0xE5},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0xFF},
+    { 25,0xA7},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0xFF},
+    { 29,0xC7},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0xFF},
+    { 33,0xCE},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0xFF},
+    { 37,0xFE},
+    { 38,0x00},
+    { 39,0x00},
+    { 40,0xFE},
+    { 41,0xF7},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0xFF},
+    { 45,0x46},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0xFF},
+    { 49,0x22},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x7F},
+    { 53,0xFF},
+    { 54,0xFF},
+    { 55,0x00},
+    { 56,0x00},
+    { 57,0x00},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x00},
+    { 61,0x00},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0x00},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0xFF},
+    { 73,0x0F},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0xFA},
+    { 77,0x8C},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0xF5},
+    { 81,0x08},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0xFD},
+    { 85,0x92},
+    { 86,0x00},
+    { 87,0x00},
+    { 88,0xF3},
+    { 89,0xA3},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0x03},
+    { 93,0xB3},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x00},
+    { 97,0x33},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0x00},
+    {101,0x71},
+    {102,0x00},
+    {103,0x00},
+    {104,0x40},
+    {105,0x60},
+    {106,0x00},
+    {107,0x00},
+    {108,0x00},
+    {109,0xE2},
+    {110,0x00},
+    {111,0x00},
+    {112,0x00},
+    {113,0xC6},
+    {114,0x00},
+    {115,0x00},
+    {116,0x00},
+    {117,0x87},
+    {118,0x00},
+    {119,0x00},
+    {120,0x00},
+    {121,0x0F},
+    {122,0x00},
+    {123,0x00},
+    {124,0x00},
+    {125,0x0A},
+    {126,0x00},
+    {127,0x00},
+    {  0,0x0B},
+    {  8,0x00},
+    {  9,0x02},
+    { 10,0x00},
+    { 11,0x00},
+    { 12,0x01},
+    { 13,0x81},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x18},
+    { 17,0x89},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0x07},
+    { 21,0xFB},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x03},
+    { 25,0xBE},
+    { 26,0x00},
+    { 27,0x00},
+    {  0,0x0},
+    {  0x7F,0x14},
+    {  0,0x01},
+    {  8,0xC0},
+    {  9,0x00},
+    { 10,0x00},
+    { 11,0x00},
+    { 12,0xC0},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    {  0,0x0},
+    {  0x7F,0x64},
+    {  0,0x01},
+    {  8,0x58},
+    {  9,0x60},
+    { 10,0x08},
+    { 11,0x01},
+    { 12,0x60},
+    { 13,0x60},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x58},
+    { 17,0x60},
+    { 18,0x00},
+    { 19,0x09},
+    { 20,0x00},
+    { 21,0x00},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x44},
+    { 25,0x00},
+    { 26,0xC0},
+    { 27,0x07},
+    { 28,0x04},
+    { 29,0x00},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0x04},
+    { 33,0x00},
+    { 34,0x00},
+    { 35,0x0D},
+    { 36,0x04},
+    { 37,0x00},
+    { 38,0x00},
+    { 39,0x08},
+    { 40,0x04},
+    { 41,0x00},
+    { 42,0x00},
+    { 43,0x04},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x00},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x44},
+    { 53,0x00},
+    { 54,0x00},
+    { 55,0x07},
+    { 56,0x21},
+    { 57,0x00},
+    { 58,0x20},
+    { 59,0x00},
+    { 60,0x4B},
+    { 61,0x00},
+    { 62,0xC0},
+    { 63,0x00},
+    { 64,0x4B},
+    { 65,0x00},
+    { 66,0xE0},
+    { 67,0x00},
+    { 68,0x10},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x10},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0x0D},
+    { 76,0x10},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0x08},
+    { 80,0x10},
+    { 81,0x00},
+    { 82,0x00},
+    { 83,0x04},
+    { 84,0x18},
+    { 85,0x01},
+    { 86,0xC0},
+    { 87,0x0F},
+    { 88,0x1C},
+    { 89,0x01},
+    { 90,0xA0},
+    { 91,0x09},
+    { 92,0x1C},
+    { 93,0x01},
+    { 94,0xA0},
+    { 95,0x03},
+    { 96,0x1C},
+    { 97,0x01},
+    { 98,0x80},
+    { 99,0x0A},
+    {100,0x1C},
+    {101,0x01},
+    {102,0x80},
+    {103,0x02},
+    {104,0x1C},
+    {105,0x01},
+    {106,0x40},
+    {107,0x0C},
+    {108,0x1C},
+    {109,0x01},
+    {110,0x40},
+    {111,0x00},
+    {112,0x1C},
+    {113,0x01},
+    {114,0x60},
+    {115,0x01},
+    {116,0x1C},
+    {117,0x01},
+    {118,0x60},
+    {119,0x0B},
+    {120,0x18},
+    {121,0x01},
+    {122,0x40},
+    {123,0x03},
+    {124,0x1C},
+    {125,0x01},
+    {126,0x40},
+    {127,0x08},
+    {  0,0x02},
+    {  8,0x1C},
+    {  9,0x01},
+    { 10,0x60},
+    { 11,0x09},
+    { 12,0x10},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x2D},
+    { 16,0x1C},
+    { 17,0x01},
+    { 18,0x60},
+    { 19,0x02},
+    { 20,0x1C},
+    { 21,0x01},
+    { 22,0x80},
+    { 23,0x01},
+    { 24,0x1C},
+    { 25,0x01},
+    { 26,0x80},
+    { 27,0x0A},
+    { 28,0x1C},
+    { 29,0x01},
+    { 30,0xA0},
+    { 31,0x00},
+    { 32,0x1C},
+    { 33,0x01},
+    { 34,0xA0},
+    { 35,0x0B},
+    { 36,0x1C},
+    { 37,0x01},
+    { 38,0xC0},
+    { 39,0x06},
+    { 40,0x00},
+    { 41,0x00},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x00},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x10},
+    { 53,0x00},
+    { 54,0x00},
+    { 55,0x0F},
+    { 56,0x18},
+    { 57,0x01},
+    { 58,0xE0},
+    { 59,0x2C},
+    { 60,0x1C},
+    { 61,0x02},
+    { 62,0x00},
+    { 63,0x11},
+    { 64,0x1C},
+    { 65,0x02},
+    { 66,0x00},
+    { 67,0x48},
+    { 68,0x1C},
+    { 69,0x01},
+    { 70,0xE0},
+    { 71,0x2D},
+    { 72,0x1C},
+    { 73,0x02},
+    { 74,0x20},
+    { 75,0x2F},
+    { 76,0x1C},
+    { 77,0x02},
+    { 78,0x20},
+    { 79,0x2A},
+    { 80,0x1C},
+    { 81,0x02},
+    { 82,0x40},
+    { 83,0x31},
+    { 84,0x1C},
+    { 85,0x02},
+    { 86,0x40},
+    { 87,0x28},
+    { 88,0x1C},
+    { 89,0x02},
+    { 90,0x60},
+    { 91,0x37},
+    { 92,0x1C},
+    { 93,0x02},
+    { 94,0x60},
+    { 95,0x22},
+    { 96,0x1C},
+    { 97,0x02},
+    { 98,0x80},
+    { 99,0x14},
+    {100,0x1C},
+    {101,0x02},
+    {102,0x80},
+    {103,0x45},
+    {104,0x1C},
+    {105,0x02},
+    {106,0xA0},
+    {107,0x12},
+    {108,0x1C},
+    {109,0x02},
+    {110,0xA0},
+    {111,0x47},
+    {112,0x1C},
+    {113,0x02},
+    {114,0xC0},
+    {115,0x38},
+    {116,0x1C},
+    {117,0x02},
+    {118,0xC0},
+    {119,0x21},
+    {120,0x1C},
+    {121,0x02},
+    {122,0xE0},
+    {123,0x33},
+    {124,0x1C},
+    {125,0x02},
+    {126,0xE0},
+    {127,0x26},
+    {  0,0x03},
+    {  8,0x1C},
+    {  9,0x03},
+    { 10,0x00},
+    { 11,0x16},
+    { 12,0x1C},
+    { 13,0x03},
+    { 14,0x00},
+    { 15,0x43},
+    { 16,0x1C},
+    { 17,0x03},
+    { 18,0xC0},
+    { 19,0x35},
+    { 20,0x1C},
+    { 21,0x03},
+    { 22,0xC0},
+    { 23,0x24},
+    { 24,0x1C},
+    { 25,0x03},
+    { 26,0xE0},
+    { 27,0x1A},
+    { 28,0x1C},
+    { 29,0x03},
+    { 30,0xE0},
+    { 31,0x3F},
+    { 32,0x1C},
+    { 33,0x04},
+    { 34,0x00},
+    { 35,0x3A},
+    { 36,0x1C},
+    { 37,0x04},
+    { 38,0x00},
+    { 39,0x1F},
+    { 40,0x1C},
+    { 41,0x04},
+    { 42,0x20},
+    { 43,0x18},
+    { 44,0x1C},
+    { 45,0x04},
+    { 46,0x20},
+    { 47,0x41},
+    { 48,0x1C},
+    { 49,0x04},
+    { 50,0x40},
+    { 51,0x1C},
+    { 52,0x1C},
+    { 53,0x04},
+    { 54,0x40},
+    { 55,0x3D},
+    { 56,0x1C},
+    { 57,0x04},
+    { 58,0x60},
+    { 59,0x19},
+    { 60,0x1C},
+    { 61,0x04},
+    { 62,0x60},
+    { 63,0x40},
+    { 64,0x1C},
+    { 65,0x04},
+    { 66,0x80},
+    { 67,0x30},
+    { 68,0x1C},
+    { 69,0x04},
+    { 70,0x80},
+    { 71,0x29},
+    { 72,0x1C},
+    { 73,0x04},
+    { 74,0xA0},
+    { 75,0x15},
+    { 76,0x1C},
+    { 77,0x04},
+    { 78,0xA0},
+    { 79,0x44},
+    { 80,0x1C},
+    { 81,0x04},
+    { 82,0xC0},
+    { 83,0x3B},
+    { 84,0x1C},
+    { 85,0x04},
+    { 86,0xC0},
+    { 87,0x1E},
+    { 88,0x1C},
+    { 89,0x04},
+    { 90,0xE0},
+    { 91,0x34},
+    { 92,0x1C},
+    { 93,0x04},
+    { 94,0xE0},
+    { 95,0x25},
+    { 96,0x1C},
+    { 97,0x05},
+    { 98,0x00},
+    { 99,0x36},
+    {100,0x1C},
+    {101,0x05},
+    {102,0x00},
+    {103,0x23},
+    {104,0x1C},
+    {105,0x05},
+    {106,0x20},
+    {107,0x32},
+    {108,0x1C},
+    {109,0x05},
+    {110,0x20},
+    {111,0x27},
+    {112,0x1C},
+    {113,0x05},
+    {114,0x40},
+    {115,0x13},
+    {116,0x1C},
+    {117,0x05},
+    {118,0x40},
+    {119,0x46},
+    {120,0x1C},
+    {121,0x05},
+    {122,0x60},
+    {123,0x2E},
+    {124,0x1C},
+    {125,0x05},
+    {126,0x60},
+    {127,0x2B},
+    {  0,0x04},
+    {  8,0x1C},
+    {  9,0x05},
+    { 10,0x80},
+    { 11,0x10},
+    { 12,0x1C},
+    { 13,0x05},
+    { 14,0x80},
+    { 15,0x49},
+    { 16,0x1C},
+    { 17,0x05},
+    { 18,0xA0},
+    { 19,0x17},
+    { 20,0x1C},
+    { 21,0x05},
+    { 22,0xA0},
+    { 23,0x42},
+    { 24,0x1C},
+    { 25,0x05},
+    { 26,0xC0},
+    { 27,0x1D},
+    { 28,0x1C},
+    { 29,0x05},
+    { 30,0xC0},
+    { 31,0x3C},
+    { 32,0x1C},
+    { 33,0x05},
+    { 34,0xE0},
+    { 35,0x1B},
+    { 36,0x1C},
+    { 37,0x05},
+    { 38,0xE0},
+    { 39,0x3E},
+    { 40,0x1C},
+    { 41,0x06},
+    { 42,0x00},
+    { 43,0x39},
+    { 44,0x1C},
+    { 45,0x06},
+    { 46,0x00},
+    { 47,0x20},
+    { 48,0x00},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x5C},
+    { 53,0x90},
+    { 54,0x40},
+    { 55,0x00},
+    { 56,0x00},
+    { 57,0x00},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x5C},
+    { 61,0x90},
+    { 62,0x20},
+    { 63,0x00},
+    { 64,0x00},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x00},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0x10},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0x49},
+    { 80,0x18},
+    { 81,0x00},
+    { 82,0x60},
+    { 83,0x4A},
+    { 84,0x1C},
+    { 85,0x00},
+    { 86,0x80},
+    { 87,0x4C},
+    { 88,0x1C},
+    { 89,0x00},
+    { 90,0x40},
+    { 91,0x49},
+    { 92,0x30},
+    { 93,0x00},
+    { 94,0x00},
+    { 95,0x4C},
+    { 96,0x1C},
+    { 97,0x00},
+    { 98,0x20},
+    { 99,0x4E},
+    {100,0x00},
+    {101,0x00},
+    {102,0x00},
+    {103,0x00},
+    {104,0x10},
+    {105,0x30},
+    {106,0x00},
+    {107,0x4B},
+    {108,0x34},
+    {109,0x00},
+    {110,0x00},
+    {111,0x4B},
+    {112,0x5C},
+    {113,0x60},
+    {114,0xA0},
+    {115,0x4B},
+    {116,0x0C},
+    {117,0x00},
+    {118,0x40},
+    {119,0x00},
+    {120,0x00},
+    {121,0x00},
+    {122,0x00},
+    {123,0x00},
+    {124,0x10},
+    {125,0x30},
+    {126,0x00},
+    {127,0x4D},
+    {  0,0x05},
+    {  8,0x10},
+    {  9,0x13},
+    { 10,0xE0},
+    { 11,0x50},
+    { 12,0x18},
+    { 13,0x01},
+    { 14,0x00},
+    { 15,0x50},
+    { 16,0x18},
+    { 17,0x03},
+    { 18,0x60},
+    { 19,0x53},
+    { 20,0x6C},
+    { 21,0x03},
+    { 22,0x40},
+    { 23,0x52},
+    { 24,0x6C},
+    { 25,0x03},
+    { 26,0x80},
+    { 27,0x55},
+    { 28,0x10},
+    { 29,0x00},
+    { 30,0x20},
+    { 31,0x51},
+    { 32,0x1C},
+    { 33,0x03},
+    { 34,0x20},
+    { 35,0x51},
+    { 36,0x1C},
+    { 37,0x03},
+    { 38,0xA0},
+    { 39,0x56},
+    { 40,0x00},
+    { 41,0x00},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x00},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x10},
+    { 53,0x00},
+    { 54,0x00},
+    { 55,0x54},
+    { 56,0x18},
+    { 57,0x01},
+    { 58,0x00},
+    { 59,0x54},
+    { 60,0x00},
+    { 61,0x00},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0x0C},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x03},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x00},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0x00},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x02},
+    { 81,0x00},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0x00},
+    { 85,0x00},
+    { 86,0x00},
+    { 87,0x00},
+};
+
+
+#define main44_miniDSP_A_reg_values_COEFF_START   0
+#define main44_miniDSP_A_reg_values_COEFF_SIZE    958
+#define main44_miniDSP_A_reg_values_INST_START    958
+#define main44_miniDSP_A_reg_values_INST_SIZE     2160
+
+reg_value main44_miniDSP_D_reg_values[] = {
+    {  0,0x0},
+    {  0x7F,0x50},
+    {  0,0x01},
+    {  8,0xFF},
+    {  9,0xFF},
+    { 10,0xFF},
+    { 11,0x00},
+    { 12,0x80},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x7F},
+    { 17,0xF7},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0x80},
+    { 21,0x09},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x7F},
+    { 25,0xEF},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0x66},
+    { 29,0x66},
+    { 30,0x60},
+    { 31,0x00},
+    { 32,0x1B},
+    { 33,0x33},
+    { 34,0x20},
+    { 35,0x00},
+    { 36,0x66},
+    { 37,0x66},
+    { 38,0x60},
+    { 39,0x00},
+    { 40,0x33},
+    { 41,0x33},
+    { 42,0x30},
+    { 43,0x00},
+    { 44,0x4C},
+    { 45,0xCC},
+    { 46,0xCD},
+    { 47,0x00},
+    { 48,0x00},
+    { 49,0x00},
+    { 50,0x01},
+    { 51,0x00},
+    { 52,0x33},
+    { 53,0x33},
+    { 54,0x30},
+    { 55,0x00},
+    { 56,0x33},
+    { 57,0x33},
+    { 58,0x30},
+    { 59,0x00},
+    { 60,0x7F},
+    { 61,0xFF},
+    { 62,0xAC},
+    { 63,0x00},
+    { 64,0x80},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x40},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x40},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0xC0},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x50},
+    { 81,0xC3},
+    { 82,0x36},
+    { 83,0x00},
+    { 84,0x02},
+    { 85,0x8F},
+    { 86,0x5C},
+    { 87,0x00},
+    { 88,0x02},
+    { 89,0xD7},
+    { 90,0x0A},
+    { 91,0x00},
+    { 92,0x00},
+    { 93,0x00},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x00},
+    { 97,0x00},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0x00},
+    {101,0x00},
+    {102,0x00},
+    {103,0x00},
+    {104,0x00},
+    {105,0x00},
+    {106,0x00},
+    {107,0x00},
+    {108,0x00},
+    {109,0x00},
+    {110,0x00},
+    {111,0x00},
+    {112,0x40},
+    {113,0x00},
+    {114,0x00},
+    {115,0x00},
+    {116,0xFF},
+    {117,0xFF},
+    {118,0xFF},
+    {119,0x00},
+    {120,0xFF},
+    {121,0xFF},
+    {122,0xFE},
+    {123,0x00},
+    {124,0xFF},
+    {125,0xFF},
+    {126,0xFD},
+    {127,0x00},
+    {  0,0x02},
+    {  8,0xFF},
+    {  9,0xFF},
+    { 10,0xFC},
+    { 11,0x00},
+    { 12,0x00},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x73},
+    { 17,0x56},
+    { 18,0x6E},
+    { 19,0x00},
+    { 20,0x7F},
+    { 21,0xF4},
+    { 22,0xA0},
+    { 23,0x00},
+    { 24,0x00},
+    { 25,0x80},
+    { 26,0x2D},
+    { 27,0x00},
+    { 28,0x7E},
+    { 29,0xFF},
+    { 30,0xA5},
+    { 31,0x00},
+    { 32,0x00},
+    { 33,0x2E},
+    { 34,0x73},
+    { 35,0x00},
+    { 36,0xFF},
+    { 37,0xD1},
+    { 38,0x8D},
+    { 39,0x00},
+    { 40,0x7F},
+    { 41,0xC1},
+    { 42,0x2F},
+    { 43,0x00},
+    { 44,0x80},
+    { 45,0x7B},
+    { 46,0x94},
+    { 47,0x00},
+    { 48,0x01},
+    { 49,0x50},
+    { 50,0xC1},
+    { 51,0x00},
+    { 52,0xFE},
+    { 53,0xAF},
+    { 54,0x3F},
+    { 55,0x00},
+    { 56,0x7F},
+    { 57,0x55},
+    { 58,0xC1},
+    { 59,0x00},
+    { 60,0x81},
+    { 61,0x4E},
+    { 62,0x4E},
+    { 63,0x00},
+    { 64,0x7F},
+    { 65,0xFF},
+    { 66,0xFF},
+    { 67,0x00},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0xC7},
+    { 73,0x2E},
+    { 74,0x8D},
+    { 75,0x00},
+    { 76,0x31},
+    { 77,0x91},
+    { 78,0x54},
+    { 79,0x00},
+    { 80,0xD1},
+    { 81,0xFC},
+    { 82,0xF4},
+    { 83,0x00},
+    { 84,0x2A},
+    { 85,0x09},
+    { 86,0x1A},
+    { 87,0x00},
+    { 88,0xEA},
+    { 89,0xD6},
+    { 90,0x1C},
+    { 91,0x00},
+    { 92,0xC5},
+    { 93,0x28},
+    { 94,0xA2},
+    { 95,0x00},
+    { 96,0x32},
+    { 97,0xD7},
+    { 98,0x53},
+    { 99,0x00},
+    {100,0xD3},
+    {101,0x74},
+    {102,0x4B},
+    {103,0x00},
+    {104,0x15},
+    {105,0x04},
+    {106,0x8D},
+    {107,0x00},
+    {108,0xF5},
+    {109,0x6B},
+    {110,0x0E},
+    {111,0x00},
+    {112,0xC0},
+    {113,0x0C},
+    {114,0x47},
+    {115,0x00},
+    {116,0x3F},
+    {117,0x99},
+    {118,0x61},
+    {119,0x00},
+    {120,0x3E},
+    {121,0xE2},
+    {122,0x1D},
+    {123,0x00},
+    {124,0x3E},
+    {125,0xE2},
+    {126,0x1D},
+    {127,0x00},
+    {  0,0x03},
+    {  8,0x0A},
+    {  9,0x57},
+    { 10,0x0D},
+    { 11,0x00},
+    { 12,0xF5},
+    { 13,0xA8},
+    { 14,0xF3},
+    { 15,0x00},
+    { 16,0x6E},
+    { 17,0x1B},
+    { 18,0xC0},
+    { 19,0x00},
+    { 20,0x89},
+    { 21,0x90},
+    { 22,0x65},
+    { 23,0x00},
+    { 24,0x1B},
+    { 25,0x6E},
+    { 26,0xFE},
+    { 27,0x00},
+    { 28,0xE4},
+    { 29,0x91},
+    { 30,0x02},
+    { 31,0x00},
+    { 32,0x5B},
+    { 33,0x45},
+    { 34,0x9C},
+    { 35,0x00},
+    { 36,0x99},
+    { 37,0x5F},
+    { 38,0xEC},
+    { 39,0x00},
+    { 40,0x15},
+    { 41,0x3D},
+    { 42,0xC9},
+    { 43,0x00},
+    { 44,0xEA},
+    { 45,0xC2},
+    { 46,0x37},
+    { 47,0x00},
+    { 48,0x40},
+    { 49,0x53},
+    { 50,0x16},
+    { 51,0x00},
+    { 52,0x93},
+    { 53,0xA5},
+    { 54,0xAE},
+    { 55,0x00},
+    { 56,0x9B},
+    { 57,0x77},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x64},
+    { 61,0x88},
+    { 62,0xF0},
+    { 63,0x00},
+    { 64,0x45},
+    { 65,0x84},
+    { 66,0x40},
+    { 67,0x00},
+    { 68,0xBA},
+    { 69,0x7B},
+    { 70,0xB0},
+    { 71,0x00},
+    { 72,0xC3},
+    { 73,0xE0},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0x3C},
+    { 77,0x1F},
+    { 78,0xF0},
+    { 79,0x00},
+    { 80,0x68},
+    { 81,0x76},
+    { 82,0x1D},
+    { 83,0x00},
+    { 84,0x97},
+    { 85,0x89},
+    { 86,0xE3},
+    { 87,0x00},
+    { 88,0x67},
+    { 89,0xEA},
+    { 90,0x3A},
+    { 91,0x00},
+    { 92,0xAD},
+    { 93,0xFC},
+    { 94,0x02},
+    { 95,0x00},
+    { 96,0x79},
+    { 97,0xEC},
+    { 98,0x4D},
+    { 99,0x00},
+    {100,0x86},
+    {101,0x13},
+    {102,0xB3},
+    {103,0x00},
+    {104,0x3A},
+    {105,0x36},
+    {106,0x6A},
+    {107,0x00},
+    {108,0x7F},
+    {109,0xFF},
+    {110,0xFF},
+    {111,0x00},
+    {112,0x00},
+    {113,0x00},
+    {114,0x00},
+    {115,0x00},
+    {116,0x00},
+    {117,0x00},
+    {118,0x00},
+    {119,0x00},
+    {120,0x00},
+    {121,0x00},
+    {122,0x00},
+    {123,0x00},
+    {124,0x00},
+    {125,0x00},
+    {126,0x00},
+    {127,0x00},
+    {  0,0x04},
+    {  8,0x7F},
+    {  9,0xFF},
+    { 10,0xFF},
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+    { 90,0x60},
+    { 91,0xF2},
+    { 92,0x4C},
+    { 93,0x13},
+    { 94,0x40},
+    { 95,0xF0},
+    { 96,0x10},
+    { 97,0x00},
+    { 98,0x40},
+    { 99,0xB8},
+    {100,0x1C},
+    {101,0x13},
+    {102,0x60},
+    {103,0xF5},
+    {104,0x18},
+    {105,0x13},
+    {106,0x20},
+    {107,0xAE},
+    {108,0x5C},
+    {109,0x90},
+    {110,0x60},
+    {111,0x03},
+    {112,0x18},
+    {113,0x13},
+    {114,0x40},
+    {115,0xB4},
+    {116,0x1C},
+    {117,0x13},
+    {118,0x60},
+    {119,0xB2},
+    {120,0x4C},
+    {121,0x13},
+    {122,0x40},
+    {123,0xB0},
+    {124,0x10},
+    {125,0x00},
+    {126,0x40},
+    {127,0xF7},
+    {  0,0x1E},
+    {  8,0x1C},
+    {  9,0x13},
+    { 10,0x60},
+    { 11,0xB5},
+    { 12,0x00},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x5C},
+    { 17,0x90},
+    { 18,0x40},
+    { 19,0x03},
+    { 20,0x18},
+    { 21,0x13},
+    { 22,0x80},
+    { 23,0xF0},
+    { 24,0x1C},
+    { 25,0x13},
+    { 26,0x80},
+    { 27,0xF5},
+    { 28,0x1C},
+    { 29,0x13},
+    { 30,0xA0},
+    { 31,0xF2},
+    { 32,0x10},
+    { 33,0x00},
+    { 34,0x40},
+    { 35,0xB7},
+    { 36,0x00},
+    { 37,0x00},
+    { 38,0x00},
+    { 39,0x00},
+    { 40,0x5C},
+    { 41,0x90},
+    { 42,0x60},
+    { 43,0x03},
+    { 44,0x18},
+    { 45,0x13},
+    { 46,0x80},
+    { 47,0xB0},
+    { 48,0x1C},
+    { 49,0x13},
+    { 50,0x80},
+    { 51,0xB5},
+    { 52,0x1C},
+    { 53,0x13},
+    { 54,0xA0},
+    { 55,0xB2},
+    { 56,0x10},
+    { 57,0x00},
+    { 58,0x40},
+    { 59,0xF6},
+    { 60,0x5C},
+    { 61,0x90},
+    { 62,0x40},
+    { 63,0x03},
+    { 64,0x00},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x00},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0x10},
+    { 77,0x00},
+    { 78,0x40},
+    { 79,0xB6},
+    { 80,0x00},
+    { 81,0x00},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0x00},
+    { 85,0x00},
+    { 86,0x00},
+    { 87,0x00},
+    { 88,0x00},
+    { 89,0x00},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0x02},
+    { 93,0x00},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x00},
+    { 97,0x00},
+    { 98,0x00},
+    { 99,0x00},
+};
+
+#define main44_miniDSP_D_reg_values_COEFF_START   0
+#define main44_miniDSP_D_reg_values_COEFF_SIZE    672
+#define main44_miniDSP_D_reg_values_INST_START    672
+#define main44_miniDSP_D_reg_values_INST_SIZE     2124
+
diff --git a/sound/soc/codecs/rt5639.c b/sound/soc/codecs/rt5639.c
new file mode 100644
index 00000000000..139503e0d32
--- /dev/null
+++ b/sound/soc/codecs/rt5639.c
@@ -0,0 +1,2444 @@
+/*
+ * rt5639.c  --  RT5639 ALSA SoC audio codec driver
+ *
+ * Copyright 2011 Realtek Semiconductor Corp.
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "rt5639.h"
+
+#define RT5639_DEMO 1 
+#define RT5639_REG_RW 1
+#define RT5639_DET_EXT_MIC 0 
+
+#ifdef RT5639_DEMO
+struct rt5639_init_reg {
+        u8 reg;
+        u16 val;
+};
+
+static struct rt5639_init_reg init_list[] = {
+        {RT5639_DUMMY1          , 0x3701},//fa[12:13] = 1'b;fa[8~10]=1;fa[0]=1
+        {RT5639_DEPOP_M1        , 0x0019},//8e[4:3] = 11'b; 8e[0] = 1'b
+        {RT5639_DEPOP_M2        , 0x3100},//8f[13] = 1'b
+        {RT5639_ADDA_CLK1       , 0x1114},//73[2] = 1'b
+        {RT5639_MICBIAS         , 0x3030},//93[5:4] = 11'b
+        {RT5639_PRIV_INDEX      , 0x003d},//PR3d[12] = 1'b
+        {RT5639_PRIV_DATA       , 0x3600},
+        {RT5639_CLS_D_OUT       , 0xa000},//8d[11] = 0'b
+        {RT5639_PRIV_INDEX      , 0x001c},//PR1c = 0D21'h
+        {RT5639_PRIV_DATA       , 0x0D21},
+        
+        {RT5639_PRIV_INDEX      , 0x001b},//PR1B = 0D21'h
+        {RT5639_PRIV_DATA       , 0x0000},
+        {RT5639_PRIV_INDEX      , 0x0012},//PR12 = 0aa8'h
+        {RT5639_PRIV_DATA       , 0x0aa8},
+        {RT5639_PRIV_INDEX      , 0x0014},//PR14 = 0aaa'h
+        {RT5639_PRIV_DATA       , 0x0aaa},
+        {RT5639_PRIV_INDEX      , 0x0020},//PR20 = 6110'h
+        {RT5639_PRIV_DATA       , 0x6110},
+        {RT5639_PRIV_INDEX      , 0x0021},//PR21 = e0e0'h
+        {RT5639_PRIV_DATA       , 0xe0e0},
+        {RT5639_PRIV_INDEX      , 0x0023},//PR23 = 1804'h
+        {RT5639_PRIV_DATA       , 0x1804},
+        /*playback*/
+        {RT5639_STO_DAC_MIXER   , 0x1414},//Dig inf 1 -> Sto DAC mixer -> DACL
+        {RT5639_OUT_L3_MIXER    , 0x01fe},//DACL1 -> OUTMIXL
+        {RT5639_OUT_R3_MIXER    , 0x01fe},//DACR1 -> OUTMIXR
+        {RT5639_HP_VOL          , 0x8888},//OUTMIX -> HPVOL
+        {RT5639_HPO_MIXER       , 0xc000},//HPVOL -> HPOLMIX
+//      {RT5639_HPO_MIXER       , 0xa000},//DAC1 -> HPOLMIX
+        {RT5639_SPK_L_MIXER     , 0x0036},//DACL1 -> SPKMIXL
+        {RT5639_SPK_R_MIXER     , 0x0036},//DACR1 -> SPKMIXR
+        {RT5639_SPK_VOL         , 0x8888},//SPKMIX -> SPKVOL
+        {RT5639_SPO_L_MIXER     , 0xe800},//SPKVOLL -> SPOLMIX
+        {RT5639_SPO_R_MIXER     , 0x2800},//SPKVOLR -> SPORMIX
+//      {RT5639_SPO_L_MIXER     , 0xb800},//DAC -> SPOLMIX
+//      {RT5639_SPO_R_MIXER     , 0x1800},//DAC -> SPORMIX  
+//      {RT5639_I2S1_SDP        , 0xD000},//change IIS1 and IIS2
+        /*record*/
+        {RT5639_IN1_IN2         , 0x5080},//IN1 boost 40db and differential mode
+        {RT5639_IN3_IN4         , 0x0500},//IN2 boost 40db and signal ended mode
+        {RT5639_REC_L2_MIXER    , 0x007d},//Mic1 -> RECMIXL
+        {RT5639_REC_R2_MIXER    , 0x007d},//Mic1 -> RECMIXR
+//      {RT5639_REC_L2_MIXER    , 0x006f},//Mic2 -> RECMIXL
+//      {RT5639_REC_R2_MIXER    , 0x006f},//Mic2 -> RECMIXR
+        {RT5639_STO_ADC_MIXER   , 0x3020},//ADC -> Sto ADC mixer
+
+#if RT5639_DET_EXT_MIC
+        {RT5639_MICBIAS         ,0x3800},//enable MICBIAS short current
+        {RT5639_GPIO_CTRL1      ,0x8400},//set GPIO1 to IRQ
+        {RT5639_GPIO_CTRL3      ,0x0004},//set GPIO1 output
+        {RT5639_IRQ_CTRL2       ,0x8000},//set MICBIAS short current to IRQ   ( if sticky set regBE : 8800 )
+#endif
+};
+#define RT5639_INIT_REG_LEN ARRAY_SIZE(init_list)
+
+static int rt5639_reg_init(struct snd_soc_codec *codec)
+{
+        int i;
+
+        for (i = 0; i < RT5639_INIT_REG_LEN; i++)
+                snd_soc_write(codec, init_list[i].reg, init_list[i].val);
+
+        return 0;
+}
+#endif
+
+static const u16 rt5639_reg[RT5639_VENDOR_ID2 + 1] = {
+        [RT5639_RESET] = 0x0008,
+        [RT5639_SPK_VOL] = 0xc8c8,
+        [RT5639_HP_VOL] = 0xc8c8,
+        [RT5639_OUTPUT] = 0xc8c8,
+        [RT5639_MONO_OUT] = 0x8000,
+        [RT5639_INL_INR_VOL] = 0x0808,
+        [RT5639_DAC1_DIG_VOL] = 0xafaf,
+        [RT5639_DAC2_DIG_VOL] = 0xafaf,
+        [RT5639_ADC_DIG_VOL] = 0x2f2f,
+        [RT5639_ADC_DATA] = 0x2f2f,
+        [RT5639_STO_ADC_MIXER] = 0x7060,
+        [RT5639_MONO_ADC_MIXER] = 0x7070,
+        [RT5639_AD_DA_MIXER] = 0x8080,
+        [RT5639_STO_DAC_MIXER] = 0x5454,
+        [RT5639_MONO_DAC_MIXER] = 0x5454,
+        [RT5639_DIG_MIXER] = 0xaa00,
+        [RT5639_DSP_PATH2] = 0xa000,
+        [RT5639_REC_L2_MIXER] = 0x007f,
+        [RT5639_REC_R2_MIXER] = 0x007f,
+        [RT5639_HPO_MIXER] = 0xe000,
+        [RT5639_SPK_L_MIXER] = 0x003e,
+        [RT5639_SPK_R_MIXER] = 0x003e,
+        [RT5639_SPO_L_MIXER] = 0xf800,
+        [RT5639_SPO_R_MIXER] = 0x3800,
+        [RT5639_SPO_CLSD_RATIO] = 0x0004,
+        [RT5639_MONO_MIXER] = 0xfc00,
+        [RT5639_OUT_L3_MIXER] = 0x01ff,
+        [RT5639_OUT_R3_MIXER] = 0x01ff,
+        [RT5639_LOUT_MIXER] = 0xf000,
+        [RT5639_PWR_ANLG1] = 0x00c0,
+        [RT5639_I2S1_SDP] = 0x8000,
+        [RT5639_I2S2_SDP] = 0x8000,
+        [RT5639_I2S3_SDP] = 0x8000,
+        [RT5639_ADDA_CLK1] = 0x1110,
+        [RT5639_ADDA_CLK2] = 0x0c00,
+        [RT5639_DMIC] = 0x1d00,
+        [RT5639_ASRC_3] = 0x0008,
+        [RT5639_HP_OVCD] = 0x0600,
+        [RT5639_CLS_D_OVCD] = 0x0228,
+        [RT5639_CLS_D_OUT] = 0xa800,
+        [RT5639_DEPOP_M1] = 0x0004,
+        [RT5639_DEPOP_M2] = 0x1100,
+        [RT5639_DEPOP_M3] = 0x0646,
+        [RT5639_CHARGE_PUMP] = 0x0c00,
+        [RT5639_MICBIAS] = 0x3000,
+        [RT5639_EQ_CTRL1] = 0x2080,
+        [RT5639_DRC_AGC_1] = 0x2206,
+        [RT5639_DRC_AGC_2] = 0x1f00,
+        [RT5639_ANC_CTRL1] = 0x034b,
+        [RT5639_ANC_CTRL2] = 0x0066,
+        [RT5639_ANC_CTRL3] = 0x000b,
+        [RT5639_GPIO_CTRL1] = 0x0400,
+        [RT5639_DSP_CTRL3] = 0x2000,
+        [RT5639_BASE_BACK] = 0x0013,
+        [RT5639_MP3_PLUS1] = 0x0680,
+        [RT5639_MP3_PLUS2] = 0x1c17,
+        [RT5639_3D_HP] = 0x8c00,
+        [RT5639_ADJ_HPF] = 0x2a20,
+        [RT5639_HP_CALIB_AMP_DET] = 0x0400,
+        [RT5639_SV_ZCD1] = 0x0809,
+        [RT5639_VENDOR_ID1] = 0x10ec,
+        [RT5639_VENDOR_ID2] = 0x6231,
+};
+
+static int rt5639_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, RT5639_RESET, 0);
+}
+
+/**
+ * rt5639_index_write - Write private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ * @value: Private register Data.
+ *
+ * Modify private register for advanced setting. It can be written through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt5639_index_write(struct snd_soc_codec *codec,
+                unsigned int reg, unsigned int value)
+{
+        int ret;
+
+        ret = snd_soc_write(codec, RT5639_PRIV_INDEX, reg);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+                goto err;
+        }
+        ret = snd_soc_write(codec, RT5639_PRIV_DATA, value);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set private value: %d\n", ret);
+                goto err;
+        }
+        return 0;
+
+err:
+        return ret;
+}
+
+/**
+ * rt5639_index_read - Read private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ *
+ * Read advanced setting from private register. It can be read through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns private register value or negative error code.
+ */
+static unsigned int rt5639_index_read(
+        struct snd_soc_codec *codec, unsigned int reg)
+{
+        int ret;
+
+        ret = snd_soc_write(codec, RT5639_PRIV_INDEX, reg);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+                return ret;
+        }
+        return snd_soc_read(codec, RT5639_PRIV_DATA);
+}
+
+/**
+ * rt5639_index_update_bits - update private register bits
+ * @codec: audio codec
+ * @reg: Private register index.
+ * @mask: register mask
+ * @value: new value
+ *
+ * Writes new register value.
+ *
+ * Returns 1 for change, 0 for no change, or negative error code.
+ */
+static int rt5639_index_update_bits(struct snd_soc_codec *codec,
+        unsigned int reg, unsigned int mask, unsigned int value)
+{
+        unsigned int old, new;
+        int change, ret;
+
+        ret = rt5639_index_read(codec, reg);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
+                goto err;
+        }
+
+        old = ret;
+        new = (old & ~mask) | (value & mask);
+        change = old != new;
+        if (change) {
+                ret = rt5639_index_write(codec, reg, new);
+                if (ret < 0) {
+                        dev_err(codec->dev,
+                                "Failed to write private reg: %d\n", ret);
+                        goto err;
+                }
+        }
+        return change;
+
+err:
+        return ret;
+}
+
+static int rt5639_volatile_register(
+        struct snd_soc_codec *codec, unsigned int reg)
+{
+        switch (reg) {
+        case RT5639_RESET:
+        case RT5639_PRIV_DATA:
+        case RT5639_ASRC_5:
+        case RT5639_EQ_CTRL1:
+        case RT5639_DRC_AGC_1:
+        case RT5639_ANC_CTRL1:
+        case RT5639_IRQ_CTRL2:
+        case RT5639_INT_IRQ_ST:
+        case RT5639_DSP_CTRL2:
+        case RT5639_DSP_CTRL3:
+        case RT5639_PGM_REG_ARR1:
+        case RT5639_PGM_REG_ARR3:
+                return 1;
+        default:
+                return 0;
+        }
+}
+
+static int rt5639_readable_register(
+        struct snd_soc_codec *codec, unsigned int reg)
+{
+        switch (reg) {
+        case RT5639_RESET:
+        case RT5639_SPK_VOL:
+        case RT5639_HP_VOL:
+        case RT5639_OUTPUT:
+        case RT5639_MONO_OUT:
+        case RT5639_IN1_IN2:
+        case RT5639_IN3_IN4:
+        case RT5639_INL_INR_VOL:
+        case RT5639_DAC1_DIG_VOL:
+        case RT5639_DAC2_DIG_VOL:
+        case RT5639_DAC2_CTRL:
+        case RT5639_ADC_DIG_VOL:
+        case RT5639_ADC_DATA:
+        case RT5639_ADC_BST_VOL:
+        case RT5639_STO_ADC_MIXER:
+        case RT5639_MONO_ADC_MIXER:
+        case RT5639_AD_DA_MIXER:
+        case RT5639_STO_DAC_MIXER:
+        case RT5639_MONO_DAC_MIXER:
+        case RT5639_DIG_MIXER:
+        case RT5639_DSP_PATH1:
+        case RT5639_DSP_PATH2:
+        case RT5639_DIG_INF_DATA:
+        case RT5639_REC_L1_MIXER:
+        case RT5639_REC_L2_MIXER:
+        case RT5639_REC_R1_MIXER:
+        case RT5639_REC_R2_MIXER:
+        case RT5639_HPO_MIXER:
+        case RT5639_SPK_L_MIXER:
+        case RT5639_SPK_R_MIXER:
+        case RT5639_SPO_L_MIXER:
+        case RT5639_SPO_R_MIXER:
+        case RT5639_SPO_CLSD_RATIO:
+        case RT5639_MONO_MIXER:
+        case RT5639_OUT_L1_MIXER:
+        case RT5639_OUT_L2_MIXER:
+        case RT5639_OUT_L3_MIXER:
+        case RT5639_OUT_R1_MIXER:
+        case RT5639_OUT_R2_MIXER:
+        case RT5639_OUT_R3_MIXER:
+        case RT5639_LOUT_MIXER:
+        case RT5639_PWR_DIG1:
+        case RT5639_PWR_DIG2:
+        case RT5639_PWR_ANLG1:
+        case RT5639_PWR_ANLG2:
+        case RT5639_PWR_MIXER:
+        case RT5639_PWR_VOL:
+        case RT5639_PRIV_INDEX:
+        case RT5639_PRIV_DATA:
+        case RT5639_I2S1_SDP:
+        case RT5639_I2S2_SDP:
+        case RT5639_I2S3_SDP:
+        case RT5639_ADDA_CLK1:
+        case RT5639_ADDA_CLK2:
+        case RT5639_DMIC:
+        case RT5639_GLB_CLK:
+        case RT5639_PLL_CTRL1:
+        case RT5639_PLL_CTRL2:
+        case RT5639_ASRC_1:
+        case RT5639_ASRC_2:
+        case RT5639_ASRC_3:
+        case RT5639_ASRC_4:
+        case RT5639_ASRC_5:
+        case RT5639_HP_OVCD:
+        case RT5639_CLS_D_OVCD:
+        case RT5639_CLS_D_OUT:
+        case RT5639_DEPOP_M1:
+        case RT5639_DEPOP_M2:
+        case RT5639_DEPOP_M3:
+        case RT5639_CHARGE_PUMP:
+        case RT5639_PV_DET_SPK_G:
+        case RT5639_MICBIAS:
+        case RT5639_EQ_CTRL1:
+        case RT5639_EQ_CTRL2:
+        case RT5639_WIND_FILTER:
+        case RT5639_DRC_AGC_1:
+        case RT5639_DRC_AGC_2:
+        case RT5639_DRC_AGC_3:
+        case RT5639_SVOL_ZC:
+        case RT5639_ANC_CTRL1:
+        case RT5639_ANC_CTRL2:
+        case RT5639_ANC_CTRL3:
+        case RT5639_JD_CTRL:
+        case RT5639_ANC_JD:
+        case RT5639_IRQ_CTRL1:
+        case RT5639_IRQ_CTRL2:
+        case RT5639_INT_IRQ_ST:
+        case RT5639_GPIO_CTRL1:
+        case RT5639_GPIO_CTRL2:
+        case RT5639_GPIO_CTRL3:
+        case RT5639_DSP_CTRL1:
+        case RT5639_DSP_CTRL2:
+        case RT5639_DSP_CTRL3:
+        case RT5639_DSP_CTRL4:
+        case RT5639_PGM_REG_ARR1:
+        case RT5639_PGM_REG_ARR2:
+        case RT5639_PGM_REG_ARR3:
+        case RT5639_PGM_REG_ARR4:
+        case RT5639_PGM_REG_ARR5:
+        case RT5639_SCB_FUNC:
+        case RT5639_SCB_CTRL:
+        case RT5639_BASE_BACK:
+        case RT5639_MP3_PLUS1:
+        case RT5639_MP3_PLUS2:
+        case RT5639_3D_HP:
+        case RT5639_ADJ_HPF:
+        case RT5639_HP_CALIB_AMP_DET:
+        case RT5639_HP_CALIB2:
+        case RT5639_SV_ZCD1:
+        case RT5639_SV_ZCD2:
+        case RT5639_DUMMY1:
+        case RT5639_DUMMY2:
+        case RT5639_DUMMY3:
+        case RT5639_VENDOR_ID:
+        case RT5639_VENDOR_ID1:
+        case RT5639_VENDOR_ID2:
+                return 1;
+        default:
+                return 0;
+        }
+}
+
+int rt5639_headset_detect(struct snd_soc_codec *codec, int jack_insert)
+{
+        int jack_type;
+
+        if (jack_insert) {
+                snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
+                        RT5639_PWR_LDO2, RT5639_PWR_LDO2);
+                snd_soc_update_bits(codec, RT5639_PWR_ANLG2,
+                        RT5639_PWR_MB1, RT5639_PWR_MB1);
+                snd_soc_update_bits(codec, RT5639_MICBIAS,
+                        RT5639_MIC1_OVCD_MASK | RT5639_MIC1_OVTH_MASK |
+                        RT5639_PWR_CLK25M_MASK | RT5639_PWR_MB_MASK,
+                        RT5639_MIC1_OVCD_EN | RT5639_MIC1_OVTH_600UA |
+                        RT5639_PWR_MB_PU | RT5639_PWR_CLK25M_PU);
+                snd_soc_update_bits(codec, RT5639_DUMMY1,
+                        0x1, 0x1);
+                msleep(50);
+                if (snd_soc_read(codec, RT5639_IRQ_CTRL2) & 0x8)
+                        jack_type = RT5639_HEADPHO_DET;
+                else
+                        jack_type = RT5639_HEADSET_DET;
+                snd_soc_update_bits(codec, RT5639_IRQ_CTRL2,
+                        RT5639_MB1_OC_CLR, 0);
+        } else {
+                snd_soc_update_bits(codec, RT5639_MICBIAS,
+                        RT5639_MIC1_OVCD_MASK,
+                        RT5639_MIC1_OVCD_DIS);
+
+                jack_type = RT5639_NO_JACK;
+        }
+
+        return jack_type;
+}
+EXPORT_SYMBOL(rt5639_headset_detect);
+
+static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
+static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
+
+/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
+static unsigned int bst_tlv[] = {
+        TLV_DB_RANGE_HEAD(7),
+        0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+        1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
+        2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
+        3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
+        6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
+        7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
+        8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
+};
+
+static int rt5639_dmic_get(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = rt5639->dmic_en;
+
+        return 0;
+}
+
+static int rt5639_dmic_put(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+
+        if (rt5639->dmic_en == ucontrol->value.integer.value[0])
+                return 0;
+
+        rt5639->dmic_en = ucontrol->value.integer.value[0];
+        switch (rt5639->dmic_en) {
+        case RT5639_DMIC_DIS:
+                snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
+                        RT5639_GP2_PIN_MASK | RT5639_GP3_PIN_MASK |
+                        RT5639_GP4_PIN_MASK,
+                        RT5639_GP2_PIN_GPIO2 | RT5639_GP3_PIN_GPIO3 |
+                        RT5639_GP4_PIN_GPIO4);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_1_DP_MASK | RT5639_DMIC_2_DP_MASK,
+                        RT5639_DMIC_1_DP_GPIO3 | RT5639_DMIC_2_DP_GPIO4);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_1_EN_MASK | RT5639_DMIC_2_EN_MASK,
+                        RT5639_DMIC_1_DIS | RT5639_DMIC_2_DIS);
+                break;
+
+        case RT5639_DMIC1:
+                snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
+                        RT5639_GP2_PIN_MASK | RT5639_GP3_PIN_MASK,
+                        RT5639_GP2_PIN_DMIC1_SCL | RT5639_GP3_PIN_DMIC1_SDA);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_1L_LH_MASK | RT5639_DMIC_1R_LH_MASK |
+                        RT5639_DMIC_1_DP_MASK,
+                        RT5639_DMIC_1L_LH_FALLING | RT5639_DMIC_1R_LH_RISING |
+                        RT5639_DMIC_1_DP_IN1P);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_1_EN_MASK, RT5639_DMIC_1_EN);
+                break;
+
+        case RT5639_DMIC2:
+                snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
+                        RT5639_GP2_PIN_MASK | RT5639_GP4_PIN_MASK,
+                        RT5639_GP2_PIN_DMIC1_SCL | RT5639_GP4_PIN_DMIC2_SDA);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_2L_LH_MASK | RT5639_DMIC_2R_LH_MASK |
+                        RT5639_DMIC_2_DP_MASK,
+                        RT5639_DMIC_2L_LH_FALLING | RT5639_DMIC_2R_LH_RISING |
+                        RT5639_DMIC_2_DP_IN1N);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_2_EN_MASK, RT5639_DMIC_2_EN);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+
+/* IN1/IN2 Input Type */
+static const char *rt5639_input_mode[] = {
+        "Single ended", "Differential"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_in1_mode_enum, RT5639_IN1_IN2,
+        RT5639_IN_SFT1, rt5639_input_mode);
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_in2_mode_enum, RT5639_IN3_IN4,
+        RT5639_IN_SFT2, rt5639_input_mode);
+
+/* Interface data select */
+static const char *rt5639_data_select[] = {
+        "Normal", "left copy to right", "right copy to left", "Swap"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if1_dac_enum, RT5639_DIG_INF_DATA,
+                                RT5639_IF1_DAC_SEL_SFT, rt5639_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if1_adc_enum, RT5639_DIG_INF_DATA,
+                                RT5639_IF1_ADC_SEL_SFT, rt5639_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if2_dac_enum, RT5639_DIG_INF_DATA,
+                                RT5639_IF2_DAC_SEL_SFT, rt5639_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if2_adc_enum, RT5639_DIG_INF_DATA,
+                                RT5639_IF2_ADC_SEL_SFT, rt5639_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if3_dac_enum, RT5639_DIG_INF_DATA,
+                                RT5639_IF3_DAC_SEL_SFT, rt5639_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if3_adc_enum, RT5639_DIG_INF_DATA,
+                                RT5639_IF3_ADC_SEL_SFT, rt5639_data_select);
+
+/* Class D speaker gain ratio */
+static const char *rt5639_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
+        "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_clsd_spk_ratio_enum, RT5639_CLS_D_OUT,
+        RT5639_CLSD_RATIO_SFT, rt5639_clsd_spk_ratio);
+
+/* DMIC */
+static const char *rt5639_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_dmic_enum, 0, 0, rt5639_dmic_mode);
+
+
+
+#ifdef RT5639_REG_RW
+#define REGVAL_MAX 0xffff
+static unsigned int regctl_addr;
+static int rt5639_regctl_info(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+        uinfo->count = 2;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = REGVAL_MAX;
+        return 0;
+}
+
+static int rt5639_regctl_get(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        ucontrol->value.integer.value[0] = regctl_addr;
+        ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
+        return 0;
+}
+
+static int rt5639_regctl_put(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        regctl_addr = ucontrol->value.integer.value[0];
+        if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
+                snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
+        return 0;
+}
+#endif
+
+
+static int rt5639_vol_rescale_get(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int val = snd_soc_read(codec, mc->reg);
+
+        ucontrol->value.integer.value[0] = RT5639_VOL_RSCL_MAX -
+                ((val & RT5639_L_VOL_MASK) >> mc->shift);
+        ucontrol->value.integer.value[1] = RT5639_VOL_RSCL_MAX -
+                (val & RT5639_R_VOL_MASK);
+
+        return 0;
+}
+
+static int rt5639_vol_rescale_put(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int val, val2;
+
+        val = RT5639_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
+        val2 = RT5639_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
+        return snd_soc_update_bits_locked(codec, mc->reg, RT5639_L_VOL_MASK |
+                        RT5639_R_VOL_MASK, val << mc->shift | val2);
+}
+
+
+static const struct snd_kcontrol_new rt5639_snd_controls[] = {
+        /* Speaker Output Volume */
+        SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5639_SPK_VOL,
+                RT5639_L_VOL_SFT, RT5639_R_VOL_SFT, RT5639_VOL_RSCL_RANGE, 0,
+                rt5639_vol_rescale_get, rt5639_vol_rescale_put, out_vol_tlv),
+        /* Headphone Output Volume */
+        SOC_DOUBLE("HP Playback Switch", RT5639_HP_VOL,
+                RT5639_L_MUTE_SFT, RT5639_R_MUTE_SFT, 1, 1),
+        SOC_DOUBLE_EXT_TLV("HP Playback Volume", RT5639_HP_VOL,
+                RT5639_L_VOL_SFT, RT5639_R_VOL_SFT, RT5639_VOL_RSCL_RANGE, 0,
+                rt5639_vol_rescale_get, rt5639_vol_rescale_put, out_vol_tlv),
+        /* OUTPUT Control */
+        SOC_DOUBLE("OUT Playback Switch", RT5639_OUTPUT,
+                RT5639_L_MUTE_SFT, RT5639_R_MUTE_SFT, 1, 1),
+        SOC_DOUBLE("OUT Channel Switch", RT5639_OUTPUT,
+                RT5639_VOL_L_SFT, RT5639_VOL_R_SFT, 1, 1),
+        SOC_DOUBLE_TLV("OUT Playback Volume", RT5639_OUTPUT,
+                RT5639_L_VOL_SFT, RT5639_R_VOL_SFT, 39, 1, out_vol_tlv),
+        /* MONO Output Control */
+        SOC_SINGLE("Mono Playback Switch", RT5639_MONO_OUT,
+                                RT5639_L_MUTE_SFT, 1, 1),
+        /* DAC Digital Volume */
+        SOC_DOUBLE("DAC2 Playback Switch", RT5639_DAC2_CTRL,
+                RT5639_M_DAC_L2_VOL_SFT, RT5639_M_DAC_R2_VOL_SFT, 1, 1),
+        SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5639_DAC1_DIG_VOL,
+                        RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
+                        175, 0, dac_vol_tlv),
+        SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5639_DAC2_DIG_VOL,
+                        RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
+                        175, 0, dac_vol_tlv),
+        /* IN1/IN2 Control */
+        SOC_ENUM("IN1 Mode Control",  rt5639_in1_mode_enum),
+        SOC_SINGLE_TLV("IN1 Boost", RT5639_IN1_IN2,
+                RT5639_BST_SFT1, 8, 0, bst_tlv),
+        SOC_ENUM("IN2 Mode Control", rt5639_in2_mode_enum),
+        SOC_SINGLE_TLV("IN2 Boost", RT5639_IN3_IN4,
+                RT5639_BST_SFT2, 8, 0, bst_tlv),
+        /* INL/INR Volume Control */
+        SOC_DOUBLE_TLV("IN Capture Volume", RT5639_INL_INR_VOL,
+                        RT5639_INL_VOL_SFT, RT5639_INR_VOL_SFT,
+                        31, 1, in_vol_tlv),
+        /* ADC Digital Volume Control */
+        SOC_DOUBLE("ADC Capture Switch", RT5639_ADC_DIG_VOL,
+                RT5639_L_MUTE_SFT, RT5639_R_MUTE_SFT, 1, 1),
+        SOC_DOUBLE_TLV("ADC Capture Volume", RT5639_ADC_DIG_VOL,
+                        RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
+                        127, 0, adc_vol_tlv),
+        SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5639_ADC_DATA,
+                        RT5639_L_VOL_SFT, RT5639_R_VOL_SFT,
+                        127, 0, adc_vol_tlv),
+        /* ADC Boost Volume Control */
+        SOC_DOUBLE_TLV("ADC Boost Gain", RT5639_ADC_BST_VOL,
+                        RT5639_ADC_L_BST_SFT, RT5639_ADC_R_BST_SFT,
+                        3, 0, adc_bst_tlv),
+        /* Class D speaker gain ratio */
+        SOC_ENUM("Class D SPK Ratio Control", rt5639_clsd_spk_ratio_enum),
+        /* DMIC */
+        SOC_ENUM_EXT("DMIC Switch", rt5639_dmic_enum,
+                rt5639_dmic_get, rt5639_dmic_put),
+
+#ifdef RT5639_REG_RW
+        {
+                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+                .name = "Register Control",
+                .info = rt5639_regctl_info,
+                .get = rt5639_regctl_get,
+                .put = rt5639_regctl_put,
+        },
+#endif
+};
+
+/**
+ * set_dmic_clk - Set parameter of dmic.
+ *
+ * @w: DAPM widget.
+ * @kcontrol: The kcontrol of this widget.
+ * @event: Event id.
+ *
+ * Choose dmic clock between 1MHz and 3MHz.
+ * It is better for clock to approximate 3MHz.
+ */
+static int set_dmic_clk(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+        int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
+
+        rate = rt5639->lrck[rt5639->aif_pu] << 8;
+        red = 3000000 * 12;
+        for (i = 0; i < ARRAY_SIZE(div); i++) {
+                bound = div[i] * 3000000;
+                if (rate > bound)
+                        continue;
+                temp = bound - rate;
+                if (temp < red) {
+                        red = temp;
+                        idx = i;
+                }
+        }
+        if (idx < 0)
+                dev_err(codec->dev, "Failed to set DMIC clock\n");
+        else
+                snd_soc_update_bits(codec, RT5639_DMIC, RT5639_DMIC_CLK_MASK,
+                                        idx << RT5639_DMIC_CLK_SFT);
+        return idx;
+}
+
+static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
+                         struct snd_soc_dapm_widget *sink)
+{
+        unsigned int val;
+
+        val = snd_soc_read(source->codec, RT5639_GLB_CLK);
+        val &= RT5639_SCLK_SRC_MASK;
+        if (val == RT5639_SCLK_SRC_PLL1)
+                return 1;
+        else
+                return 0;
+}
+
+/* Digital Mixer */
+static const struct snd_kcontrol_new rt5639_sto_adc_l_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5639_STO_ADC_MIXER,
+                        RT5639_M_ADC_L1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5639_STO_ADC_MIXER,
+                        RT5639_M_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_sto_adc_r_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5639_STO_ADC_MIXER,
+                        RT5639_M_ADC_R1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5639_STO_ADC_MIXER,
+                        RT5639_M_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_mono_adc_l_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5639_MONO_ADC_MIXER,
+                        RT5639_M_MONO_ADC_L1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5639_MONO_ADC_MIXER,
+                        RT5639_M_MONO_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_mono_adc_r_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5639_MONO_ADC_MIXER,
+                        RT5639_M_MONO_ADC_R1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5639_MONO_ADC_MIXER,
+                        RT5639_M_MONO_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_dac_l_mix[] = {
+        SOC_DAPM_SINGLE("Stereo ADC Switch", RT5639_AD_DA_MIXER,
+                        RT5639_M_ADCMIX_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INF1 Switch", RT5639_AD_DA_MIXER,
+                        RT5639_M_IF1_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_dac_r_mix[] = {
+        SOC_DAPM_SINGLE("Stereo ADC Switch", RT5639_AD_DA_MIXER,
+                        RT5639_M_ADCMIX_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INF1 Switch", RT5639_AD_DA_MIXER,
+                        RT5639_M_IF1_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_sto_dac_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_STO_DAC_MIXER,
+                        RT5639_M_DAC_L1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_STO_DAC_MIXER,
+                        RT5639_M_DAC_L2_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ANC Switch", RT5639_STO_DAC_MIXER,
+                        RT5639_M_ANC_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_sto_dac_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_STO_DAC_MIXER,
+                        RT5639_M_DAC_R1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_STO_DAC_MIXER,
+                        RT5639_M_DAC_R2_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ANC Switch", RT5639_STO_DAC_MIXER,
+                        RT5639_M_ANC_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_mono_dac_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_MONO_DAC_MIXER,
+                        RT5639_M_DAC_L1_MONO_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_MONO_DAC_MIXER,
+                        RT5639_M_DAC_L2_MONO_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_MONO_DAC_MIXER,
+                        RT5639_M_DAC_R2_MONO_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_mono_dac_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_MONO_DAC_MIXER,
+                        RT5639_M_DAC_R1_MONO_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_MONO_DAC_MIXER,
+                        RT5639_M_DAC_R2_MONO_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_MONO_DAC_MIXER,
+                        RT5639_M_DAC_L2_MONO_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_dig_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_DIG_MIXER,
+                        RT5639_M_STO_L_DAC_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_DIG_MIXER,
+                        RT5639_M_DAC_L2_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_dig_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_DIG_MIXER,
+                        RT5639_M_STO_R_DAC_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_DIG_MIXER,
+                        RT5639_M_DAC_R2_DAC_R_SFT, 1, 1),
+};
+
+/* Analog Input Mixer */
+static const struct snd_kcontrol_new rt5639_rec_l_mix[] = {
+        SOC_DAPM_SINGLE("HPOL Switch", RT5639_REC_L2_MIXER,
+                        RT5639_M_HP_L_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INL Switch", RT5639_REC_L2_MIXER,
+                        RT5639_M_IN_L_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST2 Switch", RT5639_REC_L2_MIXER,
+                        RT5639_M_BST4_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5639_REC_L2_MIXER,
+                        RT5639_M_BST1_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXL Switch", RT5639_REC_L2_MIXER,
+                        RT5639_M_OM_L_RM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_rec_r_mix[] = {
+        SOC_DAPM_SINGLE("HPOR Switch", RT5639_REC_R2_MIXER,
+                        RT5639_M_HP_R_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INR Switch", RT5639_REC_R2_MIXER,
+                        RT5639_M_IN_R_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST2 Switch", RT5639_REC_R2_MIXER,
+                        RT5639_M_BST4_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5639_REC_R2_MIXER,
+                        RT5639_M_BST1_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXR Switch", RT5639_REC_R2_MIXER,
+                        RT5639_M_OM_R_RM_R_SFT, 1, 1),
+};
+
+/* Analog Output Mixer */
+static const struct snd_kcontrol_new rt5639_spk_l_mix[] = {
+        SOC_DAPM_SINGLE("REC MIXL Switch", RT5639_SPK_L_MIXER,
+                        RT5639_M_RM_L_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INL Switch", RT5639_SPK_L_MIXER,
+                        RT5639_M_IN_L_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_SPK_L_MIXER,
+                        RT5639_M_DAC_L1_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_SPK_L_MIXER,
+                        RT5639_M_DAC_L2_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXL Switch", RT5639_SPK_L_MIXER,
+                        RT5639_M_OM_L_SM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_spk_r_mix[] = {
+        SOC_DAPM_SINGLE("REC MIXR Switch", RT5639_SPK_R_MIXER,
+                        RT5639_M_RM_R_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INR Switch", RT5639_SPK_R_MIXER,
+                        RT5639_M_IN_R_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_SPK_R_MIXER,
+                        RT5639_M_DAC_R1_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_SPK_R_MIXER,
+                        RT5639_M_DAC_R2_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXR Switch", RT5639_SPK_R_MIXER,
+                        RT5639_M_OM_R_SM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_out_l_mix[] = {
+        SOC_DAPM_SINGLE("SPK MIXL Switch", RT5639_OUT_L3_MIXER,
+                        RT5639_M_SM_L_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5639_OUT_L3_MIXER,
+                        RT5639_M_BST1_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INL Switch", RT5639_OUT_L3_MIXER,
+                        RT5639_M_IN_L_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("REC MIXL Switch", RT5639_OUT_L3_MIXER,
+                        RT5639_M_RM_L_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_OUT_L3_MIXER,
+                        RT5639_M_DAC_R2_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_OUT_L3_MIXER,
+                        RT5639_M_DAC_L2_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_OUT_L3_MIXER,
+                        RT5639_M_DAC_L1_OM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_out_r_mix[] = {
+        SOC_DAPM_SINGLE("SPK MIXR Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_SM_L_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST2 Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_BST4_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_BST1_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INR Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_IN_R_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("REC MIXR Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_RM_R_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_DAC_L2_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_DAC_R2_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_OUT_R3_MIXER,
+                        RT5639_M_DAC_R1_OM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_spo_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_SPO_L_MIXER,
+                        RT5639_M_DAC_R1_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_SPO_L_MIXER,
+                        RT5639_M_DAC_L1_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("SPKVOL R Switch", RT5639_SPO_L_MIXER,
+                        RT5639_M_SV_R_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("SPKVOL L Switch", RT5639_SPO_L_MIXER,
+                        RT5639_M_SV_L_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5639_SPO_L_MIXER,
+                        RT5639_M_BST1_SPM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_spo_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_SPO_R_MIXER,
+                        RT5639_M_DAC_R1_SPM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("SPKVOL R Switch", RT5639_SPO_R_MIXER,
+                        RT5639_M_SV_R_SPM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5639_SPO_R_MIXER,
+                        RT5639_M_BST1_SPM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_hpo_mix[] = {
+        SOC_DAPM_SINGLE("DAC2 Switch", RT5639_HPO_MIXER,
+                        RT5639_M_DAC2_HM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC1 Switch", RT5639_HPO_MIXER,
+                        RT5639_M_DAC1_HM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("HPVOL Switch", RT5639_HPO_MIXER,
+                        RT5639_M_HPVOL_HM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_lout_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5639_LOUT_MIXER,
+                        RT5639_M_DAC_L1_LM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5639_LOUT_MIXER,
+                        RT5639_M_DAC_R1_LM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL L Switch", RT5639_LOUT_MIXER,
+                        RT5639_M_OV_L_LM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL R Switch", RT5639_LOUT_MIXER,
+                        RT5639_M_OV_R_LM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5639_mono_mix[] = {
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5639_MONO_MIXER,
+                        RT5639_M_DAC_R2_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5639_MONO_MIXER,
+                        RT5639_M_DAC_L2_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL R Switch", RT5639_MONO_MIXER,
+                        RT5639_M_OV_R_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL L Switch", RT5639_MONO_MIXER,
+                        RT5639_M_OV_L_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5639_MONO_MIXER,
+                        RT5639_M_BST1_MM_SFT, 1, 1),
+};
+
+/* INL/R source */
+static const char *rt5639_inl_src[] = {"IN2P", "MonoP"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_inl_enum, RT5639_INL_INR_VOL,
+        RT5639_INL_SEL_SFT, rt5639_inl_src);
+
+static const struct snd_kcontrol_new rt5639_inl_mux =
+        SOC_DAPM_ENUM("INL source", rt5639_inl_enum);
+
+static const char *rt5639_inr_src[] = {"IN2N", "MonoN"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_inr_enum, RT5639_INL_INR_VOL,
+        RT5639_INR_SEL_SFT, rt5639_inr_src);
+
+static const struct snd_kcontrol_new rt5639_inr_mux =
+        SOC_DAPM_ENUM("INR source", rt5639_inr_enum);
+
+/* Stereo ADC source */
+static const char *rt5639_stereo_adc1_src[] = {"DIG MIX", "ADC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_stereo_adc1_enum, RT5639_STO_ADC_MIXER,
+        RT5639_ADC_1_SRC_SFT, rt5639_stereo_adc1_src);
+
+static const struct snd_kcontrol_new rt5639_sto_adc_l1_mux =
+        SOC_DAPM_ENUM("Stereo ADC L1 source", rt5639_stereo_adc1_enum);
+
+static const struct snd_kcontrol_new rt5639_sto_adc_r1_mux =
+        SOC_DAPM_ENUM("Stereo ADC R1 source", rt5639_stereo_adc1_enum);
+
+static const char *rt5639_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_stereo_adc2_enum, RT5639_STO_ADC_MIXER,
+        RT5639_ADC_2_SRC_SFT, rt5639_stereo_adc2_src);
+
+static const struct snd_kcontrol_new rt5639_sto_adc_l2_mux =
+        SOC_DAPM_ENUM("Stereo ADC L2 source", rt5639_stereo_adc2_enum);
+
+static const struct snd_kcontrol_new rt5639_sto_adc_r2_mux =
+        SOC_DAPM_ENUM("Stereo ADC R2 source", rt5639_stereo_adc2_enum);
+
+/* Mono ADC source */
+static const char *rt5639_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_mono_adc_l1_enum, RT5639_MONO_ADC_MIXER,
+        RT5639_MONO_ADC_L1_SRC_SFT, rt5639_mono_adc_l1_src);
+
+static const struct snd_kcontrol_new rt5639_mono_adc_l1_mux =
+        SOC_DAPM_ENUM("Mono ADC1 left source", rt5639_mono_adc_l1_enum);
+
+static const char *rt5639_mono_adc_l2_src[] =
+        {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_mono_adc_l2_enum, RT5639_MONO_ADC_MIXER,
+        RT5639_MONO_ADC_L2_SRC_SFT, rt5639_mono_adc_l2_src);
+
+static const struct snd_kcontrol_new rt5639_mono_adc_l2_mux =
+        SOC_DAPM_ENUM("Mono ADC2 left source", rt5639_mono_adc_l2_enum);
+
+static const char *rt5639_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_mono_adc_r1_enum, RT5639_MONO_ADC_MIXER,
+        RT5639_MONO_ADC_R1_SRC_SFT, rt5639_mono_adc_r1_src);
+
+static const struct snd_kcontrol_new rt5639_mono_adc_r1_mux =
+        SOC_DAPM_ENUM("Mono ADC1 right source", rt5639_mono_adc_r1_enum);
+
+static const char *rt5639_mono_adc_r2_src[] =
+        {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_mono_adc_r2_enum, RT5639_MONO_ADC_MIXER,
+        RT5639_MONO_ADC_R2_SRC_SFT, rt5639_mono_adc_r2_src);
+
+static const struct snd_kcontrol_new rt5639_mono_adc_r2_mux =
+        SOC_DAPM_ENUM("Mono ADC2 right source", rt5639_mono_adc_r2_enum);
+
+/* DAC2 channel source */
+static const char *rt5639_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_dac_l2_enum, RT5639_DSP_PATH2,
+                                RT5639_DAC_L2_SEL_SFT, rt5639_dac_l2_src);
+
+static const struct snd_kcontrol_new rt5639_dac_l2_mux =
+        SOC_DAPM_ENUM("DAC2 left channel source", rt5639_dac_l2_enum);
+
+static const char *rt5639_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_dac_r2_enum, RT5639_DSP_PATH2,
+        RT5639_DAC_R2_SEL_SFT, rt5639_dac_r2_src);
+
+static const struct snd_kcontrol_new rt5639_dac_r2_mux =
+        SOC_DAPM_ENUM("DAC2 right channel source", rt5639_dac_r2_enum);
+
+/* Interface 2  ADC channel source */
+static const char *rt5639_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if2_adc_l_enum, RT5639_DSP_PATH2,
+                        RT5639_IF2_ADC_L_SEL_SFT, rt5639_if2_adc_l_src);
+
+static const struct snd_kcontrol_new rt5639_if2_adc_l_mux =
+        SOC_DAPM_ENUM("IF2 ADC left channel source", rt5639_if2_adc_l_enum);
+
+static const char *rt5639_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5639_if2_adc_r_enum, RT5639_DSP_PATH2,
+                        RT5639_IF2_ADC_R_SEL_SFT, rt5639_if2_adc_r_src);
+
+static const struct snd_kcontrol_new rt5639_if2_adc_r_mux =
+        SOC_DAPM_ENUM("IF2 ADC right channel source", rt5639_if2_adc_r_enum);
+
+/* digital interface and iis interface map */
+static const char *rt5639_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
+        "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
+        "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_dai_iis_map_enum, RT5639_I2S1_SDP,
+        RT5639_I2S_IF_SFT, rt5639_dai_iis_map);
+
+static const struct snd_kcontrol_new rt5639_dai_mux =
+        SOC_DAPM_ENUM("DAI select", rt5639_dai_iis_map_enum);
+
+/* SDI select */
+static const char *rt5639_sdi_sel[] = {"IF1", "IF2"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5639_sdi_sel_enum, RT5639_I2S2_SDP,
+        RT5639_I2S2_SDI_SFT, rt5639_sdi_sel);
+
+static const struct snd_kcontrol_new rt5639_sdi_mux =
+        SOC_DAPM_ENUM("SDI select", rt5639_sdi_sel_enum);
+
+static int spk_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                printk("spk_event --SND_SOC_DAPM_POST_PMU\n");
+                snd_soc_update_bits(codec, RT5639_PWR_DIG1,
+                        RT5639_PWR_CLS_D, RT5639_PWR_CLS_D);
+                rt5639_index_update_bits(codec, 0x1c, 0xf000, 0xf000);
+                //rt5639_index_write(codec,0x1c,0xfd21);
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                printk("spk_event --SND_SOC_DAPM_POST_PMD\n");
+                //rt5639_index_write(codec,0x1c,0xfd00);
+                rt5639_index_update_bits(codec, 0x1c, 0xf000, 0x0000);
+                snd_soc_update_bits(codec,RT5639_PWR_DIG1,
+                        RT5639_PWR_CLS_D, 0);
+                break;
+
+        default:
+                return 0;
+        }
+
+        return 0;
+}
+
+static int hp_event(struct snd_soc_dapm_widget *w, 
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                printk("hp_event --SND_SOC_DAPM_POST_PMU\n");
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                printk("hp_event --SND_SOC_DAPM_POST_PMD\n");
+                break;
+
+        default:
+                return 0;
+        }
+
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget rt5639_dapm_widgets[] = {
+        SND_SOC_DAPM_SUPPLY("PLL1", RT5639_PWR_ANLG2,
+                        RT5639_PWR_PLL_BIT, 0, NULL, 0),
+        /* Input Side */
+        /* micbias */
+        SND_SOC_DAPM_SUPPLY("LDO2", RT5639_PWR_ANLG1,
+                        RT5639_PWR_LDO2_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MICBIAS("micbias1", RT5639_PWR_ANLG2,
+                        RT5639_PWR_MB1_BIT, 0),
+        SND_SOC_DAPM_MICBIAS("micbias2", RT5639_PWR_ANLG2,
+                        RT5639_PWR_MB2_BIT, 0),
+        /* Input Lines */
+
+        SND_SOC_DAPM_INPUT("MIC1"),
+        SND_SOC_DAPM_INPUT("MIC2"),
+        SND_SOC_DAPM_INPUT("DMIC1"),
+        SND_SOC_DAPM_INPUT("DMIC2"),    
+
+        SND_SOC_DAPM_INPUT("IN1P"),
+        SND_SOC_DAPM_INPUT("IN1N"),
+        SND_SOC_DAPM_INPUT("IN2P"),
+        SND_SOC_DAPM_INPUT("IN2N"),
+        SND_SOC_DAPM_INPUT("DMIC L1"),
+        SND_SOC_DAPM_INPUT("DMIC R1"),
+        SND_SOC_DAPM_INPUT("DMIC L2"),
+        SND_SOC_DAPM_INPUT("DMIC R2"),
+        SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
+                set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
+        /* Boost */
+        SND_SOC_DAPM_PGA("BST1", RT5639_PWR_ANLG2,
+                RT5639_PWR_BST1_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("BST2", RT5639_PWR_ANLG2,
+                RT5639_PWR_BST4_BIT, 0, NULL, 0),
+        /* Input Volume */
+        SND_SOC_DAPM_PGA("INL VOL", RT5639_PWR_VOL,
+                RT5639_PWR_IN_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("INR VOL", RT5639_PWR_VOL,
+                RT5639_PWR_IN_R_BIT, 0, NULL, 0),
+        /* IN Mux */
+        SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt5639_inl_mux),
+        SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt5639_inr_mux),
+        /* REC Mixer */
+        SND_SOC_DAPM_MIXER("RECMIXL", RT5639_PWR_MIXER, RT5639_PWR_RM_L_BIT, 0,
+                        rt5639_rec_l_mix, ARRAY_SIZE(rt5639_rec_l_mix)),
+        SND_SOC_DAPM_MIXER("RECMIXR", RT5639_PWR_MIXER, RT5639_PWR_RM_R_BIT, 0,
+                        rt5639_rec_r_mix, ARRAY_SIZE(rt5639_rec_r_mix)),
+        /* ADCs */
+        SND_SOC_DAPM_ADC("ADC L", NULL, RT5639_PWR_DIG1,
+                        RT5639_PWR_ADC_L_BIT, 0),
+        SND_SOC_DAPM_ADC("ADC R", NULL, RT5639_PWR_DIG1,
+                        RT5639_PWR_ADC_R_BIT, 0),
+        /* ADC Mux */
+        SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_sto_adc_l2_mux),
+        SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_sto_adc_r2_mux),
+        SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_sto_adc_l1_mux),
+        SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_sto_adc_r1_mux),
+        SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_mono_adc_l2_mux),
+        SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_mono_adc_l1_mux),
+        SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_mono_adc_r1_mux),
+        SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_mono_adc_r2_mux),
+        /* ADC Mixer */
+        SND_SOC_DAPM_SUPPLY("stereo filter", RT5639_PWR_DIG2,
+                RT5639_PWR_ADC_SF_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5639_sto_adc_l_mix, ARRAY_SIZE(rt5639_sto_adc_l_mix)),
+        SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5639_sto_adc_r_mix, ARRAY_SIZE(rt5639_sto_adc_r_mix)),
+        SND_SOC_DAPM_SUPPLY("mono left filter", RT5639_PWR_DIG2,
+                RT5639_PWR_ADC_MF_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5639_mono_adc_l_mix, ARRAY_SIZE(rt5639_mono_adc_l_mix)),
+        SND_SOC_DAPM_SUPPLY("mono right filter", RT5639_PWR_DIG2,
+                RT5639_PWR_ADC_MF_R_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5639_mono_adc_r_mix, ARRAY_SIZE(rt5639_mono_adc_r_mix)),
+
+        /* IF2 Mux */
+        SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_if2_adc_l_mux),
+        SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_if2_adc_r_mux),
+
+        /* Digital Interface */
+        SND_SOC_DAPM_SUPPLY("I2S1", RT5639_PWR_DIG1,
+                RT5639_PWR_I2S1_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("I2S2", RT5639_PWR_DIG1,
+                RT5639_PWR_I2S2_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("I2S3", RT5639_PWR_DIG1,
+                RT5639_PWR_I2S3_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        /* Digital Interface Select */
+        SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_sdi_mux),
+
+        SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_sdi_mux),
+
+        SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+        SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt5639_dai_mux),
+
+        /* Audio Interface */
+        SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
+
+        /* Audio DSP */
+        SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        /* ANC */
+        SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        /* Output Side */
+        /* DAC mixer before sound effect  */
+        SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5639_dac_l_mix, ARRAY_SIZE(rt5639_dac_l_mix)),
+        SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5639_dac_r_mix, ARRAY_SIZE(rt5639_dac_r_mix)),
+
+        /* DAC2 channel Mux */
+        SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_dac_l2_mux),
+        SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5639_dac_r2_mux),
+
+        /* DAC Mixer */
+        SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5639_sto_dac_l_mix, ARRAY_SIZE(rt5639_sto_dac_l_mix)),
+        SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5639_sto_dac_r_mix, ARRAY_SIZE(rt5639_sto_dac_r_mix)),
+        SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5639_mono_dac_l_mix, ARRAY_SIZE(rt5639_mono_dac_l_mix)),
+        SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5639_mono_dac_r_mix, ARRAY_SIZE(rt5639_mono_dac_r_mix)),
+        SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
+                rt5639_dig_l_mix, ARRAY_SIZE(rt5639_dig_l_mix)),
+        SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
+                rt5639_dig_r_mix, ARRAY_SIZE(rt5639_dig_r_mix)),
+        /* DACs */
+        SND_SOC_DAPM_DAC("DAC L1", NULL, RT5639_PWR_DIG1,
+                        RT5639_PWR_DAC_L1_BIT, 0),
+        SND_SOC_DAPM_DAC("DAC L2", NULL, RT5639_PWR_DIG1,
+                        RT5639_PWR_DAC_L2_BIT, 0),
+        SND_SOC_DAPM_DAC("DAC R1", NULL, RT5639_PWR_DIG1,
+                        RT5639_PWR_DAC_R1_BIT, 0),
+        SND_SOC_DAPM_DAC("DAC R2", NULL, RT5639_PWR_DIG1,
+                        RT5639_PWR_DAC_R2_BIT, 0),
+        /* SPK/OUT Mixer */
+        SND_SOC_DAPM_MIXER("SPK MIXL", RT5639_PWR_MIXER, RT5639_PWR_SM_L_BIT,
+                0, rt5639_spk_l_mix, ARRAY_SIZE(rt5639_spk_l_mix)),
+        SND_SOC_DAPM_MIXER("SPK MIXR", RT5639_PWR_MIXER, RT5639_PWR_SM_R_BIT,
+                0, rt5639_spk_r_mix, ARRAY_SIZE(rt5639_spk_r_mix)),
+        SND_SOC_DAPM_MIXER("OUT MIXL", RT5639_PWR_MIXER, RT5639_PWR_OM_L_BIT,
+                0, rt5639_out_l_mix, ARRAY_SIZE(rt5639_out_l_mix)),
+        SND_SOC_DAPM_MIXER("OUT MIXR", RT5639_PWR_MIXER, RT5639_PWR_OM_R_BIT,
+                0, rt5639_out_r_mix, ARRAY_SIZE(rt5639_out_r_mix)),
+        /* Ouput Volume */
+        SND_SOC_DAPM_PGA("SPKVOL L", RT5639_PWR_VOL,
+                RT5639_PWR_SV_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("SPKVOL R", RT5639_PWR_VOL,
+                RT5639_PWR_SV_R_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("OUTVOL L", RT5639_PWR_VOL,
+                RT5639_PWR_OV_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("OUTVOL R", RT5639_PWR_VOL,
+                RT5639_PWR_OV_R_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("HPOVOL L", RT5639_PWR_VOL,
+                RT5639_PWR_HV_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("HPOVOL R", RT5639_PWR_VOL,
+                RT5639_PWR_HV_R_BIT, 0, NULL, 0),
+        /* SPO/HPO/LOUT/Mono Mixer */
+        SND_SOC_DAPM_MIXER("SPOL MIX",SND_SOC_NOPM, 0,
+                0, rt5639_spo_l_mix, ARRAY_SIZE(rt5639_spo_l_mix)),
+        SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
+                0, rt5639_spo_r_mix, ARRAY_SIZE(rt5639_spo_r_mix)),
+        SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
+                rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
+        SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
+                rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
+        SND_SOC_DAPM_MIXER("LOUT MIX", RT5639_PWR_ANLG1, RT5639_PWR_LM_BIT, 0,
+                rt5639_lout_mix, ARRAY_SIZE(rt5639_lout_mix)),
+        SND_SOC_DAPM_MIXER("Mono MIX", RT5639_PWR_ANLG1, RT5639_PWR_MM_BIT, 0,
+                rt5639_mono_mix, ARRAY_SIZE(rt5639_mono_mix)),
+
+        SND_SOC_DAPM_SUPPLY("Improve mono amp drv", RT5639_PWR_ANLG1,
+                RT5639_PWR_MA_BIT, 0, NULL, 0),
+
+        SND_SOC_DAPM_SUPPLY("Improve HP amp drv", RT5639_PWR_ANLG1,
+                SND_SOC_NOPM, 0, hp_event,SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+
+        SND_SOC_DAPM_PGA("HP L amp", RT5639_PWR_ANLG1,
+                RT5639_PWR_HP_L_BIT, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("HP R amp", RT5639_PWR_ANLG1,
+                RT5639_PWR_HP_R_BIT, 0, NULL, 0),
+
+        SND_SOC_DAPM_SUPPLY("Improve SPK amp drv", SND_SOC_NOPM, 0, 0,
+                spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),               
+
+        /* Output Lines */
+        SND_SOC_DAPM_OUTPUT("SPOLP"),
+        SND_SOC_DAPM_OUTPUT("SPOLN"),
+        SND_SOC_DAPM_OUTPUT("SPORP"),
+        SND_SOC_DAPM_OUTPUT("SPORN"),
+        SND_SOC_DAPM_OUTPUT("HPOL"),
+        SND_SOC_DAPM_OUTPUT("HPOR"),
+        SND_SOC_DAPM_OUTPUT("LOUTL"),
+        SND_SOC_DAPM_OUTPUT("LOUTR"),
+};
+
+static const struct snd_soc_dapm_route rt5639_dapm_routes[] = {
+        {"IN1P", NULL, "LDO2"},
+        {"IN2P", NULL, "LDO2"},
+
+        {"IN1P", NULL, "MIC1"},
+        {"IN1N", NULL, "MIC1"},
+        {"IN2P", NULL, "MIC2"},
+        {"IN2N", NULL, "MIC2"},
+
+        {"DMIC L1", NULL, "DMIC1"},
+        {"DMIC R1", NULL, "DMIC1"},
+        {"DMIC L2", NULL, "DMIC2"},
+        {"DMIC R2", NULL, "DMIC2"},
+
+        {"BST1", NULL, "IN1P"},
+        {"BST1", NULL, "IN1N"},
+        {"BST2", NULL, "IN2P"},
+        {"BST2", NULL, "IN2N"},
+
+        {"INL VOL", NULL, "IN2P"},
+        {"INR VOL", NULL, "IN2N"},      
+        
+        {"RECMIXL", "HPOL Switch", "HPOL"},
+        {"RECMIXL", "INL Switch", "INL VOL"},
+        {"RECMIXL", "BST2 Switch", "BST2"},
+        {"RECMIXL", "BST1 Switch", "BST1"},
+        {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
+
+        {"RECMIXR", "HPOR Switch", "HPOR"},
+        {"RECMIXR", "INR Switch", "INR VOL"},
+        {"RECMIXR", "BST2 Switch", "BST2"},
+        {"RECMIXR", "BST1 Switch", "BST1"},
+        {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+        {"ADC L", NULL, "RECMIXL"},
+        {"ADC R", NULL, "RECMIXR"},
+
+        {"DMIC L1", NULL, "DMIC CLK"},
+        {"DMIC L2", NULL, "DMIC CLK"},
+
+        {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
+        {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
+        {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
+        {"Stereo ADC L1 Mux", "ADC", "ADC L"},
+        {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
+
+        {"Stereo ADC R1 Mux", "ADC", "ADC R"},
+        {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
+        {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
+        {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
+        {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
+
+        {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
+        {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
+        {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+        {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+        {"Mono ADC L1 Mux", "ADCL", "ADC L"},
+
+        {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+        {"Mono ADC R1 Mux", "ADCR", "ADC R"},
+        {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
+        {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
+        {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+
+        {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
+        {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
+        {"Stereo ADC MIXL", NULL, "stereo filter"},
+        {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
+        {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
+        {"Stereo ADC MIXR", NULL, "stereo filter"},
+        {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
+        {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
+        {"Mono ADC MIXL", NULL, "mono left filter"},
+        {"mono left filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
+        {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
+        {"Mono ADC MIXR", NULL, "mono right filter"},
+        {"mono right filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
+        {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
+
+        {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
+        {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
+        {"IF3 ADC L", NULL, "Mono ADC MIXL"},
+        {"IF3 ADC R", NULL, "Mono ADC MIXR"},
+        {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
+        {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
+
+        {"IF1 ADC", NULL, "I2S1"},
+        {"IF1 ADC", NULL, "IF1 ADC L"},
+        {"IF1 ADC", NULL, "IF1 ADC R"},
+        {"IF2 ADC", NULL, "I2S2"},
+        {"IF2 ADC", NULL, "IF2 ADC L"},
+        {"IF2 ADC", NULL, "IF2 ADC R"},
+        {"IF3 ADC", NULL, "I2S3"},
+        {"IF3 ADC", NULL, "IF3 ADC L"},
+        {"IF3 ADC", NULL, "IF3 ADC R"},
+
+        {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
+        {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
+        {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
+        {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
+        {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
+        {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
+        {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
+        {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
+        {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
+        {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
+
+        {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
+        {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
+        {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
+        {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
+        {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
+        {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
+        {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
+        {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
+        {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
+        {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
+
+        {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
+        {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
+        {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
+        {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
+        {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
+        {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
+        {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
+        {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
+
+        {"AIF1TX", NULL, "DAI1 TX Mux"},
+        {"AIF1TX", NULL, "SDI1 TX Mux"},
+        {"AIF2TX", NULL, "DAI2 TX Mux"},
+        {"AIF2TX", NULL, "SDI2 TX Mux"},
+        {"AIF3TX", NULL, "DAI3 TX Mux"},
+
+        {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
+        {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
+        {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+        {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
+        {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
+        {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+        {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
+        {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
+
+        {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
+        {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
+        {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+        {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
+        {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
+        {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+        {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
+        {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
+
+        {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
+        {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
+        {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
+        {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
+        {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
+        {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
+        {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
+        {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
+
+        {"IF1 DAC", NULL, "I2S1"},
+        {"IF1 DAC", NULL, "DAI1 RX Mux"},
+        {"IF2 DAC", NULL, "I2S2"},
+        {"IF2 DAC", NULL, "DAI2 RX Mux"},
+        {"IF3 DAC", NULL, "I2S3"},
+        {"IF3 DAC", NULL, "DAI3 RX Mux"},
+
+        {"IF1 DAC L", NULL, "IF1 DAC"},
+        {"IF1 DAC R", NULL, "IF1 DAC"},
+        {"IF2 DAC L", NULL, "IF2 DAC"},
+        {"IF2 DAC R", NULL, "IF2 DAC"},
+        {"IF3 DAC L", NULL, "IF3 DAC"},
+        {"IF3 DAC R", NULL, "IF3 DAC"},
+
+        {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
+        {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
+        {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
+        {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
+
+        {"ANC", NULL, "Stereo ADC MIXL"},
+        {"ANC", NULL, "Stereo ADC MIXR"},
+
+        {"Audio DSP", NULL, "DAC MIXL"},
+        {"Audio DSP", NULL, "DAC MIXR"},
+
+        {"DAC L2 Mux", "IF2", "IF2 DAC L"},
+        {"DAC L2 Mux", "IF3", "IF3 DAC L"},
+        {"DAC L2 Mux", "Base L/R", "Audio DSP"},
+
+        {"DAC R2 Mux", "IF2", "IF2 DAC R"},
+        {"DAC R2 Mux", "IF3", "IF3 DAC R"},
+
+        {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+        {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+        {"Stereo DAC MIXL", "ANC Switch", "ANC"},
+        {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+        {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+        {"Stereo DAC MIXR", "ANC Switch", "ANC"},
+
+        {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+        {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+        {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
+        {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+        {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+        {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
+
+        {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
+        {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+        {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
+        {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+
+        {"DAC L1", NULL, "Stereo DAC MIXL"},
+        {"DAC L1", NULL, "PLL1", check_sysclk1_source},
+        {"DAC R1", NULL, "Stereo DAC MIXR"},
+        {"DAC R1", NULL, "PLL1", check_sysclk1_source},
+
+        {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
+        {"SPK MIXL", "INL Switch", "INL VOL"},
+        {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
+        {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
+        {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
+        {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
+        {"SPK MIXR", "INR Switch", "INR VOL"},
+        {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
+        {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
+        {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+        {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
+        {"OUT MIXL", "BST1 Switch", "BST1"},
+        {"OUT MIXL", "INL Switch", "INL VOL"},
+        {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
+        {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
+        {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
+        {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
+
+        {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
+        {"OUT MIXR", "BST2 Switch", "BST2"},
+        {"OUT MIXR", "BST1 Switch", "BST1"},
+        {"OUT MIXR", "INR Switch", "INR VOL"},
+        {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
+        {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
+        {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
+        {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
+
+        {"SPKVOL L", NULL, "SPK MIXL"},
+        {"SPKVOL R", NULL, "SPK MIXR"},
+        {"HPOVOL L", NULL, "OUT MIXL"},
+        {"HPOVOL R", NULL, "OUT MIXR"},
+        {"OUTVOL L", NULL, "OUT MIXL"},
+        {"OUTVOL R", NULL, "OUT MIXR"},
+
+        {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
+        {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
+        {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
+        {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
+        {"SPOL MIX", "BST1 Switch", "BST1"},
+        {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
+        {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
+        {"SPOR MIX", "BST1 Switch", "BST1"},
+
+        {"HPOL MIX", "DAC2 Switch", "DAC L2"},
+        {"HPOL MIX", "DAC1 Switch", "DAC L1"},
+        {"HPOL MIX", "HPVOL Switch", "HPOVOL L"},
+        {"HPOR MIX", "DAC2 Switch", "DAC R2"},
+        {"HPOR MIX", "DAC1 Switch", "DAC R1"},
+        {"HPOR MIX", "HPVOL Switch", "HPOVOL R"},
+
+        {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
+        {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
+        {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
+        {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
+
+        {"Mono MIX", "DAC R2 Switch", "DAC R2"},
+        {"Mono MIX", "DAC L2 Switch", "DAC L2"},
+        {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
+        {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
+        {"Mono MIX", "BST1 Switch", "BST1"},
+
+        {"SPOLP", NULL, "Improve SPK amp drv"},
+        {"SPOLN", NULL, "Improve SPK amp drv"},
+        {"SPORP", NULL, "Improve SPK amp drv"},
+        {"SPORN", NULL, "Improve SPK amp drv"},
+        {"SPOLP", NULL, "SPOL MIX"},
+        {"SPOLN", NULL, "SPOL MIX"},
+        {"SPORP", NULL, "SPOR MIX"},
+        {"SPORN", NULL, "SPOR MIX"},
+        
+        {"HP L amp", NULL, "HPOL MIX"},
+        {"HP R amp", NULL, "HPOR MIX"},
+        {"HPOL", NULL, "Improve HP amp drv"},
+        {"HPOR", NULL, "Improve HP amp drv"},
+        {"HPOL", NULL, "HP L amp"},
+        {"HPOR", NULL, "HP R amp"},
+
+        {"LOUTL", NULL, "LOUT MIX"},
+        {"LOUTR", NULL, "LOUT MIX"},
+};
+
+static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
+{
+        int ret = 0, val = snd_soc_read(codec, RT5639_I2S1_SDP);
+
+        if(codec == NULL)
+                return -EINVAL;
+
+        val = (val & RT5639_I2S_IF_MASK) >> RT5639_I2S_IF_SFT;
+        switch (dai_id) {
+        case RT5639_AIF1:
+                if (val == RT5639_IF_123 || val == RT5639_IF_132 ||
+                        val == RT5639_IF_113)
+                        ret |= RT5639_U_IF1;
+                if (val == RT5639_IF_312 || val == RT5639_IF_213 ||
+                        val == RT5639_IF_113)
+                        ret |= RT5639_U_IF2;
+                if (val == RT5639_IF_321 || val == RT5639_IF_231)
+                        ret |= RT5639_U_IF3;
+                break;
+
+        case RT5639_AIF2:
+                if (val == RT5639_IF_231 || val == RT5639_IF_213 ||
+                        val == RT5639_IF_223)
+                        ret |= RT5639_U_IF1;
+                if (val == RT5639_IF_123 || val == RT5639_IF_321 ||
+                        val == RT5639_IF_223)
+                        ret |= RT5639_U_IF2;
+                if (val == RT5639_IF_132 || val == RT5639_IF_312)
+                        ret |= RT5639_U_IF3;
+                break;
+
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
+static int get_clk_info(int sclk, int rate)
+{
+        int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
+
+        if(sclk <= 0 || rate <= 0)
+                return -EINVAL;
+
+        rate = rate << 8;
+        for (i = 0; i < ARRAY_SIZE(pd); i++)
+                if (sclk == rate * pd[i])
+                        return i;
+
+        return -EINVAL;
+}
+
+static int rt5639_hw_params(struct snd_pcm_substream *substream,
+        struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+        unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
+        int pre_div, bclk_ms, frame_size;
+
+        rt5639->lrck[dai->id] = params_rate(params);
+        pre_div = get_clk_info(rt5639->sysclk, rt5639->lrck[dai->id]);
+        if (pre_div < 0) {
+                dev_err(codec->dev, "Unsupported clock setting\n");
+                return -EINVAL;
+        }
+        frame_size = snd_soc_params_to_frame_size(params);
+        if (frame_size < 0) {
+                dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
+                return -EINVAL;
+        }
+        bclk_ms = frame_size > 32 ? 1 : 0;
+        rt5639->bclk[dai->id] = rt5639->lrck[dai->id] * (32 << bclk_ms);
+
+        dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
+                rt5639->bclk[dai->id], rt5639->lrck[dai->id]);
+        dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
+                                bclk_ms, pre_div, dai->id);
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                val_len |= RT5639_I2S_DL_20;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                val_len |= RT5639_I2S_DL_24;
+                break;
+        case SNDRV_PCM_FORMAT_S8:
+                val_len |= RT5639_I2S_DL_8;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        dai_sel = get_sdp_info(codec, dai->id);
+        if (dai_sel < 0) {
+                dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+                return -EINVAL;
+        }
+        if (dai_sel & RT5639_U_IF1) {
+                mask_clk = RT5639_I2S_BCLK_MS1_MASK | RT5639_I2S_PD1_MASK;
+                val_clk = bclk_ms << RT5639_I2S_BCLK_MS1_SFT |
+                        pre_div << RT5639_I2S_PD1_SFT;
+                snd_soc_update_bits(codec, RT5639_I2S1_SDP,
+                        RT5639_I2S_DL_MASK, val_len);
+                snd_soc_update_bits(codec, RT5639_ADDA_CLK1, mask_clk, val_clk);
+        }
+        if (dai_sel & RT5639_U_IF2) {
+                mask_clk = RT5639_I2S_BCLK_MS2_MASK | RT5639_I2S_PD2_MASK;
+                val_clk = bclk_ms << RT5639_I2S_BCLK_MS2_SFT |
+                        pre_div << RT5639_I2S_PD2_SFT;
+                snd_soc_update_bits(codec, RT5639_I2S2_SDP,
+                        RT5639_I2S_DL_MASK, val_len);
+                snd_soc_update_bits(codec, RT5639_ADDA_CLK1, mask_clk, val_clk);
+        }
+
+        return 0;
+}
+
+static int rt5639_prepare(struct snd_pcm_substream *substream,
+                                struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+
+        rt5639->aif_pu = dai->id;
+        return 0;
+}
+
+static int rt5639_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+        unsigned int reg_val = 0, dai_sel;
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                rt5639->master[dai->id] = 1;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                reg_val |= RT5639_I2S_MS_S;
+                rt5639->master[dai->id] = 0;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                reg_val |= RT5639_I2S_BP_INV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                reg_val |= RT5639_I2S_DF_LEFT;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+                reg_val |= RT5639_I2S_DF_PCM_A;
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                reg_val |= RT5639_I2S_DF_PCM_B;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        dai_sel = get_sdp_info(codec, dai->id);
+        if (dai_sel < 0) {
+                dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+                return -EINVAL;
+        }
+        if (dai_sel & RT5639_U_IF1) {
+                snd_soc_update_bits(codec, RT5639_I2S1_SDP,
+                        RT5639_I2S_MS_MASK | RT5639_I2S_BP_MASK |
+                        RT5639_I2S_DF_MASK, reg_val);
+        }
+        if (dai_sel & RT5639_U_IF2) {
+                snd_soc_update_bits(codec, RT5639_I2S2_SDP,
+                        RT5639_I2S_MS_MASK | RT5639_I2S_BP_MASK |
+                        RT5639_I2S_DF_MASK, reg_val);
+        }
+
+        return 0;
+}
+
+static int rt5639_set_dai_sysclk(struct snd_soc_dai *dai,
+                int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+        unsigned int reg_val = 0;
+
+        if (freq == rt5639->sysclk && clk_id == rt5639->sysclk_src)
+                return 0;
+
+        switch (clk_id) {
+        case RT5639_SCLK_S_MCLK:
+                reg_val |= RT5639_SCLK_SRC_MCLK;
+                break;
+        case RT5639_SCLK_S_PLL1:
+                reg_val |= RT5639_SCLK_SRC_PLL1;
+                break;
+        case RT5639_SCLK_S_RCCLK:
+                reg_val |= RT5639_SCLK_SRC_RCCLK;
+                break;
+        default:
+                dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
+                return -EINVAL;
+        }
+        snd_soc_update_bits(codec, RT5639_GLB_CLK,
+                RT5639_SCLK_SRC_MASK, reg_val);
+        rt5639->sysclk = freq;
+        rt5639->sysclk_src = clk_id;
+
+        dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
+
+        return 0;
+}
+
+/**
+ * rt5639_pll_calc - Calcualte PLL M/N/K code.
+ * @freq_in: external clock provided to codec.
+ * @freq_out: target clock which codec works on.
+ * @pll_code: Pointer to structure with M, N, K and bypass flag.
+ *
+ * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
+ * which make calculation more efficiently.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt5639_pll_calc(const unsigned int freq_in,
+        const unsigned int freq_out, struct rt5639_pll_code *pll_code)
+{
+        int max_n = RT5639_PLL_N_MAX, max_m = RT5639_PLL_M_MAX;
+        int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
+        bool bypass = false;
+
+        if (RT5639_PLL_INP_MAX < freq_in || RT5639_PLL_INP_MIN > freq_in)
+                return -EINVAL;
+
+        for (n_t = 0; n_t <= max_n; n_t++) {
+                in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
+                if (in_t < 0)
+                        continue;
+                if (in_t == freq_out) {
+                        bypass = true;
+                        n = n_t;
+                        goto code_find;
+                }
+                for (m_t = 0; m_t <= max_m; m_t++) {
+                        out_t = in_t / (m_t + 2);
+                        red = abs(out_t - freq_out);
+                        if (red < red_t) {
+                                n = n_t;
+                                m = m_t;
+                                if(red == 0)
+                                        goto code_find;
+                                red_t = red;
+                        }
+                }
+        }
+        pr_debug("Only get approximation about PLL\n");
+
+code_find:
+
+        pll_code->m_bp = bypass;
+        pll_code->m_code= m;
+        pll_code->n_code = n;
+        pll_code->k_code = 2;
+        return 0;
+}
+
+static int rt5639_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
+                        unsigned int freq_in, unsigned int freq_out)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+        struct rt5639_pll_code pll_code;
+        int ret, dai_sel;
+
+        if (source == rt5639->pll_src && freq_in == rt5639->pll_in &&
+            freq_out == rt5639->pll_out)
+                return 0;
+
+        if (!freq_in || !freq_out) {
+                dev_dbg(codec->dev, "PLL disabled\n");
+
+                rt5639->pll_in = 0;
+                rt5639->pll_out = 0;
+                snd_soc_update_bits(codec, RT5639_GLB_CLK,
+                        RT5639_SCLK_SRC_MASK, RT5639_SCLK_SRC_MCLK);
+                return 0;
+        }
+
+        switch (source) {
+        case RT5639_PLL1_S_MCLK:
+                snd_soc_update_bits(codec, RT5639_GLB_CLK,
+                        RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_MCLK);
+                break;
+        case RT5639_PLL1_S_BCLK1:
+        case RT5639_PLL1_S_BCLK2:
+                dai_sel = get_sdp_info(codec, dai->id);
+                if (dai_sel < 0) {
+                        dev_err(codec->dev,
+                                "Failed to get sdp info: %d\n", dai_sel);
+                        return -EINVAL;
+                }
+                if (dai_sel & RT5639_U_IF1) {
+                        snd_soc_update_bits(codec, RT5639_GLB_CLK,
+                                RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_BCLK1);
+                }
+                if (dai_sel & RT5639_U_IF2) {
+                        snd_soc_update_bits(codec, RT5639_GLB_CLK,
+                                RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_BCLK2);
+                }
+                if (dai_sel & RT5639_U_IF3) {
+                        snd_soc_update_bits(codec, RT5639_GLB_CLK,
+                                RT5639_PLL1_SRC_MASK, RT5639_PLL1_SRC_BCLK3);
+                }
+                break;
+        default:
+                dev_err(codec->dev, "Unknown PLL source %d\n", source);
+                return -EINVAL;
+        }
+
+        ret = rt5639_pll_calc(freq_in, freq_out, &pll_code);
+        if (ret < 0) {
+                dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
+                return ret;
+        }
+
+        dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
+                (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
+
+        snd_soc_write(codec, RT5639_PLL_CTRL1,
+                pll_code.n_code << RT5639_PLL_N_SFT | pll_code.k_code);
+        snd_soc_write(codec, RT5639_PLL_CTRL2,
+                (pll_code.m_bp ? 0 : pll_code.m_code) << RT5639_PLL_M_SFT |
+                pll_code.m_bp << RT5639_PLL_M_BP_SFT);
+
+        rt5639->pll_in = freq_in;
+        rt5639->pll_out = freq_out;
+        rt5639->pll_src = source;
+
+        return 0;
+}
+
+/**
+ * rt5639_index_show - Dump private registers.
+ * @dev: codec device.
+ * @attr: device attribute.
+ * @buf: buffer for display.
+ *
+ * To show non-zero values of all private registers.
+ *
+ * Returns buffer length.
+ */
+static ssize_t rt5639_index_show(struct device *dev,
+        struct device_attribute *attr, char *buf)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct rt5639_priv *rt5639 = i2c_get_clientdata(client);
+        struct snd_soc_codec *codec = rt5639->codec;
+        unsigned int val;
+        int cnt = 0, i;
+
+        cnt += sprintf(buf, "RT5639 index register\n");
+        for (i = 0; i < 0xb4; i++) {
+                if (cnt + RT5639_REG_DISP_LEN >= PAGE_SIZE)
+                        break;
+                val = rt5639_index_read(codec, i);
+                if (!val)
+                        continue;
+                cnt += snprintf(buf + cnt, RT5639_REG_DISP_LEN,
+                                "%02x: %04x\n", i, val);
+        }
+
+        if (cnt >= PAGE_SIZE)
+                cnt = PAGE_SIZE - 1;
+
+        return cnt;
+}
+static DEVICE_ATTR(index_reg, 0444, rt5639_index_show, NULL);
+
+static int rt5639_set_bias_level(struct snd_soc_codec *codec,
+                        enum snd_soc_bias_level level)
+{
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+#ifdef RT5639_DEMO
+                snd_soc_update_bits(codec, RT5639_SPK_VOL,
+                        RT5639_L_MUTE | RT5639_R_MUTE, 0);
+                snd_soc_update_bits(codec, RT5639_HP_VOL,
+                        RT5639_L_MUTE | RT5639_R_MUTE, 0);
+#endif
+                break;
+
+        case SND_SOC_BIAS_PREPARE:
+#ifdef RT5639_DEMO
+                snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
+                        RT5639_PWR_VREF1 | RT5639_PWR_MB |
+                        RT5639_PWR_BG | RT5639_PWR_VREF2,
+                        RT5639_PWR_VREF1 | RT5639_PWR_MB |
+                        RT5639_PWR_BG | RT5639_PWR_VREF2);
+                msleep(100);
+
+                snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
+                        RT5639_PWR_FV1 | RT5639_PWR_FV2,        
+                        RT5639_PWR_FV1 | RT5639_PWR_FV2);
+
+                snd_soc_update_bits(codec, RT5639_PWR_ANLG2,
+                        RT5639_PWR_MB1 | RT5639_PWR_MB2,
+                        RT5639_PWR_MB1 | RT5639_PWR_MB2);
+#endif
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+#ifdef RT5639_DEMO
+                snd_soc_update_bits(codec, RT5639_SPK_VOL,
+                        RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
+                snd_soc_update_bits(codec, RT5639_HP_VOL,
+                        RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
+
+                snd_soc_update_bits(codec, RT5639_PWR_ANLG2,
+                        RT5639_PWR_MB1 | RT5639_PWR_MB2,
+                        0);
+#endif
+                if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
+                        snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
+                                RT5639_PWR_VREF1 | RT5639_PWR_MB |
+                                RT5639_PWR_BG | RT5639_PWR_VREF2,
+                                RT5639_PWR_VREF1 | RT5639_PWR_MB |
+                                RT5639_PWR_BG | RT5639_PWR_VREF2);
+                        msleep(10);
+                        snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
+                                RT5639_PWR_FV1 | RT5639_PWR_FV2,
+                                RT5639_PWR_FV1 | RT5639_PWR_FV2);
+                        codec->cache_only = false;
+                        snd_soc_cache_sync(codec);
+                }
+                break;
+
+        case SND_SOC_BIAS_OFF:
+#ifdef RT5639_DEMO
+                snd_soc_update_bits(codec, RT5639_SPK_VOL,
+                        RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
+                snd_soc_update_bits(codec, RT5639_HP_VOL,
+                        RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
+                snd_soc_update_bits(codec, RT5639_OUTPUT,
+                        RT5639_L_MUTE | RT5639_R_MUTE, RT5639_L_MUTE | RT5639_R_MUTE);
+                snd_soc_update_bits(codec, RT5639_MONO_OUT,
+                        RT5639_L_MUTE, RT5639_L_MUTE);
+#endif
+                snd_soc_write(codec, RT5639_PWR_DIG1, 0x0000);
+                snd_soc_write(codec, RT5639_PWR_DIG2, 0x0000);
+                snd_soc_write(codec, RT5639_PWR_VOL, 0x0000);
+                snd_soc_write(codec, RT5639_PWR_MIXER, 0x0000);
+                snd_soc_write(codec, RT5639_PWR_ANLG1, 0x0000);
+                snd_soc_write(codec, RT5639_PWR_ANLG2, 0x0000);
+                break;
+
+        default:
+                break;
+        }
+        codec->dapm.bias_level = level;
+
+        return 0;
+}
+
+static int rt5639_probe(struct snd_soc_codec *codec)
+{
+        struct rt5639_priv *rt5639 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        rt5639_reset(codec);
+        snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
+                RT5639_PWR_VREF1 | RT5639_PWR_MB |
+                RT5639_PWR_BG | RT5639_PWR_VREF2,
+                RT5639_PWR_VREF1 | RT5639_PWR_MB |
+                RT5639_PWR_BG | RT5639_PWR_VREF2);
+        msleep(100);
+        snd_soc_update_bits(codec, RT5639_PWR_ANLG1,
+                RT5639_PWR_FV1 | RT5639_PWR_FV2,
+                RT5639_PWR_FV1 | RT5639_PWR_FV2);
+        /* DMIC */
+        if (rt5639->dmic_en == RT5639_DMIC1) {
+                snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
+                        RT5639_GP2_PIN_MASK, RT5639_GP2_PIN_DMIC1_SCL);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_1L_LH_MASK | RT5639_DMIC_1R_LH_MASK,
+                        RT5639_DMIC_1L_LH_FALLING | RT5639_DMIC_1R_LH_RISING);
+        } else if (rt5639->dmic_en == RT5639_DMIC2) {
+                snd_soc_update_bits(codec, RT5639_GPIO_CTRL1,
+                        RT5639_GP2_PIN_MASK, RT5639_GP2_PIN_DMIC1_SCL);
+                snd_soc_update_bits(codec, RT5639_DMIC,
+                        RT5639_DMIC_2L_LH_MASK | RT5639_DMIC_2R_LH_MASK,
+                        RT5639_DMIC_2L_LH_FALLING | RT5639_DMIC_2R_LH_RISING);
+        }
+
+#ifdef RT5639_DEMO
+        rt5639_reg_init(codec);
+#endif
+
+        codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
+
+        snd_soc_add_controls(codec, rt5639_snd_controls,
+                ARRAY_SIZE(rt5639_snd_controls));
+
+        rt5639->codec = codec;
+        ret = device_create_file(codec->dev, &dev_attr_index_reg);
+        if (ret != 0) {
+                dev_err(codec->dev,
+                        "Failed to create index_reg sysfs files: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int rt5639_remove(struct snd_soc_codec *codec)
+{
+        rt5639_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int rt5639_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        rt5639_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        return 0;
+}
+
+static int rt5639_resume(struct snd_soc_codec *codec)
+{
+        rt5639_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+        return 0;
+}
+#else
+#define rt5639_suspend NULL
+#define rt5639_resume NULL
+#endif
+
+#define RT5639_STEREO_RATES SNDRV_PCM_RATE_8000_96000
+#define RT5639_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
+
+struct snd_soc_dai_ops rt5639_aif_dai_ops = {
+        .hw_params = rt5639_hw_params,
+        .prepare = rt5639_prepare,
+        .set_fmt = rt5639_set_dai_fmt,
+        .set_sysclk = rt5639_set_dai_sysclk,
+        .set_pll = rt5639_set_dai_pll,
+};
+
+struct snd_soc_dai_driver rt5639_dai[] = {
+        {
+                .name = "rt5639-aif1",
+                .id = RT5639_AIF1,
+                .playback = {
+                        .stream_name = "AIF1 Playback",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5639_STEREO_RATES,
+                        .formats = RT5639_FORMATS,
+                },
+                .capture = {
+                        .stream_name = "AIF1 Capture",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5639_STEREO_RATES,
+                        .formats = RT5639_FORMATS,
+                },
+                .ops = &rt5639_aif_dai_ops,
+        },
+        {
+                .name = "rt5639-aif2",
+                .id = RT5639_AIF2,
+                .playback = {
+                        .stream_name = "AIF2 Playback",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5639_STEREO_RATES,
+                        .formats = RT5639_FORMATS,
+                },
+                .capture = {
+                        .stream_name = "AIF2 Capture",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5639_STEREO_RATES,
+                        .formats = RT5639_FORMATS,
+                },
+                .ops = &rt5639_aif_dai_ops,
+        },
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_rt5639 = {
+        .probe = rt5639_probe,
+        .remove = rt5639_remove,
+        .suspend = rt5639_suspend,
+        .resume = rt5639_resume,
+        .set_bias_level = rt5639_set_bias_level,
+        .reg_cache_size = RT5639_VENDOR_ID2 + 1,
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = rt5639_reg,
+        .volatile_register = rt5639_volatile_register,
+        .readable_register = rt5639_readable_register,
+        .reg_cache_step = 1,
+        .dapm_widgets = rt5639_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(rt5639_dapm_widgets),
+        .dapm_routes = rt5639_dapm_routes,
+        .num_dapm_routes = ARRAY_SIZE(rt5639_dapm_routes),
+};
+
+static const struct i2c_device_id rt5639_i2c_id[] = {
+        { "rt5639", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, rt5639_i2c_id);
+
+static int rt5639_i2c_probe(struct i2c_client *i2c,
+                    const struct i2c_device_id *id)
+{
+        struct rt5639_priv *rt5639;
+        int ret;
+
+        rt5639 = kzalloc(sizeof(struct rt5639_priv), GFP_KERNEL);
+        if (NULL == rt5639)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, rt5639);
+
+        ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5639,
+                        rt5639_dai, ARRAY_SIZE(rt5639_dai));
+        if (ret < 0)
+                kfree(rt5639);
+
+        return ret;
+}
+
+static __devexit int rt5639_i2c_remove(struct i2c_client *i2c)
+{
+        snd_soc_unregister_codec(&i2c->dev);
+        kfree(i2c_get_clientdata(i2c));
+        return 0;
+}
+
+struct i2c_driver rt5639_i2c_driver = {
+        .driver = {
+                .name = "rt5639",
+                .owner = THIS_MODULE,
+        },
+        .probe = rt5639_i2c_probe,
+        .remove   = __devexit_p(rt5639_i2c_remove),
+        .id_table = rt5639_i2c_id,
+};
+
+static int __init rt5639_modinit(void)
+{
+        return i2c_add_driver(&rt5639_i2c_driver);
+}
+module_init(rt5639_modinit);
+
+static void __exit rt5639_modexit(void)
+{
+        i2c_del_driver(&rt5639_i2c_driver);
+}
+module_exit(rt5639_modexit);
+
+MODULE_DESCRIPTION("ASoC RT5639 driver");
+MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt5639.h b/sound/soc/codecs/rt5639.h
new file mode 100644
index 00000000000..f75ddad1aa0
--- /dev/null
+++ b/sound/soc/codecs/rt5639.h
@@ -0,0 +1,2104 @@
+/*
+ * rt5639.h  --  RT5639 ALSA SoC audio driver
+ *
+ * Copyright 2011 Realtek Microelectronics
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT5639_H__
+#define __RT5639_H__
+
+/* Info */
+#define RT5639_RESET                            0x00
+#define RT5639_VENDOR_ID                        0xfd
+#define RT5639_VENDOR_ID1                       0xfe
+#define RT5639_VENDOR_ID2                       0xff
+/*  I/O - Output */
+#define RT5639_SPK_VOL                          0x01
+#define RT5639_HP_VOL                           0x02
+#define RT5639_OUTPUT                           0x03
+#define RT5639_MONO_OUT                 0x04
+/* I/O - Input */
+#define RT5639_IN1_IN2                          0x0d
+#define RT5639_IN3_IN4                          0x0e
+#define RT5639_INL_INR_VOL                      0x0f
+/* I/O - ADC/DAC/DMIC */
+#define RT5639_DAC1_DIG_VOL                     0x19
+#define RT5639_DAC2_DIG_VOL                     0x1a
+#define RT5639_DAC2_CTRL                        0x1b
+#define RT5639_ADC_DIG_VOL                      0x1c
+#define RT5639_ADC_DATA                 0x1d
+#define RT5639_ADC_BST_VOL                      0x1e
+/* Mixer - D-D */
+#define RT5639_STO_ADC_MIXER                    0x27
+#define RT5639_MONO_ADC_MIXER                   0x28
+#define RT5639_AD_DA_MIXER                      0x29
+#define RT5639_STO_DAC_MIXER                    0x2a
+#define RT5639_MONO_DAC_MIXER                   0x2b
+#define RT5639_DIG_MIXER                        0x2c
+#define RT5639_DSP_PATH1                        0x2d
+#define RT5639_DSP_PATH2                        0x2e
+#define RT5639_DIG_INF_DATA                     0x2f
+/* Mixer - ADC */
+#define RT5639_REC_L1_MIXER                     0x3b
+#define RT5639_REC_L2_MIXER                     0x3c
+#define RT5639_REC_R1_MIXER                     0x3d
+#define RT5639_REC_R2_MIXER                     0x3e
+/* Mixer - DAC */
+#define RT5639_HPO_MIXER                        0x45
+#define RT5639_SPK_L_MIXER                      0x46
+#define RT5639_SPK_R_MIXER                      0x47
+#define RT5639_SPO_L_MIXER                      0x48
+#define RT5639_SPO_R_MIXER                      0x49
+#define RT5639_SPO_CLSD_RATIO                   0x4a
+#define RT5639_MONO_MIXER                       0x4c
+#define RT5639_OUT_L1_MIXER                     0x4d
+#define RT5639_OUT_L2_MIXER                     0x4e
+#define RT5639_OUT_L3_MIXER                     0x4f
+#define RT5639_OUT_R1_MIXER                     0x50
+#define RT5639_OUT_R2_MIXER                     0x51
+#define RT5639_OUT_R3_MIXER                     0x52
+#define RT5639_LOUT_MIXER                       0x53
+/* Power */
+#define RT5639_PWR_DIG1                 0x61
+#define RT5639_PWR_DIG2                 0x62
+#define RT5639_PWR_ANLG1                        0x63
+#define RT5639_PWR_ANLG2                        0x64
+#define RT5639_PWR_MIXER                        0x65
+#define RT5639_PWR_VOL                          0x66
+/* Private Register Control */
+#define RT5639_PRIV_INDEX                       0x6a
+#define RT5639_PRIV_DATA                        0x6c
+/* Format - ADC/DAC */
+#define RT5639_I2S1_SDP                         0x70
+#define RT5639_I2S2_SDP                         0x71
+#define RT5639_I2S3_SDP                         0x72
+#define RT5639_ADDA_CLK1                        0x73
+#define RT5639_ADDA_CLK2                        0x74
+#define RT5639_DMIC                             0x75
+/* Function - Analog */
+#define RT5639_GLB_CLK                          0x80
+#define RT5639_PLL_CTRL1                        0x81
+#define RT5639_PLL_CTRL2                        0x82
+#define RT5639_ASRC_1                           0x83
+#define RT5639_ASRC_2                           0x84
+#define RT5639_ASRC_3                           0x85
+#define RT5639_ASRC_4                           0x89
+#define RT5639_ASRC_5                           0x8a
+#define RT5639_HP_OVCD                          0x8b
+#define RT5639_CLS_D_OVCD                       0x8c
+#define RT5639_CLS_D_OUT                        0x8d
+#define RT5639_DEPOP_M1                 0x8e
+#define RT5639_DEPOP_M2                 0x8f
+#define RT5639_DEPOP_M3                 0x90
+#define RT5639_CHARGE_PUMP                      0x91
+#define RT5639_PV_DET_SPK_G                     0x92
+#define RT5639_MICBIAS                          0x93
+/* Function - Digital */
+#define RT5639_EQ_CTRL1                         0xb0
+#define RT5639_EQ_CTRL2                         0xb1
+#define RT5639_WIND_FILTER                      0xb2
+#define RT5639_DRC_AGC_1                        0xb4
+#define RT5639_DRC_AGC_2                        0xb5
+#define RT5639_DRC_AGC_3                        0xb6
+#define RT5639_SVOL_ZC                          0xb7
+#define RT5639_ANC_CTRL1                        0xb8
+#define RT5639_ANC_CTRL2                        0xb9
+#define RT5639_ANC_CTRL3                        0xba
+#define RT5639_JD_CTRL                          0xbb
+#define RT5639_ANC_JD                           0xbc
+#define RT5639_IRQ_CTRL1                        0xbd
+#define RT5639_IRQ_CTRL2                        0xbe
+#define RT5639_INT_IRQ_ST                       0xbf
+#define RT5639_GPIO_CTRL1                       0xc0
+#define RT5639_GPIO_CTRL2                       0xc1
+#define RT5639_GPIO_CTRL3                       0xc2
+#define RT5639_DSP_CTRL1                        0xc4
+#define RT5639_DSP_CTRL2                        0xc5
+#define RT5639_DSP_CTRL3                        0xc6
+#define RT5639_DSP_CTRL4                        0xc7
+#define RT5639_PGM_REG_ARR1                     0xc8
+#define RT5639_PGM_REG_ARR2                     0xc9
+#define RT5639_PGM_REG_ARR3                     0xca
+#define RT5639_PGM_REG_ARR4                     0xcb
+#define RT5639_PGM_REG_ARR5                     0xcc
+#define RT5639_SCB_FUNC                 0xcd
+#define RT5639_SCB_CTRL                         0xce
+#define RT5639_BASE_BACK                        0xcf
+#define RT5639_MP3_PLUS1                        0xd0
+#define RT5639_MP3_PLUS2                        0xd1
+#define RT5639_3D_HP                            0xd2
+#define RT5639_ADJ_HPF                          0xd3
+#define RT5639_HP_CALIB_AMP_DET         0xd6
+#define RT5639_HP_CALIB2                        0xd7
+#define RT5639_SV_ZCD1                          0xd9
+#define RT5639_SV_ZCD2                          0xda
+/* Dummy Register */
+#define RT5639_DUMMY1                           0xfa
+#define RT5639_DUMMY2                           0xfb
+#define RT5639_DUMMY3                           0xfc
+
+
+/* Index of Codec Private Register definition */
+#define RT5639_3D_SPK                           0x63
+#define RT5639_WND_1                            0x6c
+#define RT5639_WND_2                            0x6d
+#define RT5639_WND_3                            0x6e
+#define RT5639_WND_4                            0x6f
+#define RT5639_WND_5                            0x70
+#define RT5639_WND_8                            0x73
+#define RT5639_DIP_SPK_INF                      0x75
+#define RT5639_EQ_BW_LOP                        0xa0
+#define RT5639_EQ_GN_LOP                        0xa1
+#define RT5639_EQ_FC_BP1                        0xa2
+#define RT5639_EQ_BW_BP1                        0xa3
+#define RT5639_EQ_GN_BP1                        0xa4
+#define RT5639_EQ_FC_BP2                        0xa5
+#define RT5639_EQ_BW_BP2                        0xa6
+#define RT5639_EQ_GN_BP2                        0xa7
+#define RT5639_EQ_FC_BP3                        0xa8
+#define RT5639_EQ_BW_BP3                        0xa9
+#define RT5639_EQ_GN_BP3                        0xaa
+#define RT5639_EQ_FC_BP4                        0xab
+#define RT5639_EQ_BW_BP4                        0xac
+#define RT5639_EQ_GN_BP4                        0xad
+#define RT5639_EQ_FC_HIP1                       0xae
+#define RT5639_EQ_GN_HIP1                       0xaf
+#define RT5639_EQ_FC_HIP2                       0xb0
+#define RT5639_EQ_BW_HIP2                       0xb1
+#define RT5639_EQ_GN_HIP2                       0xb2
+#define RT5639_EQ_PRE_VOL                       0xb3
+#define RT5639_EQ_PST_VOL                       0xb4
+
+
+/* global definition */
+#define RT5639_L_MUTE                           (0x1 << 15)
+#define RT5639_L_MUTE_SFT                       15
+#define RT5639_VOL_L_MUTE                       (0x1 << 14)
+#define RT5639_VOL_L_SFT                        14
+#define RT5639_R_MUTE                           (0x1 << 7)
+#define RT5639_R_MUTE_SFT                       7
+#define RT5639_VOL_R_MUTE                       (0x1 << 6)
+#define RT5639_VOL_R_SFT                        6
+#define RT5639_L_VOL_MASK                       (0x3f << 8)
+#define RT5639_L_VOL_SFT                        8
+#define RT5639_R_VOL_MASK                       (0x3f)
+#define RT5639_R_VOL_SFT                        0
+
+/* IN1 and IN2 Control (0x0d) */
+/* IN3 and IN4 Control (0x0e) */
+#define RT5639_BST_SFT1                         12
+#define RT5639_BST_SFT2                         8
+#define RT5639_IN_DF1                           (0x1 << 7)
+#define RT5639_IN_SFT1                          7
+#define RT5639_IN_DF2                           (0x1 << 6)
+#define RT5639_IN_SFT2                          6
+
+/* INL and INR Volume Control (0x0f) */
+#define RT5639_INL_SEL_MASK                     (0x1 << 15)
+#define RT5639_INL_SEL_SFT                      15
+#define RT5639_INL_SEL_IN4P                     (0x0 << 15)
+#define RT5639_INL_SEL_MONOP                    (0x1 << 15)
+#define RT5639_INL_VOL_MASK                     (0x1f << 8)
+#define RT5639_INL_VOL_SFT                      8
+#define RT5639_INR_SEL_MASK                     (0x1 << 7)
+#define RT5639_INR_SEL_SFT                      7
+#define RT5639_INR_SEL_IN4N                     (0x0 << 7)
+#define RT5639_INR_SEL_MONON                    (0x1 << 7)
+#define RT5639_INR_VOL_MASK                     (0x1f)
+#define RT5639_INR_VOL_SFT                      0
+
+/* DAC1 Digital Volume (0x19) */
+#define RT5639_DAC_L1_VOL_MASK          (0xff << 8)
+#define RT5639_DAC_L1_VOL_SFT                   8
+#define RT5639_DAC_R1_VOL_MASK          (0xff)
+#define RT5639_DAC_R1_VOL_SFT                   0
+
+/* DAC2 Digital Volume (0x1a) */
+#define RT5639_DAC_L2_VOL_MASK          (0xff << 8)
+#define RT5639_DAC_L2_VOL_SFT                   8
+#define RT5639_DAC_R2_VOL_MASK          (0xff)
+#define RT5639_DAC_R2_VOL_SFT                   0
+
+/* DAC2 Control (0x1b) */
+#define RT5639_M_DAC_L2_VOL                     (0x1 << 13)
+#define RT5639_M_DAC_L2_VOL_SFT         13
+#define RT5639_M_DAC_R2_VOL                     (0x1 << 12)
+#define RT5639_M_DAC_R2_VOL_SFT         12
+
+/* ADC Digital Volume Control (0x1c) */
+#define RT5639_ADC_L_VOL_MASK                   (0x7f << 8)
+#define RT5639_ADC_L_VOL_SFT                    8
+#define RT5639_ADC_R_VOL_MASK                   (0x7f)
+#define RT5639_ADC_R_VOL_SFT                    0
+
+/* Mono ADC Digital Volume Control (0x1d) */
+#define RT5639_MONO_ADC_L_VOL_MASK              (0x7f << 8)
+#define RT5639_MONO_ADC_L_VOL_SFT               8
+#define RT5639_MONO_ADC_R_VOL_MASK              (0x7f)
+#define RT5639_MONO_ADC_R_VOL_SFT               0
+
+/* ADC Boost Volume Control (0x1e) */
+#define RT5639_ADC_L_BST_MASK                   (0x3 << 14)
+#define RT5639_ADC_L_BST_SFT                    14
+#define RT5639_ADC_R_BST_MASK                   (0x3 << 12)
+#define RT5639_ADC_R_BST_SFT                    12
+#define RT5639_ADC_COMP_MASK                    (0x3 << 10)
+#define RT5639_ADC_COMP_SFT                     10
+
+/* Stereo ADC Mixer Control (0x27) */
+#define RT5639_M_ADC_L1                 (0x1 << 14)
+#define RT5639_M_ADC_L1_SFT                     14
+#define RT5639_M_ADC_L2                 (0x1 << 13)
+#define RT5639_M_ADC_L2_SFT                     13
+#define RT5639_ADC_1_SRC_MASK                   (0x1 << 12)
+#define RT5639_ADC_1_SRC_SFT                    12
+#define RT5639_ADC_1_SRC_ADC                    (0x1 << 12)
+#define RT5639_ADC_1_SRC_DACMIX         (0x0 << 12)
+#define RT5639_ADC_2_SRC_MASK                   (0x3 << 10)
+#define RT5639_ADC_2_SRC_SFT                    10
+#define RT5639_ADC_2_SRC_DMIC1          (0x0 << 10)
+#define RT5639_ADC_2_SRC_DMIC2          (0x1 << 10)
+#define RT5639_ADC_2_SRC_DACMIX         (0x2 << 10)
+#define RT5639_M_ADC_R1                 (0x1 << 6)
+#define RT5639_M_ADC_R1_SFT                     6
+#define RT5639_M_ADC_R2                 (0x1 << 5)
+#define RT5639_M_ADC_R2_SFT                     5
+
+/* Mono ADC Mixer Control (0x28) */
+#define RT5639_M_MONO_ADC_L1                    (0x1 << 14)
+#define RT5639_M_MONO_ADC_L1_SFT                14
+#define RT5639_M_MONO_ADC_L2                    (0x1 << 13)
+#define RT5639_M_MONO_ADC_L2_SFT                13
+#define RT5639_MONO_ADC_L1_SRC_MASK             (0x1 << 12)
+#define RT5639_MONO_ADC_L1_SRC_SFT              12
+#define RT5639_MONO_ADC_L1_SRC_DACMIXL  (0x0 << 12)
+#define RT5639_MONO_ADC_L1_SRC_ADCL             (0x1 << 12)
+#define RT5639_MONO_ADC_L2_SRC_MASK             (0x3 << 10)
+#define RT5639_MONO_ADC_L2_SRC_SFT              10
+#define RT5639_MONO_ADC_L2_SRC_DMIC_L1  (0x0 << 10)
+#define RT5639_MONO_ADC_L2_SRC_DMIC_L2  (0x1 << 10)
+#define RT5639_MONO_ADC_L2_SRC_DACMIXL  (0x2 << 10)
+#define RT5639_M_MONO_ADC_R1                    (0x1 << 6)
+#define RT5639_M_MONO_ADC_R1_SFT                6
+#define RT5639_M_MONO_ADC_R2                    (0x1 << 5)
+#define RT5639_M_MONO_ADC_R2_SFT                5
+#define RT5639_MONO_ADC_R1_SRC_MASK             (0x1 << 4)
+#define RT5639_MONO_ADC_R1_SRC_SFT              4
+#define RT5639_MONO_ADC_R1_SRC_ADCR             (0x1 << 4)
+#define RT5639_MONO_ADC_R1_SRC_DACMIXR  (0x0 << 4)
+#define RT5639_MONO_ADC_R2_SRC_MASK             (0x3 << 2)
+#define RT5639_MONO_ADC_R2_SRC_SFT              2
+#define RT5639_MONO_ADC_R2_SRC_DMIC_R1  (0x0 << 2)
+#define RT5639_MONO_ADC_R2_SRC_DMIC_R2  (0x1 << 2)
+#define RT5639_MONO_ADC_R2_SRC_DACMIXR  (0x2 << 2)
+
+/* ADC Mixer to DAC Mixer Control (0x29) */
+#define RT5639_M_ADCMIX_L                       (0x1 << 15)
+#define RT5639_M_ADCMIX_L_SFT                   15
+#define RT5639_M_IF1_DAC_L                      (0x1 << 14)
+#define RT5639_M_IF1_DAC_L_SFT                  14
+#define RT5639_M_ADCMIX_R                       (0x1 << 7)
+#define RT5639_M_ADCMIX_R_SFT                   7
+#define RT5639_M_IF1_DAC_R                      (0x1 << 6)
+#define RT5639_M_IF1_DAC_R_SFT                  6
+
+/* Stereo DAC Mixer Control (0x2a) */
+#define RT5639_M_DAC_L1                 (0x1 << 14)
+#define RT5639_M_DAC_L1_SFT                     14
+#define RT5639_DAC_L1_STO_L_VOL_MASK            (0x1 << 13)
+#define RT5639_DAC_L1_STO_L_VOL_SFT             13
+#define RT5639_M_DAC_L2                 (0x1 << 12)
+#define RT5639_M_DAC_L2_SFT                     12
+#define RT5639_DAC_L2_STO_L_VOL_MASK            (0x1 << 11)
+#define RT5639_DAC_L2_STO_L_VOL_SFT             11
+#define RT5639_M_ANC_DAC_L                      (0x1 << 10)
+#define RT5639_M_ANC_DAC_L_SFT          10
+#define RT5639_M_DAC_R1                 (0x1 << 6)
+#define RT5639_M_DAC_R1_SFT                     6
+#define RT5639_DAC_R1_STO_R_VOL_MASK            (0x1 << 5)
+#define RT5639_DAC_R1_STO_R_VOL_SFT             5
+#define RT5639_M_DAC_R2                 (0x1 << 4)
+#define RT5639_M_DAC_R2_SFT                     4
+#define RT5639_DAC_R2_STO_R_VOL_MASK            (0x1 << 3)
+#define RT5639_DAC_R2_STO_R_VOL_SFT             3
+#define RT5639_M_ANC_DAC_R                      (0x1 << 2)
+#define RT5639_M_ANC_DAC_R_SFT          2
+
+/* Mono DAC Mixer Control (0x2b) */
+#define RT5639_M_DAC_L1_MONO_L          (0x1 << 14)
+#define RT5639_M_DAC_L1_MONO_L_SFT              14
+#define RT5639_DAC_L1_MONO_L_VOL_MASK   (0x1 << 13)
+#define RT5639_DAC_L1_MONO_L_VOL_SFT            13
+#define RT5639_M_DAC_L2_MONO_L          (0x1 << 12)
+#define RT5639_M_DAC_L2_MONO_L_SFT              12
+#define RT5639_DAC_L2_MONO_L_VOL_MASK   (0x1 << 11)
+#define RT5639_DAC_L2_MONO_L_VOL_SFT            11
+#define RT5639_M_DAC_R2_MONO_L          (0x1 << 10)
+#define RT5639_M_DAC_R2_MONO_L_SFT              10
+#define RT5639_DAC_R2_MONO_L_VOL_MASK   (0x1 << 9)
+#define RT5639_DAC_R2_MONO_L_VOL_SFT            9
+#define RT5639_M_DAC_R1_MONO_R          (0x1 << 6)
+#define RT5639_M_DAC_R1_MONO_R_SFT              6
+#define RT5639_DAC_R1_MONO_R_VOL_MASK   (0x1 << 5)
+#define RT5639_DAC_R1_MONO_R_VOL_SFT            5
+#define RT5639_M_DAC_R2_MONO_R          (0x1 << 4)
+#define RT5639_M_DAC_R2_MONO_R_SFT              4
+#define RT5639_DAC_R2_MONO_R_VOL_MASK   (0x1 << 3)
+#define RT5639_DAC_R2_MONO_R_VOL_SFT            3
+#define RT5639_M_DAC_L2_MONO_R          (0x1 << 2)
+#define RT5639_M_DAC_L2_MONO_R_SFT              2
+#define RT5639_DAC_L2_MONO_R_VOL_MASK   (0x1 << 1)
+#define RT5639_DAC_L2_MONO_R_VOL_SFT            1
+
+/* Digital Mixer Control (0x2c) */
+#define RT5639_M_STO_L_DAC_L                    (0x1 << 15)
+#define RT5639_M_STO_L_DAC_L_SFT                15
+#define RT5639_STO_L_DAC_L_VOL_MASK             (0x1 << 14)
+#define RT5639_STO_L_DAC_L_VOL_SFT              14
+#define RT5639_M_DAC_L2_DAC_L                   (0x1 << 13)
+#define RT5639_M_DAC_L2_DAC_L_SFT               13
+#define RT5639_DAC_L2_DAC_L_VOL_MASK            (0x1 << 12)
+#define RT5639_DAC_L2_DAC_L_VOL_SFT             12
+#define RT5639_M_STO_R_DAC_R                    (0x1 << 11)
+#define RT5639_M_STO_R_DAC_R_SFT                11
+#define RT5639_STO_R_DAC_R_VOL_MASK             (0x1 << 10)
+#define RT5639_STO_R_DAC_R_VOL_SFT              10
+#define RT5639_M_DAC_R2_DAC_R                   (0x1 << 9)
+#define RT5639_M_DAC_R2_DAC_R_SFT               9
+#define RT5639_DAC_R2_DAC_R_VOL_MASK            (0x1 << 8)
+#define RT5639_DAC_R2_DAC_R_VOL_SFT             8
+
+/* DSP Path Control 1 (0x2d) */
+#define RT5639_RXDP_SRC_MASK                    (0x1 << 15)
+#define RT5639_RXDP_SRC_SFT                     15
+#define RT5639_RXDP_SRC_NOR                     (0x0 << 15)
+#define RT5639_RXDP_SRC_DIV3                    (0x1 << 15)
+#define RT5639_TXDP_SRC_MASK                    (0x1 << 14)
+#define RT5639_TXDP_SRC_SFT                     14
+#define RT5639_TXDP_SRC_NOR                     (0x0 << 14)
+#define RT5639_TXDP_SRC_DIV3                    (0x1 << 14)
+
+/* DSP Path Control 2 (0x2e) */
+#define RT5639_DAC_L2_SEL_MASK          (0x3 << 14)
+#define RT5639_DAC_L2_SEL_SFT                   14
+#define RT5639_DAC_L2_SEL_IF2                   (0x0 << 14)
+#define RT5639_DAC_L2_SEL_IF3                   (0x1 << 14)
+#define RT5639_DAC_L2_SEL_TXDC                  (0x2 << 14)
+#define RT5639_DAC_L2_SEL_BASS                  (0x3 << 14)
+#define RT5639_DAC_R2_SEL_MASK          (0x3 << 12)
+#define RT5639_DAC_R2_SEL_SFT                   12
+#define RT5639_DAC_R2_SEL_IF2                   (0x0 << 12)
+#define RT5639_DAC_R2_SEL_IF3                   (0x1 << 12)
+#define RT5639_DAC_R2_SEL_TXDC          (0x2 << 12)
+#define RT5639_IF2_ADC_L_SEL_MASK               (0x1 << 11)
+#define RT5639_IF2_ADC_L_SEL_SFT                11
+#define RT5639_IF2_ADC_L_SEL_TXDP               (0x0 << 11)
+#define RT5639_IF2_ADC_L_SEL_PASS               (0x1 << 11)
+#define RT5639_IF2_ADC_R_SEL_MASK               (0x1 << 10)
+#define RT5639_IF2_ADC_R_SEL_SFT                10
+#define RT5639_IF2_ADC_R_SEL_TXDP               (0x0 << 10)
+#define RT5639_IF2_ADC_R_SEL_PASS               (0x1 << 10)
+#define RT5639_RXDC_SEL_MASK                    (0x3 << 8)
+#define RT5639_RXDC_SEL_SFT                     8
+#define RT5639_RXDC_SEL_NOR                     (0x0 << 8)
+#define RT5639_RXDC_SEL_L2R                     (0x1 << 8)
+#define RT5639_RXDC_SEL_R2L                     (0x2 << 8)
+#define RT5639_RXDC_SEL_SWAP                    (0x3 << 8)
+#define RT5639_RXDP_SEL_MASK                    (0x3 << 6)
+#define RT5639_RXDP_SEL_SFT                     6
+#define RT5639_RXDP_SEL_NOR                     (0x0 << 6)
+#define RT5639_RXDP_SEL_L2R                     (0x1 << 6)
+#define RT5639_RXDP_SEL_R2L                     (0x2 << 6)
+#define RT5639_RXDP_SEL_SWAP                    (0x3 << 6)
+#define RT5639_TXDC_SEL_MASK                    (0x3 << 4)
+#define RT5639_TXDC_SEL_SFT                     4
+#define RT5639_TXDC_SEL_NOR                     (0x0 << 4)
+#define RT5639_TXDC_SEL_L2R                     (0x1 << 4)
+#define RT5639_TXDC_SEL_R2L                     (0x2 << 4)
+#define RT5639_TXDC_SEL_SWAP                    (0x3 << 4)
+#define RT5639_TXDP_SEL_MASK                    (0x3 << 2)
+#define RT5639_TXDP_SEL_SFT                     2
+#define RT5639_TXDP_SEL_NOR                     (0x0 << 2)
+#define RT5639_TXDP_SEL_L2R                     (0x1 << 2)
+#define RT5639_TXDP_SEL_R2L                     (0x2 << 2)
+#define RT5639_TRXDP_SEL_SWAP                   (0x3 << 2)
+
+/* Digital Interface Data Control (0x2f) */
+#define RT5639_IF1_DAC_SEL_MASK         (0x3 << 14)
+#define RT5639_IF1_DAC_SEL_SFT                  14
+#define RT5639_IF1_DAC_SEL_NOR                  (0x0 << 14)
+#define RT5639_IF1_DAC_SEL_L2R                  (0x1 << 14)
+#define RT5639_IF1_DAC_SEL_R2L                  (0x2 << 14)
+#define RT5639_IF1_DAC_SEL_SWAP         (0x3 << 14)
+#define RT5639_IF1_ADC_SEL_MASK         (0x3 << 12)
+#define RT5639_IF1_ADC_SEL_SFT                  12
+#define RT5639_IF1_ADC_SEL_NOR                  (0x0 << 12)
+#define RT5639_IF1_ADC_SEL_L2R                  (0x1 << 12)
+#define RT5639_IF1_ADC_SEL_R2L                  (0x2 << 12)
+#define RT5639_IF1_ADC_SEL_SWAP         (0x3 << 12)
+#define RT5639_IF2_DAC_SEL_MASK         (0x3 << 10)
+#define RT5639_IF2_DAC_SEL_SFT                  10
+#define RT5639_IF2_DAC_SEL_NOR                  (0x0 << 10)
+#define RT5639_IF2_DAC_SEL_L2R                  (0x1 << 10)
+#define RT5639_IF2_DAC_SEL_R2L                  (0x2 << 10)
+#define RT5639_IF2_DAC_SEL_SWAP         (0x3 << 10)
+#define RT5639_IF2_ADC_SEL_MASK         (0x3 << 8)
+#define RT5639_IF2_ADC_SEL_SFT                  8
+#define RT5639_IF2_ADC_SEL_NOR                  (0x0 << 8)
+#define RT5639_IF2_ADC_SEL_L2R                  (0x1 << 8)
+#define RT5639_IF2_ADC_SEL_R2L                  (0x2 << 8)
+#define RT5639_IF2_ADC_SEL_SWAP         (0x3 << 8)
+#define RT5639_IF3_DAC_SEL_MASK         (0x3 << 6)
+#define RT5639_IF3_DAC_SEL_SFT                  6
+#define RT5639_IF3_DAC_SEL_NOR                  (0x0 << 6)
+#define RT5639_IF3_DAC_SEL_L2R                  (0x1 << 6)
+#define RT5639_IF3_DAC_SEL_R2L                  (0x2 << 6)
+#define RT5639_IF3_DAC_SEL_SWAP         (0x3 << 6)
+#define RT5639_IF3_ADC_SEL_MASK         (0x3 << 4)
+#define RT5639_IF3_ADC_SEL_SFT                  4
+#define RT5639_IF3_ADC_SEL_NOR                  (0x0 << 4)
+#define RT5639_IF3_ADC_SEL_L2R                  (0x1 << 4)
+#define RT5639_IF3_ADC_SEL_R2L                  (0x2 << 4)
+#define RT5639_IF3_ADC_SEL_SWAP         (0x3 << 4)
+
+/* REC Left Mixer Control 1 (0x3b) */
+#define RT5639_G_HP_L_RM_L_MASK         (0x7 << 13)
+#define RT5639_G_HP_L_RM_L_SFT                  13
+#define RT5639_G_IN_L_RM_L_MASK         (0x7 << 10)
+#define RT5639_G_IN_L_RM_L_SFT                  10
+#define RT5639_G_BST4_RM_L_MASK         (0x7 << 7)
+#define RT5639_G_BST4_RM_L_SFT                  7
+#define RT5639_G_BST3_RM_L_MASK         (0x7 << 4)
+#define RT5639_G_BST3_RM_L_SFT                  4
+#define RT5639_G_BST2_RM_L_MASK         (0x7 << 1)
+#define RT5639_G_BST2_RM_L_SFT                  1
+
+/* REC Left Mixer Control 2 (0x3c) */
+#define RT5639_G_BST1_RM_L_MASK         (0x7 << 13)
+#define RT5639_G_BST1_RM_L_SFT                  13
+#define RT5639_G_OM_L_RM_L_MASK         (0x7 << 10)
+#define RT5639_G_OM_L_RM_L_SFT          10
+#define RT5639_M_HP_L_RM_L                      (0x1 << 6)
+#define RT5639_M_HP_L_RM_L_SFT          6
+#define RT5639_M_IN_L_RM_L                      (0x1 << 5)
+#define RT5639_M_IN_L_RM_L_SFT                  5
+#define RT5639_M_BST4_RM_L                      (0x1 << 4)
+#define RT5639_M_BST4_RM_L_SFT          4
+#define RT5639_M_BST3_RM_L                      (0x1 << 3)
+#define RT5639_M_BST3_RM_L_SFT          3
+#define RT5639_M_BST2_RM_L                      (0x1 << 2)
+#define RT5639_M_BST2_RM_L_SFT          2
+#define RT5639_M_BST1_RM_L                      (0x1 << 1)
+#define RT5639_M_BST1_RM_L_SFT          1
+#define RT5639_M_OM_L_RM_L                      (0x1)
+#define RT5639_M_OM_L_RM_L_SFT          0
+
+/* REC Right Mixer Control 1 (0x3d) */
+#define RT5639_G_HP_R_RM_R_MASK         (0x7 << 13)
+#define RT5639_G_HP_R_RM_R_SFT          13
+#define RT5639_G_IN_R_RM_R_MASK         (0x7 << 10)
+#define RT5639_G_IN_R_RM_R_SFT                  10
+#define RT5639_G_BST4_RM_R_MASK         (0x7 << 7)
+#define RT5639_G_BST4_RM_R_SFT                  7
+#define RT5639_G_BST3_RM_R_MASK         (0x7 << 4)
+#define RT5639_G_BST3_RM_R_SFT                  4
+#define RT5639_G_BST2_RM_R_MASK         (0x7 << 1)
+#define RT5639_G_BST2_RM_R_SFT                  1
+
+/* REC Right Mixer Control 2 (0x3e) */
+#define RT5639_G_BST1_RM_R_MASK         (0x7 << 13)
+#define RT5639_G_BST1_RM_R_SFT                  13
+#define RT5639_G_OM_R_RM_R_MASK         (0x7 << 10)
+#define RT5639_G_OM_R_RM_R_SFT          10
+#define RT5639_M_HP_R_RM_R                      (0x1 << 6)
+#define RT5639_M_HP_R_RM_R_SFT          6
+#define RT5639_M_IN_R_RM_R                      (0x1 << 5)
+#define RT5639_M_IN_R_RM_R_SFT                  5
+#define RT5639_M_BST4_RM_R                      (0x1 << 4)
+#define RT5639_M_BST4_RM_R_SFT          4
+#define RT5639_M_BST3_RM_R                      (0x1 << 3)
+#define RT5639_M_BST3_RM_R_SFT          3
+#define RT5639_M_BST2_RM_R                      (0x1 << 2)
+#define RT5639_M_BST2_RM_R_SFT          2
+#define RT5639_M_BST1_RM_R                      (0x1 << 1)
+#define RT5639_M_BST1_RM_R_SFT          1
+#define RT5639_M_OM_R_RM_R                      (0x1)
+#define RT5639_M_OM_R_RM_R_SFT          0
+
+/* HPMIX Control (0x45) */
+#define RT5639_M_DAC2_HM                        (0x1 << 15)
+#define RT5639_M_DAC2_HM_SFT                    15
+#define RT5639_M_DAC1_HM                        (0x1 << 14)
+#define RT5639_M_DAC1_HM_SFT                    14
+#define RT5639_M_HPVOL_HM                       (0x1 << 13)
+#define RT5639_M_HPVOL_HM_SFT                   13
+#define RT5639_G_HPOMIX_MASK                    (0x1 << 12)
+#define RT5639_G_HPOMIX_SFT                     12
+
+/* SPK Left Mixer Control (0x46) */
+#define RT5639_G_RM_L_SM_L_MASK         (0x3 << 14)
+#define RT5639_G_RM_L_SM_L_SFT          14
+#define RT5639_G_IN_L_SM_L_MASK         (0x3 << 12)
+#define RT5639_G_IN_L_SM_L_SFT                  12
+#define RT5639_G_DAC_L1_SM_L_MASK               (0x3 << 10)
+#define RT5639_G_DAC_L1_SM_L_SFT                10
+#define RT5639_G_DAC_L2_SM_L_MASK               (0x3 << 8)
+#define RT5639_G_DAC_L2_SM_L_SFT                8
+#define RT5639_G_OM_L_SM_L_MASK         (0x3 << 6)
+#define RT5639_G_OM_L_SM_L_SFT          6
+#define RT5639_M_RM_L_SM_L                      (0x1 << 5)
+#define RT5639_M_RM_L_SM_L_SFT          5
+#define RT5639_M_IN_L_SM_L                      (0x1 << 4)
+#define RT5639_M_IN_L_SM_L_SFT                  4
+#define RT5639_M_DAC_L1_SM_L                    (0x1 << 3)
+#define RT5639_M_DAC_L1_SM_L_SFT                3
+#define RT5639_M_DAC_L2_SM_L                    (0x1 << 2)
+#define RT5639_M_DAC_L2_SM_L_SFT                2
+#define RT5639_M_OM_L_SM_L                      (0x1 << 1)
+#define RT5639_M_OM_L_SM_L_SFT          1
+
+/* SPK Right Mixer Control (0x47) */
+#define RT5639_G_RM_R_SM_R_MASK         (0x3 << 14)
+#define RT5639_G_RM_R_SM_R_SFT          14
+#define RT5639_G_IN_R_SM_R_MASK         (0x3 << 12)
+#define RT5639_G_IN_R_SM_R_SFT                  12
+#define RT5639_G_DAC_R1_SM_R_MASK               (0x3 << 10)
+#define RT5639_G_DAC_R1_SM_R_SFT                10
+#define RT5639_G_DAC_R2_SM_R_MASK               (0x3 << 8)
+#define RT5639_G_DAC_R2_SM_R_SFT                8
+#define RT5639_G_OM_R_SM_R_MASK         (0x3 << 6)
+#define RT5639_G_OM_R_SM_R_SFT          6
+#define RT5639_M_RM_R_SM_R                      (0x1 << 5)
+#define RT5639_M_RM_R_SM_R_SFT          5
+#define RT5639_M_IN_R_SM_R                      (0x1 << 4)
+#define RT5639_M_IN_R_SM_R_SFT                  4
+#define RT5639_M_DAC_R1_SM_R                    (0x1 << 3)
+#define RT5639_M_DAC_R1_SM_R_SFT                3
+#define RT5639_M_DAC_R2_SM_R                    (0x1 << 2)
+#define RT5639_M_DAC_R2_SM_R_SFT                2
+#define RT5639_M_OM_R_SM_R                      (0x1 << 1)
+#define RT5639_M_OM_R_SM_R_SFT          1
+
+/* SPOLMIX Control (0x48) */
+#define RT5639_M_DAC_R1_SPM_L                   (0x1 << 15)
+#define RT5639_M_DAC_R1_SPM_L_SFT               15
+#define RT5639_M_DAC_L1_SPM_L                   (0x1 << 14)
+#define RT5639_M_DAC_L1_SPM_L_SFT               14
+#define RT5639_M_SV_R_SPM_L                     (0x1 << 13)
+#define RT5639_M_SV_R_SPM_L_SFT         13
+#define RT5639_M_SV_L_SPM_L                     (0x1 << 12)
+#define RT5639_M_SV_L_SPM_L_SFT         12
+#define RT5639_M_BST1_SPM_L                     (0x1 << 11)
+#define RT5639_M_BST1_SPM_L_SFT         11
+
+/* SPORMIX Control (0x49) */
+#define RT5639_M_DAC_R1_SPM_R                   (0x1 << 13)
+#define RT5639_M_DAC_R1_SPM_R_SFT               13
+#define RT5639_M_SV_R_SPM_R                     (0x1 << 12)
+#define RT5639_M_SV_R_SPM_R_SFT         12
+#define RT5639_M_BST1_SPM_R                     (0x1 << 11)
+#define RT5639_M_BST1_SPM_R_SFT         11
+
+/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
+#define RT5639_SPO_CLSD_RATIO_MASK              (0x7)
+#define RT5639_SPO_CLSD_RATIO_SFT               0
+
+/* Mono Output Mixer Control (0x4c) */
+#define RT5639_M_DAC_R2_MM                      (0x1 << 15)
+#define RT5639_M_DAC_R2_MM_SFT          15
+#define RT5639_M_DAC_L2_MM                      (0x1 << 14)
+#define RT5639_M_DAC_L2_MM_SFT          14
+#define RT5639_M_OV_R_MM                        (0x1 << 13)
+#define RT5639_M_OV_R_MM_SFT                    13
+#define RT5639_M_OV_L_MM                        (0x1 << 12)
+#define RT5639_M_OV_L_MM_SFT                    12
+#define RT5639_M_BST1_MM                        (0x1 << 11)
+#define RT5639_M_BST1_MM_SFT                    11
+#define RT5639_G_MONOMIX_MASK           (0x1 << 10)
+#define RT5639_G_MONOMIX_SFT                    10
+
+/* Output Left Mixer Control 1 (0x4d) */
+#define RT5639_G_BST3_OM_L_MASK         (0x7 << 13)
+#define RT5639_G_BST3_OM_L_SFT          13
+#define RT5639_G_BST2_OM_L_MASK         (0x7 << 10)
+#define RT5639_G_BST2_OM_L_SFT          10
+#define RT5639_G_BST1_OM_L_MASK         (0x7 << 7)
+#define RT5639_G_BST1_OM_L_SFT          7
+#define RT5639_G_IN_L_OM_L_MASK         (0x7 << 4)
+#define RT5639_G_IN_L_OM_L_SFT                  4
+#define RT5639_G_RM_L_OM_L_MASK         (0x7 << 1)
+#define RT5639_G_RM_L_OM_L_SFT          1
+
+/* Output Left Mixer Control 2 (0x4e) */
+#define RT5639_G_DAC_R2_OM_L_MASK               (0x7 << 13)
+#define RT5639_G_DAC_R2_OM_L_SFT                13
+#define RT5639_G_DAC_L2_OM_L_MASK               (0x7 << 10)
+#define RT5639_G_DAC_L2_OM_L_SFT                10
+#define RT5639_G_DAC_L1_OM_L_MASK               (0x7 << 7)
+#define RT5639_G_DAC_L1_OM_L_SFT                7
+
+/* Output Left Mixer Control 3 (0x4f) */
+#define RT5639_M_SM_L_OM_L                      (0x1 << 8)
+#define RT5639_M_SM_L_OM_L_SFT          8
+#define RT5639_M_BST3_OM_L                      (0x1 << 7)
+#define RT5639_M_BST3_OM_L_SFT          7
+#define RT5639_M_BST2_OM_L                      (0x1 << 6)
+#define RT5639_M_BST2_OM_L_SFT          6
+#define RT5639_M_BST1_OM_L                      (0x1 << 5)
+#define RT5639_M_BST1_OM_L_SFT          5
+#define RT5639_M_IN_L_OM_L                      (0x1 << 4)
+#define RT5639_M_IN_L_OM_L_SFT                  4
+#define RT5639_M_RM_L_OM_L                      (0x1 << 3)
+#define RT5639_M_RM_L_OM_L_SFT          3
+#define RT5639_M_DAC_R2_OM_L                    (0x1 << 2)
+#define RT5639_M_DAC_R2_OM_L_SFT                2
+#define RT5639_M_DAC_L2_OM_L                    (0x1 << 1)
+#define RT5639_M_DAC_L2_OM_L_SFT                1
+#define RT5639_M_DAC_L1_OM_L                    (0x1)
+#define RT5639_M_DAC_L1_OM_L_SFT                0
+
+/* Output Right Mixer Control 1 (0x50) */
+#define RT5639_G_BST4_OM_R_MASK         (0x7 << 13)
+#define RT5639_G_BST4_OM_R_SFT          13
+#define RT5639_G_BST2_OM_R_MASK         (0x7 << 10)
+#define RT5639_G_BST2_OM_R_SFT          10
+#define RT5639_G_BST1_OM_R_MASK         (0x7 << 7)
+#define RT5639_G_BST1_OM_R_SFT          7
+#define RT5639_G_IN_R_OM_R_MASK         (0x7 << 4)
+#define RT5639_G_IN_R_OM_R_SFT                  4
+#define RT5639_G_RM_R_OM_R_MASK         (0x7 << 1)
+#define RT5639_G_RM_R_OM_R_SFT          1
+
+/* Output Right Mixer Control 2 (0x51) */
+#define RT5639_G_DAC_L2_OM_R_MASK               (0x7 << 13)
+#define RT5639_G_DAC_L2_OM_R_SFT                13
+#define RT5639_G_DAC_R2_OM_R_MASK               (0x7 << 10)
+#define RT5639_G_DAC_R2_OM_R_SFT                10
+#define RT5639_G_DAC_R1_OM_R_MASK               (0x7 << 7)
+#define RT5639_G_DAC_R1_OM_R_SFT                7
+
+/* Output Right Mixer Control 3 (0x52) */
+#define RT5639_M_SM_L_OM_R                      (0x1 << 8)
+#define RT5639_M_SM_L_OM_R_SFT          8
+#define RT5639_M_BST4_OM_R                      (0x1 << 7)
+#define RT5639_M_BST4_OM_R_SFT          7
+#define RT5639_M_BST2_OM_R                      (0x1 << 6)
+#define RT5639_M_BST2_OM_R_SFT          6
+#define RT5639_M_BST1_OM_R                      (0x1 << 5)
+#define RT5639_M_BST1_OM_R_SFT          5
+#define RT5639_M_IN_R_OM_R                      (0x1 << 4)
+#define RT5639_M_IN_R_OM_R_SFT          4
+#define RT5639_M_RM_R_OM_R                      (0x1 << 3)
+#define RT5639_M_RM_R_OM_R_SFT          3
+#define RT5639_M_DAC_L2_OM_R                    (0x1 << 2)
+#define RT5639_M_DAC_L2_OM_R_SFT                2
+#define RT5639_M_DAC_R2_OM_R                    (0x1 << 1)
+#define RT5639_M_DAC_R2_OM_R_SFT                1
+#define RT5639_M_DAC_R1_OM_R                    (0x1)
+#define RT5639_M_DAC_R1_OM_R_SFT                0
+
+/* LOUT Mixer Control (0x53) */
+#define RT5639_M_DAC_L1_LM                      (0x1 << 15)
+#define RT5639_M_DAC_L1_LM_SFT          15
+#define RT5639_M_DAC_R1_LM                      (0x1 << 14)
+#define RT5639_M_DAC_R1_LM_SFT          14
+#define RT5639_M_OV_L_LM                        (0x1 << 13)
+#define RT5639_M_OV_L_LM_SFT                    13
+#define RT5639_M_OV_R_LM                        (0x1 << 12)
+#define RT5639_M_OV_R_LM_SFT                    12
+#define RT5639_G_LOUTMIX_MASK                   (0x1 << 11)
+#define RT5639_G_LOUTMIX_SFT                    11
+
+/* Power Management for Digital 1 (0x61) */
+#define RT5639_PWR_I2S1                         (0x1 << 15)
+#define RT5639_PWR_I2S1_BIT                     15
+#define RT5639_PWR_I2S2                         (0x1 << 14)
+#define RT5639_PWR_I2S2_BIT                     14
+#define RT5639_PWR_I2S3                         (0x1 << 13)
+#define RT5639_PWR_I2S3_BIT                     13
+#define RT5639_PWR_DAC_L1                       (0x1 << 12)
+#define RT5639_PWR_DAC_L1_BIT                   12
+#define RT5639_PWR_DAC_R1                       (0x1 << 11)
+#define RT5639_PWR_DAC_R1_BIT                   11
+#define RT5639_PWR_DAC_L2                       (0x1 << 7)
+#define RT5639_PWR_DAC_L2_BIT                   7
+#define RT5639_PWR_DAC_R2                       (0x1 << 6)
+#define RT5639_PWR_DAC_R2_BIT                   6
+#define RT5639_PWR_ADC_L                        (0x1 << 2)
+#define RT5639_PWR_ADC_L_BIT                    2
+#define RT5639_PWR_ADC_R                        (0x1 << 1)
+#define RT5639_PWR_ADC_R_BIT                    1
+#define RT5639_PWR_CLS_D                        (0x1)
+#define RT5639_PWR_CLS_D_BIT                    0
+
+/* Power Management for Digital 2 (0x62) */
+#define RT5639_PWR_ADC_SF                       (0x1 << 15)
+#define RT5639_PWR_ADC_SF_BIT                   15
+#define RT5639_PWR_ADC_MF_L                     (0x1 << 14)
+#define RT5639_PWR_ADC_MF_L_BIT         14
+#define RT5639_PWR_ADC_MF_R                     (0x1 << 13)
+#define RT5639_PWR_ADC_MF_R_BIT         13
+#define RT5639_PWR_I2S_DSP                      (0x1 << 12)
+#define RT5639_PWR_I2S_DSP_BIT                  12
+
+/* Power Management for Analog 1 (0x63) */
+#define RT5639_PWR_VREF1                        (0x1 << 15)
+#define RT5639_PWR_VREF1_BIT                    15
+#define RT5639_PWR_FV1                          (0x1 << 14)
+#define RT5639_PWR_FV1_BIT                      14
+#define RT5639_PWR_MB                           (0x1 << 13)
+#define RT5639_PWR_MB_BIT                       13
+#define RT5639_PWR_LM                           (0x1 << 12)
+#define RT5639_PWR_LM_BIT                       12
+#define RT5639_PWR_BG                           (0x1 << 11)
+#define RT5639_PWR_BG_BIT                       11
+#define RT5639_PWR_MM                           (0x1 << 10)
+#define RT5639_PWR_MM_BIT                       10
+#define RT5639_PWR_MA                           (0x1 << 8)
+#define RT5639_PWR_MA_BIT                       8
+#define RT5639_PWR_HP_L                 (0x1 << 7)
+#define RT5639_PWR_HP_L_BIT                     7
+#define RT5639_PWR_HP_R                 (0x1 << 6)
+#define RT5639_PWR_HP_R_BIT                     6
+#define RT5639_PWR_HA                           (0x1 << 5)
+#define RT5639_PWR_HA_BIT                       5
+#define RT5639_PWR_VREF2                        (0x1 << 4)
+#define RT5639_PWR_VREF2_BIT                    4
+#define RT5639_PWR_FV2                          (0x1 << 3)
+#define RT5639_PWR_FV2_BIT                      3
+#define RT5639_PWR_LDO2                 (0x1 << 2)
+#define RT5639_PWR_LDO2_BIT                     2
+
+/* Power Management for Analog 2 (0x64) */
+#define RT5639_PWR_BST1                 (0x1 << 15)
+#define RT5639_PWR_BST1_BIT                     15
+#define RT5639_PWR_BST2                 (0x1 << 14)
+#define RT5639_PWR_BST2_BIT                     14
+#define RT5639_PWR_BST3                 (0x1 << 13)
+#define RT5639_PWR_BST3_BIT                     13
+#define RT5639_PWR_BST4                 (0x1 << 12)
+#define RT5639_PWR_BST4_BIT                     12
+#define RT5639_PWR_MB1                          (0x1 << 11)
+#define RT5639_PWR_MB1_BIT                      11
+#define RT5639_PWR_MB2                          (0x1 << 10)
+#define RT5639_PWR_MB2_BIT                      10
+#define RT5639_PWR_PLL                          (0x1 << 9)
+#define RT5639_PWR_PLL_BIT                      9
+
+/* Power Management for Mixer (0x65) */
+#define RT5639_PWR_OM_L                 (0x1 << 15)
+#define RT5639_PWR_OM_L_BIT                     15
+#define RT5639_PWR_OM_R                 (0x1 << 14)
+#define RT5639_PWR_OM_R_BIT                     14
+#define RT5639_PWR_SM_L                 (0x1 << 13)
+#define RT5639_PWR_SM_L_BIT                     13
+#define RT5639_PWR_SM_R                 (0x1 << 12)
+#define RT5639_PWR_SM_R_BIT                     12
+#define RT5639_PWR_RM_L                 (0x1 << 11)
+#define RT5639_PWR_RM_L_BIT                     11
+#define RT5639_PWR_RM_R                 (0x1 << 10)
+#define RT5639_PWR_RM_R_BIT                     10
+
+/* Power Management for Volume (0x66) */
+#define RT5639_PWR_SV_L                 (0x1 << 15)
+#define RT5639_PWR_SV_L_BIT                     15
+#define RT5639_PWR_SV_R                 (0x1 << 14)
+#define RT5639_PWR_SV_R_BIT                     14
+#define RT5639_PWR_OV_L                 (0x1 << 13)
+#define RT5639_PWR_OV_L_BIT                     13
+#define RT5639_PWR_OV_R                 (0x1 << 12)
+#define RT5639_PWR_OV_R_BIT                     12
+#define RT5639_PWR_HV_L                 (0x1 << 11)
+#define RT5639_PWR_HV_L_BIT                     11
+#define RT5639_PWR_HV_R                 (0x1 << 10)
+#define RT5639_PWR_HV_R_BIT                     10
+#define RT5639_PWR_IN_L                         (0x1 << 9)
+#define RT5639_PWR_IN_L_BIT                     9
+#define RT5639_PWR_IN_R                 (0x1 << 8)
+#define RT5639_PWR_IN_R_BIT                     8
+
+/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
+#define RT5639_I2S_MS_MASK                      (0x1 << 15)
+#define RT5639_I2S_MS_SFT                       15
+#define RT5639_I2S_MS_M                 (0x0 << 15)
+#define RT5639_I2S_MS_S                         (0x1 << 15)
+#define RT5639_I2S_IF_MASK                      (0x7 << 12)
+#define RT5639_I2S_IF_SFT                       12
+#define RT5639_I2S_O_CP_MASK                    (0x3 << 10)
+#define RT5639_I2S_O_CP_SFT                     10
+#define RT5639_I2S_O_CP_OFF                     (0x0 << 10)
+#define RT5639_I2S_O_CP_U_LAW                   (0x1 << 10)
+#define RT5639_I2S_O_CP_A_LAW                   (0x2 << 10)
+#define RT5639_I2S_I_CP_MASK                    (0x3 << 8)
+#define RT5639_I2S_I_CP_SFT                     8
+#define RT5639_I2S_I_CP_OFF                     (0x0 << 8)
+#define RT5639_I2S_I_CP_U_LAW                   (0x1 << 8)
+#define RT5639_I2S_I_CP_A_LAW                   (0x2 << 8)
+#define RT5639_I2S_BP_MASK                      (0x1 << 7)
+#define RT5639_I2S_BP_SFT                       7
+#define RT5639_I2S_BP_NOR                       (0x0 << 7)
+#define RT5639_I2S_BP_INV                       (0x1 << 7)
+#define RT5639_I2S_DL_MASK                      (0x3 << 2)
+#define RT5639_I2S_DL_SFT                       2
+#define RT5639_I2S_DL_16                        (0x0 << 2)
+#define RT5639_I2S_DL_20                        (0x1 << 2)
+#define RT5639_I2S_DL_24                        (0x2 << 2)
+#define RT5639_I2S_DL_8                         (0x3 << 2)
+#define RT5639_I2S_DF_MASK                      (0x3)
+#define RT5639_I2S_DF_SFT                       0
+#define RT5639_I2S_DF_I2S                       (0x0)
+#define RT5639_I2S_DF_LEFT                      (0x1)
+#define RT5639_I2S_DF_PCM_A                     (0x2)
+#define RT5639_I2S_DF_PCM_B                     (0x3)
+
+/* I2S2 Audio Serial Data Port Control (0x71) */
+#define RT5639_I2S2_SDI_MASK                    (0x1 << 6)
+#define RT5639_I2S2_SDI_SFT                     6
+#define RT5639_I2S2_SDI_I2S1                    (0x0 << 6)
+#define RT5639_I2S2_SDI_I2S2                    (0x1 << 6)
+
+/* ADC/DAC Clock Control 1 (0x73) */
+#define RT5639_I2S_BCLK_MS1_MASK                (0x1 << 15)
+#define RT5639_I2S_BCLK_MS1_SFT         15
+#define RT5639_I2S_BCLK_MS1_32                  (0x0 << 15)
+#define RT5639_I2S_BCLK_MS1_64                  (0x1 << 15)
+#define RT5639_I2S_PD1_MASK                     (0x7 << 12)
+#define RT5639_I2S_PD1_SFT                      12
+#define RT5639_I2S_PD1_1                        (0x0 << 12)
+#define RT5639_I2S_PD1_2                        (0x1 << 12)
+#define RT5639_I2S_PD1_3                        (0x2 << 12)
+#define RT5639_I2S_PD1_4                        (0x3 << 12)
+#define RT5639_I2S_PD1_6                        (0x4 << 12)
+#define RT5639_I2S_PD1_8                        (0x5 << 12)
+#define RT5639_I2S_PD1_12                       (0x6 << 12)
+#define RT5639_I2S_PD1_16                       (0x7 << 12)
+#define RT5639_I2S_BCLK_MS2_MASK                (0x1 << 11)
+#define RT5639_I2S_BCLK_MS2_SFT         11
+#define RT5639_I2S_BCLK_MS2_32                  (0x0 << 11)
+#define RT5639_I2S_BCLK_MS2_64                  (0x1 << 11)
+#define RT5639_I2S_PD2_MASK                     (0x7 << 8)
+#define RT5639_I2S_PD2_SFT                      8
+#define RT5639_I2S_PD2_1                        (0x0 << 8)
+#define RT5639_I2S_PD2_2                        (0x1 << 8)
+#define RT5639_I2S_PD2_3                        (0x2 << 8)
+#define RT5639_I2S_PD2_4                        (0x3 << 8)
+#define RT5639_I2S_PD2_6                        (0x4 << 8)
+#define RT5639_I2S_PD2_8                        (0x5 << 8)
+#define RT5639_I2S_PD2_12                       (0x6 << 8)
+#define RT5639_I2S_PD2_16                       (0x7 << 8)
+#define RT5639_I2S_BCLK_MS3_MASK                (0x1 << 7)
+#define RT5639_I2S_BCLK_MS3_SFT         7
+#define RT5639_I2S_BCLK_MS3_32                  (0x0 << 7)
+#define RT5639_I2S_BCLK_MS3_64                  (0x1 << 7)
+#define RT5639_I2S_PD3_MASK                     (0x7 << 4)
+#define RT5639_I2S_PD3_SFT                      4
+#define RT5639_I2S_PD3_1                        (0x0 << 4)
+#define RT5639_I2S_PD3_2                        (0x1 << 4)
+#define RT5639_I2S_PD3_3                        (0x2 << 4)
+#define RT5639_I2S_PD3_4                        (0x3 << 4)
+#define RT5639_I2S_PD3_6                        (0x4 << 4)
+#define RT5639_I2S_PD3_8                        (0x5 << 4)
+#define RT5639_I2S_PD3_12                       (0x6 << 4)
+#define RT5639_I2S_PD3_16                       (0x7 << 4)
+#define RT5639_DAC_OSR_MASK                     (0x3 << 2)
+#define RT5639_DAC_OSR_SFT                      2
+#define RT5639_DAC_OSR_128                      (0x0 << 2)
+#define RT5639_DAC_OSR_64                       (0x1 << 2)
+#define RT5639_DAC_OSR_32                       (0x2 << 2)
+#define RT5639_DAC_OSR_16                       (0x3 << 2)
+#define RT5639_ADC_OSR_MASK                     (0x3)
+#define RT5639_ADC_OSR_SFT                      0
+#define RT5639_ADC_OSR_128                      (0x0)
+#define RT5639_ADC_OSR_64                       (0x1)
+#define RT5639_ADC_OSR_32                       (0x2)
+#define RT5639_ADC_OSR_16                       (0x3)
+
+/* ADC/DAC Clock Control 2 (0x74) */
+#define RT5639_DAC_L_OSR_MASK                   (0x3 << 14)
+#define RT5639_DAC_L_OSR_SFT                    14
+#define RT5639_DAC_L_OSR_128                    (0x0 << 14)
+#define RT5639_DAC_L_OSR_64                     (0x1 << 14)
+#define RT5639_DAC_L_OSR_32                     (0x2 << 14)
+#define RT5639_DAC_L_OSR_16                     (0x3 << 14)
+#define RT5639_ADC_R_OSR_MASK                   (0x3 << 12)
+#define RT5639_ADC_R_OSR_SFT                    12
+#define RT5639_ADC_R_OSR_128                    (0x0 << 12)
+#define RT5639_ADC_R_OSR_64                     (0x1 << 12)
+#define RT5639_ADC_R_OSR_32                     (0x2 << 12)
+#define RT5639_ADC_R_OSR_16                     (0x3 << 12)
+#define RT5639_DAHPF_EN                 (0x1 << 11)
+#define RT5639_DAHPF_EN_SFT                     11
+#define RT5639_ADHPF_EN                 (0x1 << 10)
+#define RT5639_ADHPF_EN_SFT                     10
+
+/* Digital Microphone Control (0x75) */
+#define RT5639_DMIC_1_EN_MASK                   (0x1 << 15)
+#define RT5639_DMIC_1_EN_SFT                    15
+#define RT5639_DMIC_1_DIS                       (0x0 << 15)
+#define RT5639_DMIC_1_EN                        (0x1 << 15)
+#define RT5639_DMIC_2_EN_MASK                   (0x1 << 14)
+#define RT5639_DMIC_2_EN_SFT                    14
+#define RT5639_DMIC_2_DIS                       (0x0 << 14)
+#define RT5639_DMIC_2_EN                        (0x1 << 14)
+#define RT5639_DMIC_1L_LH_MASK          (0x1 << 13)
+#define RT5639_DMIC_1L_LH_SFT                   13
+#define RT5639_DMIC_1L_LH_FALLING               (0x0 << 13)
+#define RT5639_DMIC_1L_LH_RISING                (0x1 << 13)
+#define RT5639_DMIC_1R_LH_MASK          (0x1 << 12)
+#define RT5639_DMIC_1R_LH_SFT                   12
+#define RT5639_DMIC_1R_LH_FALLING               (0x0 << 12)
+#define RT5639_DMIC_1R_LH_RISING                (0x1 << 12)
+#define RT5639_DMIC_1_DP_MASK                   (0x1 << 11)
+#define RT5639_DMIC_1_DP_SFT                    11
+#define RT5639_DMIC_1_DP_GPIO3                  (0x0 << 11)
+#define RT5639_DMIC_1_DP_IN1P                   (0x1 << 11)
+#define RT5639_DMIC_2_DP_MASK                   (0x1 << 10)
+#define RT5639_DMIC_2_DP_SFT                    10
+#define RT5639_DMIC_2_DP_GPIO4                  (0x0 << 10)
+#define RT5639_DMIC_2_DP_IN1N                   (0x1 << 10)
+#define RT5639_DMIC_2L_LH_MASK          (0x1 << 9)
+#define RT5639_DMIC_2L_LH_SFT                   9
+#define RT5639_DMIC_2L_LH_FALLING               (0x0 << 9)
+#define RT5639_DMIC_2L_LH_RISING                (0x1 << 9)
+#define RT5639_DMIC_2R_LH_MASK          (0x1 << 8)
+#define RT5639_DMIC_2R_LH_SFT                   8
+#define RT5639_DMIC_2R_LH_FALLING               (0x0 << 8)
+#define RT5639_DMIC_2R_LH_RISING                (0x1 << 8)
+#define RT5639_DMIC_CLK_MASK                    (0x7 << 5)
+#define RT5639_DMIC_CLK_SFT                     5
+
+/* Global Clock Control (0x80) */
+#define RT5639_SCLK_SRC_MASK                    (0x3 << 14)
+#define RT5639_SCLK_SRC_SFT                     14
+#define RT5639_SCLK_SRC_MCLK                    (0x0 << 14)
+#define RT5639_SCLK_SRC_PLL1                    (0x1 << 14)
+#define RT5639_SCLK_SRC_RCCLK                   (0x2 << 14) /* 15MHz */
+#define RT5639_PLL1_SRC_MASK                    (0x3 << 12)
+#define RT5639_PLL1_SRC_SFT                     12
+#define RT5639_PLL1_SRC_MCLK                    (0x0 << 12)
+#define RT5639_PLL1_SRC_BCLK1                   (0x1 << 12)
+#define RT5639_PLL1_SRC_BCLK2                   (0x2 << 12)
+#define RT5639_PLL1_SRC_BCLK3                   (0x3 << 12)
+#define RT5639_PLL1_PD_MASK                     (0x1 << 3)
+#define RT5639_PLL1_PD_SFT                      3
+#define RT5639_PLL1_PD_1                        (0x0 << 3)
+#define RT5639_PLL1_PD_2                        (0x1 << 3)
+
+#define RT5639_PLL_INP_MAX                      40000000
+#define RT5639_PLL_INP_MIN                      256000
+/* PLL M/N/K Code Control 1 (0x81) */
+#define RT5639_PLL_N_MAX                        0x1ff
+#define RT5639_PLL_N_MASK                       (RT5639_PLL_N_MAX << 7)
+#define RT5639_PLL_N_SFT                        7
+#define RT5639_PLL_K_MAX                        0x1f
+#define RT5639_PLL_K_MASK                       (RT5639_PLL_K_MAX)
+#define RT5639_PLL_K_SFT                        0
+
+/* PLL M/N/K Code Control 2 (0x82) */
+#define RT5639_PLL_M_MAX                        0xf
+#define RT5639_PLL_M_MASK                       (RT5639_PLL_M_MAX << 12)
+#define RT5639_PLL_M_SFT                        12
+#define RT5639_PLL_M_BP                         (0x1 << 11)
+#define RT5639_PLL_M_BP_SFT                     11
+
+/* ASRC Control 1 (0x83) */
+#define RT5639_STO_T_MASK                       (0x1 << 15)
+#define RT5639_STO_T_SFT                        15
+#define RT5639_STO_T_SCLK                       (0x0 << 15)
+#define RT5639_STO_T_LRCK1                      (0x1 << 15)
+#define RT5639_M1_T_MASK                        (0x1 << 14)
+#define RT5639_M1_T_SFT                         14
+#define RT5639_M1_T_I2S2                        (0x0 << 14)
+#define RT5639_M1_T_I2S2_D3                     (0x1 << 14)
+#define RT5639_I2S2_F_MASK                      (0x1 << 12)
+#define RT5639_I2S2_F_SFT                       12
+#define RT5639_I2S2_F_I2S2_D2                   (0x0 << 12)
+#define RT5639_I2S2_F_I2S1_TCLK                 (0x1 << 12)
+#define RT5639_DMIC_1_M_MASK                    (0x1 << 9)
+#define RT5639_DMIC_1_M_SFT                     9
+#define RT5639_DMIC_1_M_NOR                     (0x0 << 9)
+#define RT5639_DMIC_1_M_ASYN                    (0x1 << 9)
+#define RT5639_DMIC_2_M_MASK                    (0x1 << 8)
+#define RT5639_DMIC_2_M_SFT                     8
+#define RT5639_DMIC_2_M_NOR                     (0x0 << 8)
+#define RT5639_DMIC_2_M_ASYN                    (0x1 << 8)
+
+/* ASRC Control 2 (0x84) */
+#define RT5639_MDA_L_M_MASK                     (0x1 << 15)
+#define RT5639_MDA_L_M_SFT                      15
+#define RT5639_MDA_L_M_NOR                      (0x0 << 15)
+#define RT5639_MDA_L_M_ASYN                     (0x1 << 15)
+#define RT5639_MDA_R_M_MASK                     (0x1 << 14)
+#define RT5639_MDA_R_M_SFT                      14
+#define RT5639_MDA_R_M_NOR                      (0x0 << 14)
+#define RT5639_MDA_R_M_ASYN                     (0x1 << 14)
+#define RT5639_MAD_L_M_MASK                     (0x1 << 13)
+#define RT5639_MAD_L_M_SFT                      13
+#define RT5639_MAD_L_M_NOR                      (0x0 << 13)
+#define RT5639_MAD_L_M_ASYN                     (0x1 << 13)
+#define RT5639_MAD_R_M_MASK                     (0x1 << 12)
+#define RT5639_MAD_R_M_SFT                      12
+#define RT5639_MAD_R_M_NOR                      (0x0 << 12)
+#define RT5639_MAD_R_M_ASYN                     (0x1 << 12)
+#define RT5639_ADC_M_MASK                       (0x1 << 11)
+#define RT5639_ADC_M_SFT                        11
+#define RT5639_ADC_M_NOR                        (0x0 << 11)
+#define RT5639_ADC_M_ASYN                       (0x1 << 11)
+#define RT5639_STO_DAC_M_MASK                   (0x1 << 5)
+#define RT5639_STO_DAC_M_SFT                    5
+#define RT5639_STO_DAC_M_NOR                    (0x0 << 5)
+#define RT5639_STO_DAC_M_ASYN                   (0x1 << 5)
+#define RT5639_I2S1_R_D_MASK                    (0x1 << 4)
+#define RT5639_I2S1_R_D_SFT                     4
+#define RT5639_I2S1_R_D_DIS                     (0x0 << 4)
+#define RT5639_I2S1_R_D_EN                      (0x1 << 4)
+#define RT5639_I2S2_R_D_MASK                    (0x1 << 3)
+#define RT5639_I2S2_R_D_SFT                     3
+#define RT5639_I2S2_R_D_DIS                     (0x0 << 3)
+#define RT5639_I2S2_R_D_EN                      (0x1 << 3)
+#define RT5639_PRE_SCLK_MASK                    (0x3)
+#define RT5639_PRE_SCLK_SFT                     0
+#define RT5639_PRE_SCLK_512                     (0x0)
+#define RT5639_PRE_SCLK_1024                    (0x1)
+#define RT5639_PRE_SCLK_2048                    (0x2)
+
+/* ASRC Control 3 (0x85) */
+#define RT5639_I2S1_RATE_MASK                   (0xf << 12)
+#define RT5639_I2S1_RATE_SFT                    12
+#define RT5639_I2S2_RATE_MASK                   (0xf << 8)
+#define RT5639_I2S2_RATE_SFT                    8
+
+/* ASRC Control 4 (0x89) */
+#define RT5639_I2S1_PD_MASK                     (0x7 << 12)
+#define RT5639_I2S1_PD_SFT                      12
+#define RT5639_I2S2_PD_MASK                     (0x7 << 8)
+#define RT5639_I2S2_PD_SFT                      8
+
+/* HPOUT Over Current Detection (0x8b) */
+#define RT5639_HP_OVCD_MASK                     (0x1 << 10)
+#define RT5639_HP_OVCD_SFT                      10
+#define RT5639_HP_OVCD_DIS                      (0x0 << 10)
+#define RT5639_HP_OVCD_EN                       (0x1 << 10)
+#define RT5639_HP_OC_TH_MASK                    (0x3 << 8)
+#define RT5639_HP_OC_TH_SFT                     8
+#define RT5639_HP_OC_TH_90                      (0x0 << 8)
+#define RT5639_HP_OC_TH_105                     (0x1 << 8)
+#define RT5639_HP_OC_TH_120                     (0x2 << 8)
+#define RT5639_HP_OC_TH_135                     (0x3 << 8)
+
+/* Class D Over Current Control (0x8c) */
+#define RT5639_CLSD_OC_MASK                     (0x1 << 9)
+#define RT5639_CLSD_OC_SFT                      9
+#define RT5639_CLSD_OC_PU                       (0x0 << 9)
+#define RT5639_CLSD_OC_PD                       (0x1 << 9)
+#define RT5639_AUTO_PD_MASK                     (0x1 << 8)
+#define RT5639_AUTO_PD_SFT                      8
+#define RT5639_AUTO_PD_DIS                      (0x0 << 8)
+#define RT5639_AUTO_PD_EN                       (0x1 << 8)
+#define RT5639_CLSD_OC_TH_MASK          (0x3f)
+#define RT5639_CLSD_OC_TH_SFT                   0
+
+/* Class D Output Control (0x8d) */
+#define RT5639_CLSD_RATIO_MASK          (0xf << 12)
+#define RT5639_CLSD_RATIO_SFT                   12
+#define RT5639_CLSD_OM_MASK                     (0x1 << 11)
+#define RT5639_CLSD_OM_SFT                      11
+#define RT5639_CLSD_OM_MONO                     (0x0 << 11)
+#define RT5639_CLSD_OM_STO                      (0x1 << 11)
+#define RT5639_CLSD_SCH_MASK                    (0x1 << 10)
+#define RT5639_CLSD_SCH_SFT                     10
+#define RT5639_CLSD_SCH_L                       (0x0 << 10)
+#define RT5639_CLSD_SCH_S                       (0x1 << 10)
+
+/* Depop Mode Control 1 (0x8e) */
+#define RT5639_SMT_TRIG_MASK                    (0x1 << 15)
+#define RT5639_SMT_TRIG_SFT                     15
+#define RT5639_SMT_TRIG_DIS                     (0x0 << 15)
+#define RT5639_SMT_TRIG_EN                      (0x1 << 15)
+#define RT5639_HP_L_SMT_MASK                    (0x1 << 9)
+#define RT5639_HP_L_SMT_SFT                     9
+#define RT5639_HP_L_SMT_DIS                     (0x0 << 9)
+#define RT5639_HP_L_SMT_EN                      (0x1 << 9)
+#define RT5639_HP_R_SMT_MASK                    (0x1 << 8)
+#define RT5639_HP_R_SMT_SFT                     8
+#define RT5639_HP_R_SMT_DIS                     (0x0 << 8)
+#define RT5639_HP_R_SMT_EN                      (0x1 << 8)
+#define RT5639_HP_CD_PD_MASK                    (0x1 << 7)
+#define RT5639_HP_CD_PD_SFT                     7
+#define RT5639_HP_CD_PD_DIS                     (0x0 << 7)
+#define RT5639_HP_CD_PD_EN                      (0x1 << 7)
+#define RT5639_RSTN_MASK                        (0x1 << 6)
+#define RT5639_RSTN_SFT                         6
+#define RT5639_RSTN_DIS                         (0x0 << 6)
+#define RT5639_RSTN_EN                          (0x1 << 6)
+#define RT5639_RSTP_MASK                        (0x1 << 5)
+#define RT5639_RSTP_SFT                         5
+#define RT5639_RSTP_DIS                         (0x0 << 5)
+#define RT5639_RSTP_EN                          (0x1 << 5)
+#define RT5639_HP_CO_MASK                       (0x1 << 4)
+#define RT5639_HP_CO_SFT                        4
+#define RT5639_HP_CO_DIS                        (0x0 << 4)
+#define RT5639_HP_CO_EN                 (0x1 << 4)
+#define RT5639_HP_CP_MASK                       (0x1 << 3)
+#define RT5639_HP_CP_SFT                        3
+#define RT5639_HP_CP_PD                 (0x0 << 3)
+#define RT5639_HP_CP_PU                 (0x1 << 3)
+#define RT5639_HP_SG_MASK                       (0x1 << 2)
+#define RT5639_HP_SG_SFT                        2
+#define RT5639_HP_SG_DIS                        (0x0 << 2)
+#define RT5639_HP_SG_EN                 (0x1 << 2)
+#define RT5639_HP_DP_MASK                       (0x1 << 1)
+#define RT5639_HP_DP_SFT                        1
+#define RT5639_HP_DP_PD                 (0x0 << 1)
+#define RT5639_HP_DP_PU                 (0x1 << 1)
+#define RT5639_HP_CB_MASK                       (0x1)
+#define RT5639_HP_CB_SFT                        0
+#define RT5639_HP_CB_PD                 (0x0)
+#define RT5639_HP_CB_PU                 (0x1)
+
+/* Depop Mode Control 2 (0x8f) */
+#define RT5639_DEPOP_MASK                       (0x1 << 13)
+#define RT5639_DEPOP_SFT                        13
+#define RT5639_DEPOP_AUTO                       (0x0 << 13)
+#define RT5639_DEPOP_MAN                        (0x1 << 13)
+#define RT5639_RAMP_MASK                        (0x1 << 12)
+#define RT5639_RAMP_SFT                 12
+#define RT5639_RAMP_DIS                         (0x0 << 12)
+#define RT5639_RAMP_EN                          (0x1 << 12)
+#define RT5639_BPS_MASK                 (0x1 << 11)
+#define RT5639_BPS_SFT                          11
+#define RT5639_BPS_DIS                          (0x0 << 11)
+#define RT5639_BPS_EN                           (0x1 << 11)
+#define RT5639_FAST_UPDN_MASK                   (0x1 << 10)
+#define RT5639_FAST_UPDN_SFT                    10
+#define RT5639_FAST_UPDN_DIS                    (0x0 << 10)
+#define RT5639_FAST_UPDN_EN                     (0x1 << 10)
+#define RT5639_MRES_MASK                        (0x3 << 8)
+#define RT5639_MRES_SFT                         8
+#define RT5639_MRES_15MO                        (0x0 << 8)
+#define RT5639_MRES_25MO                        (0x1 << 8)
+#define RT5639_MRES_35MO                        (0x2 << 8)
+#define RT5639_MRES_45MO                        (0x3 << 8)
+#define RT5639_VLO_MASK                 (0x1 << 7)
+#define RT5639_VLO_SFT                          7
+#define RT5639_VLO_3V                           (0x0 << 7)
+#define RT5639_VLO_32V                          (0x1 << 7)
+#define RT5639_DIG_DP_MASK                      (0x1 << 6)
+#define RT5639_DIG_DP_SFT                       6
+#define RT5639_DIG_DP_DIS                       (0x0 << 6)
+#define RT5639_DIG_DP_EN                        (0x1 << 6)
+#define RT5639_DP_TH_MASK                       (0x3 << 4)
+#define RT5639_DP_TH_SFT                        4
+
+/* Depop Mode Control 3 (0x90) */
+#define RT5639_CP_SYS_MASK                      (0x7 << 12)
+#define RT5639_CP_SYS_SFT                       12
+#define RT5639_CP_FQ1_MASK                      (0x7 << 8)
+#define RT5639_CP_FQ1_SFT                       8
+#define RT5639_CP_FQ2_MASK                      (0x7 << 4)
+#define RT5639_CP_FQ2_SFT                       4
+#define RT5639_CP_FQ3_MASK                      (0x7)
+#define RT5639_CP_FQ3_SFT                       0
+
+/* HPOUT charge pump (0x91) */
+#define RT5639_OSW_L_MASK                       (0x1 << 11)
+#define RT5639_OSW_L_SFT                        11
+#define RT5639_OSW_L_DIS                        (0x0 << 11)
+#define RT5639_OSW_L_EN                 (0x1 << 11)
+#define RT5639_OSW_R_MASK                       (0x1 << 10)
+#define RT5639_OSW_R_SFT                        10
+#define RT5639_OSW_R_DIS                        (0x0 << 10)
+#define RT5639_OSW_R_EN                 (0x1 << 10)
+#define RT5639_PM_HP_MASK                       (0x3 << 8)
+#define RT5639_PM_HP_SFT                        8
+#define RT5639_PM_HP_LV                 (0x0 << 8)
+#define RT5639_PM_HP_MV                 (0x1 << 8)
+#define RT5639_PM_HP_HV                 (0x2 << 8)
+#define RT5639_IB_HP_MASK                       (0x3 << 6)
+#define RT5639_IB_HP_SFT                        6
+#define RT5639_IB_HP_125IL                      (0x0 << 6)
+#define RT5639_IB_HP_25IL                       (0x1 << 6)
+#define RT5639_IB_HP_5IL                        (0x2 << 6)
+#define RT5639_IB_HP_1IL                        (0x3 << 6)
+
+/* PV detection and SPK gain control (0x92) */
+#define RT5639_PVDD_DET_MASK                    (0x1 << 15)
+#define RT5639_PVDD_DET_SFT                     15
+#define RT5639_PVDD_DET_DIS                     (0x0 << 15)
+#define RT5639_PVDD_DET_EN                      (0x1 << 15)
+#define RT5639_SPK_AG_MASK                      (0x1 << 14)
+#define RT5639_SPK_AG_SFT                       14
+#define RT5639_SPK_AG_DIS                       (0x0 << 14)
+#define RT5639_SPK_AG_EN                        (0x1 << 14)
+
+/* Micbias Control (0x93) */
+#define RT5639_MIC1_BS_MASK                     (0x1 << 15)
+#define RT5639_MIC1_BS_SFT                      15
+#define RT5639_MIC1_BS_9AV                      (0x0 << 15)
+#define RT5639_MIC1_BS_75AV                     (0x1 << 15)
+#define RT5639_MIC2_BS_MASK                     (0x1 << 14)
+#define RT5639_MIC2_BS_SFT                      14
+#define RT5639_MIC2_BS_9AV                      (0x0 << 14)
+#define RT5639_MIC2_BS_75AV                     (0x1 << 14)
+#define RT5639_MIC1_CLK_MASK                    (0x1 << 13)
+#define RT5639_MIC1_CLK_SFT                     13
+#define RT5639_MIC1_CLK_DIS                     (0x0 << 13)
+#define RT5639_MIC1_CLK_EN                      (0x1 << 13)
+#define RT5639_MIC2_CLK_MASK                    (0x1 << 12)
+#define RT5639_MIC2_CLK_SFT                     12
+#define RT5639_MIC2_CLK_DIS                     (0x0 << 12)
+#define RT5639_MIC2_CLK_EN                      (0x1 << 12)
+#define RT5639_MIC1_OVCD_MASK                   (0x1 << 11)
+#define RT5639_MIC1_OVCD_SFT                    11
+#define RT5639_MIC1_OVCD_DIS                    (0x0 << 11)
+#define RT5639_MIC1_OVCD_EN                     (0x1 << 11)
+#define RT5639_MIC1_OVTH_MASK                   (0x3 << 9)
+#define RT5639_MIC1_OVTH_SFT                    9
+#define RT5639_MIC1_OVTH_600UA          (0x0 << 9)
+#define RT5639_MIC1_OVTH_1500UA         (0x1 << 9)
+#define RT5639_MIC1_OVTH_2000UA         (0x2 << 9)
+#define RT5639_MIC2_OVCD_MASK                   (0x1 << 8)
+#define RT5639_MIC2_OVCD_SFT                    8
+#define RT5639_MIC2_OVCD_DIS                    (0x0 << 8)
+#define RT5639_MIC2_OVCD_EN                     (0x1 << 8)
+#define RT5639_MIC2_OVTH_MASK                   (0x3 << 6)
+#define RT5639_MIC2_OVTH_SFT                    6
+#define RT5639_MIC2_OVTH_600UA          (0x0 << 6)
+#define RT5639_MIC2_OVTH_1500UA         (0x1 << 6)
+#define RT5639_MIC2_OVTH_2000UA         (0x2 << 6)
+#define RT5639_PWR_MB_MASK                      (0x1 << 5)
+#define RT5639_PWR_MB_SFT                       5
+#define RT5639_PWR_MB_PD                        (0x0 << 5)
+#define RT5639_PWR_MB_PU                        (0x1 << 5)
+#define RT5639_PWR_CLK25M_MASK          (0x1 << 4)
+#define RT5639_PWR_CLK25M_SFT                   4
+#define RT5639_PWR_CLK25M_PD                    (0x0 << 4)
+#define RT5639_PWR_CLK25M_PU                    (0x1 << 4)
+
+/* EQ Control 1 (0xb0) */
+#define RT5639_EQ_SRC_MASK                      (0x1 << 15)
+#define RT5639_EQ_SRC_SFT                       15
+#define RT5639_EQ_SRC_DAC                       (0x0 << 15)
+#define RT5639_EQ_SRC_ADC                       (0x1 << 15)
+#define RT5639_EQ_UPD                           (0x1 << 14)
+#define RT5639_EQ_UPD_BIT                       14
+#define RT5639_EQ_CD_MASK                       (0x1 << 13)
+#define RT5639_EQ_CD_SFT                        13
+#define RT5639_EQ_CD_DIS                        (0x0 << 13)
+#define RT5639_EQ_CD_EN                 (0x1 << 13)
+#define RT5639_EQ_DITH_MASK                     (0x3 << 8)
+#define RT5639_EQ_DITH_SFT                      8
+#define RT5639_EQ_DITH_NOR                      (0x0 << 8)
+#define RT5639_EQ_DITH_LSB                      (0x1 << 8)
+#define RT5639_EQ_DITH_LSB_1                    (0x2 << 8)
+#define RT5639_EQ_DITH_LSB_2                    (0x3 << 8)
+
+/* EQ Control 2 (0xb1) */
+#define RT5639_EQ_HPF1_M_MASK                   (0x1 << 8)
+#define RT5639_EQ_HPF1_M_SFT                    8
+#define RT5639_EQ_HPF1_M_HI                     (0x0 << 8)
+#define RT5639_EQ_HPF1_M_1ST                    (0x1 << 8)
+#define RT5639_EQ_LPF1_M_MASK                   (0x1 << 7)
+#define RT5639_EQ_LPF1_M_SFT                    7
+#define RT5639_EQ_LPF1_M_LO                     (0x0 << 7)
+#define RT5639_EQ_LPF1_M_1ST                    (0x1 << 7)
+#define RT5639_EQ_HPF2_MASK                     (0x1 << 6)
+#define RT5639_EQ_HPF2_SFT                      6
+#define RT5639_EQ_HPF2_DIS                      (0x0 << 6)
+#define RT5639_EQ_HPF2_EN                       (0x1 << 6)
+#define RT5639_EQ_HPF1_MASK                     (0x1 << 5)
+#define RT5639_EQ_HPF1_SFT                      5
+#define RT5639_EQ_HPF1_DIS                      (0x0 << 5)
+#define RT5639_EQ_HPF1_EN                       (0x1 << 5)
+#define RT5639_EQ_BPF4_MASK                     (0x1 << 4)
+#define RT5639_EQ_BPF4_SFT                      4
+#define RT5639_EQ_BPF4_DIS                      (0x0 << 4)
+#define RT5639_EQ_BPF4_EN                       (0x1 << 4)
+#define RT5639_EQ_BPF3_MASK                     (0x1 << 3)
+#define RT5639_EQ_BPF3_SFT                      3
+#define RT5639_EQ_BPF3_DIS                      (0x0 << 3)
+#define RT5639_EQ_BPF3_EN                       (0x1 << 3)
+#define RT5639_EQ_BPF2_MASK                     (0x1 << 2)
+#define RT5639_EQ_BPF2_SFT                      2
+#define RT5639_EQ_BPF2_DIS                      (0x0 << 2)
+#define RT5639_EQ_BPF2_EN                       (0x1 << 2)
+#define RT5639_EQ_BPF1_MASK                     (0x1 << 1)
+#define RT5639_EQ_BPF1_SFT                      1
+#define RT5639_EQ_BPF1_DIS                      (0x0 << 1)
+#define RT5639_EQ_BPF1_EN                       (0x1 << 1)
+#define RT5639_EQ_LPF_MASK                      (0x1)
+#define RT5639_EQ_LPF_SFT                       0
+#define RT5639_EQ_LPF_DIS                       (0x0)
+#define RT5639_EQ_LPF_EN                        (0x1)
+
+/* Memory Test (0xb2) */
+#define RT5639_MT_MASK                          (0x1 << 15)
+#define RT5639_MT_SFT                           15
+#define RT5639_MT_DIS                           (0x0 << 15)
+#define RT5639_MT_EN                            (0x1 << 15)
+
+/* DRC/AGC Control 1 (0xb4) */
+#define RT5639_DRC_AGC_P_MASK                   (0x1 << 15)
+#define RT5639_DRC_AGC_P_SFT                    15
+#define RT5639_DRC_AGC_P_DAC                    (0x0 << 15)
+#define RT5639_DRC_AGC_P_ADC                    (0x1 << 15)
+#define RT5639_DRC_AGC_MASK                     (0x1 << 14)
+#define RT5639_DRC_AGC_SFT                      14
+#define RT5639_DRC_AGC_DIS                      (0x0 << 14)
+#define RT5639_DRC_AGC_EN                       (0x1 << 14)
+#define RT5639_DRC_AGC_UPD                      (0x1 << 13)
+#define RT5639_DRC_AGC_UPD_BIT          13
+#define RT5639_DRC_AGC_AR_MASK          (0x1f << 8)
+#define RT5639_DRC_AGC_AR_SFT                   8
+#define RT5639_DRC_AGC_R_MASK                   (0x7 << 5)
+#define RT5639_DRC_AGC_R_SFT                    5
+#define RT5639_DRC_AGC_R_48K                    (0x1 << 5)
+#define RT5639_DRC_AGC_R_96K                    (0x2 << 5)
+#define RT5639_DRC_AGC_R_192K                   (0x3 << 5)
+#define RT5639_DRC_AGC_R_441K                   (0x5 << 5)
+#define RT5639_DRC_AGC_R_882K                   (0x6 << 5)
+#define RT5639_DRC_AGC_R_1764K          (0x7 << 5)
+#define RT5639_DRC_AGC_RC_MASK          (0x1f)
+#define RT5639_DRC_AGC_RC_SFT                   0
+
+/* DRC/AGC Control 2 (0xb5) */
+#define RT5639_DRC_AGC_POB_MASK         (0x3f << 8)
+#define RT5639_DRC_AGC_POB_SFT          8
+#define RT5639_DRC_AGC_CP_MASK          (0x1 << 7)
+#define RT5639_DRC_AGC_CP_SFT                   7
+#define RT5639_DRC_AGC_CP_DIS                   (0x0 << 7)
+#define RT5639_DRC_AGC_CP_EN                    (0x1 << 7)
+#define RT5639_DRC_AGC_CPR_MASK         (0x3 << 5)
+#define RT5639_DRC_AGC_CPR_SFT          5
+#define RT5639_DRC_AGC_CPR_1_1          (0x0 << 5)
+#define RT5639_DRC_AGC_CPR_1_2          (0x1 << 5)
+#define RT5639_DRC_AGC_CPR_1_3          (0x2 << 5)
+#define RT5639_DRC_AGC_CPR_1_4          (0x3 << 5)
+#define RT5639_DRC_AGC_PRB_MASK         (0x1f)
+#define RT5639_DRC_AGC_PRB_SFT          0
+
+/* DRC/AGC Control 3 (0xb6) */
+#define RT5639_DRC_AGC_NGB_MASK         (0xf << 12)
+#define RT5639_DRC_AGC_NGB_SFT          12
+#define RT5639_DRC_AGC_TAR_MASK         (0x1f << 7)
+#define RT5639_DRC_AGC_TAR_SFT          7
+#define RT5639_DRC_AGC_NG_MASK          (0x1 << 6)
+#define RT5639_DRC_AGC_NG_SFT                   6
+#define RT5639_DRC_AGC_NG_DIS                   (0x0 << 6)
+#define RT5639_DRC_AGC_NG_EN                    (0x1 << 6)
+#define RT5639_DRC_AGC_NGH_MASK         (0x1 << 5)
+#define RT5639_DRC_AGC_NGH_SFT          5
+#define RT5639_DRC_AGC_NGH_DIS          (0x0 << 5)
+#define RT5639_DRC_AGC_NGH_EN                   (0x1 << 5)
+#define RT5639_DRC_AGC_NGT_MASK         (0x1f)
+#define RT5639_DRC_AGC_NGT_SFT          0
+
+/* ANC Control 1 (0xb8) */
+#define RT5639_ANC_M_MASK                       (0x1 << 15)
+#define RT5639_ANC_M_SFT                        15
+#define RT5639_ANC_M_NOR                        (0x0 << 15)
+#define RT5639_ANC_M_REV                        (0x1 << 15)
+#define RT5639_ANC_MASK                 (0x1 << 14)
+#define RT5639_ANC_SFT                          14
+#define RT5639_ANC_DIS                          (0x0 << 14)
+#define RT5639_ANC_EN                           (0x1 << 14)
+#define RT5639_ANC_MD_MASK                      (0x3 << 12)
+#define RT5639_ANC_MD_SFT                       12
+#define RT5639_ANC_MD_DIS                       (0x0 << 12)
+#define RT5639_ANC_MD_67MS                      (0x1 << 12)
+#define RT5639_ANC_MD_267MS                     (0x2 << 12)
+#define RT5639_ANC_MD_1067MS                    (0x3 << 12)
+#define RT5639_ANC_SN_MASK                      (0x1 << 11)
+#define RT5639_ANC_SN_SFT                       11
+#define RT5639_ANC_SN_DIS                       (0x0 << 11)
+#define RT5639_ANC_SN_EN                        (0x1 << 11)
+#define RT5639_ANC_CLK_MASK                     (0x1 << 10)
+#define RT5639_ANC_CLK_SFT                      10
+#define RT5639_ANC_CLK_ANC                      (0x0 << 10)
+#define RT5639_ANC_CLK_REG                      (0x1 << 10)
+#define RT5639_ANC_ZCD_MASK                     (0x3 << 8)
+#define RT5639_ANC_ZCD_SFT                      8
+#define RT5639_ANC_ZCD_DIS                      (0x0 << 8)
+#define RT5639_ANC_ZCD_T1                       (0x1 << 8)
+#define RT5639_ANC_ZCD_T2                       (0x2 << 8)
+#define RT5639_ANC_ZCD_WT                       (0x3 << 8)
+#define RT5639_ANC_CS_MASK                      (0x1 << 7)
+#define RT5639_ANC_CS_SFT                       7
+#define RT5639_ANC_CS_DIS                       (0x0 << 7)
+#define RT5639_ANC_CS_EN                        (0x1 << 7)
+#define RT5639_ANC_SW_MASK                      (0x1 << 6)
+#define RT5639_ANC_SW_SFT                       6
+#define RT5639_ANC_SW_NOR                       (0x0 << 6)
+#define RT5639_ANC_SW_AUTO                      (0x1 << 6)
+#define RT5639_ANC_CO_L_MASK                    (0x3f)
+#define RT5639_ANC_CO_L_SFT                     0
+
+/* ANC Control 2 (0xb6) */
+#define RT5639_ANC_FG_R_MASK                    (0xf << 12)
+#define RT5639_ANC_FG_R_SFT                     12
+#define RT5639_ANC_FG_L_MASK                    (0xf << 8)
+#define RT5639_ANC_FG_L_SFT                     8
+#define RT5639_ANC_CG_R_MASK                    (0xf << 4)
+#define RT5639_ANC_CG_R_SFT                     4
+#define RT5639_ANC_CG_L_MASK                    (0xf)
+#define RT5639_ANC_CG_L_SFT                     0
+
+/* ANC Control 3 (0xb6) */
+#define RT5639_ANC_CD_MASK                      (0x1 << 6)
+#define RT5639_ANC_CD_SFT                       6
+#define RT5639_ANC_CD_BOTH                      (0x0 << 6)
+#define RT5639_ANC_CD_IND                       (0x1 << 6)
+#define RT5639_ANC_CO_R_MASK                    (0x3f)
+#define RT5639_ANC_CO_R_SFT                     0
+
+/* Jack Detect Control (0xbb) */
+#define RT5639_JD_MASK                          (0x7 << 13)
+#define RT5639_JD_SFT                           13
+#define RT5639_JD_DIS                           (0x0 << 13)
+#define RT5639_JD_GPIO1                         (0x1 << 13)
+#define RT5639_JD_JD1_IN4P                      (0x2 << 13)
+#define RT5639_JD_JD2_IN4N                      (0x3 << 13)
+#define RT5639_JD_GPIO2                         (0x4 << 13)
+#define RT5639_JD_GPIO3                         (0x5 << 13)
+#define RT5639_JD_GPIO4                         (0x6 << 13)
+#define RT5639_JD_HP_MASK                       (0x1 << 11)
+#define RT5639_JD_HP_SFT                        11
+#define RT5639_JD_HP_DIS                        (0x0 << 11)
+#define RT5639_JD_HP_EN                         (0x1 << 11)
+#define RT5639_JD_HP_TRG_MASK                   (0x1 << 10)
+#define RT5639_JD_HP_TRG_SFT                    10
+#define RT5639_JD_HP_TRG_LO                     (0x0 << 10)
+#define RT5639_JD_HP_TRG_HI                     (0x1 << 10)
+#define RT5639_JD_SPL_MASK                      (0x1 << 9)
+#define RT5639_JD_SPL_SFT                       9
+#define RT5639_JD_SPL_DIS                       (0x0 << 9)
+#define RT5639_JD_SPL_EN                        (0x1 << 9)
+#define RT5639_JD_SPL_TRG_MASK                  (0x1 << 8)
+#define RT5639_JD_SPL_TRG_SFT                   8
+#define RT5639_JD_SPL_TRG_LO                    (0x0 << 8)
+#define RT5639_JD_SPL_TRG_HI                    (0x1 << 8)
+#define RT5639_JD_SPR_MASK                      (0x1 << 7)
+#define RT5639_JD_SPR_SFT                       7
+#define RT5639_JD_SPR_DIS                       (0x0 << 7)
+#define RT5639_JD_SPR_EN                        (0x1 << 7)
+#define RT5639_JD_SPR_TRG_MASK                  (0x1 << 6)
+#define RT5639_JD_SPR_TRG_SFT                   6
+#define RT5639_JD_SPR_TRG_LO                    (0x0 << 6)
+#define RT5639_JD_SPR_TRG_HI                    (0x1 << 6)
+#define RT5639_JD_MO_MASK                       (0x1 << 5)
+#define RT5639_JD_MO_SFT                        5
+#define RT5639_JD_MO_DIS                        (0x0 << 5)
+#define RT5639_JD_MO_EN                 (0x1 << 5)
+#define RT5639_JD_MO_TRG_MASK                   (0x1 << 4)
+#define RT5639_JD_MO_TRG_SFT                    4
+#define RT5639_JD_MO_TRG_LO                     (0x0 << 4)
+#define RT5639_JD_MO_TRG_HI                     (0x1 << 4)
+#define RT5639_JD_LO_MASK                       (0x1 << 3)
+#define RT5639_JD_LO_SFT                        3
+#define RT5639_JD_LO_DIS                        (0x0 << 3)
+#define RT5639_JD_LO_EN                         (0x1 << 3)
+#define RT5639_JD_LO_TRG_MASK                   (0x1 << 2)
+#define RT5639_JD_LO_TRG_SFT                    2
+#define RT5639_JD_LO_TRG_LO                     (0x0 << 2)
+#define RT5639_JD_LO_TRG_HI                     (0x1 << 2)
+#define RT5639_JD1_IN4P_MASK                    (0x1 << 1)
+#define RT5639_JD1_IN4P_SFT                     1
+#define RT5639_JD1_IN4P_DIS                     (0x0 << 1)
+#define RT5639_JD1_IN4P_EN                      (0x1 << 1)
+#define RT5639_JD2_IN4N_MASK                    (0x1)
+#define RT5639_JD2_IN4N_SFT                     0
+#define RT5639_JD2_IN4N_DIS                     (0x0)
+#define RT5639_JD2_IN4N_EN                      (0x1)
+
+/* Jack detect for ANC (0xbc) */
+#define RT5639_ANC_DET_MASK                     (0x3 << 4)
+#define RT5639_ANC_DET_SFT                      4
+#define RT5639_ANC_DET_DIS                      (0x0 << 4)
+#define RT5639_ANC_DET_MB1                      (0x1 << 4)
+#define RT5639_ANC_DET_MB2                      (0x2 << 4)
+#define RT5639_ANC_DET_JD                       (0x3 << 4)
+#define RT5639_AD_TRG_MASK                      (0x1 << 3)
+#define RT5639_AD_TRG_SFT                       3
+#define RT5639_AD_TRG_LO                        (0x0 << 3)
+#define RT5639_AD_TRG_HI                        (0x1 << 3)
+#define RT5639_ANCM_DET_MASK                    (0x3 << 4)
+#define RT5639_ANCM_DET_SFT                     4
+#define RT5639_ANCM_DET_DIS                     (0x0 << 4)
+#define RT5639_ANCM_DET_MB1                     (0x1 << 4)
+#define RT5639_ANCM_DET_MB2                     (0x2 << 4)
+#define RT5639_ANCM_DET_JD                      (0x3 << 4)
+#define RT5639_AMD_TRG_MASK                     (0x1 << 3)
+#define RT5639_AMD_TRG_SFT                      3
+#define RT5639_AMD_TRG_LO                       (0x0 << 3)
+#define RT5639_AMD_TRG_HI                       (0x1 << 3)
+
+/* IRQ Control 1 (0xbd) */
+#define RT5639_IRQ_JD_MASK                      (0x1 << 15)
+#define RT5639_IRQ_JD_SFT                       15
+#define RT5639_IRQ_JD_BP                        (0x0 << 15)
+#define RT5639_IRQ_JD_NOR                       (0x1 << 15)
+#define RT5639_IRQ_OT_MASK                      (0x1 << 14)
+#define RT5639_IRQ_OT_SFT                       14
+#define RT5639_IRQ_OT_BP                        (0x0 << 14)
+#define RT5639_IRQ_OT_NOR                       (0x1 << 14)
+#define RT5639_JD_STKY_MASK                     (0x1 << 13)
+#define RT5639_JD_STKY_SFT                      13
+#define RT5639_JD_STKY_DIS                      (0x0 << 13)
+#define RT5639_JD_STKY_EN                       (0x1 << 13)
+#define RT5639_OT_STKY_MASK                     (0x1 << 12)
+#define RT5639_OT_STKY_SFT                      12
+#define RT5639_OT_STKY_DIS                      (0x0 << 12)
+#define RT5639_OT_STKY_EN                       (0x1 << 12)
+#define RT5639_JD_P_MASK                        (0x1 << 11)
+#define RT5639_JD_P_SFT                         11
+#define RT5639_JD_P_NOR                         (0x0 << 11)
+#define RT5639_JD_P_INV                         (0x1 << 11)
+#define RT5639_OT_P_MASK                        (0x1 << 10)
+#define RT5639_OT_P_SFT                         10
+#define RT5639_OT_P_NOR                 (0x0 << 10)
+#define RT5639_OT_P_INV                         (0x1 << 10)
+
+/* IRQ Control 2 (0xbe) */
+#define RT5639_IRQ_MB1_OC_MASK          (0x1 << 15)
+#define RT5639_IRQ_MB1_OC_SFT                   15
+#define RT5639_IRQ_MB1_OC_BP                    (0x0 << 15)
+#define RT5639_IRQ_MB1_OC_NOR                   (0x1 << 15)
+#define RT5639_IRQ_MB2_OC_MASK          (0x1 << 14)
+#define RT5639_IRQ_MB2_OC_SFT                   14
+#define RT5639_IRQ_MB2_OC_BP                    (0x0 << 14)
+#define RT5639_IRQ_MB2_OC_NOR                   (0x1 << 14)
+#define RT5639_MB1_OC_STKY_MASK         (0x1 << 11)
+#define RT5639_MB1_OC_STKY_SFT          11
+#define RT5639_MB1_OC_STKY_DIS          (0x0 << 11)
+#define RT5639_MB1_OC_STKY_EN                   (0x1 << 11)
+#define RT5639_MB2_OC_STKY_MASK         (0x1 << 10)
+#define RT5639_MB2_OC_STKY_SFT          10
+#define RT5639_MB2_OC_STKY_DIS          (0x0 << 10)
+#define RT5639_MB2_OC_STKY_EN                   (0x1 << 10)
+#define RT5639_MB1_OC_P_MASK                    (0x1 << 7)
+#define RT5639_MB1_OC_P_SFT                     7
+#define RT5639_MB1_OC_P_NOR                     (0x0 << 7)
+#define RT5639_MB1_OC_P_INV                     (0x1 << 7)
+#define RT5639_MB2_OC_P_MASK                    (0x1 << 6)
+#define RT5639_MB2_OC_P_SFT                     6
+#define RT5639_MB2_OC_P_NOR                     (0x0 << 6)
+#define RT5639_MB2_OC_P_INV                     (0x1 << 6)
+#define RT5639_MB1_OC_CLR                       (0x1 << 3)
+#define RT5639_MB1_OC_CLR_SFT                   3
+#define RT5639_MB2_OC_CLR                       (0x1 << 2)
+#define RT5639_MB2_OC_CLR_SFT                   2
+
+/* GPIO Control 1 (0xc0) */
+#define RT5639_GP1_PIN_MASK                     (0x1 << 15)
+#define RT5639_GP1_PIN_SFT                      15
+#define RT5639_GP1_PIN_GPIO1                    (0x0 << 15)
+#define RT5639_GP1_PIN_IRQ                      (0x1 << 15)
+#define RT5639_GP2_PIN_MASK                     (0x1 << 14)
+#define RT5639_GP2_PIN_SFT                      14
+#define RT5639_GP2_PIN_GPIO2                    (0x0 << 14)
+#define RT5639_GP2_PIN_DMIC1_SCL                (0x1 << 14)
+#define RT5639_GP3_PIN_MASK                     (0x3 << 12)
+#define RT5639_GP3_PIN_SFT                      12
+#define RT5639_GP3_PIN_GPIO3                    (0x0 << 12)
+#define RT5639_GP3_PIN_DMIC1_SDA                (0x1 << 12)
+#define RT5639_GP3_PIN_IRQ                      (0x2 << 12)
+#define RT5639_GP4_PIN_MASK                     (0x1 << 11)
+#define RT5639_GP4_PIN_SFT                      11
+#define RT5639_GP4_PIN_GPIO4                    (0x0 << 11)
+#define RT5639_GP4_PIN_DMIC2_SDA                (0x1 << 11)
+#define RT5639_DP_SIG_MASK                      (0x1 << 10)
+#define RT5639_DP_SIG_SFT                       10
+#define RT5639_DP_SIG_TEST                      (0x0 << 10)
+#define RT5639_DP_SIG_AP                        (0x1 << 10)
+#define RT5639_GPIO_M_MASK                      (0x1 << 9)
+#define RT5639_GPIO_M_SFT                       9
+#define RT5639_GPIO_M_FLT                       (0x0 << 9)
+#define RT5639_GPIO_M_PH                        (0x1 << 9)
+
+/* GPIO Control 3 (0xc2) */
+#define RT5639_GP4_PF_MASK                      (0x1 << 11)
+#define RT5639_GP4_PF_SFT                       11
+#define RT5639_GP4_PF_IN                        (0x0 << 11)
+#define RT5639_GP4_PF_OUT                       (0x1 << 11)
+#define RT5639_GP4_OUT_MASK                     (0x1 << 10)
+#define RT5639_GP4_OUT_SFT                      10
+#define RT5639_GP4_OUT_LO                       (0x0 << 10)
+#define RT5639_GP4_OUT_HI                       (0x1 << 10)
+#define RT5639_GP4_P_MASK                       (0x1 << 9)
+#define RT5639_GP4_P_SFT                        9
+#define RT5639_GP4_P_NOR                        (0x0 << 9)
+#define RT5639_GP4_P_INV                        (0x1 << 9)
+#define RT5639_GP3_PF_MASK                      (0x1 << 8)
+#define RT5639_GP3_PF_SFT                       8
+#define RT5639_GP3_PF_IN                        (0x0 << 8)
+#define RT5639_GP3_PF_OUT                       (0x1 << 8)
+#define RT5639_GP3_OUT_MASK                     (0x1 << 7)
+#define RT5639_GP3_OUT_SFT                      7
+#define RT5639_GP3_OUT_LO                       (0x0 << 7)
+#define RT5639_GP3_OUT_HI                       (0x1 << 7)
+#define RT5639_GP3_P_MASK                       (0x1 << 6)
+#define RT5639_GP3_P_SFT                        6
+#define RT5639_GP3_P_NOR                        (0x0 << 6)
+#define RT5639_GP3_P_INV                        (0x1 << 6)
+#define RT5639_GP2_PF_MASK                      (0x1 << 5)
+#define RT5639_GP2_PF_SFT                       5
+#define RT5639_GP2_PF_IN                        (0x0 << 5)
+#define RT5639_GP2_PF_OUT                       (0x1 << 5)
+#define RT5639_GP2_OUT_MASK                     (0x1 << 4)
+#define RT5639_GP2_OUT_SFT                      4
+#define RT5639_GP2_OUT_LO                       (0x0 << 4)
+#define RT5639_GP2_OUT_HI                       (0x1 << 4)
+#define RT5639_GP2_P_MASK                       (0x1 << 3)
+#define RT5639_GP2_P_SFT                        3
+#define RT5639_GP2_P_NOR                        (0x0 << 3)
+#define RT5639_GP2_P_INV                        (0x1 << 3)
+#define RT5639_GP1_PF_MASK                      (0x1 << 2)
+#define RT5639_GP1_PF_SFT                       2
+#define RT5639_GP1_PF_IN                        (0x0 << 2)
+#define RT5639_GP1_PF_OUT                       (0x1 << 2)
+#define RT5639_GP1_OUT_MASK                     (0x1 << 1)
+#define RT5639_GP1_OUT_SFT                      1
+#define RT5639_GP1_OUT_LO                       (0x0 << 1)
+#define RT5639_GP1_OUT_HI                       (0x1 << 1)
+#define RT5639_GP1_P_MASK                       (0x1)
+#define RT5639_GP1_P_SFT                        0
+#define RT5639_GP1_P_NOR                        (0x0)
+#define RT5639_GP1_P_INV                        (0x1)
+
+/* FM34-500 Register Control 1 (0xc4) */
+#define RT5639_DSP_ADD_SFT                      0
+
+/* FM34-500 Register Control 2 (0xc5) */
+#define RT5639_DSP_DAT_SFT                      0
+
+/* FM34-500 Register Control 3 (0xc6) */
+#define RT5639_DSP_BUSY_MASK                    (0x1 << 15)
+#define RT5639_DSP_BUSY_BIT                     15
+#define RT5639_DSP_DS_MASK                      (0x1 << 14)
+#define RT5639_DSP_DS_SFT                       14
+#define RT5639_DSP_DS_FM3010                    (0x1 << 14)
+#define RT5639_DSP_DS_TEMP                      (0x1 << 14)
+#define RT5639_DSP_CLK_MASK                     (0x3 << 12)
+#define RT5639_DSP_CLK_SFT                      12
+#define RT5639_DSP_CLK_384K                     (0x0 << 12)
+#define RT5639_DSP_CLK_192K                     (0x1 << 12)
+#define RT5639_DSP_CLK_96K                      (0x2 << 12)
+#define RT5639_DSP_CLK_64K                      (0x3 << 12)
+#define RT5639_DSP_PD_PIN_MASK          (0x1 << 11)
+#define RT5639_DSP_PD_PIN_SFT                   11
+#define RT5639_DSP_PD_PIN_LO                    (0x0 << 11)
+#define RT5639_DSP_PD_PIN_HI                    (0x1 << 11)
+#define RT5639_DSP_RST_PIN_MASK         (0x1 << 10)
+#define RT5639_DSP_RST_PIN_SFT                  10
+#define RT5639_DSP_RST_PIN_LO                   (0x0 << 10)
+#define RT5639_DSP_RST_PIN_HI                   (0x1 << 10)
+#define RT5639_DSP_R_EN                         (0x1 << 9)
+#define RT5639_DSP_W_EN                 (0x1 << 8)
+#define RT5639_DSP_CMD_MASK                     (0xff)
+#define RT5639_DSP_CMD_MW                       (0x3b)  /* Memory Write */
+#define RT5639_DSP_CMD_MR                       (0x37)  /* Memory Read */
+#define RT5639_DSP_CMD_RR                       (0x60)  /* Register Read */
+#define RT5639_DSP_CMD_RW                       (0x68)  /* Register Write */
+#define RT5639_DSP_REG_DATHI                    (0x26)  /* High Data Addr */
+#define RT5639_DSP_REG_DATLO                    (0x25)  /* Low Data Addr */
+
+/* Programmable Register Array Control 1 (0xc8) */
+#define RT5639_REG_SEQ_MASK                     (0xf << 12)
+#define RT5639_REG_SEQ_SFT                      12
+#define RT5639_SEQ1_ST_MASK                     (0x1 << 11) /*RO*/
+#define RT5639_SEQ1_ST_SFT                      11
+#define RT5639_SEQ1_ST_RUN                      (0x0 << 11)
+#define RT5639_SEQ1_ST_FIN                      (0x1 << 11)
+#define RT5639_SEQ2_ST_MASK                     (0x1 << 10) /*RO*/
+#define RT5639_SEQ2_ST_SFT                      10
+#define RT5639_SEQ2_ST_RUN                      (0x0 << 10)
+#define RT5639_SEQ2_ST_FIN                      (0x1 << 10)
+#define RT5639_REG_LV_MASK                      (0x1 << 9)
+#define RT5639_REG_LV_SFT                       9
+#define RT5639_REG_LV_MX                        (0x0 << 9)
+#define RT5639_REG_LV_PR                        (0x1 << 9)
+#define RT5639_SEQ_2_PT_MASK                    (0x1 << 8)
+#define RT5639_SEQ_2_PT_BIT                     8
+#define RT5639_REG_IDX_MASK                     (0xff)
+#define RT5639_REG_IDX_SFT                      0
+
+/* Programmable Register Array Control 2 (0xc9) */
+#define RT5639_REG_DAT_MASK                     (0xffff)
+#define RT5639_REG_DAT_SFT                      0
+
+/* Programmable Register Array Control 3 (0xca) */
+#define RT5639_SEQ_DLY_MASK                     (0xff << 8)
+#define RT5639_SEQ_DLY_SFT                      8
+#define RT5639_PROG_MASK                        (0x1 << 7)
+#define RT5639_PROG_SFT                         7
+#define RT5639_PROG_DIS                         (0x0 << 7)
+#define RT5639_PROG_EN                          (0x1 << 7)
+#define RT5639_SEQ1_PT_RUN                      (0x1 << 6)
+#define RT5639_SEQ1_PT_RUN_BIT                  6
+#define RT5639_SEQ2_PT_RUN                      (0x1 << 5)
+#define RT5639_SEQ2_PT_RUN_BIT                  5
+
+/* Programmable Register Array Control 4 (0xcb) */
+#define RT5639_SEQ1_START_MASK          (0xf << 8)
+#define RT5639_SEQ1_START_SFT                   8
+#define RT5639_SEQ1_END_MASK                    (0xf)
+#define RT5639_SEQ1_END_SFT                     0
+
+/* Programmable Register Array Control 5 (0xcc) */
+#define RT5639_SEQ2_START_MASK          (0xf << 8)
+#define RT5639_SEQ2_START_SFT                   8
+#define RT5639_SEQ2_END_MASK                    (0xf)
+#define RT5639_SEQ2_END_SFT                     0
+
+/* Scramble Function (0xcd) */
+#define RT5639_SCB_KEY_MASK                     (0xff)
+#define RT5639_SCB_KEY_SFT                      0
+
+/* Scramble Control (0xce) */
+#define RT5639_SCB_SWAP_MASK                    (0x1 << 15)
+#define RT5639_SCB_SWAP_SFT                     15
+#define RT5639_SCB_SWAP_DIS                     (0x0 << 15)
+#define RT5639_SCB_SWAP_EN                      (0x1 << 15)
+#define RT5639_SCB_MASK                 (0x1 << 14)
+#define RT5639_SCB_SFT                          14
+#define RT5639_SCB_DIS                          (0x0 << 14)
+#define RT5639_SCB_EN                           (0x1 << 14)
+
+/* Baseback Control (0xcf) */
+#define RT5639_BB_MASK                          (0x1 << 15)
+#define RT5639_BB_SFT                           15
+#define RT5639_BB_DIS                           (0x0 << 15)
+#define RT5639_BB_EN                            (0x1 << 15)
+#define RT5639_BB_CT_MASK                       (0x7 << 12)
+#define RT5639_BB_CT_SFT                        12
+#define RT5639_BB_CT_A                          (0x0 << 12)
+#define RT5639_BB_CT_B                          (0x1 << 12)
+#define RT5639_BB_CT_C                          (0x2 << 12)
+#define RT5639_BB_CT_D                          (0x3 << 12)
+#define RT5639_M_BB_L_MASK                      (0x1 << 9)
+#define RT5639_M_BB_L_SFT                       9
+#define RT5639_M_BB_R_MASK                      (0x1 << 8)
+#define RT5639_M_BB_R_SFT                       8
+#define RT5639_M_BB_HPF_L_MASK          (0x1 << 7)
+#define RT5639_M_BB_HPF_L_SFT                   7
+#define RT5639_M_BB_HPF_R_MASK          (0x1 << 6)
+#define RT5639_M_BB_HPF_R_SFT                   6
+#define RT5639_G_BB_BST_MASK                    (0x3f)
+#define RT5639_G_BB_BST_SFT                     0
+
+/* MP3 Plus Control 1 (0xd0) */
+#define RT5639_M_MP3_L_MASK                     (0x1 << 15)
+#define RT5639_M_MP3_L_SFT                      15
+#define RT5639_M_MP3_R_MASK                     (0x1 << 14)
+#define RT5639_M_MP3_R_SFT                      14
+#define RT5639_M_MP3_MASK                       (0x1 << 13)
+#define RT5639_M_MP3_SFT                        13
+#define RT5639_M_MP3_DIS                        (0x0 << 13)
+#define RT5639_M_MP3_EN                 (0x1 << 13)
+#define RT5639_EG_MP3_MASK                      (0x1f << 8)
+#define RT5639_EG_MP3_SFT                       8
+#define RT5639_MP3_HLP_MASK                     (0x1 << 7)
+#define RT5639_MP3_HLP_SFT                      7
+#define RT5639_MP3_HLP_DIS                      (0x0 << 7)
+#define RT5639_MP3_HLP_EN                       (0x1 << 7)
+#define RT5639_M_MP3_ORG_L_MASK         (0x1 << 6)
+#define RT5639_M_MP3_ORG_L_SFT          6
+#define RT5639_M_MP3_ORG_R_MASK         (0x1 << 5)
+#define RT5639_M_MP3_ORG_R_SFT          5
+
+/* MP3 Plus Control 2 (0xd1) */
+#define RT5639_MP3_WT_MASK                      (0x1 << 13)
+#define RT5639_MP3_WT_SFT                       13
+#define RT5639_MP3_WT_1_4                       (0x0 << 13)
+#define RT5639_MP3_WT_1_2                       (0x1 << 13)
+#define RT5639_OG_MP3_MASK                      (0x1f << 8)
+#define RT5639_OG_MP3_SFT                       8
+#define RT5639_HG_MP3_MASK                      (0x3f)
+#define RT5639_HG_MP3_SFT                       0
+
+/* 3D HP Control 1 (0xd2) */
+#define RT5639_3D_CF_MASK                       (0x1 << 15)
+#define RT5639_3D_CF_SFT                        15
+#define RT5639_3D_CF_DIS                        (0x0 << 15)
+#define RT5639_3D_CF_EN                 (0x1 << 15)
+#define RT5639_3D_HP_MASK                       (0x1 << 14)
+#define RT5639_3D_HP_SFT                        14
+#define RT5639_3D_HP_DIS                        (0x0 << 14)
+#define RT5639_3D_HP_EN                 (0x1 << 14)
+#define RT5639_3D_BT_MASK                       (0x1 << 13)
+#define RT5639_3D_BT_SFT                        13
+#define RT5639_3D_BT_DIS                        (0x0 << 13)
+#define RT5639_3D_BT_EN                         (0x1 << 13)
+#define RT5639_3D_1F_MIX_MASK                   (0x3 << 11)
+#define RT5639_3D_1F_MIX_SFT                    11
+#define RT5639_3D_HP_M_MASK                     (0x1 << 10)
+#define RT5639_3D_HP_M_SFT                      10
+#define RT5639_3D_HP_M_SUR                      (0x0 << 10)
+#define RT5639_3D_HP_M_FRO                      (0x1 << 10)
+#define RT5639_M_3D_HRTF_MASK                   (0x1 << 9)
+#define RT5639_M_3D_HRTF_SFT                    9
+#define RT5639_M_3D_D2H_MASK                    (0x1 << 8)
+#define RT5639_M_3D_D2H_SFT                     8
+#define RT5639_M_3D_D2R_MASK                    (0x1 << 7)
+#define RT5639_M_3D_D2R_SFT                     7
+#define RT5639_M_3D_REVB_MASK                   (0x1 << 6)
+#define RT5639_M_3D_REVB_SFT                    6
+
+/* Adjustable high pass filter control 1 (0xd3) */
+#define RT5639_2ND_HPF_MASK                     (0x1 << 15)
+#define RT5639_2ND_HPF_SFT                      15
+#define RT5639_2ND_HPF_DIS                      (0x0 << 15)
+#define RT5639_2ND_HPF_EN                       (0x1 << 15)
+#define RT5639_HPF_CF_L_MASK                    (0x7 << 12)
+#define RT5639_HPF_CF_L_SFT                     12
+#define RT5639_1ST_HPF_MASK                     (0x1 << 11)
+#define RT5639_1ST_HPF_SFT                      11
+#define RT5639_1ST_HPF_DIS                      (0x0 << 11)
+#define RT5639_1ST_HPF_EN                       (0x1 << 11)
+#define RT5639_HPF_CF_R_MASK                    (0x7 << 8)
+#define RT5639_HPF_CF_R_SFT                     8
+#define RT5639_ZD_T_MASK                        (0x3 << 6)
+#define RT5639_ZD_T_SFT                         6
+#define RT5639_ZD_F_MASK                        (0x3 << 4)
+#define RT5639_ZD_F_SFT                         4
+#define RT5639_ZD_F_IM                          (0x0 << 4)
+#define RT5639_ZD_F_ZC_IM                       (0x1 << 4)
+#define RT5639_ZD_F_ZC_IOD                      (0x2 << 4)
+#define RT5639_ZD_F_UN                          (0x3 << 4)
+
+/* HP calibration control and Amp detection (0xd6) */
+#define RT5639_SI_DAC_MASK                      (0x1 << 11)
+#define RT5639_SI_DAC_SFT                       11
+#define RT5639_SI_DAC_AUTO                      (0x0 << 11)
+#define RT5639_SI_DAC_TEST                      (0x1 << 11)
+#define RT5639_DC_CAL_M_MASK                    (0x1 << 10)
+#define RT5639_DC_CAL_M_SFT                     10
+#define RT5639_DC_CAL_M_CAL                     (0x0 << 10)
+#define RT5639_DC_CAL_M_NOR                     (0x1 << 10)
+#define RT5639_DC_CAL_MASK                      (0x1 << 9)
+#define RT5639_DC_CAL_SFT                       9
+#define RT5639_DC_CAL_DIS                       (0x0 << 9)
+#define RT5639_DC_CAL_EN                        (0x1 << 9)
+#define RT5639_HPD_RCV_MASK                     (0x7 << 6)
+#define RT5639_HPD_RCV_SFT                      6
+#define RT5639_HPD_PS_MASK                      (0x1 << 5)
+#define RT5639_HPD_PS_SFT                       5
+#define RT5639_HPD_PS_DIS                       (0x0 << 5)
+#define RT5639_HPD_PS_EN                        (0x1 << 5)
+#define RT5639_CAL_M_MASK                       (0x1 << 4)
+#define RT5639_CAL_M_SFT                        4
+#define RT5639_CAL_M_DEP                        (0x0 << 4)
+#define RT5639_CAL_M_CAL                        (0x1 << 4)
+#define RT5639_CAL_MASK                 (0x1 << 3)
+#define RT5639_CAL_SFT                          3
+#define RT5639_CAL_DIS                          (0x0 << 3)
+#define RT5639_CAL_EN                           (0x1 << 3)
+#define RT5639_CAL_TEST_MASK                    (0x1 << 2)
+#define RT5639_CAL_TEST_SFT                     2
+#define RT5639_CAL_TEST_DIS                     (0x0 << 2)
+#define RT5639_CAL_TEST_EN                      (0x1 << 2)
+#define RT5639_CAL_P_MASK                       (0x3)
+#define RT5639_CAL_P_SFT                        0
+#define RT5639_CAL_P_NONE                       (0x0)
+#define RT5639_CAL_P_CAL                        (0x1)
+#define RT5639_CAL_P_DAC_CAL                    (0x2)
+
+/* Soft volume and zero cross control 1 (0xd9) */
+#define RT5639_SV_MASK                          (0x1 << 15)
+#define RT5639_SV_SFT                           15
+#define RT5639_SV_DIS                           (0x0 << 15)
+#define RT5639_SV_EN                            (0x1 << 15)
+#define RT5639_SPO_SV_MASK                      (0x1 << 14)
+#define RT5639_SPO_SV_SFT                       14
+#define RT5639_SPO_SV_DIS                       (0x0 << 14)
+#define RT5639_SPO_SV_EN                        (0x1 << 14)
+#define RT5639_OUT_SV_MASK                      (0x1 << 13)
+#define RT5639_OUT_SV_SFT                       13
+#define RT5639_OUT_SV_DIS                       (0x0 << 13)
+#define RT5639_OUT_SV_EN                        (0x1 << 13)
+#define RT5639_HP_SV_MASK                       (0x1 << 12)
+#define RT5639_HP_SV_SFT                        12
+#define RT5639_HP_SV_DIS                        (0x0 << 12)
+#define RT5639_HP_SV_EN                 (0x1 << 12)
+#define RT5639_ZCD_DIG_MASK                     (0x1 << 11)
+#define RT5639_ZCD_DIG_SFT                      11
+#define RT5639_ZCD_DIG_DIS                      (0x0 << 11)
+#define RT5639_ZCD_DIG_EN                       (0x1 << 11)
+#define RT5639_ZCD_MASK                 (0x1 << 10)
+#define RT5639_ZCD_SFT                          10
+#define RT5639_ZCD_PD                           (0x0 << 10)
+#define RT5639_ZCD_PU                           (0x1 << 10)
+#define RT5639_M_ZCD_MASK                       (0x3f << 4)
+#define RT5639_M_ZCD_SFT                        4
+#define RT5639_M_ZCD_RM_L                       (0x1 << 9)
+#define RT5639_M_ZCD_RM_R                       (0x1 << 8)
+#define RT5639_M_ZCD_SM_L                       (0x1 << 7)
+#define RT5639_M_ZCD_SM_R                       (0x1 << 6)
+#define RT5639_M_ZCD_OM_L                       (0x1 << 5)
+#define RT5639_M_ZCD_OM_R                       (0x1 << 4)
+#define RT5639_SV_DLY_MASK                      (0xf)
+#define RT5639_SV_DLY_SFT                       0
+
+/* Soft volume and zero cross control 2 (0xda) */
+#define RT5639_ZCD_HP_MASK                      (0x1 << 15)
+#define RT5639_ZCD_HP_SFT                       15
+#define RT5639_ZCD_HP_DIS                       (0x0 << 15)
+#define RT5639_ZCD_HP_EN                        (0x1 << 15)
+
+
+/* Codec Private Register definition */
+/* 3D Speaker Control (0x63) */
+#define RT5639_3D_SPK_MASK                      (0x1 << 15)
+#define RT5639_3D_SPK_SFT                       15
+#define RT5639_3D_SPK_DIS                       (0x0 << 15)
+#define RT5639_3D_SPK_EN                        (0x1 << 15)
+#define RT5639_3D_SPK_M_MASK                    (0x3 << 13)
+#define RT5639_3D_SPK_M_SFT                     13
+#define RT5639_3D_SPK_CG_MASK                   (0x1f << 8)
+#define RT5639_3D_SPK_CG_SFT                    8
+#define RT5639_3D_SPK_SG_MASK                   (0x1f)
+#define RT5639_3D_SPK_SG_SFT                    0
+
+/* Wind Noise Detection Control 1 (0x6c) */
+#define RT5639_WND_MASK                 (0x1 << 15)
+#define RT5639_WND_SFT                          15
+#define RT5639_WND_DIS                          (0x0 << 15)
+#define RT5639_WND_EN                           (0x1 << 15)
+
+/* Wind Noise Detection Control 2 (0x6d) */
+#define RT5639_WND_FC_NW_MASK           (0x3f << 10)
+#define RT5639_WND_FC_NW_SFT                    10
+#define RT5639_WND_FC_WK_MASK           (0x3f << 4)
+#define RT5639_WND_FC_WK_SFT                    4
+
+/* Wind Noise Detection Control 3 (0x6e) */
+#define RT5639_HPF_FC_MASK                      (0x3f << 6)
+#define RT5639_HPF_FC_SFT                       6
+#define RT5639_WND_FC_ST_MASK                   (0x3f)
+#define RT5639_WND_FC_ST_SFT                    0
+
+/* Wind Noise Detection Control 4 (0x6f) */
+#define RT5639_WND_TH_LO_MASK           (0x3ff)
+#define RT5639_WND_TH_LO_SFT                    0
+
+/* Wind Noise Detection Control 5 (0x70) */
+#define RT5639_WND_TH_HI_MASK                   (0x3ff)
+#define RT5639_WND_TH_HI_SFT                    0
+
+/* Wind Noise Detection Control 8 (0x73) */
+#define RT5639_WND_WIND_MASK                    (0x1 << 13) /* Read-Only */
+#define RT5639_WND_WIND_SFT                     13
+#define RT5639_WND_STRONG_MASK          (0x1 << 12) /* Read-Only */
+#define RT5639_WND_STRONG_SFT                   12
+enum {
+        RT5639_NO_WIND,
+        RT5639_BREEZE,
+        RT5639_STORM,
+};
+
+/* Dipole Speaker Interface (0x75) */
+#define RT5639_DP_ATT_MASK                      (0x3 << 14)
+#define RT5639_DP_ATT_SFT                       14
+#define RT5639_DP_SPK_MASK                      (0x1 << 10)
+#define RT5639_DP_SPK_SFT                       10
+#define RT5639_DP_SPK_DIS                       (0x0 << 10)
+#define RT5639_DP_SPK_EN                        (0x1 << 10)
+
+/* EQ Pre Volume Control (0xb3) */
+#define RT5639_EQ_PRE_VOL_MASK          (0xffff)
+#define RT5639_EQ_PRE_VOL_SFT                   0
+
+/* EQ Post Volume Control (0xb4) */
+#define RT5639_EQ_PST_VOL_MASK          (0xffff)
+#define RT5639_EQ_PST_VOL_SFT                   0
+
+
+
+/* Volume Rescale */
+#define RT5639_VOL_RSCL_MAX 0x27
+#define RT5639_VOL_RSCL_RANGE 0x1F
+/* Debug String Length */
+#define RT5639_REG_DISP_LEN 10
+
+#define RT5639_NO_JACK          BIT(0)
+#define RT5639_HEADSET_DET      BIT(1)
+#define RT5639_HEADPHO_DET      BIT(2)
+
+int rt5639_headset_detect(struct snd_soc_codec *codec, int jack_insert);
+
+/* System Clock Source */
+enum {
+        RT5639_SCLK_S_MCLK,
+        RT5639_SCLK_S_PLL1,
+        RT5639_SCLK_S_RCCLK,
+};
+
+/* PLL1 Source */
+enum {
+        RT5639_PLL1_S_MCLK,
+        RT5639_PLL1_S_BCLK1,
+        RT5639_PLL1_S_BCLK2,
+        RT5639_PLL1_S_BCLK3,
+};
+
+enum {
+        RT5639_AIF1,
+        RT5639_AIF2,
+        RT5639_AIF3,
+        RT5639_AIFS,
+};
+
+#define RT5639_U_IF1 (0x1)
+#define RT5639_U_IF2 (0x1 << 1)
+#define RT5639_U_IF3 (0x1 << 2)
+
+enum {
+        RT5639_IF_123,
+        RT5639_IF_132,
+        RT5639_IF_312,
+        RT5639_IF_321,
+        RT5639_IF_231,
+        RT5639_IF_213,
+        RT5639_IF_113,
+        RT5639_IF_223,
+        RT5639_IF_ALL,
+};
+
+enum {
+        RT5639_DMIC_DIS,
+        RT5639_DMIC1,
+        RT5639_DMIC2,
+};
+
+struct rt5639_pll_code {
+        bool m_bp; /* Indicates bypass m code or not. */
+        int m_code;
+        int n_code;
+        int k_code;
+};
+
+struct rt5639_priv {
+        struct snd_soc_codec *codec;
+
+        int aif_pu;
+        int sysclk;
+        int sysclk_src;
+        int lrck[RT5639_AIFS];
+        int bclk[RT5639_AIFS];
+        int master[RT5639_AIFS];
+
+        int pll_src;
+        int pll_in;
+        int pll_out;
+
+        int dmic_en;
+        int dsp_sw;
+};
+
+
+#endif /* __RT5639_H__ */
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
new file mode 100644
index 00000000000..e3d0af02e39
--- /dev/null
+++ b/sound/soc/codecs/rt5640.c
@@ -0,0 +1,2546 @@
+/*
+ * rt5640.c  --  RT5640 ALSA SoC audio codec driver
+ *
+ * Copyright 2011 Realtek Semiconductor Corp.
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "rt5640.h"
+#if (CONFIG_SND_SOC_RT5642_MODULE | CONFIG_SND_SOC_RT5642)
+#include "rt5640-dsp.h"
+#endif
+
+#define RT5640_DEMO 1
+#define RT5640_REG_RW 1
+#define RT5640_DET_EXT_MIC 0
+
+#ifdef RT5640_DEMO
+struct rt5640_init_reg {
+        u8 reg;
+        u16 val;
+};
+
+static struct rt5640_init_reg init_list[] = {
+        {RT5640_DUMMY1          , 0x3701},/*fa[12:13] = 1'b;fa[8~10]=1;fa[0]=1*/
+        {RT5640_DEPOP_M1        , 0x0019},/* 8e[4:3] = 11'b; 8e[0] = 1'b */
+        {RT5640_DEPOP_M2        , 0x3100},/* 8f[13] = 1'b */
+        {RT5640_ADDA_CLK1       , 0x1114},/* 73[2] = 1'b  */
+        {RT5640_MICBIAS         , 0x3030},/* 93[5:4] = 11'b */
+        {RT5640_PRIV_INDEX      , 0x003d},/* PR3d[12] = 1'b */
+        {RT5640_PRIV_DATA       , 0x3600},
+        {RT5640_CLS_D_OUT       , 0xa000},/* 8d[11] = 0'b */
+        {RT5640_PRIV_INDEX      , 0x001c},/* PR1c = 0D21'h */
+        {RT5640_PRIV_DATA       , 0x0D21},
+        {RT5640_PRIV_INDEX      , 0x001b},/* PR1B = 0D21'h */
+        {RT5640_PRIV_DATA       , 0x0000},
+        {RT5640_PRIV_INDEX      , 0x0012},/* PR12 = 0aa8'h */
+        {RT5640_PRIV_DATA       , 0x0aa8},
+        {RT5640_PRIV_INDEX      , 0x0014},/* PR14 = 0aaa'h */
+        {RT5640_PRIV_DATA       , 0x0aaa},
+        {RT5640_PRIV_INDEX      , 0x0020},/* PR20 = 6110'h */
+        {RT5640_PRIV_DATA       , 0x6110},
+        {RT5640_PRIV_INDEX      , 0x0021},/* PR21 = e0e0'h */
+        {RT5640_PRIV_DATA       , 0xe0e0},
+        {RT5640_PRIV_INDEX      , 0x0023},/* PR23 = 1804'h */
+        {RT5640_PRIV_DATA       , 0x1804},
+        /*playback*/
+        {RT5640_STO_DAC_MIXER   , 0x1414},/*Dig inf 1 -> Sto DAC mixer -> DACL*/
+        {RT5640_OUT_L3_MIXER    , 0x01fe},/*DACL1 -> OUTMIXL*/
+        {RT5640_OUT_R3_MIXER    , 0x01fe},/*DACR1 -> OUTMIXR */
+        {RT5640_HP_VOL          , 0x8888},/* OUTMIX -> HPVOL */
+        {RT5640_HPO_MIXER       , 0xc000},/* HPVOL -> HPOLMIX */
+/*      {RT5640_HPO_MIXER       , 0xa000},// DAC1 -> HPOLMIX   */
+        {RT5640_SPK_L_MIXER     , 0x0036},/* DACL1 -> SPKMIXL */
+        {RT5640_SPK_R_MIXER     , 0x0036},/* DACR1 -> SPKMIXR */
+        {RT5640_SPK_VOL         , 0x8888},/* SPKMIX -> SPKVOL */
+        {RT5640_SPO_L_MIXER     , 0xe800},/* SPKVOLL -> SPOLMIX */
+        {RT5640_SPO_R_MIXER     , 0x2800},/* SPKVOLR -> SPORMIX */
+/*      {RT5640_SPO_L_MIXER     , 0xb800},//DAC -> SPOLMIX */
+/*      {RT5640_SPO_R_MIXER     , 0x1800},//DAC -> SPORMIX */
+/*      {RT5640_I2S1_SDP        , 0xD000},//change IIS1 and IIS2 */
+        /*record*/
+        {RT5640_IN1_IN2         , 0x5080},/*IN1 boost 40db & differential mode*/
+        {RT5640_IN3_IN4         , 0x0500},/*IN2 boost 40db & signal ended mode*/
+        {RT5640_REC_L2_MIXER    , 0x005f},/* enable Mic1 -> RECMIXL */
+        {RT5640_REC_R2_MIXER    , 0x005f},/* enable Mic1 -> RECMIXR */
+/*      {RT5640_REC_L2_MIXER    , 0x006f},//Mic2 -> RECMIXL */
+/*      {RT5640_REC_R2_MIXER    , 0x006f},//Mic2 -> RECMIXR */
+        {RT5640_STO_ADC_MIXER   , 0x3020},/* ADC -> Sto ADC mixer */
+
+#if RT5640_DET_EXT_MIC
+        {RT5640_MICBIAS , 0x3800},/* enable MICBIAS short current */
+        {RT5640_GPIO_CTRL1      , 0x8400},/* set GPIO1 to IRQ */
+        {RT5640_GPIO_CTRL3      , 0x0004},/* set GPIO1 output */
+        {RT5640_IRQ_CTRL2       , 0x8000},/*set MICBIAS short current to IRQ */
+                                        /*( if sticky set regBE : 8800 ) */
+#endif
+
+};
+#define RT5640_INIT_REG_LEN ARRAY_SIZE(init_list)
+
+static int rt5640_reg_init(struct snd_soc_codec *codec)
+{
+        int i;
+        for (i = 0; i < RT5640_INIT_REG_LEN; i++)
+                snd_soc_write(codec, init_list[i].reg, init_list[i].val);
+        return 0;
+}
+#endif
+
+static const u16 rt5640_reg[RT5640_VENDOR_ID2 + 1] = {
+        [RT5640_RESET] = 0x000c,
+        [RT5640_SPK_VOL] = 0xc8c8,
+        [RT5640_HP_VOL] = 0xc8c8,
+        [RT5640_OUTPUT] = 0xc8c8,
+        [RT5640_MONO_OUT] = 0x8000,
+        [RT5640_INL_INR_VOL] = 0x0808,
+        [RT5640_DAC1_DIG_VOL] = 0xafaf,
+        [RT5640_DAC2_DIG_VOL] = 0xafaf,
+        [RT5640_ADC_DIG_VOL] = 0x2f2f,
+        [RT5640_ADC_DATA] = 0x2f2f,
+        [RT5640_STO_ADC_MIXER] = 0x7060,
+        [RT5640_MONO_ADC_MIXER] = 0x7070,
+        [RT5640_AD_DA_MIXER] = 0x8080,
+        [RT5640_STO_DAC_MIXER] = 0x5454,
+        [RT5640_MONO_DAC_MIXER] = 0x5454,
+        [RT5640_DIG_MIXER] = 0xaa00,
+        [RT5640_DSP_PATH2] = 0xa000,
+        [RT5640_REC_L2_MIXER] = 0x007f,
+        [RT5640_REC_R2_MIXER] = 0x007f,
+        [RT5640_HPO_MIXER] = 0xe000,
+        [RT5640_SPK_L_MIXER] = 0x003e,
+        [RT5640_SPK_R_MIXER] = 0x003e,
+        [RT5640_SPO_L_MIXER] = 0xf800,
+        [RT5640_SPO_R_MIXER] = 0x3800,
+        [RT5640_SPO_CLSD_RATIO] = 0x0004,
+        [RT5640_MONO_MIXER] = 0xfc00,
+        [RT5640_OUT_L3_MIXER] = 0x01ff,
+        [RT5640_OUT_R3_MIXER] = 0x01ff,
+        [RT5640_LOUT_MIXER] = 0xf000,
+        [RT5640_PWR_ANLG1] = 0x00c0,
+        [RT5640_I2S1_SDP] = 0x8000,
+        [RT5640_I2S2_SDP] = 0x8000,
+        [RT5640_I2S3_SDP] = 0x8000,
+        [RT5640_ADDA_CLK1] = 0x1110,
+        [RT5640_ADDA_CLK2] = 0x0c00,
+        [RT5640_DMIC] = 0x1d00,
+        [RT5640_ASRC_3] = 0x0008,
+        [RT5640_HP_OVCD] = 0x0600,
+        [RT5640_CLS_D_OVCD] = 0x0228,
+        [RT5640_CLS_D_OUT] = 0xa800,
+        [RT5640_DEPOP_M1] = 0x0004,
+        [RT5640_DEPOP_M2] = 0x1100,
+        [RT5640_DEPOP_M3] = 0x0646,
+        [RT5640_CHARGE_PUMP] = 0x0c00,
+        [RT5640_MICBIAS] = 0x3000,
+        [RT5640_EQ_CTRL1] = 0x2080,
+        [RT5640_DRC_AGC_1] = 0x2206,
+        [RT5640_DRC_AGC_2] = 0x1f00,
+        [RT5640_ANC_CTRL1] = 0x034b,
+        [RT5640_ANC_CTRL2] = 0x0066,
+        [RT5640_ANC_CTRL3] = 0x000b,
+        [RT5640_GPIO_CTRL1] = 0x0400,
+        [RT5640_DSP_CTRL3] = 0x2000,
+        [RT5640_BASE_BACK] = 0x0013,
+        [RT5640_MP3_PLUS1] = 0x0680,
+        [RT5640_MP3_PLUS2] = 0x1c17,
+        [RT5640_3D_HP] = 0x8c00,
+        [RT5640_ADJ_HPF] = 0x2a20,
+        [RT5640_HP_CALIB_AMP_DET] = 0x0400,
+        [RT5640_SV_ZCD1] = 0x0809,
+        [RT5640_VENDOR_ID1] = 0x10ec,
+        [RT5640_VENDOR_ID2] = 0x6231,
+};
+
+static int rt5640_reset(struct snd_soc_codec *codec)
+{
+        return snd_soc_write(codec, RT5640_RESET, 0);
+}
+
+/**
+ * rt5640_index_write - Write private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ * @value: Private register Data.
+ *
+ * Modify private register for advanced setting. It can be written through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt5640_index_write(struct snd_soc_codec *codec,
+                unsigned int reg, unsigned int value)
+{
+        int ret;
+
+        ret = snd_soc_write(codec, RT5640_PRIV_INDEX, reg);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+                goto err;
+        }
+        ret = snd_soc_write(codec, RT5640_PRIV_DATA, value);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set private value: %d\n", ret);
+                goto err;
+        }
+        return 0;
+
+err:
+        return ret;
+}
+
+/**
+ * rt5640_index_read - Read private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ *
+ * Read advanced setting from private register. It can be read through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns private register value or negative error code.
+ */
+static unsigned int rt5640_index_read(
+        struct snd_soc_codec *codec, unsigned int reg)
+{
+        int ret;
+
+        ret = snd_soc_write(codec, RT5640_PRIV_INDEX, reg);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+                return ret;
+        }
+        return snd_soc_read(codec, RT5640_PRIV_DATA);
+}
+
+/**
+ * rt5640_index_update_bits - update private register bits
+ * @codec: audio codec
+ * @reg: Private register index.
+ * @mask: register mask
+ * @value: new value
+ *
+ * Writes new register value.
+ *
+ * Returns 1 for change, 0 for no change, or negative error code.
+ */
+static int rt5640_index_update_bits(struct snd_soc_codec *codec,
+        unsigned int reg, unsigned int mask, unsigned int value)
+{
+        unsigned int old, new;
+        int change, ret;
+
+        ret = rt5640_index_read(codec, reg);
+        if (ret < 0) {
+                dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
+                goto err;
+        }
+
+        old = ret;
+        new = (old & ~mask) | (value & mask);
+        change = old != new;
+        if (change) {
+                ret = rt5640_index_write(codec, reg, new);
+                if (ret < 0) {
+                        dev_err(codec->dev,
+                                "Failed to write private reg: %d\n", ret);
+                        goto err;
+                }
+        }
+        return change;
+
+err:
+        return ret;
+}
+
+static int rt5640_volatile_register(
+        struct snd_soc_codec *codec, unsigned int reg)
+{
+        switch (reg) {
+        case RT5640_RESET:
+        case RT5640_PRIV_DATA:
+        case RT5640_ASRC_5:
+        case RT5640_EQ_CTRL1:
+        case RT5640_DRC_AGC_1:
+        case RT5640_ANC_CTRL1:
+        case RT5640_IRQ_CTRL2:
+        case RT5640_INT_IRQ_ST:
+        case RT5640_DSP_CTRL2:
+        case RT5640_DSP_CTRL3:
+        case RT5640_PGM_REG_ARR1:
+        case RT5640_PGM_REG_ARR3:
+                return 1;
+        default:
+                return 0;
+        }
+}
+
+static int rt5640_readable_register(
+        struct snd_soc_codec *codec, unsigned int reg)
+{
+        switch (reg) {
+        case RT5640_RESET:
+        case RT5640_SPK_VOL:
+        case RT5640_HP_VOL:
+        case RT5640_OUTPUT:
+        case RT5640_MONO_OUT:
+        case RT5640_IN1_IN2:
+        case RT5640_IN3_IN4:
+        case RT5640_INL_INR_VOL:
+        case RT5640_DAC1_DIG_VOL:
+        case RT5640_DAC2_DIG_VOL:
+        case RT5640_DAC2_CTRL:
+        case RT5640_ADC_DIG_VOL:
+        case RT5640_ADC_DATA:
+        case RT5640_ADC_BST_VOL:
+        case RT5640_STO_ADC_MIXER:
+        case RT5640_MONO_ADC_MIXER:
+        case RT5640_AD_DA_MIXER:
+        case RT5640_STO_DAC_MIXER:
+        case RT5640_MONO_DAC_MIXER:
+        case RT5640_DIG_MIXER:
+        case RT5640_DSP_PATH1:
+        case RT5640_DSP_PATH2:
+        case RT5640_DIG_INF_DATA:
+        case RT5640_REC_L1_MIXER:
+        case RT5640_REC_L2_MIXER:
+        case RT5640_REC_R1_MIXER:
+        case RT5640_REC_R2_MIXER:
+        case RT5640_HPO_MIXER:
+        case RT5640_SPK_L_MIXER:
+        case RT5640_SPK_R_MIXER:
+        case RT5640_SPO_L_MIXER:
+        case RT5640_SPO_R_MIXER:
+        case RT5640_SPO_CLSD_RATIO:
+        case RT5640_MONO_MIXER:
+        case RT5640_OUT_L1_MIXER:
+        case RT5640_OUT_L2_MIXER:
+        case RT5640_OUT_L3_MIXER:
+        case RT5640_OUT_R1_MIXER:
+        case RT5640_OUT_R2_MIXER:
+        case RT5640_OUT_R3_MIXER:
+        case RT5640_LOUT_MIXER:
+        case RT5640_PWR_DIG1:
+        case RT5640_PWR_DIG2:
+        case RT5640_PWR_ANLG1:
+        case RT5640_PWR_ANLG2:
+        case RT5640_PWR_MIXER:
+        case RT5640_PWR_VOL:
+        case RT5640_PRIV_INDEX:
+        case RT5640_PRIV_DATA:
+        case RT5640_I2S1_SDP:
+        case RT5640_I2S2_SDP:
+        case RT5640_I2S3_SDP:
+        case RT5640_ADDA_CLK1:
+        case RT5640_ADDA_CLK2:
+        case RT5640_DMIC:
+        case RT5640_GLB_CLK:
+        case RT5640_PLL_CTRL1:
+        case RT5640_PLL_CTRL2:
+        case RT5640_ASRC_1:
+        case RT5640_ASRC_2:
+        case RT5640_ASRC_3:
+        case RT5640_ASRC_4:
+        case RT5640_ASRC_5:
+        case RT5640_HP_OVCD:
+        case RT5640_CLS_D_OVCD:
+        case RT5640_CLS_D_OUT:
+        case RT5640_DEPOP_M1:
+        case RT5640_DEPOP_M2:
+        case RT5640_DEPOP_M3:
+        case RT5640_CHARGE_PUMP:
+        case RT5640_PV_DET_SPK_G:
+        case RT5640_MICBIAS:
+        case RT5640_EQ_CTRL1:
+        case RT5640_EQ_CTRL2:
+        case RT5640_WIND_FILTER:
+        case RT5640_DRC_AGC_1:
+        case RT5640_DRC_AGC_2:
+        case RT5640_DRC_AGC_3:
+        case RT5640_SVOL_ZC:
+        case RT5640_ANC_CTRL1:
+        case RT5640_ANC_CTRL2:
+        case RT5640_ANC_CTRL3:
+        case RT5640_JD_CTRL:
+        case RT5640_ANC_JD:
+        case RT5640_IRQ_CTRL1:
+        case RT5640_IRQ_CTRL2:
+        case RT5640_INT_IRQ_ST:
+        case RT5640_GPIO_CTRL1:
+        case RT5640_GPIO_CTRL2:
+        case RT5640_GPIO_CTRL3:
+        case RT5640_DSP_CTRL1:
+        case RT5640_DSP_CTRL2:
+        case RT5640_DSP_CTRL3:
+        case RT5640_DSP_CTRL4:
+        case RT5640_PGM_REG_ARR1:
+        case RT5640_PGM_REG_ARR2:
+        case RT5640_PGM_REG_ARR3:
+        case RT5640_PGM_REG_ARR4:
+        case RT5640_PGM_REG_ARR5:
+        case RT5640_SCB_FUNC:
+        case RT5640_SCB_CTRL:
+        case RT5640_BASE_BACK:
+        case RT5640_MP3_PLUS1:
+        case RT5640_MP3_PLUS2:
+        case RT5640_3D_HP:
+        case RT5640_ADJ_HPF:
+        case RT5640_HP_CALIB_AMP_DET:
+        case RT5640_HP_CALIB2:
+        case RT5640_SV_ZCD1:
+        case RT5640_SV_ZCD2:
+        case RT5640_DUMMY1:
+        case RT5640_DUMMY2:
+        case RT5640_DUMMY3:
+        case RT5640_VENDOR_ID:
+        case RT5640_VENDOR_ID1:
+        case RT5640_VENDOR_ID2:
+                return 1;
+        default:
+                return 0;
+        }
+}
+
+int rt5640_headset_detect(struct snd_soc_codec *codec, int jack_insert)
+{
+        int jack_type;
+
+        if (jack_insert) {
+                snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                        RT5640_PWR_LDO2, RT5640_PWR_LDO2);
+                snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
+                        RT5640_PWR_MB1, RT5640_PWR_MB1);
+                snd_soc_update_bits(codec, RT5640_MICBIAS,
+                        RT5640_MIC1_OVCD_MASK | RT5640_MIC1_OVTH_MASK |
+                        RT5640_PWR_CLK25M_MASK | RT5640_PWR_MB_MASK,
+                        RT5640_MIC1_OVCD_EN | RT5640_MIC1_OVTH_600UA |
+                        RT5640_PWR_MB_PU | RT5640_PWR_CLK25M_PU);
+                snd_soc_update_bits(codec, RT5640_DUMMY1,
+                        0x1, 0x1);
+                msleep(50);
+                if (snd_soc_read(codec, RT5640_IRQ_CTRL2) & 0x8)
+                        jack_type = RT5640_HEADPHO_DET;
+                else
+                        jack_type = RT5640_HEADSET_DET;
+                snd_soc_update_bits(codec, RT5640_IRQ_CTRL2,
+                        RT5640_MB1_OC_CLR, 0);
+        } else {
+                snd_soc_update_bits(codec, RT5640_MICBIAS,
+                        RT5640_MIC1_OVCD_MASK,
+                        RT5640_MIC1_OVCD_DIS);
+
+                jack_type = RT5640_NO_JACK;
+        }
+
+        return jack_type;
+}
+EXPORT_SYMBOL(rt5640_headset_detect);
+
+static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
+static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
+
+/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
+static unsigned int bst_tlv[] = {
+        TLV_DB_RANGE_HEAD(7),
+        0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+        1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
+        2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
+        3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
+        6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
+        7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
+        8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
+};
+
+static int rt5640_dmic_get(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+
+        ucontrol->value.integer.value[0] = rt5640->dmic_en;
+
+        return 0;
+}
+
+static int rt5640_dmic_put(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+
+        if (rt5640->dmic_en == ucontrol->value.integer.value[0])
+                return 0;
+
+        rt5640->dmic_en = ucontrol->value.integer.value[0];
+        switch (rt5640->dmic_en) {
+        case RT5640_DMIC_DIS:
+                snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                        RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK |
+                        RT5640_GP4_PIN_MASK,
+                        RT5640_GP2_PIN_GPIO2 | RT5640_GP3_PIN_GPIO3 |
+                        RT5640_GP4_PIN_GPIO4);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_1_DP_MASK | RT5640_DMIC_2_DP_MASK,
+                        RT5640_DMIC_1_DP_GPIO3 | RT5640_DMIC_2_DP_GPIO4);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_1_EN_MASK | RT5640_DMIC_2_EN_MASK,
+                        RT5640_DMIC_1_DIS | RT5640_DMIC_2_DIS);
+                break;
+
+        case RT5640_DMIC1:
+                snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                        RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK,
+                        RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP3_PIN_DMIC1_SDA);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK |
+                        RT5640_DMIC_1_DP_MASK,
+                        RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING |
+                        RT5640_DMIC_1_DP_IN1P);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_1_EN_MASK, RT5640_DMIC_1_EN);
+                break;
+
+        case RT5640_DMIC2:
+                snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                        RT5640_GP2_PIN_MASK | RT5640_GP4_PIN_MASK,
+                        RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP4_PIN_DMIC2_SDA);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK |
+                        RT5640_DMIC_2_DP_MASK,
+                        RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING |
+                        RT5640_DMIC_2_DP_IN1N);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_2_EN_MASK, RT5640_DMIC_2_EN);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+
+/* IN1/IN2 Input Type */
+static const char *rt5640_input_mode[] = {
+        "Single ended", "Differential"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_in1_mode_enum, RT5640_IN1_IN2,
+        RT5640_IN_SFT1, rt5640_input_mode);
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_in2_mode_enum, RT5640_IN3_IN4,
+        RT5640_IN_SFT2, rt5640_input_mode);
+
+/* Interface data select */
+static const char *rt5640_data_select[] = {
+        "Normal", "left copy to right", "right copy to left", "Swap"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
+                                RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if1_adc_enum, RT5640_DIG_INF_DATA,
+                                RT5640_IF1_ADC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_dac_enum, RT5640_DIG_INF_DATA,
+                                RT5640_IF2_DAC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_enum, RT5640_DIG_INF_DATA,
+                                RT5640_IF2_ADC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if3_dac_enum, RT5640_DIG_INF_DATA,
+                                RT5640_IF3_DAC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if3_adc_enum, RT5640_DIG_INF_DATA,
+                                RT5640_IF3_ADC_SEL_SFT, rt5640_data_select);
+
+/* Class D speaker gain ratio */
+static const char *rt5640_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
+        "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_clsd_spk_ratio_enum, RT5640_CLS_D_OUT,
+        RT5640_CLSD_RATIO_SFT, rt5640_clsd_spk_ratio);
+
+/* DMIC */
+static const char *rt5640_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_dmic_enum, 0, 0, rt5640_dmic_mode);
+
+
+
+#ifdef RT5640_REG_RW
+#define REGVAL_MAX 0xffff
+static unsigned int regctl_addr;
+static int rt5640_regctl_info(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_info *uinfo) {
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+        uinfo->count = 2;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = REGVAL_MAX;
+        return 0;
+}
+
+static int rt5640_regctl_get(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        ucontrol->value.integer.value[0] = regctl_addr;
+        ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
+        return 0;
+}
+
+static int rt5640_regctl_put(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        regctl_addr = ucontrol->value.integer.value[0];
+        if (ucontrol->value.integer.value[1] <= REGVAL_MAX)
+                snd_soc_write(codec, regctl_addr,
+                ucontrol->value.integer.value[1]);
+        return 0;
+}
+#endif
+
+
+#define VOL_RESCALE_MAX_VOL 0x27 /* 39 */
+#define VOL_RESCALE_MIX_RANGE 0x1F /* 31 */
+
+static int rt5640_vol_rescale_get(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int val = snd_soc_read(codec, mc->reg);
+
+        ucontrol->value.integer.value[0] = VOL_RESCALE_MAX_VOL -
+                ((val & RT5640_L_VOL_MASK) >> mc->shift);
+        ucontrol->value.integer.value[1] = VOL_RESCALE_MAX_VOL -
+                (val & RT5640_R_VOL_MASK);
+
+        return 0;
+}
+
+static int rt5640_vol_rescale_put(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int val, val2;
+
+        val = VOL_RESCALE_MAX_VOL - ucontrol->value.integer.value[0];
+        val2 = VOL_RESCALE_MAX_VOL - ucontrol->value.integer.value[1];
+        return snd_soc_update_bits_locked(codec, mc->reg, RT5640_L_VOL_MASK |
+                        RT5640_R_VOL_MASK, val << mc->shift | val2);
+}
+
+
+static const struct snd_kcontrol_new rt5640_snd_controls[] = {
+        /* Speaker Output Volume */
+        SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5640_SPK_VOL,
+                RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, VOL_RESCALE_MIX_RANGE, 0,
+                rt5640_vol_rescale_get, rt5640_vol_rescale_put, out_vol_tlv),
+
+        /* Headphone Output Volume */
+        SOC_DOUBLE("HP Playback Switch", RT5640_HP_VOL,
+                RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
+
+        SOC_DOUBLE_EXT_TLV("HP Playback Volume", RT5640_HP_VOL,
+                RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, VOL_RESCALE_MIX_RANGE, 0,
+                rt5640_vol_rescale_get, rt5640_vol_rescale_put, out_vol_tlv),
+
+        /* OUTPUT Control */
+        SOC_DOUBLE("OUT Playback Switch", RT5640_OUTPUT,
+                RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
+        SOC_DOUBLE("OUT Channel Switch", RT5640_OUTPUT,
+                RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
+        SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
+                RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
+        /* MONO Output Control */
+        SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT,
+                                RT5640_L_MUTE_SFT, 1, 1),
+        /* DAC Digital Volume */
+        SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
+                RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
+        SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
+                        RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                        175, 0, dac_vol_tlv),
+        SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5640_DAC2_DIG_VOL,
+                        RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                        175, 0, dac_vol_tlv),
+        /* IN1/IN2 Control */
+        SOC_ENUM("IN1 Mode Control",  rt5640_in1_mode_enum),
+        SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
+                RT5640_BST_SFT1, 8, 0, bst_tlv),
+        SOC_ENUM("IN2 Mode Control", rt5640_in2_mode_enum),
+        SOC_SINGLE_TLV("IN2 Boost", RT5640_IN3_IN4,
+                RT5640_BST_SFT2, 8, 0, bst_tlv),
+        /* INL/INR Volume Control */
+        SOC_DOUBLE_TLV("IN Capture Volume", RT5640_INL_INR_VOL,
+                        RT5640_INL_VOL_SFT, RT5640_INR_VOL_SFT,
+                        31, 1, in_vol_tlv),
+        /* ADC Digital Volume Control */
+        SOC_DOUBLE("ADC Capture Switch", RT5640_ADC_DIG_VOL,
+                RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
+        SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
+                        RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                        127, 0, adc_vol_tlv),
+        SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
+                        RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                        127, 0, adc_vol_tlv),
+        /* ADC Boost Volume Control */
+        SOC_DOUBLE_TLV("ADC Boost Gain", RT5640_ADC_BST_VOL,
+                        RT5640_ADC_L_BST_SFT, RT5640_ADC_R_BST_SFT,
+                        3, 0, adc_bst_tlv),
+        /* Class D speaker gain ratio */
+        SOC_ENUM("Class D SPK Ratio Control", rt5640_clsd_spk_ratio_enum),
+        /* DMIC */
+        SOC_ENUM_EXT("DMIC Switch", rt5640_dmic_enum,
+                rt5640_dmic_get, rt5640_dmic_put),
+
+#ifdef RT5640_REG_RW
+        {
+                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+                .name = "Register Control",
+                .info = rt5640_regctl_info,
+                .get = rt5640_regctl_get,
+                .put = rt5640_regctl_put,
+        },
+#endif
+};
+
+/**
+ * set_dmic_clk - Set parameter of dmic.
+ *
+ * @w: DAPM widget.
+ * @kcontrol: The kcontrol of this widget.
+ * @event: Event id.
+ *
+ * Choose dmic clock between 1MHz and 3MHz.
+ * It is better for clock to approximate 3MHz.
+ */
+static int set_dmic_clk(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+        int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
+
+        rate = rt5640->lrck[rt5640->aif_pu] << 8;
+        red = 3000000 * 12;
+        for (i = 0; i < ARRAY_SIZE(div); i++) {
+                bound = div[i] * 3000000;
+                if (rate > bound)
+                        continue;
+                temp = bound - rate;
+                if (temp < red) {
+                        red = temp;
+                        idx = i;
+                }
+        }
+        if (idx < 0)
+                dev_err(codec->dev, "Failed to set DMIC clock\n");
+        else
+                snd_soc_update_bits(codec, RT5640_DMIC, RT5640_DMIC_CLK_MASK,
+                                        idx << RT5640_DMIC_CLK_SFT);
+        return idx;
+}
+
+static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
+                         struct snd_soc_dapm_widget *sink)
+{
+        unsigned int val;
+
+        val = snd_soc_read(source->codec, RT5640_GLB_CLK);
+        val &= RT5640_SCLK_SRC_MASK;
+        if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T)
+                return 1;
+        else
+                return 0;
+}
+
+/* Digital Mixer */
+static const struct snd_kcontrol_new rt5640_sto_adc_l_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
+                        RT5640_M_ADC_L1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
+                        RT5640_M_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_sto_adc_r_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
+                        RT5640_M_ADC_R1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
+                        RT5640_M_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_adc_l_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
+                        RT5640_M_MONO_ADC_L1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
+                        RT5640_M_MONO_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_adc_r_mix[] = {
+        SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
+                        RT5640_M_MONO_ADC_R1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
+                        RT5640_M_MONO_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dac_l_mix[] = {
+        SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
+                        RT5640_M_ADCMIX_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
+                        RT5640_M_IF1_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dac_r_mix[] = {
+        SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
+                        RT5640_M_ADCMIX_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
+                        RT5640_M_IF1_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_sto_dac_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
+                        RT5640_M_DAC_L1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
+                        RT5640_M_DAC_L2_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
+                        RT5640_M_ANC_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
+                        RT5640_M_DAC_R1_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
+                        RT5640_M_DAC_R2_SFT, 1, 1),
+        SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
+                        RT5640_M_ANC_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
+                        RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
+                        RT5640_M_DAC_L2_MONO_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
+                        RT5640_M_DAC_R2_MONO_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_dac_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
+                        RT5640_M_DAC_R1_MONO_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
+                        RT5640_M_DAC_R2_MONO_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
+                        RT5640_M_DAC_L2_MONO_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dig_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_DIG_MIXER,
+                        RT5640_M_STO_L_DAC_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
+                        RT5640_M_DAC_L2_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dig_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
+                        RT5640_M_STO_R_DAC_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
+                        RT5640_M_DAC_R2_DAC_R_SFT, 1, 1),
+};
+
+/* Analog Input Mixer */
+static const struct snd_kcontrol_new rt5640_rec_l_mix[] = {
+        SOC_DAPM_SINGLE("HPOL Switch", RT5640_REC_L2_MIXER,
+                        RT5640_M_HP_L_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INL Switch", RT5640_REC_L2_MIXER,
+                        RT5640_M_IN_L_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_L2_MIXER,
+                        RT5640_M_BST4_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_L2_MIXER,
+                        RT5640_M_BST1_RM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_REC_L2_MIXER,
+                        RT5640_M_OM_L_RM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_rec_r_mix[] = {
+        SOC_DAPM_SINGLE("HPOR Switch", RT5640_REC_R2_MIXER,
+                        RT5640_M_HP_R_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INR Switch", RT5640_REC_R2_MIXER,
+                        RT5640_M_IN_R_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_R2_MIXER,
+                        RT5640_M_BST4_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_R2_MIXER,
+                        RT5640_M_BST1_RM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_REC_R2_MIXER,
+                        RT5640_M_OM_R_RM_R_SFT, 1, 1),
+};
+
+/* Analog Output Mixer */
+static const struct snd_kcontrol_new rt5640_spk_l_mix[] = {
+        SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_SPK_L_MIXER,
+                        RT5640_M_RM_L_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INL Switch", RT5640_SPK_L_MIXER,
+                        RT5640_M_IN_L_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPK_L_MIXER,
+                        RT5640_M_DAC_L1_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
+                        RT5640_M_DAC_L2_SM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_SPK_L_MIXER,
+                        RT5640_M_OM_L_SM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_spk_r_mix[] = {
+        SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_SPK_R_MIXER,
+                        RT5640_M_RM_R_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INR Switch", RT5640_SPK_R_MIXER,
+                        RT5640_M_IN_R_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
+                        RT5640_M_DAC_R1_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
+                        RT5640_M_DAC_R2_SM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_SPK_R_MIXER,
+                        RT5640_M_OM_R_SM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_out_l_mix[] = {
+        SOC_DAPM_SINGLE("SPK MIXL Switch", RT5640_OUT_L3_MIXER,
+                        RT5640_M_SM_L_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
+                        RT5640_M_BST1_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
+                        RT5640_M_IN_L_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
+                        RT5640_M_RM_L_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
+                        RT5640_M_DAC_R2_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
+                        RT5640_M_DAC_L2_OM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
+                        RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
+        SOC_DAPM_SINGLE("SPK MIXR Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_SM_L_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_BST4_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_BST1_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_IN_R_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_RM_R_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_DAC_L2_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_DAC_R2_OM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
+                        RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
+                        RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPO_L_MIXER,
+                        RT5640_M_DAC_L1_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_L_MIXER,
+                        RT5640_M_SV_R_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("SPKVOL L Switch", RT5640_SPO_L_MIXER,
+                        RT5640_M_SV_L_SPM_L_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_L_MIXER,
+                        RT5640_M_BST1_SPM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_spo_r_mix[] = {
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
+                        RT5640_M_DAC_R1_SPM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_R_MIXER,
+                        RT5640_M_SV_R_SPM_R_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_R_MIXER,
+                        RT5640_M_BST1_SPM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
+        SOC_DAPM_SINGLE("DAC2 Switch", RT5640_HPO_MIXER,
+                        RT5640_M_DAC2_HM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC1 Switch", RT5640_HPO_MIXER,
+                        RT5640_M_DAC1_HM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("HPVOL Switch", RT5640_HPO_MIXER,
+                        RT5640_M_HPVOL_HM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_lout_mix[] = {
+        SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
+                        RT5640_M_DAC_L1_LM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
+                        RT5640_M_DAC_R1_LM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_LOUT_MIXER,
+                        RT5640_M_OV_L_LM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_LOUT_MIXER,
+                        RT5640_M_OV_R_LM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_mix[] = {
+        SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
+                        RT5640_M_DAC_R2_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
+                        RT5640_M_DAC_L2_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_MONO_MIXER,
+                        RT5640_M_OV_R_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_MONO_MIXER,
+                        RT5640_M_OV_L_MM_SFT, 1, 1),
+        SOC_DAPM_SINGLE("BST1 Switch", RT5640_MONO_MIXER,
+                        RT5640_M_BST1_MM_SFT, 1, 1),
+};
+
+/* INL/R source */
+static const char *rt5640_inl_src[] = {"IN2P", "MonoP"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_inl_enum, RT5640_INL_INR_VOL,
+        RT5640_INL_SEL_SFT, rt5640_inl_src);
+
+static const struct snd_kcontrol_new rt5640_inl_mux =
+        SOC_DAPM_ENUM("INL source", rt5640_inl_enum);
+
+static const char *rt5640_inr_src[] = {"IN2N", "MonoN"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_inr_enum, RT5640_INL_INR_VOL,
+        RT5640_INR_SEL_SFT, rt5640_inr_src);
+
+static const struct snd_kcontrol_new rt5640_inr_mux =
+        SOC_DAPM_ENUM("INR source", rt5640_inr_enum);
+
+/* Stereo ADC source */
+static const char *rt5640_stereo_adc1_src[] = {"DIG MIX", "ADC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_stereo_adc1_enum, RT5640_STO_ADC_MIXER,
+        RT5640_ADC_1_SRC_SFT, rt5640_stereo_adc1_src);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_l1_mux =
+        SOC_DAPM_ENUM("Stereo ADC L1 source", rt5640_stereo_adc1_enum);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_r1_mux =
+        SOC_DAPM_ENUM("Stereo ADC R1 source", rt5640_stereo_adc1_enum);
+
+static const char *rt5640_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_stereo_adc2_enum, RT5640_STO_ADC_MIXER,
+        RT5640_ADC_2_SRC_SFT, rt5640_stereo_adc2_src);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_l2_mux =
+        SOC_DAPM_ENUM("Stereo ADC L2 source", rt5640_stereo_adc2_enum);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_r2_mux =
+        SOC_DAPM_ENUM("Stereo ADC R2 source", rt5640_stereo_adc2_enum);
+
+/* Mono ADC source */
+static const char *rt5640_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_mono_adc_l1_enum, RT5640_MONO_ADC_MIXER,
+        RT5640_MONO_ADC_L1_SRC_SFT, rt5640_mono_adc_l1_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_l1_mux =
+        SOC_DAPM_ENUM("Mono ADC1 left source", rt5640_mono_adc_l1_enum);
+
+static const char *rt5640_mono_adc_l2_src[] = {
+        "DMIC L1", "DMIC L2", "Mono DAC MIXL"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_mono_adc_l2_enum, RT5640_MONO_ADC_MIXER,
+        RT5640_MONO_ADC_L2_SRC_SFT, rt5640_mono_adc_l2_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_l2_mux =
+        SOC_DAPM_ENUM("Mono ADC2 left source", rt5640_mono_adc_l2_enum);
+
+static const char *rt5640_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_mono_adc_r1_enum, RT5640_MONO_ADC_MIXER,
+        RT5640_MONO_ADC_R1_SRC_SFT, rt5640_mono_adc_r1_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_r1_mux =
+        SOC_DAPM_ENUM("Mono ADC1 right source", rt5640_mono_adc_r1_enum);
+
+static const char *rt5640_mono_adc_r2_src[] = {
+        "DMIC R1", "DMIC R2", "Mono DAC MIXR"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_mono_adc_r2_enum, RT5640_MONO_ADC_MIXER,
+        RT5640_MONO_ADC_R2_SRC_SFT, rt5640_mono_adc_r2_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_r2_mux =
+        SOC_DAPM_ENUM("Mono ADC2 right source", rt5640_mono_adc_r2_enum);
+
+/* DAC2 channel source */
+static const char *rt5640_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_dac_l2_enum, RT5640_DSP_PATH2,
+                                RT5640_DAC_L2_SEL_SFT, rt5640_dac_l2_src);
+
+static const struct snd_kcontrol_new rt5640_dac_l2_mux =
+        SOC_DAPM_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
+
+static const char *rt5640_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_dac_r2_enum, RT5640_DSP_PATH2,
+        RT5640_DAC_R2_SEL_SFT, rt5640_dac_r2_src);
+
+static const struct snd_kcontrol_new rt5640_dac_r2_mux =
+        SOC_DAPM_ENUM("DAC2 right channel source", rt5640_dac_r2_enum);
+
+/* Interface 2  ADC channel source */
+static const char *rt5640_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_l_enum, RT5640_DSP_PATH2,
+                        RT5640_IF2_ADC_L_SEL_SFT, rt5640_if2_adc_l_src);
+
+static const struct snd_kcontrol_new rt5640_if2_adc_l_mux =
+        SOC_DAPM_ENUM("IF2 ADC left channel source", rt5640_if2_adc_l_enum);
+
+static const char *rt5640_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_r_enum, RT5640_DSP_PATH2,
+                        RT5640_IF2_ADC_R_SEL_SFT, rt5640_if2_adc_r_src);
+
+static const struct snd_kcontrol_new rt5640_if2_adc_r_mux =
+        SOC_DAPM_ENUM("IF2 ADC right channel source", rt5640_if2_adc_r_enum);
+
+/* digital interface and iis interface map */
+static const char *rt5640_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
+        "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
+        "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_dai_iis_map_enum, RT5640_I2S1_SDP,
+        RT5640_I2S_IF_SFT, rt5640_dai_iis_map);
+
+static const struct snd_kcontrol_new rt5640_dai_mux =
+        SOC_DAPM_ENUM("DAI select", rt5640_dai_iis_map_enum);
+
+/* SDI select */
+static const char *rt5640_sdi_sel[] = {"IF1", "IF2"};
+
+static const SOC_ENUM_SINGLE_DECL(
+        rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
+        RT5640_I2S2_SDI_SFT, rt5640_sdi_sel);
+
+static const struct snd_kcontrol_new rt5640_sdi_mux =
+        SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
+
+static int spk_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        static unsigned int spkl_out_enable;
+        static unsigned int spkr_out_enable;
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                pr_info("spk_event --SND_SOC_DAPM_POST_PMU\n");
+                snd_soc_update_bits(codec, RT5640_PWR_DIG1, 0x0001, 0x0001);
+                rt5640_index_update_bits(codec, 0x1c, 0xf000, 0xf000);
+                /* rt5640_index_write(codec, 0x1c, 0xfd21); */
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                pr_info("spk_event --SND_SOC_DAPM_POST_PMD\n");
+                /* rt5640_index_write(codec, 0x1c, 0xfd00); */
+                rt5640_index_update_bits(codec, 0x1c, 0xf000, 0x0000);
+                snd_soc_update_bits(codec, RT5640_PWR_DIG1, 0x0001, 0x0000);
+                break;
+
+        default:
+                return 0;
+        }
+        return 0;
+}
+
+static int hp_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        struct snd_soc_codec *codec = w->codec;
+        static unsigned int hp_out_enable;
+
+        switch (event) {
+        case SND_SOC_DAPM_POST_PMU:
+                pr_info("hp_event --SND_SOC_DAPM_POST_PMU\n");
+                break;
+
+        case SND_SOC_DAPM_PRE_PMD:
+                pr_info("hp_event --SND_SOC_DAPM_POST_PMD\n");
+                break;
+
+        default:
+                return 0;
+        }
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
+        SND_SOC_DAPM_SUPPLY("PLL1", RT5640_PWR_ANLG2,
+                        RT5640_PWR_PLL_BIT, 0, NULL, 0),
+        /* Input Side */
+        /* micbias */
+        SND_SOC_DAPM_SUPPLY("LDO2", RT5640_PWR_ANLG1,
+                        RT5640_PWR_LDO2_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MICBIAS("micbias1", RT5640_PWR_ANLG2,
+                        RT5640_PWR_MB1_BIT, 0),
+        SND_SOC_DAPM_MICBIAS("micbias2", RT5640_PWR_ANLG2,
+                        RT5640_PWR_MB2_BIT, 0),
+        /* Input Lines */
+
+        SND_SOC_DAPM_INPUT("MIC1"),
+        SND_SOC_DAPM_INPUT("MIC2"),
+        SND_SOC_DAPM_INPUT("DMIC1"),
+        SND_SOC_DAPM_INPUT("DMIC2"),
+        SND_SOC_DAPM_INPUT("IN1P"),
+        SND_SOC_DAPM_INPUT("IN1N"),
+        SND_SOC_DAPM_INPUT("IN2P"),
+        SND_SOC_DAPM_INPUT("IN2N"),
+        SND_SOC_DAPM_INPUT("DMIC L1"),
+        SND_SOC_DAPM_INPUT("DMIC R1"),
+        SND_SOC_DAPM_INPUT("DMIC L2"),
+        SND_SOC_DAPM_INPUT("DMIC R2"),
+        SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
+                set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
+        /* Boost */
+        SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
+                RT5640_PWR_BST1_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("BST2", RT5640_PWR_ANLG2,
+                RT5640_PWR_BST4_BIT, 0, NULL, 0),
+        /* Input Volume */
+        SND_SOC_DAPM_PGA("INL VOL", RT5640_PWR_VOL,
+                RT5640_PWR_IN_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("INR VOL", RT5640_PWR_VOL,
+                RT5640_PWR_IN_R_BIT, 0, NULL, 0),
+        /* IN Mux */
+        SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt5640_inl_mux),
+        SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt5640_inr_mux),
+        /* REC Mixer */
+        SND_SOC_DAPM_MIXER("RECMIXL", RT5640_PWR_MIXER, RT5640_PWR_RM_L_BIT, 0,
+                        rt5640_rec_l_mix, ARRAY_SIZE(rt5640_rec_l_mix)),
+        SND_SOC_DAPM_MIXER("RECMIXR", RT5640_PWR_MIXER, RT5640_PWR_RM_R_BIT, 0,
+                        rt5640_rec_r_mix, ARRAY_SIZE(rt5640_rec_r_mix)),
+        /* ADCs */
+        SND_SOC_DAPM_ADC("ADC L", NULL, RT5640_PWR_DIG1,
+                        RT5640_PWR_ADC_L_BIT, 0),
+        SND_SOC_DAPM_ADC("ADC R", NULL, RT5640_PWR_DIG1,
+                        RT5640_PWR_ADC_R_BIT, 0),
+        /* ADC Mux */
+        SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_sto_adc_l2_mux),
+        SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_sto_adc_r2_mux),
+        SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_sto_adc_l1_mux),
+        SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_sto_adc_r1_mux),
+        SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_mono_adc_l2_mux),
+        SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_mono_adc_l1_mux),
+        SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_mono_adc_r1_mux),
+        SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_mono_adc_r2_mux),
+        /* ADC Mixer */
+        SND_SOC_DAPM_SUPPLY("stereo filter", RT5640_PWR_DIG2,
+                RT5640_PWR_ADC_SF_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5640_sto_adc_l_mix, ARRAY_SIZE(rt5640_sto_adc_l_mix)),
+        SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5640_sto_adc_r_mix, ARRAY_SIZE(rt5640_sto_adc_r_mix)),
+        SND_SOC_DAPM_SUPPLY("mono left filter", RT5640_PWR_DIG2,
+                RT5640_PWR_ADC_MF_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5640_mono_adc_l_mix, ARRAY_SIZE(rt5640_mono_adc_l_mix)),
+        SND_SOC_DAPM_SUPPLY("mono right filter", RT5640_PWR_DIG2,
+                RT5640_PWR_ADC_MF_R_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5640_mono_adc_r_mix, ARRAY_SIZE(rt5640_mono_adc_r_mix)),
+
+        /* IF2 Mux */
+        SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_if2_adc_l_mux),
+        SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_if2_adc_r_mux),
+
+        /* Digital Interface */
+        SND_SOC_DAPM_SUPPLY("I2S1", RT5640_PWR_DIG1,
+                RT5640_PWR_I2S1_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("I2S2", RT5640_PWR_DIG1,
+                RT5640_PWR_I2S2_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("I2S3", RT5640_PWR_DIG1,
+                RT5640_PWR_I2S3_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        /* Digital Interface Select */
+        SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
+
+        SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
+
+        SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+        SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+
+        /* Audio Interface */
+        SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
+
+        /* Audio DSP */
+        SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        /* ANC */
+        SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        /* Output Side */
+        /* DAC mixer before sound effect  */
+        SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
+        SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
+
+        /* DAC2 channel Mux */
+        SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_dac_l2_mux),
+        SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
+                                &rt5640_dac_r2_mux),
+
+        /* DAC Mixer */
+        SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
+        SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
+        SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
+                rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
+        SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
+                rt5640_mono_dac_r_mix, ARRAY_SIZE(rt5640_mono_dac_r_mix)),
+        SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
+                rt5640_dig_l_mix, ARRAY_SIZE(rt5640_dig_l_mix)),
+        SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
+                rt5640_dig_r_mix, ARRAY_SIZE(rt5640_dig_r_mix)),
+        /* DACs */
+        SND_SOC_DAPM_DAC("DAC L1", NULL, RT5640_PWR_DIG1,
+                        RT5640_PWR_DAC_L1_BIT, 0),
+        SND_SOC_DAPM_DAC("DAC L2", NULL, RT5640_PWR_DIG1,
+                        RT5640_PWR_DAC_L2_BIT, 0),
+        SND_SOC_DAPM_DAC("DAC R1", NULL, RT5640_PWR_DIG1,
+                        RT5640_PWR_DAC_R1_BIT, 0),
+        SND_SOC_DAPM_DAC("DAC R2", NULL, RT5640_PWR_DIG1,
+                        RT5640_PWR_DAC_R2_BIT, 0),
+        /* SPK/OUT Mixer */
+        SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
+                0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
+        SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
+                0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
+        SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
+                0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
+        SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
+                0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
+        /* Ouput Volume */
+        SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
+                RT5640_PWR_SV_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("SPKVOL R", RT5640_PWR_VOL,
+                RT5640_PWR_SV_R_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("OUTVOL L", RT5640_PWR_VOL,
+                RT5640_PWR_OV_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("OUTVOL R", RT5640_PWR_VOL,
+                RT5640_PWR_OV_R_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("HPOVOL L", RT5640_PWR_VOL,
+                RT5640_PWR_HV_L_BIT, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("HPOVOL R", RT5640_PWR_VOL,
+                RT5640_PWR_HV_R_BIT, 0, NULL, 0),
+        /* SPO/HPO/LOUT/Mono Mixer */
+        SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
+                0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
+        SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
+                0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
+
+        SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
+                rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
+        SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
+                rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
+        SND_SOC_DAPM_MIXER("LOUT MIX", RT5640_PWR_ANLG1, RT5640_PWR_LM_BIT, 0,
+                rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
+        SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
+                rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
+
+        SND_SOC_DAPM_SUPPLY("Improve mono amp drv", RT5640_PWR_ANLG1,
+                RT5640_PWR_MA_BIT, 0, NULL, 0),
+
+        SND_SOC_DAPM_SUPPLY("Improve HP amp drv", RT5640_PWR_ANLG1,
+        SND_SOC_NOPM, 0, hp_event, SND_SOC_DAPM_PRE_PMD |
+                                        SND_SOC_DAPM_POST_PMU),
+
+        SND_SOC_DAPM_PGA("HP L amp", RT5640_PWR_ANLG1,
+                RT5640_PWR_HP_L_BIT, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("HP R amp", RT5640_PWR_ANLG1,
+                RT5640_PWR_HP_R_BIT, 0, NULL, 0),
+
+        SND_SOC_DAPM_SUPPLY("Improve SPK amp drv", RT5640_PWR_DIG1,
+                SND_SOC_NOPM, 0, spk_event,
+                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+
+        /* Output Lines */
+        SND_SOC_DAPM_OUTPUT("SPOLP"),
+        SND_SOC_DAPM_OUTPUT("SPOLN"),
+        SND_SOC_DAPM_OUTPUT("SPORP"),
+        SND_SOC_DAPM_OUTPUT("SPORN"),
+        SND_SOC_DAPM_OUTPUT("HPOL"),
+        SND_SOC_DAPM_OUTPUT("HPOR"),
+        SND_SOC_DAPM_OUTPUT("LOUTL"),
+        SND_SOC_DAPM_OUTPUT("LOUTR"),
+        SND_SOC_DAPM_OUTPUT("MonoP"),
+        SND_SOC_DAPM_OUTPUT("MonoN"),
+};
+
+static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
+        {"IN1P", NULL, "LDO2"},
+        {"IN2P", NULL, "LDO2"},
+
+        {"IN1P", NULL, "MIC1"},
+        {"IN1N", NULL, "MIC1"},
+        {"IN2P", NULL, "MIC2"},
+        {"IN2N", NULL, "MIC2"},
+
+        {"DMIC L1", NULL, "DMIC1"},
+        {"DMIC R1", NULL, "DMIC1"},
+        {"DMIC L2", NULL, "DMIC2"},
+        {"DMIC R2", NULL, "DMIC2"},
+
+        {"BST1", NULL, "IN1P"},
+        {"BST1", NULL, "IN1N"},
+        {"BST2", NULL, "IN2P"},
+        {"BST2", NULL, "IN2N"},
+
+        {"INL VOL", NULL, "IN2P"},
+        {"INR VOL", NULL, "IN2N"},
+
+        {"RECMIXL", "HPOL Switch", "HPOL"},
+        {"RECMIXL", "INL Switch", "INL VOL"},
+        {"RECMIXL", "BST2 Switch", "BST2"},
+        {"RECMIXL", "BST1 Switch", "BST1"},
+        {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
+
+        {"RECMIXR", "HPOR Switch", "HPOR"},
+        {"RECMIXR", "INR Switch", "INR VOL"},
+        {"RECMIXR", "BST2 Switch", "BST2"},
+        {"RECMIXR", "BST1 Switch", "BST1"},
+        {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+        {"ADC L", NULL, "RECMIXL"},
+        {"ADC R", NULL, "RECMIXR"},
+
+        {"DMIC L1", NULL, "DMIC CLK"},
+        {"DMIC L2", NULL, "DMIC CLK"},
+
+        {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
+        {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
+        {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
+        {"Stereo ADC L1 Mux", "ADC", "ADC L"},
+        {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
+
+        {"Stereo ADC R1 Mux", "ADC", "ADC R"},
+        {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
+        {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
+        {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
+        {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
+
+        {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
+        {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
+        {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+        {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+        {"Mono ADC L1 Mux", "ADCL", "ADC L"},
+
+        {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+        {"Mono ADC R1 Mux", "ADCR", "ADC R"},
+        {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
+        {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
+        {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+
+        {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
+        {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
+        {"Stereo ADC MIXL", NULL, "stereo filter"},
+        {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
+        {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
+        {"Stereo ADC MIXR", NULL, "stereo filter"},
+        {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
+        {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
+        {"Mono ADC MIXL", NULL, "mono left filter"},
+        {"mono left filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
+        {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
+        {"Mono ADC MIXR", NULL, "mono right filter"},
+        {"mono right filter", NULL, "PLL1", check_sysclk1_source},
+
+        {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
+        {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
+
+        {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
+        {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
+        {"IF3 ADC L", NULL, "Mono ADC MIXL"},
+        {"IF3 ADC R", NULL, "Mono ADC MIXR"},
+        {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
+        {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
+
+        {"IF1 ADC", NULL, "I2S1"},
+        {"IF1 ADC", NULL, "IF1 ADC L"},
+        {"IF1 ADC", NULL, "IF1 ADC R"},
+        {"IF2 ADC", NULL, "I2S2"},
+        {"IF2 ADC", NULL, "IF2 ADC L"},
+        {"IF2 ADC", NULL, "IF2 ADC R"},
+        {"IF3 ADC", NULL, "I2S3"},
+        {"IF3 ADC", NULL, "IF3 ADC L"},
+        {"IF3 ADC", NULL, "IF3 ADC R"},
+
+        {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
+        {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
+        {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
+        {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
+        {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
+        {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
+        {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
+        {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
+        {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
+        {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
+
+        {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
+        {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
+        {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
+        {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
+        {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
+        {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
+        {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
+        {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
+        {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
+        {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
+
+        {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
+        {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
+        {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
+        {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
+        {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
+        {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
+        {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
+        {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
+
+        {"AIF1TX", NULL, "DAI1 TX Mux"},
+        {"AIF1TX", NULL, "SDI1 TX Mux"},
+        {"AIF2TX", NULL, "DAI2 TX Mux"},
+        {"AIF2TX", NULL, "SDI2 TX Mux"},
+        {"AIF3TX", NULL, "DAI3 TX Mux"},
+
+        {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
+        {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
+        {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+        {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
+        {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
+        {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+        {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
+        {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
+
+        {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
+        {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
+        {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+        {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
+        {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
+        {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+        {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
+        {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
+
+        {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
+        {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
+        {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
+        {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
+        {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
+        {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
+        {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
+        {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
+
+        {"IF1 DAC", NULL, "I2S1"},
+        {"IF1 DAC", NULL, "DAI1 RX Mux"},
+        {"IF2 DAC", NULL, "I2S2"},
+        {"IF2 DAC", NULL, "DAI2 RX Mux"},
+        {"IF3 DAC", NULL, "I2S3"},
+        {"IF3 DAC", NULL, "DAI3 RX Mux"},
+
+        {"IF1 DAC L", NULL, "IF1 DAC"},
+        {"IF1 DAC R", NULL, "IF1 DAC"},
+        {"IF2 DAC L", NULL, "IF2 DAC"},
+        {"IF2 DAC R", NULL, "IF2 DAC"},
+        {"IF3 DAC L", NULL, "IF3 DAC"},
+        {"IF3 DAC R", NULL, "IF3 DAC"},
+
+        {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
+        {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
+        {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
+        {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
+
+        {"ANC", NULL, "Stereo ADC MIXL"},
+        {"ANC", NULL, "Stereo ADC MIXR"},
+
+        {"Audio DSP", NULL, "DAC MIXL"},
+        {"Audio DSP", NULL, "DAC MIXR"},
+
+        {"DAC L2 Mux", "IF2", "IF2 DAC L"},
+        {"DAC L2 Mux", "IF3", "IF3 DAC L"},
+        {"DAC L2 Mux", "Base L/R", "Audio DSP"},
+
+        {"DAC R2 Mux", "IF2", "IF2 DAC R"},
+        {"DAC R2 Mux", "IF3", "IF3 DAC R"},
+
+        {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+        {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+        {"Stereo DAC MIXL", "ANC Switch", "ANC"},
+        {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+        {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+        {"Stereo DAC MIXR", "ANC Switch", "ANC"},
+
+        {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+        {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+        {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
+        {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+        {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+        {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
+
+        {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
+        {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+        {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
+        {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+
+        {"DAC L1", NULL, "Stereo DAC MIXL"},
+        {"DAC L1", NULL, "PLL1", check_sysclk1_source},
+        {"DAC R1", NULL, "Stereo DAC MIXR"},
+        {"DAC R1", NULL, "PLL1", check_sysclk1_source},
+        {"DAC L2", NULL, "Mono DAC MIXL"},
+        {"DAC L2", NULL, "PLL1", check_sysclk1_source},
+        {"DAC R2", NULL, "Mono DAC MIXR"},
+        {"DAC R2", NULL, "PLL1", check_sysclk1_source},
+
+        {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
+        {"SPK MIXL", "INL Switch", "INL VOL"},
+        {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
+        {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
+        {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
+        {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
+        {"SPK MIXR", "INR Switch", "INR VOL"},
+        {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
+        {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
+        {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+        {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
+        {"OUT MIXL", "BST1 Switch", "BST1"},
+        {"OUT MIXL", "INL Switch", "INL VOL"},
+        {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
+        {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
+        {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
+        {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
+
+        {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
+        {"OUT MIXR", "BST2 Switch", "BST2"},
+        {"OUT MIXR", "BST1 Switch", "BST1"},
+        {"OUT MIXR", "INR Switch", "INR VOL"},
+        {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
+        {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
+        {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
+        {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
+
+        {"SPKVOL L", NULL, "SPK MIXL"},
+        {"SPKVOL R", NULL, "SPK MIXR"},
+        {"HPOVOL L", NULL, "OUT MIXL"},
+        {"HPOVOL R", NULL, "OUT MIXR"},
+        {"OUTVOL L", NULL, "OUT MIXL"},
+        {"OUTVOL R", NULL, "OUT MIXR"},
+
+        {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
+        {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
+        {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
+        {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
+        {"SPOL MIX", "BST1 Switch", "BST1"},
+        {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
+        {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
+        {"SPOR MIX", "BST1 Switch", "BST1"},
+
+        {"HPOL MIX", "DAC2 Switch", "DAC L2"},
+        {"HPOL MIX", "DAC1 Switch", "DAC L1"},
+        {"HPOL MIX", "HPVOL Switch", "HPOVOL L"},
+        {"HPOR MIX", "DAC2 Switch", "DAC R2"},
+        {"HPOR MIX", "DAC1 Switch", "DAC R1"},
+        {"HPOR MIX", "HPVOL Switch", "HPOVOL R"},
+
+        {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
+        {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
+        {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
+        {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
+
+        {"Mono MIX", "DAC R2 Switch", "DAC R2"},
+        {"Mono MIX", "DAC L2 Switch", "DAC L2"},
+        {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
+        {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
+        {"Mono MIX", "BST1 Switch", "BST1"},
+
+        {"HP L amp", NULL, "HPOL MIX"},
+        {"HP R amp", NULL, "HPOR MIX"},
+
+/*      {"HP L amp", NULL, "Improve HP amp drv"},
+        {"HP R amp", NULL, "Improve HP amp drv"}, */
+
+        {"SPOLP", NULL, "SPOL MIX"},
+        {"SPOLN", NULL, "SPOL MIX"},
+        {"SPORP", NULL, "SPOR MIX"},
+        {"SPORN", NULL, "SPOR MIX"},
+
+        {"SPOLP", NULL, "Improve SPK amp drv"},
+        {"SPOLN", NULL, "Improve SPK amp drv"},
+        {"SPORP", NULL, "Improve SPK amp drv"},
+        {"SPORN", NULL, "Improve SPK amp drv"},
+
+        {"HPOL", NULL, "Improve HP amp drv"},
+        {"HPOR", NULL, "Improve HP amp drv"},
+
+        {"HPOL", NULL, "HP L amp"},
+        {"HPOR", NULL, "HP R amp"},
+        {"LOUTL", NULL, "LOUT MIX"},
+        {"LOUTR", NULL, "LOUT MIX"},
+        {"MonoP", NULL, "Mono MIX"},
+        {"MonoN", NULL, "Mono MIX"},
+        {"MonoP", NULL, "Improve mono amp drv"},
+};
+
+static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
+{
+        int ret = 0, val = snd_soc_read(codec, RT5640_I2S1_SDP);
+
+        if (codec == NULL)
+                return -EINVAL;
+
+        val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT;
+        switch (dai_id) {
+        case RT5640_AIF1:
+                if (val == RT5640_IF_123 || val == RT5640_IF_132 ||
+                        val == RT5640_IF_113)
+                        ret |= RT5640_U_IF1;
+                if (val == RT5640_IF_312 || val == RT5640_IF_213 ||
+                        val == RT5640_IF_113)
+                        ret |= RT5640_U_IF2;
+                if (val == RT5640_IF_321 || val == RT5640_IF_231)
+                        ret |= RT5640_U_IF3;
+                break;
+
+        case RT5640_AIF2:
+                if (val == RT5640_IF_231 || val == RT5640_IF_213 ||
+                        val == RT5640_IF_223)
+                        ret |= RT5640_U_IF1;
+                if (val == RT5640_IF_123 || val == RT5640_IF_321 ||
+                        val == RT5640_IF_223)
+                        ret |= RT5640_U_IF2;
+                if (val == RT5640_IF_132 || val == RT5640_IF_312)
+                        ret |= RT5640_U_IF3;
+                break;
+
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                        CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+
+        case RT5640_AIF3:
+                if (val == RT5640_IF_312 || val == RT5640_IF_321)
+                        ret |= RT5640_U_IF1;
+                if (val == RT5640_IF_132 || val == RT5640_IF_231)
+                        ret |= RT5640_U_IF2;
+                if (val == RT5640_IF_123 || val == RT5640_IF_213 ||
+                        val == RT5640_IF_113 || val == RT5640_IF_223)
+                        ret |= RT5640_U_IF3;
+                break;
+#endif
+
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
+static int get_clk_info(int sclk, int rate)
+{
+        int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
+
+        if (sclk <= 0 || rate <= 0)
+                return -EINVAL;
+
+        rate = rate << 8;
+        for (i = 0; i < ARRAY_SIZE(pd); i++)
+                if (sclk == rate * pd[i])
+                        return i;
+
+        return -EINVAL;
+}
+
+static int rt5640_hw_params(struct snd_pcm_substream *substream,
+        struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+        unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
+        int pre_div, bclk_ms, frame_size;
+
+        rt5640->lrck[dai->id] = params_rate(params);
+        pre_div = get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
+        if (pre_div < 0) {
+                dev_err(codec->dev, "Unsupported clock setting\n");
+                return -EINVAL;
+        }
+        frame_size = snd_soc_params_to_frame_size(params);
+        if (frame_size < 0) {
+                dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
+                return -EINVAL;
+        }
+        bclk_ms = frame_size > 32 ? 1 : 0;
+        rt5640->bclk[dai->id] = rt5640->lrck[dai->id] * (32 << bclk_ms);
+
+        dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
+                rt5640->bclk[dai->id], rt5640->lrck[dai->id]);
+        dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
+                                bclk_ms, pre_div, dai->id);
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                val_len |= RT5640_I2S_DL_20;
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                val_len |= RT5640_I2S_DL_24;
+                break;
+        case SNDRV_PCM_FORMAT_S8:
+                val_len |= RT5640_I2S_DL_8;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        dai_sel = get_sdp_info(codec, dai->id);
+        if (dai_sel < 0) {
+                dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+                return -EINVAL;
+        }
+        if (dai_sel & RT5640_U_IF1) {
+                mask_clk = RT5640_I2S_BCLK_MS1_MASK | RT5640_I2S_PD1_MASK;
+                val_clk = bclk_ms << RT5640_I2S_BCLK_MS1_SFT |
+                        pre_div << RT5640_I2S_PD1_SFT;
+                snd_soc_update_bits(codec, RT5640_I2S1_SDP,
+                        RT5640_I2S_DL_MASK, val_len);
+                snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
+        }
+        if (dai_sel & RT5640_U_IF2) {
+                mask_clk = RT5640_I2S_BCLK_MS2_MASK | RT5640_I2S_PD2_MASK;
+                val_clk = bclk_ms << RT5640_I2S_BCLK_MS2_SFT |
+                        pre_div << RT5640_I2S_PD2_SFT;
+                snd_soc_update_bits(codec, RT5640_I2S2_SDP,
+                        RT5640_I2S_DL_MASK, val_len);
+                snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
+        }
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                        CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+        if (dai_sel & RT5640_U_IF3) {
+                mask_clk = RT5640_I2S_BCLK_MS3_MASK | RT5640_I2S_PD3_MASK;
+                val_clk = bclk_ms << RT5640_I2S_BCLK_MS3_SFT |
+                        pre_div << RT5640_I2S_PD3_SFT;
+                snd_soc_update_bits(codec, RT5640_I2S3_SDP,
+                        RT5640_I2S_DL_MASK, val_len);
+                snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
+        }
+#endif
+        return 0;
+}
+
+static int rt5640_prepare(struct snd_pcm_substream *substream,
+                                struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+
+        rt5640->aif_pu = dai->id;
+        return 0;
+}
+
+static int rt5640_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+        unsigned int reg_val = 0, dai_sel;
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                rt5640->master[dai->id] = 1;
+                break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                reg_val |= RT5640_I2S_MS_S;
+                rt5640->master[dai->id] = 0;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                reg_val |= RT5640_I2S_BP_INV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                reg_val |= RT5640_I2S_DF_LEFT;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+                reg_val |= RT5640_I2S_DF_PCM_A;
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                reg_val  |= RT5640_I2S_DF_PCM_B;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        dai_sel = get_sdp_info(codec, dai->id);
+        if (dai_sel < 0) {
+                dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+                return -EINVAL;
+        }
+        if (dai_sel & RT5640_U_IF1) {
+                snd_soc_update_bits(codec, RT5640_I2S1_SDP,
+                        RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
+                        RT5640_I2S_DF_MASK, reg_val);
+        }
+        if (dai_sel & RT5640_U_IF2) {
+                snd_soc_update_bits(codec, RT5640_I2S2_SDP,
+                        RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
+                        RT5640_I2S_DF_MASK, reg_val);
+        }
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                        CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+        if (dai_sel & RT5640_U_IF3) {
+                snd_soc_update_bits(codec, RT5640_I2S3_SDP,
+                        RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
+                        RT5640_I2S_DF_MASK, reg_val);
+        }
+#endif
+        return 0;
+}
+
+static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
+                int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+        unsigned int reg_val = 0;
+
+        if (freq == rt5640->sysclk && clk_id == rt5640->sysclk_src)
+                return 0;
+
+        switch (clk_id) {
+        case RT5640_SCLK_S_MCLK:
+                reg_val |= RT5640_SCLK_SRC_MCLK;
+                break;
+        case RT5640_SCLK_S_PLL1:
+                reg_val |= RT5640_SCLK_SRC_PLL1;
+                break;
+        case RT5640_SCLK_S_PLL1_TK:
+                reg_val |= RT5640_SCLK_SRC_PLL1T;
+                break;
+        case RT5640_SCLK_S_RCCLK:
+                reg_val |= RT5640_SCLK_SRC_RCCLK;
+                break;
+        default:
+                dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
+                return -EINVAL;
+        }
+        snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                RT5640_SCLK_SRC_MASK, reg_val);
+        rt5640->sysclk = freq;
+        rt5640->sysclk_src = clk_id;
+
+        dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
+        return 0;
+}
+
+/**
+ * rt5640_pll_calc - Calcualte PLL M/N/K code.
+ * @freq_in: external clock provided to codec.
+ * @freq_out: target clock which codec works on.
+ * @pll_code: Pointer to structure with M, N, K and bypass flag.
+ *
+ * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
+ * which make calculation more efficiently.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt5640_pll_calc(const unsigned int freq_in,
+        const unsigned int freq_out, struct rt5640_pll_code *pll_code)
+{
+        int max_n = RT5640_PLL_N_MAX, max_m = RT5640_PLL_M_MAX;
+        int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
+        bool bypass = false;
+
+        if (RT5640_PLL_INP_MAX < freq_in || RT5640_PLL_INP_MIN > freq_in)
+                return -EINVAL;
+
+        for (n_t = 0; n_t <= max_n; n_t++) {
+                in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
+                if (in_t < 0)
+                        continue;
+                if (in_t == freq_out) {
+                        bypass = true;
+                        n = n_t;
+                        goto code_find;
+                }
+                for (m_t = 0; m_t <= max_m; m_t++) {
+                        out_t = in_t / (m_t + 2);
+                        red = abs(out_t - freq_out);
+                        if (red < red_t) {
+                                n = n_t;
+                                m = m_t;
+                                if (red == 0)
+                                        goto code_find;
+                                red_t = red;
+                        }
+                }
+        }
+        pr_debug("Only get approximation about PLL\n");
+
+code_find:
+
+        pll_code->m_bp = bypass;
+        pll_code->m_code = m;
+        pll_code->n_code = n;
+        pll_code->k_code = 2;
+        return 0;
+}
+
+static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
+                        unsigned int freq_in, unsigned int freq_out)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+        struct rt5640_pll_code pll_code;
+        int ret, dai_sel;
+
+        if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
+            freq_out == rt5640->pll_out)
+                return 0;
+
+        if (!freq_in || !freq_out) {
+                dev_dbg(codec->dev, "PLL disabled\n");
+
+                rt5640->pll_in = 0;
+                rt5640->pll_out = 0;
+                snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                        RT5640_SCLK_SRC_MASK, RT5640_SCLK_SRC_MCLK);
+                return 0;
+        }
+
+        switch (source) {
+        case RT5640_PLL1_S_MCLK:
+                snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                        RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_MCLK);
+                break;
+        case RT5640_PLL1_S_BCLK1:
+        case RT5640_PLL1_S_BCLK2:
+
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                        CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+
+        case RT5640_PLL1_S_BCLK3:
+
+#endif
+                dai_sel = get_sdp_info(codec, dai->id);
+                if (dai_sel < 0) {
+                        dev_err(codec->dev,
+                                "Failed to get sdp info: %d\n", dai_sel);
+                        return -EINVAL;
+                }
+                if (dai_sel & RT5640_U_IF1) {
+                        snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                                RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK1);
+                }
+                if (dai_sel & RT5640_U_IF2) {
+                        snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                                RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK2);
+                }
+                if (dai_sel & RT5640_U_IF3) {
+                        snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                                RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK3);
+                }
+                break;
+        default:
+                dev_err(codec->dev, "Unknown PLL source %d\n", source);
+                return -EINVAL;
+        }
+
+        ret = rt5640_pll_calc(freq_in, freq_out, &pll_code);
+        if (ret < 0) {
+                dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
+                return ret;
+        }
+
+        dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
+                (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
+
+        snd_soc_write(codec, RT5640_PLL_CTRL1,
+                pll_code.n_code << RT5640_PLL_N_SFT | pll_code.k_code);
+        snd_soc_write(codec, RT5640_PLL_CTRL2,
+                (pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT |
+                pll_code.m_bp << RT5640_PLL_M_BP_SFT);
+
+        rt5640->pll_in = freq_in;
+        rt5640->pll_out = freq_out;
+        rt5640->pll_src = source;
+
+        return 0;
+}
+
+/**
+ * rt5640_index_show - Dump private registers.
+ * @dev: codec device.
+ * @attr: device attribute.
+ * @buf: buffer for display.
+ *
+ * To show non-zero values of all private registers.
+ *
+ * Returns buffer length.
+ */
+static ssize_t rt5640_index_show(struct device *dev,
+        struct device_attribute *attr, char *buf)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct rt5640_priv *rt5640 = i2c_get_clientdata(client);
+        struct snd_soc_codec *codec = rt5640->codec;
+        unsigned int val;
+        int cnt = 0, i;
+
+        cnt += sprintf(buf, "RT5640 index register\n");
+        for (i = 0; i < 0xb4; i++) {
+                if (cnt + 9 >= PAGE_SIZE - 1)
+                        break;
+                val = rt5640_index_read(codec, i);
+                if (!val)
+                        continue;
+                cnt += snprintf(buf + cnt, 10, "%02x: %04x\n", i, val);
+        }
+
+        if (cnt >= PAGE_SIZE)
+                cnt = PAGE_SIZE - 1;
+
+        return cnt;
+}
+static DEVICE_ATTR(index_reg, 0444, rt5640_index_show, NULL);
+
+static int rt5640_set_bias_level(struct snd_soc_codec *codec,
+                        enum snd_soc_bias_level level)
+{
+        switch (level) {
+        case SND_SOC_BIAS_ON:
+#ifdef RT5640_DEMO
+                snd_soc_update_bits(codec, RT5640_SPK_VOL,
+                        RT5640_L_MUTE | RT5640_R_MUTE, 0);
+                snd_soc_update_bits(codec, RT5640_HP_VOL,
+                        RT5640_L_MUTE | RT5640_R_MUTE, 0);
+                break;
+#endif
+        case SND_SOC_BIAS_PREPARE:
+#ifdef RT5640_DEMO
+                snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                        RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                        RT5640_PWR_BG | RT5640_PWR_VREF2,
+                        RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                        RT5640_PWR_BG | RT5640_PWR_VREF2);
+                msleep(100);
+
+                snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                        RT5640_PWR_FV1 | RT5640_PWR_FV2,
+                        RT5640_PWR_FV1 | RT5640_PWR_FV2);
+
+                snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
+                        RT5640_PWR_MB1 | RT5640_PWR_MB2,
+                        RT5640_PWR_MB1 | RT5640_PWR_MB2);
+#endif
+                break;
+
+        case SND_SOC_BIAS_STANDBY:
+#ifdef RT5640_DEMO
+                snd_soc_update_bits(codec, RT5640_SPK_VOL, RT5640_L_MUTE |
+                        RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+                snd_soc_update_bits(codec, RT5640_HP_VOL, RT5640_L_MUTE |
+                        RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+
+                snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
+                        RT5640_PWR_MB1 | RT5640_PWR_MB2,
+                        0);
+#endif
+                if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
+                        snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                                RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                                RT5640_PWR_BG | RT5640_PWR_VREF2,
+                                RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                                RT5640_PWR_BG | RT5640_PWR_VREF2);
+                        msleep(10);
+                        snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                                RT5640_PWR_FV1 | RT5640_PWR_FV2,
+                                RT5640_PWR_FV1 | RT5640_PWR_FV2);
+                        codec->cache_only = false;
+                        snd_soc_cache_sync(codec);
+                }
+                break;
+
+        case SND_SOC_BIAS_OFF:
+#ifdef RT5640_DEMO
+                snd_soc_update_bits(codec, RT5640_SPK_VOL, RT5640_L_MUTE |
+                        RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+                snd_soc_update_bits(codec, RT5640_HP_VOL, RT5640_L_MUTE |
+                        RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+                snd_soc_update_bits(codec, RT5640_OUTPUT, RT5640_L_MUTE |
+                        RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+                snd_soc_update_bits(codec, RT5640_MONO_OUT,
+                        RT5640_L_MUTE, RT5640_L_MUTE);
+#endif
+                snd_soc_write(codec, RT5640_PWR_DIG1, 0x0000);
+                snd_soc_write(codec, RT5640_PWR_DIG2, 0x0000);
+                snd_soc_write(codec, RT5640_PWR_VOL, 0x0000);
+                snd_soc_write(codec, RT5640_PWR_MIXER, 0x0000);
+                snd_soc_write(codec, RT5640_PWR_ANLG1, 0x0000);
+                snd_soc_write(codec, RT5640_PWR_ANLG2, 0x0000);
+                break;
+
+        default:
+                break;
+        }
+        codec->dapm.bias_level = level;
+
+        return 0;
+}
+
+static int rt5640_probe(struct snd_soc_codec *codec)
+{
+        struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+        int ret;
+        u16 val;
+
+        ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+
+        val = snd_soc_read(codec, RT5640_RESET);
+        if (val != rt5640_reg[RT5640_RESET]) {
+                dev_err(codec->dev,
+                        "Device with ID register %x is not a rt5640\n", val);
+                return -ENODEV;
+        }
+
+        rt5640_reset(codec);
+        snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                RT5640_PWR_BG | RT5640_PWR_VREF2,
+                RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                RT5640_PWR_BG | RT5640_PWR_VREF2);
+        msleep(100);
+        snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                RT5640_PWR_FV1 | RT5640_PWR_FV2,
+                RT5640_PWR_FV1 | RT5640_PWR_FV2);
+        /* DMIC */
+        if (rt5640->dmic_en == RT5640_DMIC1) {
+                snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                        RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK,
+                        RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING);
+        } else if (rt5640->dmic_en == RT5640_DMIC2) {
+                snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                        RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
+                snd_soc_update_bits(codec, RT5640_DMIC,
+                        RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK,
+                        RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING);
+        }
+
+#ifdef RT5640_DEMO
+        rt5640_reg_init(codec);
+#endif
+
+
+#if (CONFIG_SND_SOC_RT5642_MODULE | CONFIG_SND_SOC_RT5642)
+        rt5640_register_dsp(codec);
+#endif
+
+        codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
+
+        snd_soc_add_controls(codec, rt5640_snd_controls,
+                ARRAY_SIZE(rt5640_snd_controls));
+
+        rt5640->codec = codec;
+        ret = device_create_file(codec->dev, &dev_attr_index_reg);
+        if (ret != 0) {
+                dev_err(codec->dev,
+                        "Failed to create index_reg sysfs files: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int rt5640_remove(struct snd_soc_codec *codec)
+{
+        rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        rt5640_reset(codec);
+        snd_soc_write(codec, RT5640_PWR_ANLG1, 0);
+
+        return 0;
+}
+#ifdef CONFIG_PM
+static int rt5640_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
+        snd_soc_write(codec, RT5640_PWR_ANLG1, 0);
+
+        return 0;
+}
+
+static int rt5640_resume(struct snd_soc_codec *codec)
+{
+        rt5640_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        return 0;
+}
+#else
+#define rt5640_suspend NULL
+#define rt5640_resume NULL
+#endif
+
+#define RT5640_STEREO_RATES SNDRV_PCM_RATE_8000_96000
+#define RT5640_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+                        SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
+
+struct snd_soc_dai_ops rt5640_aif_dai_ops = {
+        .hw_params = rt5640_hw_params,
+        .prepare = rt5640_prepare,
+        .set_fmt = rt5640_set_dai_fmt,
+        .set_sysclk = rt5640_set_dai_sysclk,
+        .set_pll = rt5640_set_dai_pll,
+};
+
+struct snd_soc_dai_driver rt5640_dai[] = {
+        {
+                .name = "rt5640-aif1",
+                .id = RT5640_AIF1,
+                .playback = {
+                        .stream_name = "AIF1 Playback",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5640_STEREO_RATES,
+                        .formats = RT5640_FORMATS,
+                },
+                .capture = {
+                        .stream_name = "AIF1 Capture",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5640_STEREO_RATES,
+                        .formats = RT5640_FORMATS,
+                },
+                .ops = &rt5640_aif_dai_ops,
+        },
+        {
+                .name = "rt5640-aif2",
+                .id = RT5640_AIF2,
+                .playback = {
+                        .stream_name = "AIF2 Playback",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5640_STEREO_RATES,
+                        .formats = RT5640_FORMATS,
+                },
+                .capture = {
+                        .stream_name = "AIF2 Capture",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5640_STEREO_RATES,
+                        .formats = RT5640_FORMATS,
+                },
+                .ops = &rt5640_aif_dai_ops,
+        },
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                        CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+        {
+                .name = "rt5640-aif3",
+                .id = RT5640_AIF3,
+                .playback = {
+                        .stream_name = "AIF3 Playback",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5640_STEREO_RATES,
+                        .formats = RT5640_FORMATS,
+                },
+                .capture = {
+                        .stream_name = "AIF3 Capture",
+                        .channels_min = 1,
+                        .channels_max = 2,
+                        .rates = RT5640_STEREO_RATES,
+                        .formats = RT5640_FORMATS,
+                },
+                .ops = &rt5640_aif_dai_ops,
+        },
+#endif
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_rt5640 = {
+        .probe = rt5640_probe,
+        .remove = rt5640_remove,
+        .suspend = rt5640_suspend,
+        .resume = rt5640_resume,
+        .set_bias_level = rt5640_set_bias_level,
+        .reg_cache_size = RT5640_VENDOR_ID2 + 1,
+        .reg_word_size = sizeof(u16),
+        .reg_cache_default = rt5640_reg,
+        .volatile_register = rt5640_volatile_register,
+        .readable_register = rt5640_readable_register,
+        .reg_cache_step = 1,
+        .dapm_widgets = rt5640_dapm_widgets,
+        .num_dapm_widgets = ARRAY_SIZE(rt5640_dapm_widgets),
+        .dapm_routes = rt5640_dapm_routes,
+        .num_dapm_routes = ARRAY_SIZE(rt5640_dapm_routes),
+};
+
+static const struct i2c_device_id rt5640_i2c_id[] = {
+        { "rt5640", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
+
+static int rt5640_i2c_probe(struct i2c_client *i2c,
+                    const struct i2c_device_id *id)
+{
+        struct rt5640_priv *rt5640;
+        int ret;
+
+        rt5640 = kzalloc(sizeof(struct rt5640_priv), GFP_KERNEL);
+        if (NULL == rt5640)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, rt5640);
+
+        ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640,
+                        rt5640_dai, ARRAY_SIZE(rt5640_dai));
+        if (ret < 0)
+                kfree(rt5640);
+
+        return ret;
+}
+
+static __devexit int rt5640_i2c_remove(struct i2c_client *i2c)
+{
+        snd_soc_unregister_codec(&i2c->dev);
+        kfree(i2c_get_clientdata(i2c));
+        return 0;
+}
+
+struct i2c_driver rt5640_i2c_driver = {
+        .driver = {
+                .name = "rt5640",
+                .owner = THIS_MODULE,
+        },
+        .probe = rt5640_i2c_probe,
+        .remove   = __devexit_p(rt5640_i2c_remove),
+        .id_table = rt5640_i2c_id,
+};
+
+static int __init rt5640_modinit(void)
+{
+        return i2c_add_driver(&rt5640_i2c_driver);
+}
+module_init(rt5640_modinit);
+
+static void __exit rt5640_modexit(void)
+{
+        i2c_del_driver(&rt5640_i2c_driver);
+}
+module_exit(rt5640_modexit);
+
+MODULE_DESCRIPTION("ASoC RT5640 driver");
+MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
new file mode 100644
index 00000000000..d6920f00e08
--- /dev/null
+++ b/sound/soc/codecs/rt5640.h
@@ -0,0 +1,2098 @@
+/*
+ * rt5640.h  --  RT5640 ALSA SoC audio driver
+ *
+ * Copyright 2011 Realtek Microelectronics
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT5640_H__
+#define __RT5640_H__
+
+/* Info */
+#define RT5640_RESET                            0x00
+#define RT5640_VENDOR_ID                        0xfd
+#define RT5640_VENDOR_ID1                       0xfe
+#define RT5640_VENDOR_ID2                       0xff
+/*  I/O - Output */
+#define RT5640_SPK_VOL                          0x01
+#define RT5640_HP_VOL                           0x02
+#define RT5640_OUTPUT                           0x03
+#define RT5640_MONO_OUT                 0x04
+/* I/O - Input */
+#define RT5640_IN1_IN2                          0x0d
+#define RT5640_IN3_IN4                          0x0e
+#define RT5640_INL_INR_VOL                      0x0f
+/* I/O - ADC/DAC/DMIC */
+#define RT5640_DAC1_DIG_VOL                     0x19
+#define RT5640_DAC2_DIG_VOL                     0x1a
+#define RT5640_DAC2_CTRL                        0x1b
+#define RT5640_ADC_DIG_VOL                      0x1c
+#define RT5640_ADC_DATA                 0x1d
+#define RT5640_ADC_BST_VOL                      0x1e
+/* Mixer - D-D */
+#define RT5640_STO_ADC_MIXER                    0x27
+#define RT5640_MONO_ADC_MIXER                   0x28
+#define RT5640_AD_DA_MIXER                      0x29
+#define RT5640_STO_DAC_MIXER                    0x2a
+#define RT5640_MONO_DAC_MIXER                   0x2b
+#define RT5640_DIG_MIXER                        0x2c
+#define RT5640_DSP_PATH1                        0x2d
+#define RT5640_DSP_PATH2                        0x2e
+#define RT5640_DIG_INF_DATA                     0x2f
+/* Mixer - ADC */
+#define RT5640_REC_L1_MIXER                     0x3b
+#define RT5640_REC_L2_MIXER                     0x3c
+#define RT5640_REC_R1_MIXER                     0x3d
+#define RT5640_REC_R2_MIXER                     0x3e
+/* Mixer - DAC */
+#define RT5640_HPO_MIXER                        0x45
+#define RT5640_SPK_L_MIXER                      0x46
+#define RT5640_SPK_R_MIXER                      0x47
+#define RT5640_SPO_L_MIXER                      0x48
+#define RT5640_SPO_R_MIXER                      0x49
+#define RT5640_SPO_CLSD_RATIO                   0x4a
+#define RT5640_MONO_MIXER                       0x4c
+#define RT5640_OUT_L1_MIXER                     0x4d
+#define RT5640_OUT_L2_MIXER                     0x4e
+#define RT5640_OUT_L3_MIXER                     0x4f
+#define RT5640_OUT_R1_MIXER                     0x50
+#define RT5640_OUT_R2_MIXER                     0x51
+#define RT5640_OUT_R3_MIXER                     0x52
+#define RT5640_LOUT_MIXER                       0x53
+/* Power */
+#define RT5640_PWR_DIG1                 0x61
+#define RT5640_PWR_DIG2                 0x62
+#define RT5640_PWR_ANLG1                        0x63
+#define RT5640_PWR_ANLG2                        0x64
+#define RT5640_PWR_MIXER                        0x65
+#define RT5640_PWR_VOL                          0x66
+/* Private Register Control */
+#define RT5640_PRIV_INDEX                       0x6a
+#define RT5640_PRIV_DATA                        0x6c
+/* Format - ADC/DAC */
+#define RT5640_I2S1_SDP                         0x70
+#define RT5640_I2S2_SDP                         0x71
+#define RT5640_I2S3_SDP                         0x72
+#define RT5640_ADDA_CLK1                        0x73
+#define RT5640_ADDA_CLK2                        0x74
+#define RT5640_DMIC                             0x75
+/* Function - Analog */
+#define RT5640_GLB_CLK                          0x80
+#define RT5640_PLL_CTRL1                        0x81
+#define RT5640_PLL_CTRL2                        0x82
+#define RT5640_ASRC_1                           0x83
+#define RT5640_ASRC_2                           0x84
+#define RT5640_ASRC_3                           0x85
+#define RT5640_ASRC_4                           0x89
+#define RT5640_ASRC_5                           0x8a
+#define RT5640_HP_OVCD                          0x8b
+#define RT5640_CLS_D_OVCD                       0x8c
+#define RT5640_CLS_D_OUT                        0x8d
+#define RT5640_DEPOP_M1                 0x8e
+#define RT5640_DEPOP_M2                 0x8f
+#define RT5640_DEPOP_M3                 0x90
+#define RT5640_CHARGE_PUMP                      0x91
+#define RT5640_PV_DET_SPK_G                     0x92
+#define RT5640_MICBIAS                          0x93
+/* Function - Digital */
+#define RT5640_EQ_CTRL1                         0xb0
+#define RT5640_EQ_CTRL2                         0xb1
+#define RT5640_WIND_FILTER                      0xb2
+#define RT5640_DRC_AGC_1                        0xb4
+#define RT5640_DRC_AGC_2                        0xb5
+#define RT5640_DRC_AGC_3                        0xb6
+#define RT5640_SVOL_ZC                          0xb7
+#define RT5640_ANC_CTRL1                        0xb8
+#define RT5640_ANC_CTRL2                        0xb9
+#define RT5640_ANC_CTRL3                        0xba
+#define RT5640_JD_CTRL                          0xbb
+#define RT5640_ANC_JD                           0xbc
+#define RT5640_IRQ_CTRL1                        0xbd
+#define RT5640_IRQ_CTRL2                        0xbe
+#define RT5640_INT_IRQ_ST                       0xbf
+#define RT5640_GPIO_CTRL1                       0xc0
+#define RT5640_GPIO_CTRL2                       0xc1
+#define RT5640_GPIO_CTRL3                       0xc2
+#define RT5640_DSP_CTRL1                        0xc4
+#define RT5640_DSP_CTRL2                        0xc5
+#define RT5640_DSP_CTRL3                        0xc6
+#define RT5640_DSP_CTRL4                        0xc7
+#define RT5640_PGM_REG_ARR1                     0xc8
+#define RT5640_PGM_REG_ARR2                     0xc9
+#define RT5640_PGM_REG_ARR3                     0xca
+#define RT5640_PGM_REG_ARR4                     0xcb
+#define RT5640_PGM_REG_ARR5                     0xcc
+#define RT5640_SCB_FUNC                 0xcd
+#define RT5640_SCB_CTRL                         0xce
+#define RT5640_BASE_BACK                        0xcf
+#define RT5640_MP3_PLUS1                        0xd0
+#define RT5640_MP3_PLUS2                        0xd1
+#define RT5640_3D_HP                            0xd2
+#define RT5640_ADJ_HPF                          0xd3
+#define RT5640_HP_CALIB_AMP_DET         0xd6
+#define RT5640_HP_CALIB2                        0xd7
+#define RT5640_SV_ZCD1                          0xd9
+#define RT5640_SV_ZCD2                          0xda
+/* Dummy Register */
+#define RT5640_DUMMY1                           0xfa
+#define RT5640_DUMMY2                           0xfb
+#define RT5640_DUMMY3                           0xfc
+
+
+/* Index of Codec Private Register definition */
+#define RT5640_3D_SPK                           0x63
+#define RT5640_WND_1                            0x6c
+#define RT5640_WND_2                            0x6d
+#define RT5640_WND_3                            0x6e
+#define RT5640_WND_4                            0x6f
+#define RT5640_WND_5                            0x70
+#define RT5640_WND_8                            0x73
+#define RT5640_DIP_SPK_INF                      0x75
+#define RT5640_EQ_BW_LOP                        0xa0
+#define RT5640_EQ_GN_LOP                        0xa1
+#define RT5640_EQ_FC_BP1                        0xa2
+#define RT5640_EQ_BW_BP1                        0xa3
+#define RT5640_EQ_GN_BP1                        0xa4
+#define RT5640_EQ_FC_BP2                        0xa5
+#define RT5640_EQ_BW_BP2                        0xa6
+#define RT5640_EQ_GN_BP2                        0xa7
+#define RT5640_EQ_FC_BP3                        0xa8
+#define RT5640_EQ_BW_BP3                        0xa9
+#define RT5640_EQ_GN_BP3                        0xaa
+#define RT5640_EQ_FC_BP4                        0xab
+#define RT5640_EQ_BW_BP4                        0xac
+#define RT5640_EQ_GN_BP4                        0xad
+#define RT5640_EQ_FC_HIP1                       0xae
+#define RT5640_EQ_GN_HIP1                       0xaf
+#define RT5640_EQ_FC_HIP2                       0xb0
+#define RT5640_EQ_BW_HIP2                       0xb1
+#define RT5640_EQ_GN_HIP2                       0xb2
+#define RT5640_EQ_PRE_VOL                       0xb3
+#define RT5640_EQ_PST_VOL                       0xb4
+
+
+/* global definition */
+#define RT5640_L_MUTE                           (0x1 << 15)
+#define RT5640_L_MUTE_SFT                       15
+#define RT5640_VOL_L_MUTE                       (0x1 << 14)
+#define RT5640_VOL_L_SFT                        14
+#define RT5640_R_MUTE                           (0x1 << 7)
+#define RT5640_R_MUTE_SFT                       7
+#define RT5640_VOL_R_MUTE                       (0x1 << 6)
+#define RT5640_VOL_R_SFT                        6
+#define RT5640_L_VOL_MASK                       (0x3f << 8)
+#define RT5640_L_VOL_SFT                        8
+#define RT5640_R_VOL_MASK                       (0x3f)
+#define RT5640_R_VOL_SFT                        0
+
+/* IN1 and IN2 Control (0x0d) */
+/* IN3 and IN4 Control (0x0e) */
+#define RT5640_BST_SFT1                         12
+#define RT5640_BST_SFT2                         8
+#define RT5640_IN_DF1                           (0x1 << 7)
+#define RT5640_IN_SFT1                          7
+#define RT5640_IN_DF2                           (0x1 << 6)
+#define RT5640_IN_SFT2                          6
+
+/* INL and INR Volume Control (0x0f) */
+#define RT5640_INL_SEL_MASK                     (0x1 << 15)
+#define RT5640_INL_SEL_SFT                      15
+#define RT5640_INL_SEL_IN4P                     (0x0 << 15)
+#define RT5640_INL_SEL_MONOP                    (0x1 << 15)
+#define RT5640_INL_VOL_MASK                     (0x1f << 8)
+#define RT5640_INL_VOL_SFT                      8
+#define RT5640_INR_SEL_MASK                     (0x1 << 7)
+#define RT5640_INR_SEL_SFT                      7
+#define RT5640_INR_SEL_IN4N                     (0x0 << 7)
+#define RT5640_INR_SEL_MONON                    (0x1 << 7)
+#define RT5640_INR_VOL_MASK                     (0x1f)
+#define RT5640_INR_VOL_SFT                      0
+
+/* DAC1 Digital Volume (0x19) */
+#define RT5640_DAC_L1_VOL_MASK          (0xff << 8)
+#define RT5640_DAC_L1_VOL_SFT                   8
+#define RT5640_DAC_R1_VOL_MASK          (0xff)
+#define RT5640_DAC_R1_VOL_SFT                   0
+
+/* DAC2 Digital Volume (0x1a) */
+#define RT5640_DAC_L2_VOL_MASK          (0xff << 8)
+#define RT5640_DAC_L2_VOL_SFT                   8
+#define RT5640_DAC_R2_VOL_MASK          (0xff)
+#define RT5640_DAC_R2_VOL_SFT                   0
+
+/* DAC2 Control (0x1b) */
+#define RT5640_M_DAC_L2_VOL                     (0x1 << 13)
+#define RT5640_M_DAC_L2_VOL_SFT         13
+#define RT5640_M_DAC_R2_VOL                     (0x1 << 12)
+#define RT5640_M_DAC_R2_VOL_SFT         12
+
+/* ADC Digital Volume Control (0x1c) */
+#define RT5640_ADC_L_VOL_MASK                   (0x7f << 8)
+#define RT5640_ADC_L_VOL_SFT                    8
+#define RT5640_ADC_R_VOL_MASK                   (0x7f)
+#define RT5640_ADC_R_VOL_SFT                    0
+
+/* Mono ADC Digital Volume Control (0x1d) */
+#define RT5640_MONO_ADC_L_VOL_MASK              (0x7f << 8)
+#define RT5640_MONO_ADC_L_VOL_SFT               8
+#define RT5640_MONO_ADC_R_VOL_MASK              (0x7f)
+#define RT5640_MONO_ADC_R_VOL_SFT               0
+
+/* ADC Boost Volume Control (0x1e) */
+#define RT5640_ADC_L_BST_MASK                   (0x3 << 14)
+#define RT5640_ADC_L_BST_SFT                    14
+#define RT5640_ADC_R_BST_MASK                   (0x3 << 12)
+#define RT5640_ADC_R_BST_SFT                    12
+#define RT5640_ADC_COMP_MASK                    (0x3 << 10)
+#define RT5640_ADC_COMP_SFT                     10
+
+/* Stereo ADC Mixer Control (0x27) */
+#define RT5640_M_ADC_L1                 (0x1 << 14)
+#define RT5640_M_ADC_L1_SFT                     14
+#define RT5640_M_ADC_L2                 (0x1 << 13)
+#define RT5640_M_ADC_L2_SFT                     13
+#define RT5640_ADC_1_SRC_MASK                   (0x1 << 12)
+#define RT5640_ADC_1_SRC_SFT                    12
+#define RT5640_ADC_1_SRC_ADC                    (0x1 << 12)
+#define RT5640_ADC_1_SRC_DACMIX         (0x0 << 12)
+#define RT5640_ADC_2_SRC_MASK                   (0x3 << 10)
+#define RT5640_ADC_2_SRC_SFT                    10
+#define RT5640_ADC_2_SRC_DMIC1          (0x0 << 10)
+#define RT5640_ADC_2_SRC_DMIC2          (0x1 << 10)
+#define RT5640_ADC_2_SRC_DACMIX         (0x2 << 10)
+#define RT5640_M_ADC_R1                 (0x1 << 6)
+#define RT5640_M_ADC_R1_SFT                     6
+#define RT5640_M_ADC_R2                 (0x1 << 5)
+#define RT5640_M_ADC_R2_SFT                     5
+
+/* Mono ADC Mixer Control (0x28) */
+#define RT5640_M_MONO_ADC_L1                    (0x1 << 14)
+#define RT5640_M_MONO_ADC_L1_SFT                14
+#define RT5640_M_MONO_ADC_L2                    (0x1 << 13)
+#define RT5640_M_MONO_ADC_L2_SFT                13
+#define RT5640_MONO_ADC_L1_SRC_MASK             (0x1 << 12)
+#define RT5640_MONO_ADC_L1_SRC_SFT              12
+#define RT5640_MONO_ADC_L1_SRC_DACMIXL  (0x0 << 12)
+#define RT5640_MONO_ADC_L1_SRC_ADCL             (0x1 << 12)
+#define RT5640_MONO_ADC_L2_SRC_MASK             (0x3 << 10)
+#define RT5640_MONO_ADC_L2_SRC_SFT              10
+#define RT5640_MONO_ADC_L2_SRC_DMIC_L1  (0x0 << 10)
+#define RT5640_MONO_ADC_L2_SRC_DMIC_L2  (0x1 << 10)
+#define RT5640_MONO_ADC_L2_SRC_DACMIXL  (0x2 << 10)
+#define RT5640_M_MONO_ADC_R1                    (0x1 << 6)
+#define RT5640_M_MONO_ADC_R1_SFT                6
+#define RT5640_M_MONO_ADC_R2                    (0x1 << 5)
+#define RT5640_M_MONO_ADC_R2_SFT                5
+#define RT5640_MONO_ADC_R1_SRC_MASK             (0x1 << 4)
+#define RT5640_MONO_ADC_R1_SRC_SFT              4
+#define RT5640_MONO_ADC_R1_SRC_ADCR             (0x1 << 4)
+#define RT5640_MONO_ADC_R1_SRC_DACMIXR  (0x0 << 4)
+#define RT5640_MONO_ADC_R2_SRC_MASK             (0x3 << 2)
+#define RT5640_MONO_ADC_R2_SRC_SFT              2
+#define RT5640_MONO_ADC_R2_SRC_DMIC_R1  (0x0 << 2)
+#define RT5640_MONO_ADC_R2_SRC_DMIC_R2  (0x1 << 2)
+#define RT5640_MONO_ADC_R2_SRC_DACMIXR  (0x2 << 2)
+
+/* ADC Mixer to DAC Mixer Control (0x29) */
+#define RT5640_M_ADCMIX_L                       (0x1 << 15)
+#define RT5640_M_ADCMIX_L_SFT                   15
+#define RT5640_M_IF1_DAC_L                      (0x1 << 14)
+#define RT5640_M_IF1_DAC_L_SFT                  14
+#define RT5640_M_ADCMIX_R                       (0x1 << 7)
+#define RT5640_M_ADCMIX_R_SFT                   7
+#define RT5640_M_IF1_DAC_R                      (0x1 << 6)
+#define RT5640_M_IF1_DAC_R_SFT                  6
+
+/* Stereo DAC Mixer Control (0x2a) */
+#define RT5640_M_DAC_L1                 (0x1 << 14)
+#define RT5640_M_DAC_L1_SFT                     14
+#define RT5640_DAC_L1_STO_L_VOL_MASK            (0x1 << 13)
+#define RT5640_DAC_L1_STO_L_VOL_SFT             13
+#define RT5640_M_DAC_L2                 (0x1 << 12)
+#define RT5640_M_DAC_L2_SFT                     12
+#define RT5640_DAC_L2_STO_L_VOL_MASK            (0x1 << 11)
+#define RT5640_DAC_L2_STO_L_VOL_SFT             11
+#define RT5640_M_ANC_DAC_L                      (0x1 << 10)
+#define RT5640_M_ANC_DAC_L_SFT          10
+#define RT5640_M_DAC_R1                 (0x1 << 6)
+#define RT5640_M_DAC_R1_SFT                     6
+#define RT5640_DAC_R1_STO_R_VOL_MASK            (0x1 << 5)
+#define RT5640_DAC_R1_STO_R_VOL_SFT             5
+#define RT5640_M_DAC_R2                 (0x1 << 4)
+#define RT5640_M_DAC_R2_SFT                     4
+#define RT5640_DAC_R2_STO_R_VOL_MASK            (0x1 << 3)
+#define RT5640_DAC_R2_STO_R_VOL_SFT             3
+#define RT5640_M_ANC_DAC_R                      (0x1 << 2)
+#define RT5640_M_ANC_DAC_R_SFT          2
+
+/* Mono DAC Mixer Control (0x2b) */
+#define RT5640_M_DAC_L1_MONO_L          (0x1 << 14)
+#define RT5640_M_DAC_L1_MONO_L_SFT              14
+#define RT5640_DAC_L1_MONO_L_VOL_MASK   (0x1 << 13)
+#define RT5640_DAC_L1_MONO_L_VOL_SFT            13
+#define RT5640_M_DAC_L2_MONO_L          (0x1 << 12)
+#define RT5640_M_DAC_L2_MONO_L_SFT              12
+#define RT5640_DAC_L2_MONO_L_VOL_MASK   (0x1 << 11)
+#define RT5640_DAC_L2_MONO_L_VOL_SFT            11
+#define RT5640_M_DAC_R2_MONO_L          (0x1 << 10)
+#define RT5640_M_DAC_R2_MONO_L_SFT              10
+#define RT5640_DAC_R2_MONO_L_VOL_MASK   (0x1 << 9)
+#define RT5640_DAC_R2_MONO_L_VOL_SFT            9
+#define RT5640_M_DAC_R1_MONO_R          (0x1 << 6)
+#define RT5640_M_DAC_R1_MONO_R_SFT              6
+#define RT5640_DAC_R1_MONO_R_VOL_MASK   (0x1 << 5)
+#define RT5640_DAC_R1_MONO_R_VOL_SFT            5
+#define RT5640_M_DAC_R2_MONO_R          (0x1 << 4)
+#define RT5640_M_DAC_R2_MONO_R_SFT              4
+#define RT5640_DAC_R2_MONO_R_VOL_MASK   (0x1 << 3)
+#define RT5640_DAC_R2_MONO_R_VOL_SFT            3
+#define RT5640_M_DAC_L2_MONO_R          (0x1 << 2)
+#define RT5640_M_DAC_L2_MONO_R_SFT              2
+#define RT5640_DAC_L2_MONO_R_VOL_MASK   (0x1 << 1)
+#define RT5640_DAC_L2_MONO_R_VOL_SFT            1
+
+/* Digital Mixer Control (0x2c) */
+#define RT5640_M_STO_L_DAC_L                    (0x1 << 15)
+#define RT5640_M_STO_L_DAC_L_SFT                15
+#define RT5640_STO_L_DAC_L_VOL_MASK             (0x1 << 14)
+#define RT5640_STO_L_DAC_L_VOL_SFT              14
+#define RT5640_M_DAC_L2_DAC_L                   (0x1 << 13)
+#define RT5640_M_DAC_L2_DAC_L_SFT               13
+#define RT5640_DAC_L2_DAC_L_VOL_MASK            (0x1 << 12)
+#define RT5640_DAC_L2_DAC_L_VOL_SFT             12
+#define RT5640_M_STO_R_DAC_R                    (0x1 << 11)
+#define RT5640_M_STO_R_DAC_R_SFT                11
+#define RT5640_STO_R_DAC_R_VOL_MASK             (0x1 << 10)
+#define RT5640_STO_R_DAC_R_VOL_SFT              10
+#define RT5640_M_DAC_R2_DAC_R                   (0x1 << 9)
+#define RT5640_M_DAC_R2_DAC_R_SFT               9
+#define RT5640_DAC_R2_DAC_R_VOL_MASK            (0x1 << 8)
+#define RT5640_DAC_R2_DAC_R_VOL_SFT             8
+
+/* DSP Path Control 1 (0x2d) */
+#define RT5640_RXDP_SRC_MASK                    (0x1 << 15)
+#define RT5640_RXDP_SRC_SFT                     15
+#define RT5640_RXDP_SRC_NOR                     (0x0 << 15)
+#define RT5640_RXDP_SRC_DIV3                    (0x1 << 15)
+#define RT5640_TXDP_SRC_MASK                    (0x1 << 14)
+#define RT5640_TXDP_SRC_SFT                     14
+#define RT5640_TXDP_SRC_NOR                     (0x0 << 14)
+#define RT5640_TXDP_SRC_DIV3                    (0x1 << 14)
+
+/* DSP Path Control 2 (0x2e) */
+#define RT5640_DAC_L2_SEL_MASK          (0x3 << 14)
+#define RT5640_DAC_L2_SEL_SFT                   14
+#define RT5640_DAC_L2_SEL_IF2                   (0x0 << 14)
+#define RT5640_DAC_L2_SEL_IF3                   (0x1 << 14)
+#define RT5640_DAC_L2_SEL_TXDC                  (0x2 << 14)
+#define RT5640_DAC_L2_SEL_BASS                  (0x3 << 14)
+#define RT5640_DAC_R2_SEL_MASK          (0x3 << 12)
+#define RT5640_DAC_R2_SEL_SFT                   12
+#define RT5640_DAC_R2_SEL_IF2                   (0x0 << 12)
+#define RT5640_DAC_R2_SEL_IF3                   (0x1 << 12)
+#define RT5640_DAC_R2_SEL_TXDC          (0x2 << 12)
+#define RT5640_IF2_ADC_L_SEL_MASK               (0x1 << 11)
+#define RT5640_IF2_ADC_L_SEL_SFT                11
+#define RT5640_IF2_ADC_L_SEL_TXDP               (0x0 << 11)
+#define RT5640_IF2_ADC_L_SEL_PASS               (0x1 << 11)
+#define RT5640_IF2_ADC_R_SEL_MASK               (0x1 << 10)
+#define RT5640_IF2_ADC_R_SEL_SFT                10
+#define RT5640_IF2_ADC_R_SEL_TXDP               (0x0 << 10)
+#define RT5640_IF2_ADC_R_SEL_PASS               (0x1 << 10)
+#define RT5640_RXDC_SEL_MASK                    (0x3 << 8)
+#define RT5640_RXDC_SEL_SFT                     8
+#define RT5640_RXDC_SEL_NOR                     (0x0 << 8)
+#define RT5640_RXDC_SEL_L2R                     (0x1 << 8)
+#define RT5640_RXDC_SEL_R2L                     (0x2 << 8)
+#define RT5640_RXDC_SEL_SWAP                    (0x3 << 8)
+#define RT5640_RXDP_SEL_MASK                    (0x3 << 6)
+#define RT5640_RXDP_SEL_SFT                     6
+#define RT5640_RXDP_SEL_NOR                     (0x0 << 6)
+#define RT5640_RXDP_SEL_L2R                     (0x1 << 6)
+#define RT5640_RXDP_SEL_R2L                     (0x2 << 6)
+#define RT5640_RXDP_SEL_SWAP                    (0x3 << 6)
+#define RT5640_TXDC_SEL_MASK                    (0x3 << 4)
+#define RT5640_TXDC_SEL_SFT                     4
+#define RT5640_TXDC_SEL_NOR                     (0x0 << 4)
+#define RT5640_TXDC_SEL_L2R                     (0x1 << 4)
+#define RT5640_TXDC_SEL_R2L                     (0x2 << 4)
+#define RT5640_TXDC_SEL_SWAP                    (0x3 << 4)
+#define RT5640_TXDP_SEL_MASK                    (0x3 << 2)
+#define RT5640_TXDP_SEL_SFT                     2
+#define RT5640_TXDP_SEL_NOR                     (0x0 << 2)
+#define RT5640_TXDP_SEL_L2R                     (0x1 << 2)
+#define RT5640_TXDP_SEL_R2L                     (0x2 << 2)
+#define RT5640_TRXDP_SEL_SWAP                   (0x3 << 2)
+
+/* Digital Interface Data Control (0x2f) */
+#define RT5640_IF1_DAC_SEL_MASK         (0x3 << 14)
+#define RT5640_IF1_DAC_SEL_SFT                  14
+#define RT5640_IF1_DAC_SEL_NOR                  (0x0 << 14)
+#define RT5640_IF1_DAC_SEL_L2R                  (0x1 << 14)
+#define RT5640_IF1_DAC_SEL_R2L                  (0x2 << 14)
+#define RT5640_IF1_DAC_SEL_SWAP         (0x3 << 14)
+#define RT5640_IF1_ADC_SEL_MASK         (0x3 << 12)
+#define RT5640_IF1_ADC_SEL_SFT                  12
+#define RT5640_IF1_ADC_SEL_NOR                  (0x0 << 12)
+#define RT5640_IF1_ADC_SEL_L2R                  (0x1 << 12)
+#define RT5640_IF1_ADC_SEL_R2L                  (0x2 << 12)
+#define RT5640_IF1_ADC_SEL_SWAP         (0x3 << 12)
+#define RT5640_IF2_DAC_SEL_MASK         (0x3 << 10)
+#define RT5640_IF2_DAC_SEL_SFT                  10
+#define RT5640_IF2_DAC_SEL_NOR                  (0x0 << 10)
+#define RT5640_IF2_DAC_SEL_L2R                  (0x1 << 10)
+#define RT5640_IF2_DAC_SEL_R2L                  (0x2 << 10)
+#define RT5640_IF2_DAC_SEL_SWAP         (0x3 << 10)
+#define RT5640_IF2_ADC_SEL_MASK         (0x3 << 8)
+#define RT5640_IF2_ADC_SEL_SFT                  8
+#define RT5640_IF2_ADC_SEL_NOR                  (0x0 << 8)
+#define RT5640_IF2_ADC_SEL_L2R                  (0x1 << 8)
+#define RT5640_IF2_ADC_SEL_R2L                  (0x2 << 8)
+#define RT5640_IF2_ADC_SEL_SWAP         (0x3 << 8)
+#define RT5640_IF3_DAC_SEL_MASK         (0x3 << 6)
+#define RT5640_IF3_DAC_SEL_SFT                  6
+#define RT5640_IF3_DAC_SEL_NOR                  (0x0 << 6)
+#define RT5640_IF3_DAC_SEL_L2R                  (0x1 << 6)
+#define RT5640_IF3_DAC_SEL_R2L                  (0x2 << 6)
+#define RT5640_IF3_DAC_SEL_SWAP         (0x3 << 6)
+#define RT5640_IF3_ADC_SEL_MASK         (0x3 << 4)
+#define RT5640_IF3_ADC_SEL_SFT                  4
+#define RT5640_IF3_ADC_SEL_NOR                  (0x0 << 4)
+#define RT5640_IF3_ADC_SEL_L2R                  (0x1 << 4)
+#define RT5640_IF3_ADC_SEL_R2L                  (0x2 << 4)
+#define RT5640_IF3_ADC_SEL_SWAP         (0x3 << 4)
+
+/* REC Left Mixer Control 1 (0x3b) */
+#define RT5640_G_HP_L_RM_L_MASK         (0x7 << 13)
+#define RT5640_G_HP_L_RM_L_SFT                  13
+#define RT5640_G_IN_L_RM_L_MASK         (0x7 << 10)
+#define RT5640_G_IN_L_RM_L_SFT                  10
+#define RT5640_G_BST4_RM_L_MASK         (0x7 << 7)
+#define RT5640_G_BST4_RM_L_SFT                  7
+#define RT5640_G_BST3_RM_L_MASK         (0x7 << 4)
+#define RT5640_G_BST3_RM_L_SFT                  4
+#define RT5640_G_BST2_RM_L_MASK         (0x7 << 1)
+#define RT5640_G_BST2_RM_L_SFT                  1
+
+/* REC Left Mixer Control 2 (0x3c) */
+#define RT5640_G_BST1_RM_L_MASK         (0x7 << 13)
+#define RT5640_G_BST1_RM_L_SFT                  13
+#define RT5640_G_OM_L_RM_L_MASK         (0x7 << 10)
+#define RT5640_G_OM_L_RM_L_SFT          10
+#define RT5640_M_HP_L_RM_L                      (0x1 << 6)
+#define RT5640_M_HP_L_RM_L_SFT          6
+#define RT5640_M_IN_L_RM_L                      (0x1 << 5)
+#define RT5640_M_IN_L_RM_L_SFT                  5
+#define RT5640_M_BST4_RM_L                      (0x1 << 4)
+#define RT5640_M_BST4_RM_L_SFT          4
+#define RT5640_M_BST3_RM_L                      (0x1 << 3)
+#define RT5640_M_BST3_RM_L_SFT          3
+#define RT5640_M_BST2_RM_L                      (0x1 << 2)
+#define RT5640_M_BST2_RM_L_SFT          2
+#define RT5640_M_BST1_RM_L                      (0x1 << 1)
+#define RT5640_M_BST1_RM_L_SFT          1
+#define RT5640_M_OM_L_RM_L                      (0x1)
+#define RT5640_M_OM_L_RM_L_SFT          0
+
+/* REC Right Mixer Control 1 (0x3d) */
+#define RT5640_G_HP_R_RM_R_MASK         (0x7 << 13)
+#define RT5640_G_HP_R_RM_R_SFT          13
+#define RT5640_G_IN_R_RM_R_MASK         (0x7 << 10)
+#define RT5640_G_IN_R_RM_R_SFT                  10
+#define RT5640_G_BST4_RM_R_MASK         (0x7 << 7)
+#define RT5640_G_BST4_RM_R_SFT                  7
+#define RT5640_G_BST3_RM_R_MASK         (0x7 << 4)
+#define RT5640_G_BST3_RM_R_SFT                  4
+#define RT5640_G_BST2_RM_R_MASK         (0x7 << 1)
+#define RT5640_G_BST2_RM_R_SFT                  1
+
+/* REC Right Mixer Control 2 (0x3e) */
+#define RT5640_G_BST1_RM_R_MASK         (0x7 << 13)
+#define RT5640_G_BST1_RM_R_SFT                  13
+#define RT5640_G_OM_R_RM_R_MASK         (0x7 << 10)
+#define RT5640_G_OM_R_RM_R_SFT          10
+#define RT5640_M_HP_R_RM_R                      (0x1 << 6)
+#define RT5640_M_HP_R_RM_R_SFT          6
+#define RT5640_M_IN_R_RM_R                      (0x1 << 5)
+#define RT5640_M_IN_R_RM_R_SFT                  5
+#define RT5640_M_BST4_RM_R                      (0x1 << 4)
+#define RT5640_M_BST4_RM_R_SFT          4
+#define RT5640_M_BST3_RM_R                      (0x1 << 3)
+#define RT5640_M_BST3_RM_R_SFT          3
+#define RT5640_M_BST2_RM_R                      (0x1 << 2)
+#define RT5640_M_BST2_RM_R_SFT          2
+#define RT5640_M_BST1_RM_R                      (0x1 << 1)
+#define RT5640_M_BST1_RM_R_SFT          1
+#define RT5640_M_OM_R_RM_R                      (0x1)
+#define RT5640_M_OM_R_RM_R_SFT          0
+
+/* HPMIX Control (0x45) */
+#define RT5640_M_DAC2_HM                        (0x1 << 15)
+#define RT5640_M_DAC2_HM_SFT                    15
+#define RT5640_M_DAC1_HM                        (0x1 << 14)
+#define RT5640_M_DAC1_HM_SFT                    14
+#define RT5640_M_HPVOL_HM                       (0x1 << 13)
+#define RT5640_M_HPVOL_HM_SFT                   13
+#define RT5640_G_HPOMIX_MASK                    (0x1 << 12)
+#define RT5640_G_HPOMIX_SFT                     12
+
+/* SPK Left Mixer Control (0x46) */
+#define RT5640_G_RM_L_SM_L_MASK         (0x3 << 14)
+#define RT5640_G_RM_L_SM_L_SFT          14
+#define RT5640_G_IN_L_SM_L_MASK         (0x3 << 12)
+#define RT5640_G_IN_L_SM_L_SFT                  12
+#define RT5640_G_DAC_L1_SM_L_MASK               (0x3 << 10)
+#define RT5640_G_DAC_L1_SM_L_SFT                10
+#define RT5640_G_DAC_L2_SM_L_MASK               (0x3 << 8)
+#define RT5640_G_DAC_L2_SM_L_SFT                8
+#define RT5640_G_OM_L_SM_L_MASK         (0x3 << 6)
+#define RT5640_G_OM_L_SM_L_SFT          6
+#define RT5640_M_RM_L_SM_L                      (0x1 << 5)
+#define RT5640_M_RM_L_SM_L_SFT          5
+#define RT5640_M_IN_L_SM_L                      (0x1 << 4)
+#define RT5640_M_IN_L_SM_L_SFT                  4
+#define RT5640_M_DAC_L1_SM_L                    (0x1 << 3)
+#define RT5640_M_DAC_L1_SM_L_SFT                3
+#define RT5640_M_DAC_L2_SM_L                    (0x1 << 2)
+#define RT5640_M_DAC_L2_SM_L_SFT                2
+#define RT5640_M_OM_L_SM_L                      (0x1 << 1)
+#define RT5640_M_OM_L_SM_L_SFT          1
+
+/* SPK Right Mixer Control (0x47) */
+#define RT5640_G_RM_R_SM_R_MASK         (0x3 << 14)
+#define RT5640_G_RM_R_SM_R_SFT          14
+#define RT5640_G_IN_R_SM_R_MASK         (0x3 << 12)
+#define RT5640_G_IN_R_SM_R_SFT                  12
+#define RT5640_G_DAC_R1_SM_R_MASK               (0x3 << 10)
+#define RT5640_G_DAC_R1_SM_R_SFT                10
+#define RT5640_G_DAC_R2_SM_R_MASK               (0x3 << 8)
+#define RT5640_G_DAC_R2_SM_R_SFT                8
+#define RT5640_G_OM_R_SM_R_MASK         (0x3 << 6)
+#define RT5640_G_OM_R_SM_R_SFT          6
+#define RT5640_M_RM_R_SM_R                      (0x1 << 5)
+#define RT5640_M_RM_R_SM_R_SFT          5
+#define RT5640_M_IN_R_SM_R                      (0x1 << 4)
+#define RT5640_M_IN_R_SM_R_SFT                  4
+#define RT5640_M_DAC_R1_SM_R                    (0x1 << 3)
+#define RT5640_M_DAC_R1_SM_R_SFT                3
+#define RT5640_M_DAC_R2_SM_R                    (0x1 << 2)
+#define RT5640_M_DAC_R2_SM_R_SFT                2
+#define RT5640_M_OM_R_SM_R                      (0x1 << 1)
+#define RT5640_M_OM_R_SM_R_SFT          1
+
+/* SPOLMIX Control (0x48) */
+#define RT5640_M_DAC_R1_SPM_L                   (0x1 << 15)
+#define RT5640_M_DAC_R1_SPM_L_SFT               15
+#define RT5640_M_DAC_L1_SPM_L                   (0x1 << 14)
+#define RT5640_M_DAC_L1_SPM_L_SFT               14
+#define RT5640_M_SV_R_SPM_L                     (0x1 << 13)
+#define RT5640_M_SV_R_SPM_L_SFT         13
+#define RT5640_M_SV_L_SPM_L                     (0x1 << 12)
+#define RT5640_M_SV_L_SPM_L_SFT         12
+#define RT5640_M_BST1_SPM_L                     (0x1 << 11)
+#define RT5640_M_BST1_SPM_L_SFT         11
+
+/* SPORMIX Control (0x49) */
+#define RT5640_M_DAC_R1_SPM_R                   (0x1 << 13)
+#define RT5640_M_DAC_R1_SPM_R_SFT               13
+#define RT5640_M_SV_R_SPM_R                     (0x1 << 12)
+#define RT5640_M_SV_R_SPM_R_SFT         12
+#define RT5640_M_BST1_SPM_R                     (0x1 << 11)
+#define RT5640_M_BST1_SPM_R_SFT         11
+
+/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
+#define RT5640_SPO_CLSD_RATIO_MASK              (0x7)
+#define RT5640_SPO_CLSD_RATIO_SFT               0
+
+/* Mono Output Mixer Control (0x4c) */
+#define RT5640_M_DAC_R2_MM                      (0x1 << 15)
+#define RT5640_M_DAC_R2_MM_SFT          15
+#define RT5640_M_DAC_L2_MM                      (0x1 << 14)
+#define RT5640_M_DAC_L2_MM_SFT          14
+#define RT5640_M_OV_R_MM                        (0x1 << 13)
+#define RT5640_M_OV_R_MM_SFT                    13
+#define RT5640_M_OV_L_MM                        (0x1 << 12)
+#define RT5640_M_OV_L_MM_SFT                    12
+#define RT5640_M_BST1_MM                        (0x1 << 11)
+#define RT5640_M_BST1_MM_SFT                    11
+#define RT5640_G_MONOMIX_MASK           (0x1 << 10)
+#define RT5640_G_MONOMIX_SFT                    10
+
+/* Output Left Mixer Control 1 (0x4d) */
+#define RT5640_G_BST3_OM_L_MASK         (0x7 << 13)
+#define RT5640_G_BST3_OM_L_SFT          13
+#define RT5640_G_BST2_OM_L_MASK         (0x7 << 10)
+#define RT5640_G_BST2_OM_L_SFT          10
+#define RT5640_G_BST1_OM_L_MASK         (0x7 << 7)
+#define RT5640_G_BST1_OM_L_SFT          7
+#define RT5640_G_IN_L_OM_L_MASK         (0x7 << 4)
+#define RT5640_G_IN_L_OM_L_SFT                  4
+#define RT5640_G_RM_L_OM_L_MASK         (0x7 << 1)
+#define RT5640_G_RM_L_OM_L_SFT          1
+
+/* Output Left Mixer Control 2 (0x4e) */
+#define RT5640_G_DAC_R2_OM_L_MASK               (0x7 << 13)
+#define RT5640_G_DAC_R2_OM_L_SFT                13
+#define RT5640_G_DAC_L2_OM_L_MASK               (0x7 << 10)
+#define RT5640_G_DAC_L2_OM_L_SFT                10
+#define RT5640_G_DAC_L1_OM_L_MASK               (0x7 << 7)
+#define RT5640_G_DAC_L1_OM_L_SFT                7
+
+/* Output Left Mixer Control 3 (0x4f) */
+#define RT5640_M_SM_L_OM_L                      (0x1 << 8)
+#define RT5640_M_SM_L_OM_L_SFT          8
+#define RT5640_M_BST3_OM_L                      (0x1 << 7)
+#define RT5640_M_BST3_OM_L_SFT          7
+#define RT5640_M_BST2_OM_L                      (0x1 << 6)
+#define RT5640_M_BST2_OM_L_SFT          6
+#define RT5640_M_BST1_OM_L                      (0x1 << 5)
+#define RT5640_M_BST1_OM_L_SFT          5
+#define RT5640_M_IN_L_OM_L                      (0x1 << 4)
+#define RT5640_M_IN_L_OM_L_SFT                  4
+#define RT5640_M_RM_L_OM_L                      (0x1 << 3)
+#define RT5640_M_RM_L_OM_L_SFT          3
+#define RT5640_M_DAC_R2_OM_L                    (0x1 << 2)
+#define RT5640_M_DAC_R2_OM_L_SFT                2
+#define RT5640_M_DAC_L2_OM_L                    (0x1 << 1)
+#define RT5640_M_DAC_L2_OM_L_SFT                1
+#define RT5640_M_DAC_L1_OM_L                    (0x1)
+#define RT5640_M_DAC_L1_OM_L_SFT                0
+
+/* Output Right Mixer Control 1 (0x50) */
+#define RT5640_G_BST4_OM_R_MASK         (0x7 << 13)
+#define RT5640_G_BST4_OM_R_SFT          13
+#define RT5640_G_BST2_OM_R_MASK         (0x7 << 10)
+#define RT5640_G_BST2_OM_R_SFT          10
+#define RT5640_G_BST1_OM_R_MASK         (0x7 << 7)
+#define RT5640_G_BST1_OM_R_SFT          7
+#define RT5640_G_IN_R_OM_R_MASK         (0x7 << 4)
+#define RT5640_G_IN_R_OM_R_SFT                  4
+#define RT5640_G_RM_R_OM_R_MASK         (0x7 << 1)
+#define RT5640_G_RM_R_OM_R_SFT          1
+
+/* Output Right Mixer Control 2 (0x51) */
+#define RT5640_G_DAC_L2_OM_R_MASK               (0x7 << 13)
+#define RT5640_G_DAC_L2_OM_R_SFT                13
+#define RT5640_G_DAC_R2_OM_R_MASK               (0x7 << 10)
+#define RT5640_G_DAC_R2_OM_R_SFT                10
+#define RT5640_G_DAC_R1_OM_R_MASK               (0x7 << 7)
+#define RT5640_G_DAC_R1_OM_R_SFT                7
+
+/* Output Right Mixer Control 3 (0x52) */
+#define RT5640_M_SM_L_OM_R                      (0x1 << 8)
+#define RT5640_M_SM_L_OM_R_SFT          8
+#define RT5640_M_BST4_OM_R                      (0x1 << 7)
+#define RT5640_M_BST4_OM_R_SFT          7
+#define RT5640_M_BST2_OM_R                      (0x1 << 6)
+#define RT5640_M_BST2_OM_R_SFT          6
+#define RT5640_M_BST1_OM_R                      (0x1 << 5)
+#define RT5640_M_BST1_OM_R_SFT          5
+#define RT5640_M_IN_R_OM_R                      (0x1 << 4)
+#define RT5640_M_IN_R_OM_R_SFT          4
+#define RT5640_M_RM_R_OM_R                      (0x1 << 3)
+#define RT5640_M_RM_R_OM_R_SFT          3
+#define RT5640_M_DAC_L2_OM_R                    (0x1 << 2)
+#define RT5640_M_DAC_L2_OM_R_SFT                2
+#define RT5640_M_DAC_R2_OM_R                    (0x1 << 1)
+#define RT5640_M_DAC_R2_OM_R_SFT                1
+#define RT5640_M_DAC_R1_OM_R                    (0x1)
+#define RT5640_M_DAC_R1_OM_R_SFT                0
+
+/* LOUT Mixer Control (0x53) */
+#define RT5640_M_DAC_L1_LM                      (0x1 << 15)
+#define RT5640_M_DAC_L1_LM_SFT          15
+#define RT5640_M_DAC_R1_LM                      (0x1 << 14)
+#define RT5640_M_DAC_R1_LM_SFT          14
+#define RT5640_M_OV_L_LM                        (0x1 << 13)
+#define RT5640_M_OV_L_LM_SFT                    13
+#define RT5640_M_OV_R_LM                        (0x1 << 12)
+#define RT5640_M_OV_R_LM_SFT                    12
+#define RT5640_G_LOUTMIX_MASK                   (0x1 << 11)
+#define RT5640_G_LOUTMIX_SFT                    11
+
+/* Power Management for Digital 1 (0x61) */
+#define RT5640_PWR_I2S1                         (0x1 << 15)
+#define RT5640_PWR_I2S1_BIT                     15
+#define RT5640_PWR_I2S2                         (0x1 << 14)
+#define RT5640_PWR_I2S2_BIT                     14
+#define RT5640_PWR_I2S3                         (0x1 << 13)
+#define RT5640_PWR_I2S3_BIT                     13
+#define RT5640_PWR_DAC_L1                       (0x1 << 12)
+#define RT5640_PWR_DAC_L1_BIT                   12
+#define RT5640_PWR_DAC_R1                       (0x1 << 11)
+#define RT5640_PWR_DAC_R1_BIT                   11
+#define RT5640_PWR_DAC_L2                       (0x1 << 7)
+#define RT5640_PWR_DAC_L2_BIT                   7
+#define RT5640_PWR_DAC_R2                       (0x1 << 6)
+#define RT5640_PWR_DAC_R2_BIT                   6
+#define RT5640_PWR_ADC_L                        (0x1 << 2)
+#define RT5640_PWR_ADC_L_BIT                    2
+#define RT5640_PWR_ADC_R                        (0x1 << 1)
+#define RT5640_PWR_ADC_R_BIT                    1
+#define RT5640_PWR_CLS_D                        (0x1)
+#define RT5640_PWR_CLS_D_BIT                    0
+
+/* Power Management for Digital 2 (0x62) */
+#define RT5640_PWR_ADC_SF                       (0x1 << 15)
+#define RT5640_PWR_ADC_SF_BIT                   15
+#define RT5640_PWR_ADC_MF_L                     (0x1 << 14)
+#define RT5640_PWR_ADC_MF_L_BIT         14
+#define RT5640_PWR_ADC_MF_R                     (0x1 << 13)
+#define RT5640_PWR_ADC_MF_R_BIT         13
+#define RT5640_PWR_I2S_DSP                      (0x1 << 12)
+#define RT5640_PWR_I2S_DSP_BIT                  12
+
+/* Power Management for Analog 1 (0x63) */
+#define RT5640_PWR_VREF1                        (0x1 << 15)
+#define RT5640_PWR_VREF1_BIT                    15
+#define RT5640_PWR_FV1                          (0x1 << 14)
+#define RT5640_PWR_FV1_BIT                      14
+#define RT5640_PWR_MB                           (0x1 << 13)
+#define RT5640_PWR_MB_BIT                       13
+#define RT5640_PWR_LM                           (0x1 << 12)
+#define RT5640_PWR_LM_BIT                       12
+#define RT5640_PWR_BG                           (0x1 << 11)
+#define RT5640_PWR_BG_BIT                       11
+#define RT5640_PWR_MM                           (0x1 << 10)
+#define RT5640_PWR_MM_BIT                       10
+#define RT5640_PWR_MA                           (0x1 << 8)
+#define RT5640_PWR_MA_BIT                       8
+#define RT5640_PWR_HP_L                 (0x1 << 7)
+#define RT5640_PWR_HP_L_BIT                     7
+#define RT5640_PWR_HP_R                 (0x1 << 6)
+#define RT5640_PWR_HP_R_BIT                     6
+#define RT5640_PWR_HA                           (0x1 << 5)
+#define RT5640_PWR_HA_BIT                       5
+#define RT5640_PWR_VREF2                        (0x1 << 4)
+#define RT5640_PWR_VREF2_BIT                    4
+#define RT5640_PWR_FV2                          (0x1 << 3)
+#define RT5640_PWR_FV2_BIT                      3
+#define RT5640_PWR_LDO2                 (0x1 << 2)
+#define RT5640_PWR_LDO2_BIT                     2
+
+/* Power Management for Analog 2 (0x64) */
+#define RT5640_PWR_BST1                 (0x1 << 15)
+#define RT5640_PWR_BST1_BIT                     15
+#define RT5640_PWR_BST2                 (0x1 << 14)
+#define RT5640_PWR_BST2_BIT                     14
+#define RT5640_PWR_BST3                 (0x1 << 13)
+#define RT5640_PWR_BST3_BIT                     13
+#define RT5640_PWR_BST4                 (0x1 << 12)
+#define RT5640_PWR_BST4_BIT                     12
+#define RT5640_PWR_MB1                          (0x1 << 11)
+#define RT5640_PWR_MB1_BIT                      11
+#define RT5640_PWR_MB2                          (0x1 << 10)
+#define RT5640_PWR_MB2_BIT                      10
+#define RT5640_PWR_PLL                          (0x1 << 9)
+#define RT5640_PWR_PLL_BIT                      9
+
+/* Power Management for Mixer (0x65) */
+#define RT5640_PWR_OM_L                 (0x1 << 15)
+#define RT5640_PWR_OM_L_BIT                     15
+#define RT5640_PWR_OM_R                 (0x1 << 14)
+#define RT5640_PWR_OM_R_BIT                     14
+#define RT5640_PWR_SM_L                 (0x1 << 13)
+#define RT5640_PWR_SM_L_BIT                     13
+#define RT5640_PWR_SM_R                 (0x1 << 12)
+#define RT5640_PWR_SM_R_BIT                     12
+#define RT5640_PWR_RM_L                 (0x1 << 11)
+#define RT5640_PWR_RM_L_BIT                     11
+#define RT5640_PWR_RM_R                 (0x1 << 10)
+#define RT5640_PWR_RM_R_BIT                     10
+
+/* Power Management for Volume (0x66) */
+#define RT5640_PWR_SV_L                 (0x1 << 15)
+#define RT5640_PWR_SV_L_BIT                     15
+#define RT5640_PWR_SV_R                 (0x1 << 14)
+#define RT5640_PWR_SV_R_BIT                     14
+#define RT5640_PWR_OV_L                 (0x1 << 13)
+#define RT5640_PWR_OV_L_BIT                     13
+#define RT5640_PWR_OV_R                 (0x1 << 12)
+#define RT5640_PWR_OV_R_BIT                     12
+#define RT5640_PWR_HV_L                 (0x1 << 11)
+#define RT5640_PWR_HV_L_BIT                     11
+#define RT5640_PWR_HV_R                 (0x1 << 10)
+#define RT5640_PWR_HV_R_BIT                     10
+#define RT5640_PWR_IN_L                         (0x1 << 9)
+#define RT5640_PWR_IN_L_BIT                     9
+#define RT5640_PWR_IN_R                 (0x1 << 8)
+#define RT5640_PWR_IN_R_BIT                     8
+
+/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
+#define RT5640_I2S_MS_MASK                      (0x1 << 15)
+#define RT5640_I2S_MS_SFT                       15
+#define RT5640_I2S_MS_M                 (0x0 << 15)
+#define RT5640_I2S_MS_S                         (0x1 << 15)
+#define RT5640_I2S_IF_MASK                      (0x7 << 12)
+#define RT5640_I2S_IF_SFT                       12
+#define RT5640_I2S_O_CP_MASK                    (0x3 << 10)
+#define RT5640_I2S_O_CP_SFT                     10
+#define RT5640_I2S_O_CP_OFF                     (0x0 << 10)
+#define RT5640_I2S_O_CP_U_LAW                   (0x1 << 10)
+#define RT5640_I2S_O_CP_A_LAW                   (0x2 << 10)
+#define RT5640_I2S_I_CP_MASK                    (0x3 << 8)
+#define RT5640_I2S_I_CP_SFT                     8
+#define RT5640_I2S_I_CP_OFF                     (0x0 << 8)
+#define RT5640_I2S_I_CP_U_LAW                   (0x1 << 8)
+#define RT5640_I2S_I_CP_A_LAW                   (0x2 << 8)
+#define RT5640_I2S_BP_MASK                      (0x1 << 7)
+#define RT5640_I2S_BP_SFT                       7
+#define RT5640_I2S_BP_NOR                       (0x0 << 7)
+#define RT5640_I2S_BP_INV                       (0x1 << 7)
+#define RT5640_I2S_DL_MASK                      (0x3 << 2)
+#define RT5640_I2S_DL_SFT                       2
+#define RT5640_I2S_DL_16                        (0x0 << 2)
+#define RT5640_I2S_DL_20                        (0x1 << 2)
+#define RT5640_I2S_DL_24                        (0x2 << 2)
+#define RT5640_I2S_DL_8                         (0x3 << 2)
+#define RT5640_I2S_DF_MASK                      (0x3)
+#define RT5640_I2S_DF_SFT                       0
+#define RT5640_I2S_DF_I2S                       (0x0)
+#define RT5640_I2S_DF_LEFT                      (0x1)
+#define RT5640_I2S_DF_PCM_A                     (0x2)
+#define RT5640_I2S_DF_PCM_B                     (0x3)
+
+/* I2S2 Audio Serial Data Port Control (0x71) */
+#define RT5640_I2S2_SDI_MASK                    (0x1 << 6)
+#define RT5640_I2S2_SDI_SFT                     6
+#define RT5640_I2S2_SDI_I2S1                    (0x0 << 6)
+#define RT5640_I2S2_SDI_I2S2                    (0x1 << 6)
+
+/* ADC/DAC Clock Control 1 (0x73) */
+#define RT5640_I2S_BCLK_MS1_MASK                (0x1 << 15)
+#define RT5640_I2S_BCLK_MS1_SFT         15
+#define RT5640_I2S_BCLK_MS1_32                  (0x0 << 15)
+#define RT5640_I2S_BCLK_MS1_64                  (0x1 << 15)
+#define RT5640_I2S_PD1_MASK                     (0x7 << 12)
+#define RT5640_I2S_PD1_SFT                      12
+#define RT5640_I2S_PD1_1                        (0x0 << 12)
+#define RT5640_I2S_PD1_2                        (0x1 << 12)
+#define RT5640_I2S_PD1_3                        (0x2 << 12)
+#define RT5640_I2S_PD1_4                        (0x3 << 12)
+#define RT5640_I2S_PD1_6                        (0x4 << 12)
+#define RT5640_I2S_PD1_8                        (0x5 << 12)
+#define RT5640_I2S_PD1_12                       (0x6 << 12)
+#define RT5640_I2S_PD1_16                       (0x7 << 12)
+#define RT5640_I2S_BCLK_MS2_MASK                (0x1 << 11)
+#define RT5640_I2S_BCLK_MS2_SFT         11
+#define RT5640_I2S_BCLK_MS2_32                  (0x0 << 11)
+#define RT5640_I2S_BCLK_MS2_64                  (0x1 << 11)
+#define RT5640_I2S_PD2_MASK                     (0x7 << 8)
+#define RT5640_I2S_PD2_SFT                      8
+#define RT5640_I2S_PD2_1                        (0x0 << 8)
+#define RT5640_I2S_PD2_2                        (0x1 << 8)
+#define RT5640_I2S_PD2_3                        (0x2 << 8)
+#define RT5640_I2S_PD2_4                        (0x3 << 8)
+#define RT5640_I2S_PD2_6                        (0x4 << 8)
+#define RT5640_I2S_PD2_8                        (0x5 << 8)
+#define RT5640_I2S_PD2_12                       (0x6 << 8)
+#define RT5640_I2S_PD2_16                       (0x7 << 8)
+#define RT5640_I2S_BCLK_MS3_MASK                (0x1 << 7)
+#define RT5640_I2S_BCLK_MS3_SFT         7
+#define RT5640_I2S_BCLK_MS3_32                  (0x0 << 7)
+#define RT5640_I2S_BCLK_MS3_64                  (0x1 << 7)
+#define RT5640_I2S_PD3_MASK                     (0x7 << 4)
+#define RT5640_I2S_PD3_SFT                      4
+#define RT5640_I2S_PD3_1                        (0x0 << 4)
+#define RT5640_I2S_PD3_2                        (0x1 << 4)
+#define RT5640_I2S_PD3_3                        (0x2 << 4)
+#define RT5640_I2S_PD3_4                        (0x3 << 4)
+#define RT5640_I2S_PD3_6                        (0x4 << 4)
+#define RT5640_I2S_PD3_8                        (0x5 << 4)
+#define RT5640_I2S_PD3_12                       (0x6 << 4)
+#define RT5640_I2S_PD3_16                       (0x7 << 4)
+#define RT5640_DAC_OSR_MASK                     (0x3 << 2)
+#define RT5640_DAC_OSR_SFT                      2
+#define RT5640_DAC_OSR_128                      (0x0 << 2)
+#define RT5640_DAC_OSR_64                       (0x1 << 2)
+#define RT5640_DAC_OSR_32                       (0x2 << 2)
+#define RT5640_DAC_OSR_16                       (0x3 << 2)
+#define RT5640_ADC_OSR_MASK                     (0x3)
+#define RT5640_ADC_OSR_SFT                      0
+#define RT5640_ADC_OSR_128                      (0x0)
+#define RT5640_ADC_OSR_64                       (0x1)
+#define RT5640_ADC_OSR_32                       (0x2)
+#define RT5640_ADC_OSR_16                       (0x3)
+
+/* ADC/DAC Clock Control 2 (0x74) */
+#define RT5640_DAC_L_OSR_MASK                   (0x3 << 14)
+#define RT5640_DAC_L_OSR_SFT                    14
+#define RT5640_DAC_L_OSR_128                    (0x0 << 14)
+#define RT5640_DAC_L_OSR_64                     (0x1 << 14)
+#define RT5640_DAC_L_OSR_32                     (0x2 << 14)
+#define RT5640_DAC_L_OSR_16                     (0x3 << 14)
+#define RT5640_ADC_R_OSR_MASK                   (0x3 << 12)
+#define RT5640_ADC_R_OSR_SFT                    12
+#define RT5640_ADC_R_OSR_128                    (0x0 << 12)
+#define RT5640_ADC_R_OSR_64                     (0x1 << 12)
+#define RT5640_ADC_R_OSR_32                     (0x2 << 12)
+#define RT5640_ADC_R_OSR_16                     (0x3 << 12)
+#define RT5640_DAHPF_EN                 (0x1 << 11)
+#define RT5640_DAHPF_EN_SFT                     11
+#define RT5640_ADHPF_EN                 (0x1 << 10)
+#define RT5640_ADHPF_EN_SFT                     10
+
+/* Digital Microphone Control (0x75) */
+#define RT5640_DMIC_1_EN_MASK                   (0x1 << 15)
+#define RT5640_DMIC_1_EN_SFT                    15
+#define RT5640_DMIC_1_DIS                       (0x0 << 15)
+#define RT5640_DMIC_1_EN                        (0x1 << 15)
+#define RT5640_DMIC_2_EN_MASK                   (0x1 << 14)
+#define RT5640_DMIC_2_EN_SFT                    14
+#define RT5640_DMIC_2_DIS                       (0x0 << 14)
+#define RT5640_DMIC_2_EN                        (0x1 << 14)
+#define RT5640_DMIC_1L_LH_MASK          (0x1 << 13)
+#define RT5640_DMIC_1L_LH_SFT                   13
+#define RT5640_DMIC_1L_LH_FALLING               (0x0 << 13)
+#define RT5640_DMIC_1L_LH_RISING                (0x1 << 13)
+#define RT5640_DMIC_1R_LH_MASK          (0x1 << 12)
+#define RT5640_DMIC_1R_LH_SFT                   12
+#define RT5640_DMIC_1R_LH_FALLING               (0x0 << 12)
+#define RT5640_DMIC_1R_LH_RISING                (0x1 << 12)
+#define RT5640_DMIC_1_DP_MASK                   (0x1 << 11)
+#define RT5640_DMIC_1_DP_SFT                    11
+#define RT5640_DMIC_1_DP_GPIO3                  (0x0 << 11)
+#define RT5640_DMIC_1_DP_IN1P                   (0x1 << 11)
+#define RT5640_DMIC_2_DP_MASK                   (0x1 << 10)
+#define RT5640_DMIC_2_DP_SFT                    10
+#define RT5640_DMIC_2_DP_GPIO4                  (0x0 << 10)
+#define RT5640_DMIC_2_DP_IN1N                   (0x1 << 10)
+#define RT5640_DMIC_2L_LH_MASK          (0x1 << 9)
+#define RT5640_DMIC_2L_LH_SFT                   9
+#define RT5640_DMIC_2L_LH_FALLING               (0x0 << 9)
+#define RT5640_DMIC_2L_LH_RISING                (0x1 << 9)
+#define RT5640_DMIC_2R_LH_MASK          (0x1 << 8)
+#define RT5640_DMIC_2R_LH_SFT                   8
+#define RT5640_DMIC_2R_LH_FALLING               (0x0 << 8)
+#define RT5640_DMIC_2R_LH_RISING                (0x1 << 8)
+#define RT5640_DMIC_CLK_MASK                    (0x7 << 5)
+#define RT5640_DMIC_CLK_SFT                     5
+
+/* Global Clock Control (0x80) */
+#define RT5640_SCLK_SRC_MASK                    (0x3 << 14)
+#define RT5640_SCLK_SRC_SFT                     14
+#define RT5640_SCLK_SRC_MCLK                    (0x0 << 14)
+#define RT5640_SCLK_SRC_PLL1                    (0x1 << 14)
+#define RT5640_SCLK_SRC_PLL1T                   (0x2 << 14)
+#define RT5640_SCLK_SRC_RCCLK                   (0x3 << 14) /* 15MHz */
+#define RT5640_PLL1_SRC_MASK                    (0x3 << 12)
+#define RT5640_PLL1_SRC_SFT                     12
+#define RT5640_PLL1_SRC_MCLK                    (0x0 << 12)
+#define RT5640_PLL1_SRC_BCLK1                   (0x1 << 12)
+#define RT5640_PLL1_SRC_BCLK2                   (0x2 << 12)
+#define RT5640_PLL1_SRC_BCLK3                   (0x3 << 12)
+#define RT5640_PLL1_PD_MASK                     (0x1 << 3)
+#define RT5640_PLL1_PD_SFT                      3
+#define RT5640_PLL1_PD_1                        (0x0 << 3)
+#define RT5640_PLL1_PD_2                        (0x1 << 3)
+
+#define RT5640_PLL_INP_MAX                      40000000
+#define RT5640_PLL_INP_MIN                      256000
+/* PLL M/N/K Code Control 1 (0x81) */
+#define RT5640_PLL_N_MAX                        0x1ff
+#define RT5640_PLL_N_MASK                       (RT5640_PLL_N_MAX << 7)
+#define RT5640_PLL_N_SFT                        7
+#define RT5640_PLL_K_MAX                        0x1f
+#define RT5640_PLL_K_MASK                       (RT5640_PLL_K_MAX)
+#define RT5640_PLL_K_SFT                        0
+
+/* PLL M/N/K Code Control 2 (0x82) */
+#define RT5640_PLL_M_MAX                        0xf
+#define RT5640_PLL_M_MASK                       (RT5640_PLL_M_MAX << 12)
+#define RT5640_PLL_M_SFT                        12
+#define RT5640_PLL_M_BP                         (0x1 << 11)
+#define RT5640_PLL_M_BP_SFT                     11
+
+/* ASRC Control 1 (0x83) */
+#define RT5640_STO_T_MASK                       (0x1 << 15)
+#define RT5640_STO_T_SFT                        15
+#define RT5640_STO_T_SCLK                       (0x0 << 15)
+#define RT5640_STO_T_LRCK1                      (0x1 << 15)
+#define RT5640_M1_T_MASK                        (0x1 << 14)
+#define RT5640_M1_T_SFT                         14
+#define RT5640_M1_T_I2S2                        (0x0 << 14)
+#define RT5640_M1_T_I2S2_D3                     (0x1 << 14)
+#define RT5640_I2S2_F_MASK                      (0x1 << 12)
+#define RT5640_I2S2_F_SFT                       12
+#define RT5640_I2S2_F_I2S2_D2                   (0x0 << 12)
+#define RT5640_I2S2_F_I2S1_TCLK                 (0x1 << 12)
+#define RT5640_DMIC_1_M_MASK                    (0x1 << 9)
+#define RT5640_DMIC_1_M_SFT                     9
+#define RT5640_DMIC_1_M_NOR                     (0x0 << 9)
+#define RT5640_DMIC_1_M_ASYN                    (0x1 << 9)
+#define RT5640_DMIC_2_M_MASK                    (0x1 << 8)
+#define RT5640_DMIC_2_M_SFT                     8
+#define RT5640_DMIC_2_M_NOR                     (0x0 << 8)
+#define RT5640_DMIC_2_M_ASYN                    (0x1 << 8)
+
+/* ASRC Control 2 (0x84) */
+#define RT5640_MDA_L_M_MASK                     (0x1 << 15)
+#define RT5640_MDA_L_M_SFT                      15
+#define RT5640_MDA_L_M_NOR                      (0x0 << 15)
+#define RT5640_MDA_L_M_ASYN                     (0x1 << 15)
+#define RT5640_MDA_R_M_MASK                     (0x1 << 14)
+#define RT5640_MDA_R_M_SFT                      14
+#define RT5640_MDA_R_M_NOR                      (0x0 << 14)
+#define RT5640_MDA_R_M_ASYN                     (0x1 << 14)
+#define RT5640_MAD_L_M_MASK                     (0x1 << 13)
+#define RT5640_MAD_L_M_SFT                      13
+#define RT5640_MAD_L_M_NOR                      (0x0 << 13)
+#define RT5640_MAD_L_M_ASYN                     (0x1 << 13)
+#define RT5640_MAD_R_M_MASK                     (0x1 << 12)
+#define RT5640_MAD_R_M_SFT                      12
+#define RT5640_MAD_R_M_NOR                      (0x0 << 12)
+#define RT5640_MAD_R_M_ASYN                     (0x1 << 12)
+#define RT5640_ADC_M_MASK                       (0x1 << 11)
+#define RT5640_ADC_M_SFT                        11
+#define RT5640_ADC_M_NOR                        (0x0 << 11)
+#define RT5640_ADC_M_ASYN                       (0x1 << 11)
+#define RT5640_STO_DAC_M_MASK                   (0x1 << 5)
+#define RT5640_STO_DAC_M_SFT                    5
+#define RT5640_STO_DAC_M_NOR                    (0x0 << 5)
+#define RT5640_STO_DAC_M_ASYN                   (0x1 << 5)
+#define RT5640_I2S1_R_D_MASK                    (0x1 << 4)
+#define RT5640_I2S1_R_D_SFT                     4
+#define RT5640_I2S1_R_D_DIS                     (0x0 << 4)
+#define RT5640_I2S1_R_D_EN                      (0x1 << 4)
+#define RT5640_I2S2_R_D_MASK                    (0x1 << 3)
+#define RT5640_I2S2_R_D_SFT                     3
+#define RT5640_I2S2_R_D_DIS                     (0x0 << 3)
+#define RT5640_I2S2_R_D_EN                      (0x1 << 3)
+#define RT5640_PRE_SCLK_MASK                    (0x3)
+#define RT5640_PRE_SCLK_SFT                     0
+#define RT5640_PRE_SCLK_512                     (0x0)
+#define RT5640_PRE_SCLK_1024                    (0x1)
+#define RT5640_PRE_SCLK_2048                    (0x2)
+
+/* ASRC Control 3 (0x85) */
+#define RT5640_I2S1_RATE_MASK                   (0xf << 12)
+#define RT5640_I2S1_RATE_SFT                    12
+#define RT5640_I2S2_RATE_MASK                   (0xf << 8)
+#define RT5640_I2S2_RATE_SFT                    8
+
+/* ASRC Control 4 (0x89) */
+#define RT5640_I2S1_PD_MASK                     (0x7 << 12)
+#define RT5640_I2S1_PD_SFT                      12
+#define RT5640_I2S2_PD_MASK                     (0x7 << 8)
+#define RT5640_I2S2_PD_SFT                      8
+
+/* HPOUT Over Current Detection (0x8b) */
+#define RT5640_HP_OVCD_MASK                     (0x1 << 10)
+#define RT5640_HP_OVCD_SFT                      10
+#define RT5640_HP_OVCD_DIS                      (0x0 << 10)
+#define RT5640_HP_OVCD_EN                       (0x1 << 10)
+#define RT5640_HP_OC_TH_MASK                    (0x3 << 8)
+#define RT5640_HP_OC_TH_SFT                     8
+#define RT5640_HP_OC_TH_90                      (0x0 << 8)
+#define RT5640_HP_OC_TH_105                     (0x1 << 8)
+#define RT5640_HP_OC_TH_120                     (0x2 << 8)
+#define RT5640_HP_OC_TH_135                     (0x3 << 8)
+
+/* Class D Over Current Control (0x8c) */
+#define RT5640_CLSD_OC_MASK                     (0x1 << 9)
+#define RT5640_CLSD_OC_SFT                      9
+#define RT5640_CLSD_OC_PU                       (0x0 << 9)
+#define RT5640_CLSD_OC_PD                       (0x1 << 9)
+#define RT5640_AUTO_PD_MASK                     (0x1 << 8)
+#define RT5640_AUTO_PD_SFT                      8
+#define RT5640_AUTO_PD_DIS                      (0x0 << 8)
+#define RT5640_AUTO_PD_EN                       (0x1 << 8)
+#define RT5640_CLSD_OC_TH_MASK          (0x3f)
+#define RT5640_CLSD_OC_TH_SFT                   0
+
+/* Class D Output Control (0x8d) */
+#define RT5640_CLSD_RATIO_MASK          (0xf << 12)
+#define RT5640_CLSD_RATIO_SFT                   12
+#define RT5640_CLSD_OM_MASK                     (0x1 << 11)
+#define RT5640_CLSD_OM_SFT                      11
+#define RT5640_CLSD_OM_MONO                     (0x0 << 11)
+#define RT5640_CLSD_OM_STO                      (0x1 << 11)
+#define RT5640_CLSD_SCH_MASK                    (0x1 << 10)
+#define RT5640_CLSD_SCH_SFT                     10
+#define RT5640_CLSD_SCH_L                       (0x0 << 10)
+#define RT5640_CLSD_SCH_S                       (0x1 << 10)
+
+/* Depop Mode Control 1 (0x8e) */
+#define RT5640_SMT_TRIG_MASK                    (0x1 << 15)
+#define RT5640_SMT_TRIG_SFT                     15
+#define RT5640_SMT_TRIG_DIS                     (0x0 << 15)
+#define RT5640_SMT_TRIG_EN                      (0x1 << 15)
+#define RT5640_HP_L_SMT_MASK                    (0x1 << 9)
+#define RT5640_HP_L_SMT_SFT                     9
+#define RT5640_HP_L_SMT_DIS                     (0x0 << 9)
+#define RT5640_HP_L_SMT_EN                      (0x1 << 9)
+#define RT5640_HP_R_SMT_MASK                    (0x1 << 8)
+#define RT5640_HP_R_SMT_SFT                     8
+#define RT5640_HP_R_SMT_DIS                     (0x0 << 8)
+#define RT5640_HP_R_SMT_EN                      (0x1 << 8)
+#define RT5640_HP_CD_PD_MASK                    (0x1 << 7)
+#define RT5640_HP_CD_PD_SFT                     7
+#define RT5640_HP_CD_PD_DIS                     (0x0 << 7)
+#define RT5640_HP_CD_PD_EN                      (0x1 << 7)
+#define RT5640_RSTN_MASK                        (0x1 << 6)
+#define RT5640_RSTN_SFT                         6
+#define RT5640_RSTN_DIS                         (0x0 << 6)
+#define RT5640_RSTN_EN                          (0x1 << 6)
+#define RT5640_RSTP_MASK                        (0x1 << 5)
+#define RT5640_RSTP_SFT                         5
+#define RT5640_RSTP_DIS                         (0x0 << 5)
+#define RT5640_RSTP_EN                          (0x1 << 5)
+#define RT5640_HP_CO_MASK                       (0x1 << 4)
+#define RT5640_HP_CO_SFT                        4
+#define RT5640_HP_CO_DIS                        (0x0 << 4)
+#define RT5640_HP_CO_EN                 (0x1 << 4)
+#define RT5640_HP_CP_MASK                       (0x1 << 3)
+#define RT5640_HP_CP_SFT                        3
+#define RT5640_HP_CP_PD                 (0x0 << 3)
+#define RT5640_HP_CP_PU                 (0x1 << 3)
+#define RT5640_HP_SG_MASK                       (0x1 << 2)
+#define RT5640_HP_SG_SFT                        2
+#define RT5640_HP_SG_DIS                        (0x0 << 2)
+#define RT5640_HP_SG_EN                 (0x1 << 2)
+#define RT5640_HP_DP_MASK                       (0x1 << 1)
+#define RT5640_HP_DP_SFT                        1
+#define RT5640_HP_DP_PD                 (0x0 << 1)
+#define RT5640_HP_DP_PU                 (0x1 << 1)
+#define RT5640_HP_CB_MASK                       (0x1)
+#define RT5640_HP_CB_SFT                        0
+#define RT5640_HP_CB_PD                 (0x0)
+#define RT5640_HP_CB_PU                 (0x1)
+
+/* Depop Mode Control 2 (0x8f) */
+#define RT5640_DEPOP_MASK                       (0x1 << 13)
+#define RT5640_DEPOP_SFT                        13
+#define RT5640_DEPOP_AUTO                       (0x0 << 13)
+#define RT5640_DEPOP_MAN                        (0x1 << 13)
+#define RT5640_RAMP_MASK                        (0x1 << 12)
+#define RT5640_RAMP_SFT                 12
+#define RT5640_RAMP_DIS                         (0x0 << 12)
+#define RT5640_RAMP_EN                          (0x1 << 12)
+#define RT5640_BPS_MASK                 (0x1 << 11)
+#define RT5640_BPS_SFT                          11
+#define RT5640_BPS_DIS                          (0x0 << 11)
+#define RT5640_BPS_EN                           (0x1 << 11)
+#define RT5640_FAST_UPDN_MASK                   (0x1 << 10)
+#define RT5640_FAST_UPDN_SFT                    10
+#define RT5640_FAST_UPDN_DIS                    (0x0 << 10)
+#define RT5640_FAST_UPDN_EN                     (0x1 << 10)
+#define RT5640_MRES_MASK                        (0x3 << 8)
+#define RT5640_MRES_SFT                         8
+#define RT5640_MRES_15MO                        (0x0 << 8)
+#define RT5640_MRES_25MO                        (0x1 << 8)
+#define RT5640_MRES_35MO                        (0x2 << 8)
+#define RT5640_MRES_45MO                        (0x3 << 8)
+#define RT5640_VLO_MASK                 (0x1 << 7)
+#define RT5640_VLO_SFT                          7
+#define RT5640_VLO_3V                           (0x0 << 7)
+#define RT5640_VLO_32V                          (0x1 << 7)
+#define RT5640_DIG_DP_MASK                      (0x1 << 6)
+#define RT5640_DIG_DP_SFT                       6
+#define RT5640_DIG_DP_DIS                       (0x0 << 6)
+#define RT5640_DIG_DP_EN                        (0x1 << 6)
+#define RT5640_DP_TH_MASK                       (0x3 << 4)
+#define RT5640_DP_TH_SFT                        4
+
+/* Depop Mode Control 3 (0x90) */
+#define RT5640_CP_SYS_MASK                      (0x7 << 12)
+#define RT5640_CP_SYS_SFT                       12
+#define RT5640_CP_FQ1_MASK                      (0x7 << 8)
+#define RT5640_CP_FQ1_SFT                       8
+#define RT5640_CP_FQ2_MASK                      (0x7 << 4)
+#define RT5640_CP_FQ2_SFT                       4
+#define RT5640_CP_FQ3_MASK                      (0x7)
+#define RT5640_CP_FQ3_SFT                       0
+
+/* HPOUT charge pump (0x91) */
+#define RT5640_OSW_L_MASK                       (0x1 << 11)
+#define RT5640_OSW_L_SFT                        11
+#define RT5640_OSW_L_DIS                        (0x0 << 11)
+#define RT5640_OSW_L_EN                 (0x1 << 11)
+#define RT5640_OSW_R_MASK                       (0x1 << 10)
+#define RT5640_OSW_R_SFT                        10
+#define RT5640_OSW_R_DIS                        (0x0 << 10)
+#define RT5640_OSW_R_EN                 (0x1 << 10)
+#define RT5640_PM_HP_MASK                       (0x3 << 8)
+#define RT5640_PM_HP_SFT                        8
+#define RT5640_PM_HP_LV                 (0x0 << 8)
+#define RT5640_PM_HP_MV                 (0x1 << 8)
+#define RT5640_PM_HP_HV                 (0x2 << 8)
+#define RT5640_IB_HP_MASK                       (0x3 << 6)
+#define RT5640_IB_HP_SFT                        6
+#define RT5640_IB_HP_125IL                      (0x0 << 6)
+#define RT5640_IB_HP_25IL                       (0x1 << 6)
+#define RT5640_IB_HP_5IL                        (0x2 << 6)
+#define RT5640_IB_HP_1IL                        (0x3 << 6)
+
+/* PV detection and SPK gain control (0x92) */
+#define RT5640_PVDD_DET_MASK                    (0x1 << 15)
+#define RT5640_PVDD_DET_SFT                     15
+#define RT5640_PVDD_DET_DIS                     (0x0 << 15)
+#define RT5640_PVDD_DET_EN                      (0x1 << 15)
+#define RT5640_SPK_AG_MASK                      (0x1 << 14)
+#define RT5640_SPK_AG_SFT                       14
+#define RT5640_SPK_AG_DIS                       (0x0 << 14)
+#define RT5640_SPK_AG_EN                        (0x1 << 14)
+
+/* Micbias Control (0x93) */
+#define RT5640_MIC1_BS_MASK                     (0x1 << 15)
+#define RT5640_MIC1_BS_SFT                      15
+#define RT5640_MIC1_BS_9AV                      (0x0 << 15)
+#define RT5640_MIC1_BS_75AV                     (0x1 << 15)
+#define RT5640_MIC2_BS_MASK                     (0x1 << 14)
+#define RT5640_MIC2_BS_SFT                      14
+#define RT5640_MIC2_BS_9AV                      (0x0 << 14)
+#define RT5640_MIC2_BS_75AV                     (0x1 << 14)
+#define RT5640_MIC1_CLK_MASK                    (0x1 << 13)
+#define RT5640_MIC1_CLK_SFT                     13
+#define RT5640_MIC1_CLK_DIS                     (0x0 << 13)
+#define RT5640_MIC1_CLK_EN                      (0x1 << 13)
+#define RT5640_MIC2_CLK_MASK                    (0x1 << 12)
+#define RT5640_MIC2_CLK_SFT                     12
+#define RT5640_MIC2_CLK_DIS                     (0x0 << 12)
+#define RT5640_MIC2_CLK_EN                      (0x1 << 12)
+#define RT5640_MIC1_OVCD_MASK                   (0x1 << 11)
+#define RT5640_MIC1_OVCD_SFT                    11
+#define RT5640_MIC1_OVCD_DIS                    (0x0 << 11)
+#define RT5640_MIC1_OVCD_EN                     (0x1 << 11)
+#define RT5640_MIC1_OVTH_MASK                   (0x3 << 9)
+#define RT5640_MIC1_OVTH_SFT                    9
+#define RT5640_MIC1_OVTH_600UA          (0x0 << 9)
+#define RT5640_MIC1_OVTH_1500UA         (0x1 << 9)
+#define RT5640_MIC1_OVTH_2000UA         (0x2 << 9)
+#define RT5640_MIC2_OVCD_MASK                   (0x1 << 8)
+#define RT5640_MIC2_OVCD_SFT                    8
+#define RT5640_MIC2_OVCD_DIS                    (0x0 << 8)
+#define RT5640_MIC2_OVCD_EN                     (0x1 << 8)
+#define RT5640_MIC2_OVTH_MASK                   (0x3 << 6)
+#define RT5640_MIC2_OVTH_SFT                    6
+#define RT5640_MIC2_OVTH_600UA          (0x0 << 6)
+#define RT5640_MIC2_OVTH_1500UA         (0x1 << 6)
+#define RT5640_MIC2_OVTH_2000UA         (0x2 << 6)
+#define RT5640_PWR_MB_MASK                      (0x1 << 5)
+#define RT5640_PWR_MB_SFT                       5
+#define RT5640_PWR_MB_PD                        (0x0 << 5)
+#define RT5640_PWR_MB_PU                        (0x1 << 5)
+#define RT5640_PWR_CLK25M_MASK          (0x1 << 4)
+#define RT5640_PWR_CLK25M_SFT                   4
+#define RT5640_PWR_CLK25M_PD                    (0x0 << 4)
+#define RT5640_PWR_CLK25M_PU                    (0x1 << 4)
+
+/* EQ Control 1 (0xb0) */
+#define RT5640_EQ_SRC_MASK                      (0x1 << 15)
+#define RT5640_EQ_SRC_SFT                       15
+#define RT5640_EQ_SRC_DAC                       (0x0 << 15)
+#define RT5640_EQ_SRC_ADC                       (0x1 << 15)
+#define RT5640_EQ_UPD                           (0x1 << 14)
+#define RT5640_EQ_UPD_BIT                       14
+#define RT5640_EQ_CD_MASK                       (0x1 << 13)
+#define RT5640_EQ_CD_SFT                        13
+#define RT5640_EQ_CD_DIS                        (0x0 << 13)
+#define RT5640_EQ_CD_EN                 (0x1 << 13)
+#define RT5640_EQ_DITH_MASK                     (0x3 << 8)
+#define RT5640_EQ_DITH_SFT                      8
+#define RT5640_EQ_DITH_NOR                      (0x0 << 8)
+#define RT5640_EQ_DITH_LSB                      (0x1 << 8)
+#define RT5640_EQ_DITH_LSB_1                    (0x2 << 8)
+#define RT5640_EQ_DITH_LSB_2                    (0x3 << 8)
+
+/* EQ Control 2 (0xb1) */
+#define RT5640_EQ_HPF1_M_MASK                   (0x1 << 8)
+#define RT5640_EQ_HPF1_M_SFT                    8
+#define RT5640_EQ_HPF1_M_HI                     (0x0 << 8)
+#define RT5640_EQ_HPF1_M_1ST                    (0x1 << 8)
+#define RT5640_EQ_LPF1_M_MASK                   (0x1 << 7)
+#define RT5640_EQ_LPF1_M_SFT                    7
+#define RT5640_EQ_LPF1_M_LO                     (0x0 << 7)
+#define RT5640_EQ_LPF1_M_1ST                    (0x1 << 7)
+#define RT5640_EQ_HPF2_MASK                     (0x1 << 6)
+#define RT5640_EQ_HPF2_SFT                      6
+#define RT5640_EQ_HPF2_DIS                      (0x0 << 6)
+#define RT5640_EQ_HPF2_EN                       (0x1 << 6)
+#define RT5640_EQ_HPF1_MASK                     (0x1 << 5)
+#define RT5640_EQ_HPF1_SFT                      5
+#define RT5640_EQ_HPF1_DIS                      (0x0 << 5)
+#define RT5640_EQ_HPF1_EN                       (0x1 << 5)
+#define RT5640_EQ_BPF4_MASK                     (0x1 << 4)
+#define RT5640_EQ_BPF4_SFT                      4
+#define RT5640_EQ_BPF4_DIS                      (0x0 << 4)
+#define RT5640_EQ_BPF4_EN                       (0x1 << 4)
+#define RT5640_EQ_BPF3_MASK                     (0x1 << 3)
+#define RT5640_EQ_BPF3_SFT                      3
+#define RT5640_EQ_BPF3_DIS                      (0x0 << 3)
+#define RT5640_EQ_BPF3_EN                       (0x1 << 3)
+#define RT5640_EQ_BPF2_MASK                     (0x1 << 2)
+#define RT5640_EQ_BPF2_SFT                      2
+#define RT5640_EQ_BPF2_DIS                      (0x0 << 2)
+#define RT5640_EQ_BPF2_EN                       (0x1 << 2)
+#define RT5640_EQ_BPF1_MASK                     (0x1 << 1)
+#define RT5640_EQ_BPF1_SFT                      1
+#define RT5640_EQ_BPF1_DIS                      (0x0 << 1)
+#define RT5640_EQ_BPF1_EN                       (0x1 << 1)
+#define RT5640_EQ_LPF_MASK                      (0x1)
+#define RT5640_EQ_LPF_SFT                       0
+#define RT5640_EQ_LPF_DIS                       (0x0)
+#define RT5640_EQ_LPF_EN                        (0x1)
+
+/* Memory Test (0xb2) */
+#define RT5640_MT_MASK                          (0x1 << 15)
+#define RT5640_MT_SFT                           15
+#define RT5640_MT_DIS                           (0x0 << 15)
+#define RT5640_MT_EN                            (0x1 << 15)
+
+/* DRC/AGC Control 1 (0xb4) */
+#define RT5640_DRC_AGC_P_MASK                   (0x1 << 15)
+#define RT5640_DRC_AGC_P_SFT                    15
+#define RT5640_DRC_AGC_P_DAC                    (0x0 << 15)
+#define RT5640_DRC_AGC_P_ADC                    (0x1 << 15)
+#define RT5640_DRC_AGC_MASK                     (0x1 << 14)
+#define RT5640_DRC_AGC_SFT                      14
+#define RT5640_DRC_AGC_DIS                      (0x0 << 14)
+#define RT5640_DRC_AGC_EN                       (0x1 << 14)
+#define RT5640_DRC_AGC_UPD                      (0x1 << 13)
+#define RT5640_DRC_AGC_UPD_BIT          13
+#define RT5640_DRC_AGC_AR_MASK          (0x1f << 8)
+#define RT5640_DRC_AGC_AR_SFT                   8
+#define RT5640_DRC_AGC_R_MASK                   (0x7 << 5)
+#define RT5640_DRC_AGC_R_SFT                    5
+#define RT5640_DRC_AGC_R_48K                    (0x1 << 5)
+#define RT5640_DRC_AGC_R_96K                    (0x2 << 5)
+#define RT5640_DRC_AGC_R_192K                   (0x3 << 5)
+#define RT5640_DRC_AGC_R_441K                   (0x5 << 5)
+#define RT5640_DRC_AGC_R_882K                   (0x6 << 5)
+#define RT5640_DRC_AGC_R_1764K          (0x7 << 5)
+#define RT5640_DRC_AGC_RC_MASK          (0x1f)
+#define RT5640_DRC_AGC_RC_SFT                   0
+
+/* DRC/AGC Control 2 (0xb5) */
+#define RT5640_DRC_AGC_POB_MASK         (0x3f << 8)
+#define RT5640_DRC_AGC_POB_SFT          8
+#define RT5640_DRC_AGC_CP_MASK          (0x1 << 7)
+#define RT5640_DRC_AGC_CP_SFT                   7
+#define RT5640_DRC_AGC_CP_DIS                   (0x0 << 7)
+#define RT5640_DRC_AGC_CP_EN                    (0x1 << 7)
+#define RT5640_DRC_AGC_CPR_MASK         (0x3 << 5)
+#define RT5640_DRC_AGC_CPR_SFT          5
+#define RT5640_DRC_AGC_CPR_1_1          (0x0 << 5)
+#define RT5640_DRC_AGC_CPR_1_2          (0x1 << 5)
+#define RT5640_DRC_AGC_CPR_1_3          (0x2 << 5)
+#define RT5640_DRC_AGC_CPR_1_4          (0x3 << 5)
+#define RT5640_DRC_AGC_PRB_MASK         (0x1f)
+#define RT5640_DRC_AGC_PRB_SFT          0
+
+/* DRC/AGC Control 3 (0xb6) */
+#define RT5640_DRC_AGC_NGB_MASK         (0xf << 12)
+#define RT5640_DRC_AGC_NGB_SFT          12
+#define RT5640_DRC_AGC_TAR_MASK         (0x1f << 7)
+#define RT5640_DRC_AGC_TAR_SFT          7
+#define RT5640_DRC_AGC_NG_MASK          (0x1 << 6)
+#define RT5640_DRC_AGC_NG_SFT                   6
+#define RT5640_DRC_AGC_NG_DIS                   (0x0 << 6)
+#define RT5640_DRC_AGC_NG_EN                    (0x1 << 6)
+#define RT5640_DRC_AGC_NGH_MASK         (0x1 << 5)
+#define RT5640_DRC_AGC_NGH_SFT          5
+#define RT5640_DRC_AGC_NGH_DIS          (0x0 << 5)
+#define RT5640_DRC_AGC_NGH_EN                   (0x1 << 5)
+#define RT5640_DRC_AGC_NGT_MASK         (0x1f)
+#define RT5640_DRC_AGC_NGT_SFT          0
+
+/* ANC Control 1 (0xb8) */
+#define RT5640_ANC_M_MASK                       (0x1 << 15)
+#define RT5640_ANC_M_SFT                        15
+#define RT5640_ANC_M_NOR                        (0x0 << 15)
+#define RT5640_ANC_M_REV                        (0x1 << 15)
+#define RT5640_ANC_MASK                 (0x1 << 14)
+#define RT5640_ANC_SFT                          14
+#define RT5640_ANC_DIS                          (0x0 << 14)
+#define RT5640_ANC_EN                           (0x1 << 14)
+#define RT5640_ANC_MD_MASK                      (0x3 << 12)
+#define RT5640_ANC_MD_SFT                       12
+#define RT5640_ANC_MD_DIS                       (0x0 << 12)
+#define RT5640_ANC_MD_67MS                      (0x1 << 12)
+#define RT5640_ANC_MD_267MS                     (0x2 << 12)
+#define RT5640_ANC_MD_1067MS                    (0x3 << 12)
+#define RT5640_ANC_SN_MASK                      (0x1 << 11)
+#define RT5640_ANC_SN_SFT                       11
+#define RT5640_ANC_SN_DIS                       (0x0 << 11)
+#define RT5640_ANC_SN_EN                        (0x1 << 11)
+#define RT5640_ANC_CLK_MASK                     (0x1 << 10)
+#define RT5640_ANC_CLK_SFT                      10
+#define RT5640_ANC_CLK_ANC                      (0x0 << 10)
+#define RT5640_ANC_CLK_REG                      (0x1 << 10)
+#define RT5640_ANC_ZCD_MASK                     (0x3 << 8)
+#define RT5640_ANC_ZCD_SFT                      8
+#define RT5640_ANC_ZCD_DIS                      (0x0 << 8)
+#define RT5640_ANC_ZCD_T1                       (0x1 << 8)
+#define RT5640_ANC_ZCD_T2                       (0x2 << 8)
+#define RT5640_ANC_ZCD_WT                       (0x3 << 8)
+#define RT5640_ANC_CS_MASK                      (0x1 << 7)
+#define RT5640_ANC_CS_SFT                       7
+#define RT5640_ANC_CS_DIS                       (0x0 << 7)
+#define RT5640_ANC_CS_EN                        (0x1 << 7)
+#define RT5640_ANC_SW_MASK                      (0x1 << 6)
+#define RT5640_ANC_SW_SFT                       6
+#define RT5640_ANC_SW_NOR                       (0x0 << 6)
+#define RT5640_ANC_SW_AUTO                      (0x1 << 6)
+#define RT5640_ANC_CO_L_MASK                    (0x3f)
+#define RT5640_ANC_CO_L_SFT                     0
+
+/* ANC Control 2 (0xb6) */
+#define RT5640_ANC_FG_R_MASK                    (0xf << 12)
+#define RT5640_ANC_FG_R_SFT                     12
+#define RT5640_ANC_FG_L_MASK                    (0xf << 8)
+#define RT5640_ANC_FG_L_SFT                     8
+#define RT5640_ANC_CG_R_MASK                    (0xf << 4)
+#define RT5640_ANC_CG_R_SFT                     4
+#define RT5640_ANC_CG_L_MASK                    (0xf)
+#define RT5640_ANC_CG_L_SFT                     0
+
+/* ANC Control 3 (0xb6) */
+#define RT5640_ANC_CD_MASK                      (0x1 << 6)
+#define RT5640_ANC_CD_SFT                       6
+#define RT5640_ANC_CD_BOTH                      (0x0 << 6)
+#define RT5640_ANC_CD_IND                       (0x1 << 6)
+#define RT5640_ANC_CO_R_MASK                    (0x3f)
+#define RT5640_ANC_CO_R_SFT                     0
+
+/* Jack Detect Control (0xbb) */
+#define RT5640_JD_MASK                          (0x7 << 13)
+#define RT5640_JD_SFT                           13
+#define RT5640_JD_DIS                           (0x0 << 13)
+#define RT5640_JD_GPIO1                         (0x1 << 13)
+#define RT5640_JD_JD1_IN4P                      (0x2 << 13)
+#define RT5640_JD_JD2_IN4N                      (0x3 << 13)
+#define RT5640_JD_GPIO2                         (0x4 << 13)
+#define RT5640_JD_GPIO3                         (0x5 << 13)
+#define RT5640_JD_GPIO4                         (0x6 << 13)
+#define RT5640_JD_HP_MASK                       (0x1 << 11)
+#define RT5640_JD_HP_SFT                        11
+#define RT5640_JD_HP_DIS                        (0x0 << 11)
+#define RT5640_JD_HP_EN                         (0x1 << 11)
+#define RT5640_JD_HP_TRG_MASK                   (0x1 << 10)
+#define RT5640_JD_HP_TRG_SFT                    10
+#define RT5640_JD_HP_TRG_LO                     (0x0 << 10)
+#define RT5640_JD_HP_TRG_HI                     (0x1 << 10)
+#define RT5640_JD_SPL_MASK                      (0x1 << 9)
+#define RT5640_JD_SPL_SFT                       9
+#define RT5640_JD_SPL_DIS                       (0x0 << 9)
+#define RT5640_JD_SPL_EN                        (0x1 << 9)
+#define RT5640_JD_SPL_TRG_MASK                  (0x1 << 8)
+#define RT5640_JD_SPL_TRG_SFT                   8
+#define RT5640_JD_SPL_TRG_LO                    (0x0 << 8)
+#define RT5640_JD_SPL_TRG_HI                    (0x1 << 8)
+#define RT5640_JD_SPR_MASK                      (0x1 << 7)
+#define RT5640_JD_SPR_SFT                       7
+#define RT5640_JD_SPR_DIS                       (0x0 << 7)
+#define RT5640_JD_SPR_EN                        (0x1 << 7)
+#define RT5640_JD_SPR_TRG_MASK                  (0x1 << 6)
+#define RT5640_JD_SPR_TRG_SFT                   6
+#define RT5640_JD_SPR_TRG_LO                    (0x0 << 6)
+#define RT5640_JD_SPR_TRG_HI                    (0x1 << 6)
+#define RT5640_JD_MO_MASK                       (0x1 << 5)
+#define RT5640_JD_MO_SFT                        5
+#define RT5640_JD_MO_DIS                        (0x0 << 5)
+#define RT5640_JD_MO_EN                 (0x1 << 5)
+#define RT5640_JD_MO_TRG_MASK                   (0x1 << 4)
+#define RT5640_JD_MO_TRG_SFT                    4
+#define RT5640_JD_MO_TRG_LO                     (0x0 << 4)
+#define RT5640_JD_MO_TRG_HI                     (0x1 << 4)
+#define RT5640_JD_LO_MASK                       (0x1 << 3)
+#define RT5640_JD_LO_SFT                        3
+#define RT5640_JD_LO_DIS                        (0x0 << 3)
+#define RT5640_JD_LO_EN                         (0x1 << 3)
+#define RT5640_JD_LO_TRG_MASK                   (0x1 << 2)
+#define RT5640_JD_LO_TRG_SFT                    2
+#define RT5640_JD_LO_TRG_LO                     (0x0 << 2)
+#define RT5640_JD_LO_TRG_HI                     (0x1 << 2)
+#define RT5640_JD1_IN4P_MASK                    (0x1 << 1)
+#define RT5640_JD1_IN4P_SFT                     1
+#define RT5640_JD1_IN4P_DIS                     (0x0 << 1)
+#define RT5640_JD1_IN4P_EN                      (0x1 << 1)
+#define RT5640_JD2_IN4N_MASK                    (0x1)
+#define RT5640_JD2_IN4N_SFT                     0
+#define RT5640_JD2_IN4N_DIS                     (0x0)
+#define RT5640_JD2_IN4N_EN                      (0x1)
+
+/* Jack detect for ANC (0xbc) */
+#define RT5640_ANC_DET_MASK                     (0x3 << 4)
+#define RT5640_ANC_DET_SFT                      4
+#define RT5640_ANC_DET_DIS                      (0x0 << 4)
+#define RT5640_ANC_DET_MB1                      (0x1 << 4)
+#define RT5640_ANC_DET_MB2                      (0x2 << 4)
+#define RT5640_ANC_DET_JD                       (0x3 << 4)
+#define RT5640_AD_TRG_MASK                      (0x1 << 3)
+#define RT5640_AD_TRG_SFT                       3
+#define RT5640_AD_TRG_LO                        (0x0 << 3)
+#define RT5640_AD_TRG_HI                        (0x1 << 3)
+#define RT5640_ANCM_DET_MASK                    (0x3 << 4)
+#define RT5640_ANCM_DET_SFT                     4
+#define RT5640_ANCM_DET_DIS                     (0x0 << 4)
+#define RT5640_ANCM_DET_MB1                     (0x1 << 4)
+#define RT5640_ANCM_DET_MB2                     (0x2 << 4)
+#define RT5640_ANCM_DET_JD                      (0x3 << 4)
+#define RT5640_AMD_TRG_MASK                     (0x1 << 3)
+#define RT5640_AMD_TRG_SFT                      3
+#define RT5640_AMD_TRG_LO                       (0x0 << 3)
+#define RT5640_AMD_TRG_HI                       (0x1 << 3)
+
+/* IRQ Control 1 (0xbd) */
+#define RT5640_IRQ_JD_MASK                      (0x1 << 15)
+#define RT5640_IRQ_JD_SFT                       15
+#define RT5640_IRQ_JD_BP                        (0x0 << 15)
+#define RT5640_IRQ_JD_NOR                       (0x1 << 15)
+#define RT5640_IRQ_OT_MASK                      (0x1 << 14)
+#define RT5640_IRQ_OT_SFT                       14
+#define RT5640_IRQ_OT_BP                        (0x0 << 14)
+#define RT5640_IRQ_OT_NOR                       (0x1 << 14)
+#define RT5640_JD_STKY_MASK                     (0x1 << 13)
+#define RT5640_JD_STKY_SFT                      13
+#define RT5640_JD_STKY_DIS                      (0x0 << 13)
+#define RT5640_JD_STKY_EN                       (0x1 << 13)
+#define RT5640_OT_STKY_MASK                     (0x1 << 12)
+#define RT5640_OT_STKY_SFT                      12
+#define RT5640_OT_STKY_DIS                      (0x0 << 12)
+#define RT5640_OT_STKY_EN                       (0x1 << 12)
+#define RT5640_JD_P_MASK                        (0x1 << 11)
+#define RT5640_JD_P_SFT                         11
+#define RT5640_JD_P_NOR                         (0x0 << 11)
+#define RT5640_JD_P_INV                         (0x1 << 11)
+#define RT5640_OT_P_MASK                        (0x1 << 10)
+#define RT5640_OT_P_SFT                         10
+#define RT5640_OT_P_NOR                 (0x0 << 10)
+#define RT5640_OT_P_INV                         (0x1 << 10)
+
+/* IRQ Control 2 (0xbe) */
+#define RT5640_IRQ_MB1_OC_MASK          (0x1 << 15)
+#define RT5640_IRQ_MB1_OC_SFT                   15
+#define RT5640_IRQ_MB1_OC_BP                    (0x0 << 15)
+#define RT5640_IRQ_MB1_OC_NOR                   (0x1 << 15)
+#define RT5640_IRQ_MB2_OC_MASK          (0x1 << 14)
+#define RT5640_IRQ_MB2_OC_SFT                   14
+#define RT5640_IRQ_MB2_OC_BP                    (0x0 << 14)
+#define RT5640_IRQ_MB2_OC_NOR                   (0x1 << 14)
+#define RT5640_MB1_OC_STKY_MASK         (0x1 << 11)
+#define RT5640_MB1_OC_STKY_SFT          11
+#define RT5640_MB1_OC_STKY_DIS          (0x0 << 11)
+#define RT5640_MB1_OC_STKY_EN                   (0x1 << 11)
+#define RT5640_MB2_OC_STKY_MASK         (0x1 << 10)
+#define RT5640_MB2_OC_STKY_SFT          10
+#define RT5640_MB2_OC_STKY_DIS          (0x0 << 10)
+#define RT5640_MB2_OC_STKY_EN                   (0x1 << 10)
+#define RT5640_MB1_OC_P_MASK                    (0x1 << 7)
+#define RT5640_MB1_OC_P_SFT                     7
+#define RT5640_MB1_OC_P_NOR                     (0x0 << 7)
+#define RT5640_MB1_OC_P_INV                     (0x1 << 7)
+#define RT5640_MB2_OC_P_MASK                    (0x1 << 6)
+#define RT5640_MB2_OC_P_SFT                     6
+#define RT5640_MB2_OC_P_NOR                     (0x0 << 6)
+#define RT5640_MB2_OC_P_INV                     (0x1 << 6)
+#define RT5640_MB1_OC_CLR                       (0x1 << 3)
+#define RT5640_MB1_OC_CLR_SFT                   3
+#define RT5640_MB2_OC_CLR                       (0x1 << 2)
+#define RT5640_MB2_OC_CLR_SFT                   2
+
+/* GPIO Control 1 (0xc0) */
+#define RT5640_GP1_PIN_MASK                     (0x1 << 15)
+#define RT5640_GP1_PIN_SFT                      15
+#define RT5640_GP1_PIN_GPIO1                    (0x0 << 15)
+#define RT5640_GP1_PIN_IRQ                      (0x1 << 15)
+#define RT5640_GP2_PIN_MASK                     (0x1 << 14)
+#define RT5640_GP2_PIN_SFT                      14
+#define RT5640_GP2_PIN_GPIO2                    (0x0 << 14)
+#define RT5640_GP2_PIN_DMIC1_SCL                (0x1 << 14)
+#define RT5640_GP3_PIN_MASK                     (0x3 << 12)
+#define RT5640_GP3_PIN_SFT                      12
+#define RT5640_GP3_PIN_GPIO3                    (0x0 << 12)
+#define RT5640_GP3_PIN_DMIC1_SDA                (0x1 << 12)
+#define RT5640_GP3_PIN_IRQ                      (0x2 << 12)
+#define RT5640_GP4_PIN_MASK                     (0x1 << 11)
+#define RT5640_GP4_PIN_SFT                      11
+#define RT5640_GP4_PIN_GPIO4                    (0x0 << 11)
+#define RT5640_GP4_PIN_DMIC2_SDA                (0x1 << 11)
+#define RT5640_DP_SIG_MASK                      (0x1 << 10)
+#define RT5640_DP_SIG_SFT                       10
+#define RT5640_DP_SIG_TEST                      (0x0 << 10)
+#define RT5640_DP_SIG_AP                        (0x1 << 10)
+#define RT5640_GPIO_M_MASK                      (0x1 << 9)
+#define RT5640_GPIO_M_SFT                       9
+#define RT5640_GPIO_M_FLT                       (0x0 << 9)
+#define RT5640_GPIO_M_PH                        (0x1 << 9)
+
+/* GPIO Control 3 (0xc2) */
+#define RT5640_GP4_PF_MASK                      (0x1 << 11)
+#define RT5640_GP4_PF_SFT                       11
+#define RT5640_GP4_PF_IN                        (0x0 << 11)
+#define RT5640_GP4_PF_OUT                       (0x1 << 11)
+#define RT5640_GP4_OUT_MASK                     (0x1 << 10)
+#define RT5640_GP4_OUT_SFT                      10
+#define RT5640_GP4_OUT_LO                       (0x0 << 10)
+#define RT5640_GP4_OUT_HI                       (0x1 << 10)
+#define RT5640_GP4_P_MASK                       (0x1 << 9)
+#define RT5640_GP4_P_SFT                        9
+#define RT5640_GP4_P_NOR                        (0x0 << 9)
+#define RT5640_GP4_P_INV                        (0x1 << 9)
+#define RT5640_GP3_PF_MASK                      (0x1 << 8)
+#define RT5640_GP3_PF_SFT                       8
+#define RT5640_GP3_PF_IN                        (0x0 << 8)
+#define RT5640_GP3_PF_OUT                       (0x1 << 8)
+#define RT5640_GP3_OUT_MASK                     (0x1 << 7)
+#define RT5640_GP3_OUT_SFT                      7
+#define RT5640_GP3_OUT_LO                       (0x0 << 7)
+#define RT5640_GP3_OUT_HI                       (0x1 << 7)
+#define RT5640_GP3_P_MASK                       (0x1 << 6)
+#define RT5640_GP3_P_SFT                        6
+#define RT5640_GP3_P_NOR                        (0x0 << 6)
+#define RT5640_GP3_P_INV                        (0x1 << 6)
+#define RT5640_GP2_PF_MASK                      (0x1 << 5)
+#define RT5640_GP2_PF_SFT                       5
+#define RT5640_GP2_PF_IN                        (0x0 << 5)
+#define RT5640_GP2_PF_OUT                       (0x1 << 5)
+#define RT5640_GP2_OUT_MASK                     (0x1 << 4)
+#define RT5640_GP2_OUT_SFT                      4
+#define RT5640_GP2_OUT_LO                       (0x0 << 4)
+#define RT5640_GP2_OUT_HI                       (0x1 << 4)
+#define RT5640_GP2_P_MASK                       (0x1 << 3)
+#define RT5640_GP2_P_SFT                        3
+#define RT5640_GP2_P_NOR                        (0x0 << 3)
+#define RT5640_GP2_P_INV                        (0x1 << 3)
+#define RT5640_GP1_PF_MASK                      (0x1 << 2)
+#define RT5640_GP1_PF_SFT                       2
+#define RT5640_GP1_PF_IN                        (0x0 << 2)
+#define RT5640_GP1_PF_OUT                       (0x1 << 2)
+#define RT5640_GP1_OUT_MASK                     (0x1 << 1)
+#define RT5640_GP1_OUT_SFT                      1
+#define RT5640_GP1_OUT_LO                       (0x0 << 1)
+#define RT5640_GP1_OUT_HI                       (0x1 << 1)
+#define RT5640_GP1_P_MASK                       (0x1)
+#define RT5640_GP1_P_SFT                        0
+#define RT5640_GP1_P_NOR                        (0x0)
+#define RT5640_GP1_P_INV                        (0x1)
+
+/* FM34-500 Register Control 1 (0xc4) */
+#define RT5640_DSP_ADD_SFT                      0
+
+/* FM34-500 Register Control 2 (0xc5) */
+#define RT5640_DSP_DAT_SFT                      0
+
+/* FM34-500 Register Control 3 (0xc6) */
+#define RT5640_DSP_BUSY_MASK                    (0x1 << 15)
+#define RT5640_DSP_BUSY_BIT                     15
+#define RT5640_DSP_DS_MASK                      (0x1 << 14)
+#define RT5640_DSP_DS_SFT                       14
+#define RT5640_DSP_DS_FM3010                    (0x1 << 14)
+#define RT5640_DSP_DS_TEMP                      (0x1 << 14)
+#define RT5640_DSP_CLK_MASK                     (0x3 << 12)
+#define RT5640_DSP_CLK_SFT                      12
+#define RT5640_DSP_CLK_384K                     (0x0 << 12)
+#define RT5640_DSP_CLK_192K                     (0x1 << 12)
+#define RT5640_DSP_CLK_96K                      (0x2 << 12)
+#define RT5640_DSP_CLK_64K                      (0x3 << 12)
+#define RT5640_DSP_PD_PIN_MASK          (0x1 << 11)
+#define RT5640_DSP_PD_PIN_SFT                   11
+#define RT5640_DSP_PD_PIN_LO                    (0x0 << 11)
+#define RT5640_DSP_PD_PIN_HI                    (0x1 << 11)
+#define RT5640_DSP_RST_PIN_MASK         (0x1 << 10)
+#define RT5640_DSP_RST_PIN_SFT                  10
+#define RT5640_DSP_RST_PIN_LO                   (0x0 << 10)
+#define RT5640_DSP_RST_PIN_HI                   (0x1 << 10)
+#define RT5640_DSP_R_EN                         (0x1 << 9)
+#define RT5640_DSP_R_EN_BIT                     9
+#define RT5640_DSP_W_EN                 (0x1 << 8)
+#define RT5640_DSP_W_EN_BIT                     8
+#define RT5640_DSP_CMD_MASK                     (0xff)
+#define RT5640_DSP_CMD_SFT                      0
+#define RT5640_DSP_CMD_MW                       (0x3B)  /* Memory Write */
+#define RT5640_DSP_CMD_MR                       (0x37)  /* Memory Read */
+#define RT5640_DSP_CMD_RR                       (0x60)  /* Register Read */
+#define RT5640_DSP_CMD_RW                       (0x68)  /* Register Write */
+
+/* Programmable Register Array Control 1 (0xc8) */
+#define RT5640_REG_SEQ_MASK                     (0xf << 12)
+#define RT5640_REG_SEQ_SFT                      12
+#define RT5640_SEQ1_ST_MASK                     (0x1 << 11) /*RO*/
+#define RT5640_SEQ1_ST_SFT                      11
+#define RT5640_SEQ1_ST_RUN                      (0x0 << 11)
+#define RT5640_SEQ1_ST_FIN                      (0x1 << 11)
+#define RT5640_SEQ2_ST_MASK                     (0x1 << 10) /*RO*/
+#define RT5640_SEQ2_ST_SFT                      10
+#define RT5640_SEQ2_ST_RUN                      (0x0 << 10)
+#define RT5640_SEQ2_ST_FIN                      (0x1 << 10)
+#define RT5640_REG_LV_MASK                      (0x1 << 9)
+#define RT5640_REG_LV_SFT                       9
+#define RT5640_REG_LV_MX                        (0x0 << 9)
+#define RT5640_REG_LV_PR                        (0x1 << 9)
+#define RT5640_SEQ_2_PT_MASK                    (0x1 << 8)
+#define RT5640_SEQ_2_PT_BIT                     8
+#define RT5640_REG_IDX_MASK                     (0xff)
+#define RT5640_REG_IDX_SFT                      0
+
+/* Programmable Register Array Control 2 (0xc9) */
+#define RT5640_REG_DAT_MASK                     (0xffff)
+#define RT5640_REG_DAT_SFT                      0
+
+/* Programmable Register Array Control 3 (0xca) */
+#define RT5640_SEQ_DLY_MASK                     (0xff << 8)
+#define RT5640_SEQ_DLY_SFT                      8
+#define RT5640_PROG_MASK                        (0x1 << 7)
+#define RT5640_PROG_SFT                         7
+#define RT5640_PROG_DIS                         (0x0 << 7)
+#define RT5640_PROG_EN                          (0x1 << 7)
+#define RT5640_SEQ1_PT_RUN                      (0x1 << 6)
+#define RT5640_SEQ1_PT_RUN_BIT                  6
+#define RT5640_SEQ2_PT_RUN                      (0x1 << 5)
+#define RT5640_SEQ2_PT_RUN_BIT                  5
+
+/* Programmable Register Array Control 4 (0xcb) */
+#define RT5640_SEQ1_START_MASK          (0xf << 8)
+#define RT5640_SEQ1_START_SFT                   8
+#define RT5640_SEQ1_END_MASK                    (0xf)
+#define RT5640_SEQ1_END_SFT                     0
+
+/* Programmable Register Array Control 5 (0xcc) */
+#define RT5640_SEQ2_START_MASK          (0xf << 8)
+#define RT5640_SEQ2_START_SFT                   8
+#define RT5640_SEQ2_END_MASK                    (0xf)
+#define RT5640_SEQ2_END_SFT                     0
+
+/* Scramble Function (0xcd) */
+#define RT5640_SCB_KEY_MASK                     (0xff)
+#define RT5640_SCB_KEY_SFT                      0
+
+/* Scramble Control (0xce) */
+#define RT5640_SCB_SWAP_MASK                    (0x1 << 15)
+#define RT5640_SCB_SWAP_SFT                     15
+#define RT5640_SCB_SWAP_DIS                     (0x0 << 15)
+#define RT5640_SCB_SWAP_EN                      (0x1 << 15)
+#define RT5640_SCB_MASK                 (0x1 << 14)
+#define RT5640_SCB_SFT                          14
+#define RT5640_SCB_DIS                          (0x0 << 14)
+#define RT5640_SCB_EN                           (0x1 << 14)
+
+/* Baseback Control (0xcf) */
+#define RT5640_BB_MASK                          (0x1 << 15)
+#define RT5640_BB_SFT                           15
+#define RT5640_BB_DIS                           (0x0 << 15)
+#define RT5640_BB_EN                            (0x1 << 15)
+#define RT5640_BB_CT_MASK                       (0x7 << 12)
+#define RT5640_BB_CT_SFT                        12
+#define RT5640_BB_CT_A                          (0x0 << 12)
+#define RT5640_BB_CT_B                          (0x1 << 12)
+#define RT5640_BB_CT_C                          (0x2 << 12)
+#define RT5640_BB_CT_D                          (0x3 << 12)
+#define RT5640_M_BB_L_MASK                      (0x1 << 9)
+#define RT5640_M_BB_L_SFT                       9
+#define RT5640_M_BB_R_MASK                      (0x1 << 8)
+#define RT5640_M_BB_R_SFT                       8
+#define RT5640_M_BB_HPF_L_MASK          (0x1 << 7)
+#define RT5640_M_BB_HPF_L_SFT                   7
+#define RT5640_M_BB_HPF_R_MASK          (0x1 << 6)
+#define RT5640_M_BB_HPF_R_SFT                   6
+#define RT5640_G_BB_BST_MASK                    (0x3f)
+#define RT5640_G_BB_BST_SFT                     0
+
+/* MP3 Plus Control 1 (0xd0) */
+#define RT5640_M_MP3_L_MASK                     (0x1 << 15)
+#define RT5640_M_MP3_L_SFT                      15
+#define RT5640_M_MP3_R_MASK                     (0x1 << 14)
+#define RT5640_M_MP3_R_SFT                      14
+#define RT5640_M_MP3_MASK                       (0x1 << 13)
+#define RT5640_M_MP3_SFT                        13
+#define RT5640_M_MP3_DIS                        (0x0 << 13)
+#define RT5640_M_MP3_EN                 (0x1 << 13)
+#define RT5640_EG_MP3_MASK                      (0x1f << 8)
+#define RT5640_EG_MP3_SFT                       8
+#define RT5640_MP3_HLP_MASK                     (0x1 << 7)
+#define RT5640_MP3_HLP_SFT                      7
+#define RT5640_MP3_HLP_DIS                      (0x0 << 7)
+#define RT5640_MP3_HLP_EN                       (0x1 << 7)
+#define RT5640_M_MP3_ORG_L_MASK         (0x1 << 6)
+#define RT5640_M_MP3_ORG_L_SFT          6
+#define RT5640_M_MP3_ORG_R_MASK         (0x1 << 5)
+#define RT5640_M_MP3_ORG_R_SFT          5
+
+/* MP3 Plus Control 2 (0xd1) */
+#define RT5640_MP3_WT_MASK                      (0x1 << 13)
+#define RT5640_MP3_WT_SFT                       13
+#define RT5640_MP3_WT_1_4                       (0x0 << 13)
+#define RT5640_MP3_WT_1_2                       (0x1 << 13)
+#define RT5640_OG_MP3_MASK                      (0x1f << 8)
+#define RT5640_OG_MP3_SFT                       8
+#define RT5640_HG_MP3_MASK                      (0x3f)
+#define RT5640_HG_MP3_SFT                       0
+
+/* 3D HP Control 1 (0xd2) */
+#define RT5640_3D_CF_MASK                       (0x1 << 15)
+#define RT5640_3D_CF_SFT                        15
+#define RT5640_3D_CF_DIS                        (0x0 << 15)
+#define RT5640_3D_CF_EN                 (0x1 << 15)
+#define RT5640_3D_HP_MASK                       (0x1 << 14)
+#define RT5640_3D_HP_SFT                        14
+#define RT5640_3D_HP_DIS                        (0x0 << 14)
+#define RT5640_3D_HP_EN                 (0x1 << 14)
+#define RT5640_3D_BT_MASK                       (0x1 << 13)
+#define RT5640_3D_BT_SFT                        13
+#define RT5640_3D_BT_DIS                        (0x0 << 13)
+#define RT5640_3D_BT_EN                         (0x1 << 13)
+#define RT5640_3D_1F_MIX_MASK                   (0x3 << 11)
+#define RT5640_3D_1F_MIX_SFT                    11
+#define RT5640_3D_HP_M_MASK                     (0x1 << 10)
+#define RT5640_3D_HP_M_SFT                      10
+#define RT5640_3D_HP_M_SUR                      (0x0 << 10)
+#define RT5640_3D_HP_M_FRO                      (0x1 << 10)
+#define RT5640_M_3D_HRTF_MASK                   (0x1 << 9)
+#define RT5640_M_3D_HRTF_SFT                    9
+#define RT5640_M_3D_D2H_MASK                    (0x1 << 8)
+#define RT5640_M_3D_D2H_SFT                     8
+#define RT5640_M_3D_D2R_MASK                    (0x1 << 7)
+#define RT5640_M_3D_D2R_SFT                     7
+#define RT5640_M_3D_REVB_MASK                   (0x1 << 6)
+#define RT5640_M_3D_REVB_SFT                    6
+
+/* Adjustable high pass filter control 1 (0xd3) */
+#define RT5640_2ND_HPF_MASK                     (0x1 << 15)
+#define RT5640_2ND_HPF_SFT                      15
+#define RT5640_2ND_HPF_DIS                      (0x0 << 15)
+#define RT5640_2ND_HPF_EN                       (0x1 << 15)
+#define RT5640_HPF_CF_L_MASK                    (0x7 << 12)
+#define RT5640_HPF_CF_L_SFT                     12
+#define RT5640_1ST_HPF_MASK                     (0x1 << 11)
+#define RT5640_1ST_HPF_SFT                      11
+#define RT5640_1ST_HPF_DIS                      (0x0 << 11)
+#define RT5640_1ST_HPF_EN                       (0x1 << 11)
+#define RT5640_HPF_CF_R_MASK                    (0x7 << 8)
+#define RT5640_HPF_CF_R_SFT                     8
+#define RT5640_ZD_T_MASK                        (0x3 << 6)
+#define RT5640_ZD_T_SFT                         6
+#define RT5640_ZD_F_MASK                        (0x3 << 4)
+#define RT5640_ZD_F_SFT                         4
+#define RT5640_ZD_F_IM                          (0x0 << 4)
+#define RT5640_ZD_F_ZC_IM                       (0x1 << 4)
+#define RT5640_ZD_F_ZC_IOD                      (0x2 << 4)
+#define RT5640_ZD_F_UN                          (0x3 << 4)
+
+/* HP calibration control and Amp detection (0xd6) */
+#define RT5640_SI_DAC_MASK                      (0x1 << 11)
+#define RT5640_SI_DAC_SFT                       11
+#define RT5640_SI_DAC_AUTO                      (0x0 << 11)
+#define RT5640_SI_DAC_TEST                      (0x1 << 11)
+#define RT5640_DC_CAL_M_MASK                    (0x1 << 10)
+#define RT5640_DC_CAL_M_SFT                     10
+#define RT5640_DC_CAL_M_CAL                     (0x0 << 10)
+#define RT5640_DC_CAL_M_NOR                     (0x1 << 10)
+#define RT5640_DC_CAL_MASK                      (0x1 << 9)
+#define RT5640_DC_CAL_SFT                       9
+#define RT5640_DC_CAL_DIS                       (0x0 << 9)
+#define RT5640_DC_CAL_EN                        (0x1 << 9)
+#define RT5640_HPD_RCV_MASK                     (0x7 << 6)
+#define RT5640_HPD_RCV_SFT                      6
+#define RT5640_HPD_PS_MASK                      (0x1 << 5)
+#define RT5640_HPD_PS_SFT                       5
+#define RT5640_HPD_PS_DIS                       (0x0 << 5)
+#define RT5640_HPD_PS_EN                        (0x1 << 5)
+#define RT5640_CAL_M_MASK                       (0x1 << 4)
+#define RT5640_CAL_M_SFT                        4
+#define RT5640_CAL_M_DEP                        (0x0 << 4)
+#define RT5640_CAL_M_CAL                        (0x1 << 4)
+#define RT5640_CAL_MASK                 (0x1 << 3)
+#define RT5640_CAL_SFT                          3
+#define RT5640_CAL_DIS                          (0x0 << 3)
+#define RT5640_CAL_EN                           (0x1 << 3)
+#define RT5640_CAL_TEST_MASK                    (0x1 << 2)
+#define RT5640_CAL_TEST_SFT                     2
+#define RT5640_CAL_TEST_DIS                     (0x0 << 2)
+#define RT5640_CAL_TEST_EN                      (0x1 << 2)
+#define RT5640_CAL_P_MASK                       (0x3)
+#define RT5640_CAL_P_SFT                        0
+#define RT5640_CAL_P_NONE                       (0x0)
+#define RT5640_CAL_P_CAL                        (0x1)
+#define RT5640_CAL_P_DAC_CAL                    (0x2)
+
+/* Soft volume and zero cross control 1 (0xd9) */
+#define RT5640_SV_MASK                          (0x1 << 15)
+#define RT5640_SV_SFT                           15
+#define RT5640_SV_DIS                           (0x0 << 15)
+#define RT5640_SV_EN                            (0x1 << 15)
+#define RT5640_SPO_SV_MASK                      (0x1 << 14)
+#define RT5640_SPO_SV_SFT                       14
+#define RT5640_SPO_SV_DIS                       (0x0 << 14)
+#define RT5640_SPO_SV_EN                        (0x1 << 14)
+#define RT5640_OUT_SV_MASK                      (0x1 << 13)
+#define RT5640_OUT_SV_SFT                       13
+#define RT5640_OUT_SV_DIS                       (0x0 << 13)
+#define RT5640_OUT_SV_EN                        (0x1 << 13)
+#define RT5640_HP_SV_MASK                       (0x1 << 12)
+#define RT5640_HP_SV_SFT                        12
+#define RT5640_HP_SV_DIS                        (0x0 << 12)
+#define RT5640_HP_SV_EN                 (0x1 << 12)
+#define RT5640_ZCD_DIG_MASK                     (0x1 << 11)
+#define RT5640_ZCD_DIG_SFT                      11
+#define RT5640_ZCD_DIG_DIS                      (0x0 << 11)
+#define RT5640_ZCD_DIG_EN                       (0x1 << 11)
+#define RT5640_ZCD_MASK                 (0x1 << 10)
+#define RT5640_ZCD_SFT                          10
+#define RT5640_ZCD_PD                           (0x0 << 10)
+#define RT5640_ZCD_PU                           (0x1 << 10)
+#define RT5640_M_ZCD_MASK                       (0x3f << 4)
+#define RT5640_M_ZCD_SFT                        4
+#define RT5640_M_ZCD_RM_L                       (0x1 << 9)
+#define RT5640_M_ZCD_RM_R                       (0x1 << 8)
+#define RT5640_M_ZCD_SM_L                       (0x1 << 7)
+#define RT5640_M_ZCD_SM_R                       (0x1 << 6)
+#define RT5640_M_ZCD_OM_L                       (0x1 << 5)
+#define RT5640_M_ZCD_OM_R                       (0x1 << 4)
+#define RT5640_SV_DLY_MASK                      (0xf)
+#define RT5640_SV_DLY_SFT                       0
+
+/* Soft volume and zero cross control 2 (0xda) */
+#define RT5640_ZCD_HP_MASK                      (0x1 << 15)
+#define RT5640_ZCD_HP_SFT                       15
+#define RT5640_ZCD_HP_DIS                       (0x0 << 15)
+#define RT5640_ZCD_HP_EN                        (0x1 << 15)
+
+
+/* Codec Private Register definition */
+/* 3D Speaker Control (0x63) */
+#define RT5640_3D_SPK_MASK                      (0x1 << 15)
+#define RT5640_3D_SPK_SFT                       15
+#define RT5640_3D_SPK_DIS                       (0x0 << 15)
+#define RT5640_3D_SPK_EN                        (0x1 << 15)
+#define RT5640_3D_SPK_M_MASK                    (0x3 << 13)
+#define RT5640_3D_SPK_M_SFT                     13
+#define RT5640_3D_SPK_CG_MASK                   (0x1f << 8)
+#define RT5640_3D_SPK_CG_SFT                    8
+#define RT5640_3D_SPK_SG_MASK                   (0x1f)
+#define RT5640_3D_SPK_SG_SFT                    0
+
+/* Wind Noise Detection Control 1 (0x6c) */
+#define RT5640_WND_MASK                 (0x1 << 15)
+#define RT5640_WND_SFT                          15
+#define RT5640_WND_DIS                          (0x0 << 15)
+#define RT5640_WND_EN                           (0x1 << 15)
+
+/* Wind Noise Detection Control 2 (0x6d) */
+#define RT5640_WND_FC_NW_MASK           (0x3f << 10)
+#define RT5640_WND_FC_NW_SFT                    10
+#define RT5640_WND_FC_WK_MASK           (0x3f << 4)
+#define RT5640_WND_FC_WK_SFT                    4
+
+/* Wind Noise Detection Control 3 (0x6e) */
+#define RT5640_HPF_FC_MASK                      (0x3f << 6)
+#define RT5640_HPF_FC_SFT                       6
+#define RT5640_WND_FC_ST_MASK                   (0x3f)
+#define RT5640_WND_FC_ST_SFT                    0
+
+/* Wind Noise Detection Control 4 (0x6f) */
+#define RT5640_WND_TH_LO_MASK           (0x3ff)
+#define RT5640_WND_TH_LO_SFT                    0
+
+/* Wind Noise Detection Control 5 (0x70) */
+#define RT5640_WND_TH_HI_MASK                   (0x3ff)
+#define RT5640_WND_TH_HI_SFT                    0
+
+/* Wind Noise Detection Control 8 (0x73) */
+#define RT5640_WND_WIND_MASK                    (0x1 << 13) /* Read-Only */
+#define RT5640_WND_WIND_SFT                     13
+#define RT5640_WND_STRONG_MASK          (0x1 << 12) /* Read-Only */
+#define RT5640_WND_STRONG_SFT                   12
+enum {
+        RT5640_NO_WIND,
+        RT5640_BREEZE,
+        RT5640_STORM,
+};
+
+/* Dipole Speaker Interface (0x75) */
+#define RT5640_DP_ATT_MASK                      (0x3 << 14)
+#define RT5640_DP_ATT_SFT                       14
+#define RT5640_DP_SPK_MASK                      (0x1 << 10)
+#define RT5640_DP_SPK_SFT                       10
+#define RT5640_DP_SPK_DIS                       (0x0 << 10)
+#define RT5640_DP_SPK_EN                        (0x1 << 10)
+
+/* EQ Pre Volume Control (0xb3) */
+#define RT5640_EQ_PRE_VOL_MASK          (0xffff)
+#define RT5640_EQ_PRE_VOL_SFT                   0
+
+/* EQ Post Volume Control (0xb4) */
+#define RT5640_EQ_PST_VOL_MASK          (0xffff)
+#define RT5640_EQ_PST_VOL_SFT                   0
+
+#define RT5640_NO_JACK          BIT(0)
+#define RT5640_HEADSET_DET      BIT(1)
+#define RT5640_HEADPHO_DET      BIT(2)
+
+int rt5640_headset_detect(struct snd_soc_codec *codec, int jack_insert);
+
+/* System Clock Source */
+#define RT5640_SCLK_S_MCLK 0
+#define RT5640_SCLK_S_PLL1 1
+#define RT5640_SCLK_S_PLL1_TK 2
+#define RT5640_SCLK_S_RCCLK 3
+
+/* PLL1 Source */
+#define RT5640_PLL1_S_MCLK 0
+#define RT5640_PLL1_S_BCLK1 1
+#define RT5640_PLL1_S_BCLK2 2
+#define RT5640_PLL1_S_BCLK3 3
+
+
+enum {
+        RT5640_AIF1,
+        RT5640_AIF2,
+        RT5640_AIF3,
+        RT5640_AIFS,
+};
+
+enum {
+        RT5640_U_IF1 = 0x1,
+        RT5640_U_IF2 = 0x2,
+        RT5640_U_IF3 = 0x4,
+};
+
+enum {
+        RT5640_IF_123,
+        RT5640_IF_132,
+        RT5640_IF_312,
+        RT5640_IF_321,
+        RT5640_IF_231,
+        RT5640_IF_213,
+        RT5640_IF_113,
+        RT5640_IF_223,
+        RT5640_IF_ALL,
+};
+
+enum {
+        RT5640_DMIC_DIS,
+        RT5640_DMIC1,
+        RT5640_DMIC2,
+};
+
+struct rt5640_pll_code {
+        bool m_bp; /* Indicates bypass m code or not. */
+        int m_code;
+        int n_code;
+        int k_code;
+};
+
+struct rt5640_priv {
+        struct snd_soc_codec *codec;
+
+        int aif_pu;
+        int sysclk;
+        int sysclk_src;
+        int lrck[RT5640_AIFS];
+        int bclk[RT5640_AIFS];
+        int master[RT5640_AIFS];
+
+        int pll_src;
+        int pll_in;
+        int pll_out;
+
+        int dmic_en;
+        int dsp_sw;
+};
+
+
+#endif /* __RT5640_H__ */
diff --git a/sound/soc/codecs/second_rate_pps_driver.h b/sound/soc/codecs/second_rate_pps_driver.h
new file mode 100644
index 00000000000..c6c128a027d
--- /dev/null
+++ b/sound/soc/codecs/second_rate_pps_driver.h
@@ -0,0 +1,3626 @@
+//CONTROL LOCATIONS
+
+
+
+static control main44_MUX_controls[] = {
+};
+
+static char *main44_MUX_control_names[] = {
+};
+
+static control main44_VOLUME_controls[] = {
+};
+
+static char *main44_VOLUME_control_names[] = {
+};
+
+
+
+static char *main44_REG_Section_names[] = {
+    "miniDSP_A_reg_values",
+    "miniDSP_D_reg_values",
+};
+
+reg_value main44_REG_Section_init_program[] = {
+    {  0,0x0},
+    {  0x7F,0x00},
+//                      # Set AutoINC
+    {121,0x01},
+    {  0x7F,0x78},
+//                      # reg[120][0][50] = 0x88                     ; Interpolation Ratio is 8, FIFO = Enabled
+    { 50,0x88},
+    {  0x7F,0x64},
+//                      # reg[100][0][50] = 0xa4                     ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled
+    { 50,0x84},
+    {  0x7F,0x78},
+//                      # reg[120][0][24]=0x80
+    { 24,0x80},
+    {255,0x00},
+};
+reg_value main44_REG_Section_post_program[] = {    
+    {  0,0x0},
+    {  0x7F,0x28},
+//                      # reg[40][0][1] = 0x04                        ; adaptive mode for ADC
+    {  1,0x04},
+    {  0x7F,0x50},
+//                      # reg[80][0][1] = 0x04                        ; adaptive mode for DAC
+    {  1,0x04},
+    {  0x7F,0x64},
+//                      # reg[100][0][48] = 4;IDAC  = 256    ; MDAC*DOSR;IADC  = 256    ; MADC*AOSR;IDAC  = 512    ; MDAC*DOSR;IADC  = 512    ; MADC*AOSR;IDAC  = 1024    ; MDAC*DOSR;IADC  = 1024    ; MADC*AOSR;IDAC  = 1536    ; MDAC*DOSR;IADC  = 1536   ; MADC*AOSR;IDAC  = 2048    ; MDAC*DOSR;IADC  = 2048   ; MADC*AOSR;IDAC  = 3072    ; MDAC*DOSR;IADC  = 3072   ; MADC*AOSR;IDAC  = 4096    ; MDAC*DOSR;IADC  = 4096   ; MADC*AOSR;IDAC  = 6144    ; MDAC*DOSR;IADC  = 6144   ; MADC*AOSR
+    { 48,0x04},
+//                      # reg[100][0][49] = 0
+    { 49,0x00},
+    {  0x7F,0x78},
+//                      # reg[120][0][48] = 4
+    { 48,0x04},
+//                      # reg[120][0][49] = 0
+    { 49,0x00},
+    {  0,0x0},
+    {  0x7F,0x64},
+//                      # reg[100][0][20] = 0x80 ; Disable ADC double buffer mode; Disable DAC double buffer mode; Enable ADC double buffer mode
+    { 20,0x80},
+    {  0x7F,0x78},
+//                      # reg[120][0][20] = 0x80 ; Enable DAC double buffer mode
+    { 20,0x80},
+};
+
+reg_value main44_miniDSP_A_reg_values[] = {
+    {  0,0x0},
+    {  0x7F,0x28},
+    {  0,0x01},
+    {  8,0x01},
+    {  9,0xF0},
+    { 10,0x18},
+    { 11,0x00},
+    { 12,0x7C},
+    { 13,0x1F},
+    { 14,0xD0},
+    { 15,0x00},
+    { 16,0x7F},
+    { 17,0xFF},
+    { 18,0xFF},
+    { 19,0x00},
+    { 20,0x00},
+    { 21,0x00},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x00},
+    { 25,0x00},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0x60},
+    { 29,0x00},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0x60},
+    { 33,0x00},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0xFF},
+    { 37,0xFF},
+    { 38,0xFF},
+    { 39,0x00},
+    { 40,0x80},
+    { 41,0x00},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0x7F},
+    { 45,0xFF},
+    { 46,0xFF},
+    { 47,0x00},
+    { 48,0x60},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x60},
+    { 53,0x00},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0x40},
+    { 57,0x00},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x00},
+    { 61,0x00},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0xFF},
+    { 65,0x9E},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x7F},
+    { 73,0xFF},
+    { 74,0xFF},
+    { 75,0x00},
+    { 76,0xF7},
+    { 77,0x10},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x26},
+    { 81,0xF0},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0x02},
+    { 85,0x61},
+    { 86,0x00},
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+    { 70,0x00},
+    { 71,0x9A},
+    { 72,0x18},
+    { 73,0x00},
+    { 74,0x60},
+    { 75,0x4A},
+    { 76,0x1C},
+    { 77,0x00},
+    { 78,0x80},
+    { 79,0x4C},
+    { 80,0x1C},
+    { 81,0x00},
+    { 82,0x40},
+    { 83,0x49},
+    { 84,0x30},
+    { 85,0x00},
+    { 86,0x00},
+    { 87,0x4C},
+    { 88,0x1C},
+    { 89,0x00},
+    { 90,0x20},
+    { 91,0x4E},
+    { 92,0x00},
+    { 93,0x00},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x10},
+    { 97,0x30},
+    { 98,0x00},
+    { 99,0x4B},
+    {100,0x34},
+    {101,0x00},
+    {102,0x00},
+    {103,0x4B},
+    {104,0x18},
+    {105,0x00},
+    {106,0x60},
+    {107,0x9B},
+    {108,0x0C},
+    {109,0x00},
+    {110,0x40},
+    {111,0x00},
+    {112,0x1C},
+    {113,0x00},
+    {114,0x80},
+    {115,0x9D},
+    {116,0x10},
+    {117,0x30},
+    {118,0x00},
+    {119,0x4D},
+    {120,0x1C},
+    {121,0x00},
+    {122,0x40},
+    {123,0x9A},
+    {124,0x30},
+    {125,0x00},
+    {126,0x00},
+    {127,0x9D},
+    {  0,0x09},
+    {  8,0x1C},
+    {  9,0x00},
+    { 10,0x20},
+    { 11,0x9F},
+    { 12,0x00},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x10},
+    { 17,0x30},
+    { 18,0x00},
+    { 19,0x9C},
+    { 20,0x34},
+    { 21,0x00},
+    { 22,0x00},
+    { 23,0x9C},
+    { 24,0x5C},
+    { 25,0x60},
+    { 26,0xC0},
+    { 27,0x9C},
+    { 28,0x0C},
+    { 29,0x00},
+    { 30,0x60},
+    { 31,0x00},
+    { 32,0x5C},
+    { 33,0x60},
+    { 34,0xA0},
+    { 35,0x4B},
+    { 36,0x10},
+    { 37,0x30},
+    { 38,0x00},
+    { 39,0x9E},
+    { 40,0x10},
+    { 41,0x13},
+    { 42,0xE0},
+    { 43,0xA1},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x10},
+    { 49,0x13},
+    { 50,0xE0},
+    { 51,0x50},
+    { 52,0x18},
+    { 53,0x00},
+    { 54,0xA0},
+    { 55,0x50},
+    { 56,0x1C},
+    { 57,0x00},
+    { 58,0xC0},
+    { 59,0xA1},
+    { 60,0x00},
+    { 61,0x00},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0x00},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x10},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0xA2},
+    { 76,0x05},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0xA3},
+    { 80,0x05},
+    { 81,0x00},
+    { 82,0x20},
+    { 83,0xA4},
+    { 84,0x18},
+    { 85,0x01},
+    { 86,0x40},
+    { 87,0xA4},
+    { 88,0x1C},
+    { 89,0x01},
+    { 90,0x60},
+    { 91,0xA2},
+    { 92,0x00},
+    { 93,0x00},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x00},
+    { 97,0x00},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0x00},
+    {101,0x00},
+    {102,0x00},
+    {103,0x00},
+    {104,0x10},
+    {105,0x00},
+    {106,0x00},
+    {107,0xA5},
+    {108,0x18},
+    {109,0x01},
+    {110,0x80},
+    {111,0xA5},
+    {112,0x18},
+    {113,0x01},
+    {114,0x80},
+    {115,0xA5},
+    {116,0x0C},
+    {117,0x00},
+    {118,0x00},
+    {119,0x03},
+    {120,0x0C},
+    {121,0x00},
+    {122,0x20},
+    {123,0x03},
+    {124,0x18},
+    {125,0x01},
+    {126,0xE0},
+    {127,0xA3},
+    {  0,0x0A},
+    {  8,0x1C},
+    {  9,0x02},
+    { 10,0x00},
+    { 11,0xA2},
+    { 12,0x00},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x00},
+    { 17,0x00},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0x00},
+    { 21,0x00},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x10},
+    { 25,0x00},
+    { 26,0x00},
+    { 27,0xA6},
+    { 28,0x18},
+    { 29,0x01},
+    { 30,0x80},
+    { 31,0xA6},
+    { 32,0x18},
+    { 33,0x01},
+    { 34,0x80},
+    { 35,0xA6},
+    { 36,0x0C},
+    { 37,0x02},
+    { 38,0x00},
+    { 39,0x03},
+    { 40,0x0C},
+    { 41,0x02},
+    { 42,0x20},
+    { 43,0x03},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x00},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x00},
+    { 53,0x00},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0x02},
+    { 57,0x00},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x00},
+    { 61,0x00},
+    { 62,0x00},
+    { 63,0x00},
+};
+#define main44_miniDSP_A_reg_values_COEFF_START   0
+#define main44_miniDSP_A_reg_values_COEFF_SIZE    628
+#define main44_miniDSP_A_reg_values_INST_START    628
+#define main44_miniDSP_A_reg_values_INST_SIZE     1148
+
+reg_value main44_miniDSP_D_reg_values[] = {
+    {  0,0x0},
+    {  0x7F,0x50},
+    {  0,0x01},
+    {  8,0xFF},
+    {  9,0xFF},
+    { 10,0xFF},
+    { 11,0x00},
+    { 12,0x80},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x7F},
+    { 17,0xF7},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0x80},
+    { 21,0x09},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x7F},
+    { 25,0xEF},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0x60},
+    { 29,0x00},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0x60},
+    { 33,0x00},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0x40},
+    { 37,0x00},
+    { 38,0x00},
+    { 39,0x00},
+    { 40,0x7F},
+    { 41,0xFF},
+    { 42,0xFF},
+    { 43,0x00},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x60},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x60},
+    { 53,0x00},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0x00},
+    { 57,0x0D},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x00},
+    { 61,0x1C},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0x00},
+    { 65,0x3E},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x40},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x60},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0x00},
+    { 77,0x78},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x02},
+    { 81,0x4C},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0x00},
+    { 85,0xD5},
+    { 86,0x00},
+    { 87,0x00},
+    { 88,0x01},
+    { 89,0x65},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0x03},
+    { 93,0xE9},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x07},
+    { 97,0xCA},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0xFF},
+    {101,0xEF},
+    {102,0x00},
+    {103,0x00},
+    {104,0xFE},
+    {105,0xEB},
+    {106,0x00},
+    {107,0x00},
+    {108,0xFF},
+    {109,0xA8},
+    {110,0x00},
+    {111,0x00},
+    {112,0xFD},
+    {113,0x08},
+    {114,0x00},
+    {115,0x00},
+    {116,0xFF},
+    {117,0x5E},
+    {118,0x00},
+    {119,0x00},
+    {120,0xFF},
+    {121,0xD5},
+    {122,0x00},
+    {123,0x00},
+    {124,0xFE},
+    {125,0x36},
+    {126,0x00},
+    {127,0x00},
+    {  0,0x02},
+    {  8,0xFA},
+    {  9,0xAC},
+    { 10,0x00},
+    { 11,0x00},
+    { 12,0xF2},
+    { 13,0xA3},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x28},
+    { 17,0xAB},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0x3F},
+    { 21,0xFF},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0xFF},
+    { 25,0x98},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0xF6},
+    { 29,0xF9},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0x26},
+    { 33,0xFB},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0x02},
+    { 37,0x72},
+    { 38,0x00},
+    { 39,0x00},
+    { 40,0x40},
+    { 41,0x02},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0xFB},
+    { 45,0xCB},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x20},
+    { 49,0xA7},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0xFF},
+    { 53,0x6A},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0x3A},
+    { 57,0x0F},
+    { 58,0x00},
+    { 59,0x00},
+    {  0,0x09},
+    { 72,0xFF},
+    { 73,0xFF},
+    { 74,0xFF},
+    { 75,0x00},
+    { 76,0x80},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x7F},
+    { 81,0xF7},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0x80},
+    { 85,0x09},
+    { 86,0x00},
+    { 87,0x00},
+    { 88,0x7F},
+    { 89,0xEF},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0x60},
+    { 93,0x00},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x60},
+    { 97,0x00},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0x40},
+    {101,0x00},
+    {102,0x00},
+    {103,0x00},
+    {104,0x7F},
+    {105,0xFF},
+    {106,0xFF},
+    {107,0x00},
+    {108,0x00},
+    {109,0x00},
+    {110,0x00},
+    {111,0x00},
+    {112,0x60},
+    {113,0x00},
+    {114,0x00},
+    {115,0x00},
+    {116,0x60},
+    {117,0x00},
+    {118,0x00},
+    {119,0x00},
+    {120,0x00},
+    {121,0x0D},
+    {122,0x00},
+    {123,0x00},
+    {124,0x00},
+    {125,0x1C},
+    {126,0x00},
+    {127,0x00},
+    {  0,0x0A},
+    {  8,0x00},
+    {  9,0x3E},
+    { 10,0x00},
+    { 11,0x00},
+    { 12,0x40},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x60},
+    { 17,0x00},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0x00},
+    { 21,0x78},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x02},
+    { 25,0x4C},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0x00},
+    { 29,0xD5},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0x01},
+    { 33,0x65},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0x03},
+    { 37,0xE9},
+    { 38,0x00},
+    { 39,0x00},
+    { 40,0x07},
+    { 41,0xCA},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0xFF},
+    { 45,0xEF},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0xFE},
+    { 49,0xEB},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0xFF},
+    { 53,0xA8},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0xFD},
+    { 57,0x08},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0xFF},
+    { 61,0x5E},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0xFF},
+    { 65,0xD5},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0xFE},
+    { 69,0x36},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0xFA},
+    { 73,0xAC},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0xF2},
+    { 77,0xA3},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x28},
+    { 81,0xAB},
+    { 82,0x00},
+    { 83,0x00},
+    { 84,0x3F},
+    { 85,0xFF},
+    { 86,0x00},
+    { 87,0x00},
+    { 88,0xFF},
+    { 89,0x98},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0xF6},
+    { 93,0xF9},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x26},
+    { 97,0xFB},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0x02},
+    {101,0x72},
+    {102,0x00},
+    {103,0x00},
+    {104,0x40},
+    {105,0x02},
+    {106,0x00},
+    {107,0x00},
+    {108,0xFB},
+    {109,0xCB},
+    {110,0x00},
+    {111,0x00},
+    {112,0x20},
+    {113,0xA7},
+    {114,0x00},
+    {115,0x00},
+    {116,0xFF},
+    {117,0x6A},
+    {118,0x00},
+    {119,0x00},
+    {120,0x3A},
+    {121,0x0F},
+    {122,0x00},
+    {123,0x00},
+    {  0,0x0},
+    {  0x7F,0x3C},
+    {  0,0x01},
+    {  8,0xC0},
+    {  9,0x00},
+    { 10,0x00},
+    { 11,0x00},
+    { 12,0xC0},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    {  0,0x0},
+    {  0x7F,0x78},
+    {  0,0x01},
+    {  8,0x04},
+    {  9,0x00},
+    { 10,0x00},
+    { 11,0x03},
+    { 12,0x04},
+    { 13,0x00},
+    { 14,0x20},
+    { 15,0x04},
+    { 16,0x48},
+    { 17,0x02},
+    { 18,0x00},
+    { 19,0x00},
+    { 20,0x48},
+    { 21,0x02},
+    { 22,0x20},
+    { 23,0x00},
+    { 24,0x48},
+    { 25,0x05},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0x01},
+    { 29,0x00},
+    { 30,0x60},
+    { 31,0x10},
+    { 32,0x00},
+    { 33,0x00},
+    { 34,0x00},
+    { 35,0x00},
+    { 36,0x58},
+    { 37,0x60},
+    { 38,0x08},
+    { 39,0x00},
+    { 40,0x60},
+    { 41,0x60},
+    { 42,0x00},
+    { 43,0x00},
+    { 44,0x00},
+    { 45,0x00},
+    { 46,0x00},
+    { 47,0x00},
+    { 48,0x00},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 52,0x44},
+    { 53,0x00},
+    { 54,0xC0},
+    { 55,0x03},
+    { 56,0x00},
+    { 57,0x00},
+    { 58,0x00},
+    { 59,0x00},
+    { 60,0x00},
+    { 61,0x00},
+    { 62,0x00},
+    { 63,0x00},
+    { 64,0x44},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x03},
+    { 68,0x21},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x03},
+    { 73,0x80},
+    { 74,0x00},
+    { 75,0x10},
+    { 76,0x00},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x45},
+    { 81,0x02},
+    { 82,0x80},
+    { 83,0x00},
+    { 84,0x45},
+    { 85,0x02},
+    { 86,0xA0},
+    { 87,0x00},
+    { 88,0x58},
+    { 89,0x60},
+    { 90,0x08},
+    { 91,0x01},
+    { 92,0x60},
+    { 93,0x60},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x58},
+    { 97,0x60},
+    { 98,0x00},
+    { 99,0x09},
+    {100,0x00},
+    {101,0x00},
+    {102,0x00},
+    {103,0x00},
+    {104,0x44},
+    {105,0x00},
+    {106,0xC0},
+    {107,0x16},
+    {108,0x08},
+    {109,0x00},
+    {110,0x00},
+    {111,0x46},
+    {112,0x08},
+    {113,0x00},
+    {114,0x20},
+    {115,0x86},
+    {116,0x08},
+    {117,0x00},
+    {118,0x00},
+    {119,0x45},
+    {120,0x08},
+    {121,0x00},
+    {122,0x20},
+    {123,0x85},
+    {124,0x08},
+    {125,0x00},
+    {126,0x00},
+    {127,0x44},
+    {  0,0x02},
+    {  8,0x08},
+    {  9,0x00},
+    { 10,0x20},
+    { 11,0x84},
+    { 12,0x08},
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+    { 10,0x20},
+    { 11,0x3B},
+    { 12,0x1C},
+    { 13,0x05},
+    { 14,0x40},
+    { 15,0x39},
+    { 16,0x10},
+    { 17,0x00},
+    { 18,0x40},
+    { 19,0x84},
+    { 20,0x18},
+    { 21,0x04},
+    { 22,0xC0},
+    { 23,0x72},
+    { 24,0x5C},
+    { 25,0x90},
+    { 26,0x40},
+    { 27,0x03},
+    { 28,0x18},
+    { 29,0x04},
+    { 30,0xE0},
+    { 31,0x7B},
+    { 32,0x1C},
+    { 33,0x05},
+    { 34,0x00},
+    { 35,0x7C},
+    { 36,0x4C},
+    { 37,0x04},
+    { 38,0xE0},
+    { 39,0x7D},
+    { 40,0x10},
+    { 41,0x00},
+    { 42,0x40},
+    { 43,0x44},
+    { 44,0x1C},
+    { 45,0x05},
+    { 46,0x00},
+    { 47,0x79},
+    { 48,0x18},
+    { 49,0x04},
+    { 50,0xC0},
+    { 51,0x32},
+    { 52,0x5C},
+    { 53,0x90},
+    { 54,0x60},
+    { 55,0x03},
+    { 56,0x18},
+    { 57,0x04},
+    { 58,0xE0},
+    { 59,0x3B},
+    { 60,0x1C},
+    { 61,0x05},
+    { 62,0x00},
+    { 63,0x3C},
+    { 64,0x4C},
+    { 65,0x04},
+    { 66,0xE0},
+    { 67,0x3D},
+    { 68,0x10},
+    { 69,0x00},
+    { 70,0x40},
+    { 71,0x83},
+    { 72,0x1C},
+    { 73,0x05},
+    { 74,0x00},
+    { 75,0x39},
+    { 76,0x00},
+    { 77,0x00},
+    { 78,0x00},
+    { 79,0x00},
+    { 80,0x5C},
+    { 81,0x90},
+    { 82,0x40},
+    { 83,0x03},
+    { 84,0x18},
+    { 85,0x05},
+    { 86,0x20},
+    { 87,0x7D},
+    { 88,0x1C},
+    { 89,0x05},
+    { 90,0x20},
+    { 91,0x79},
+    { 92,0x1C},
+    { 93,0x05},
+    { 94,0x40},
+    { 95,0x7C},
+    { 96,0x10},
+    { 97,0x00},
+    { 98,0x40},
+    { 99,0x43},
+    {100,0x5C},
+    {101,0x90},
+    {102,0x60},
+    {103,0x03},
+    {104,0x00},
+    {105,0x00},
+    {106,0x00},
+    {107,0x00},
+    {108,0x00},
+    {109,0x00},
+    {110,0x00},
+    {111,0x00},
+    {112,0x00},
+    {113,0x00},
+    {114,0x00},
+    {115,0x00},
+    {116,0x10},
+    {117,0x00},
+    {118,0x40},
+    {119,0x82},
+    {120,0x18},
+    {121,0x05},
+    {122,0x20},
+    {123,0x3D},
+    {124,0x1C},
+    {125,0x05},
+    {126,0x20},
+    {127,0x39},
+    {  0,0x09},
+    {  8,0x1C},
+    {  9,0x05},
+    { 10,0x40},
+    { 11,0x3C},
+    { 12,0x18},
+    { 13,0x04},
+    { 14,0x20},
+    { 15,0x5D},
+    { 16,0x5C},
+    { 17,0x90},
+    { 18,0x40},
+    { 19,0x03},
+    { 20,0x18},
+    { 21,0x04},
+    { 22,0x40},
+    { 23,0x78},
+    { 24,0x1C},
+    { 25,0x04},
+    { 26,0x60},
+    { 27,0x71},
+    { 28,0x4C},
+    { 29,0x04},
+    { 30,0x40},
+    { 31,0x70},
+    { 32,0x10},
+    { 33,0x00},
+    { 34,0x40},
+    { 35,0x42},
+    { 36,0x1C},
+    { 37,0x04},
+    { 38,0x60},
+    { 39,0x77},
+    { 40,0x1C},
+    { 41,0x04},
+    { 42,0x80},
+    { 43,0x76},
+    { 44,0x1C},
+    { 45,0x04},
+    { 46,0x80},
+    { 47,0x72},
+    { 48,0x1C},
+    { 49,0x04},
+    { 50,0xA0},
+    { 51,0x75},
+    { 52,0x1C},
+    { 53,0x04},
+    { 54,0xA0},
+    { 55,0x73},
+    { 56,0x18},
+    { 57,0x05},
+    { 58,0x00},
+    { 59,0x7D},
+    { 60,0x1C},
+    { 61,0x05},
+    { 62,0x00},
+    { 63,0x7C},
+    { 64,0x1C},
+    { 65,0x04},
+    { 66,0xE0},
+    { 67,0x79},
+    { 68,0x4C},
+    { 69,0x04},
+    { 70,0xE0},
+    { 71,0x7A},
+    { 72,0x18},
+    { 73,0x04},
+    { 74,0x20},
+    { 75,0x1D},
+    { 76,0x5C},
+    { 77,0x90},
+    { 78,0x60},
+    { 79,0x03},
+    { 80,0x18},
+    { 81,0x04},
+    { 82,0x40},
+    { 83,0x38},
+    { 84,0x1C},
+    { 85,0x04},
+    { 86,0x60},
+    { 87,0x31},
+    { 88,0x4C},
+    { 89,0x04},
+    { 90,0x40},
+    { 91,0x30},
+    { 92,0x10},
+    { 93,0x00},
+    { 94,0x40},
+    { 95,0x81},
+    { 96,0x1C},
+    { 97,0x04},
+    { 98,0x60},
+    { 99,0x37},
+    {100,0x1C},
+    {101,0x04},
+    {102,0x80},
+    {103,0x36},
+    {104,0x1C},
+    {105,0x04},
+    {106,0x80},
+    {107,0x32},
+    {108,0x1C},
+    {109,0x04},
+    {110,0xA0},
+    {111,0x35},
+    {112,0x1C},
+    {113,0x04},
+    {114,0xA0},
+    {115,0x33},
+    {116,0x18},
+    {117,0x05},
+    {118,0x00},
+    {119,0x3D},
+    {120,0x1C},
+    {121,0x05},
+    {122,0x00},
+    {123,0x3C},
+    {124,0x1C},
+    {125,0x04},
+    {126,0xE0},
+    {127,0x39},
+    {  0,0x0A},
+    {  8,0x4C},
+    {  9,0x04},
+    { 10,0xE0},
+    { 11,0x3A},
+    { 12,0x00},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x5C},
+    { 17,0x90},
+    { 18,0x40},
+    { 19,0x03},
+    { 20,0x00},
+    { 21,0x00},
+    { 22,0x00},
+    { 23,0x00},
+    { 24,0x00},
+    { 25,0x00},
+    { 26,0x00},
+    { 27,0x00},
+    { 28,0x00},
+    { 29,0x00},
+    { 30,0x00},
+    { 31,0x00},
+    { 32,0x10},
+    { 33,0x00},
+    { 34,0x40},
+    { 35,0x40},
+    { 36,0x18},
+    { 37,0x05},
+    { 38,0x20},
+    { 39,0x7A},
+    { 40,0x1C},
+    { 41,0x05},
+    { 42,0x20},
+    { 43,0x7C},
+    { 44,0x1C},
+    { 45,0x05},
+    { 46,0x40},
+    { 47,0x7D},
+    { 48,0x10},
+    { 49,0x00},
+    { 50,0x40},
+    { 51,0x41},
+    { 52,0x00},
+    { 53,0x00},
+    { 54,0x00},
+    { 55,0x00},
+    { 56,0x5C},
+    { 57,0x90},
+    { 58,0x60},
+    { 59,0x03},
+    { 60,0x18},
+    { 61,0x05},
+    { 62,0x20},
+    { 63,0x3A},
+    { 64,0x1C},
+    { 65,0x05},
+    { 66,0x20},
+    { 67,0x3C},
+    { 68,0x1C},
+    { 69,0x05},
+    { 70,0x40},
+    { 71,0x3D},
+    { 72,0x10},
+    { 73,0x00},
+    { 74,0x40},
+    { 75,0x80},
+    { 76,0x18},
+    { 77,0x04},
+    { 78,0xC0},
+    { 79,0x76},
+    { 80,0x5C},
+    { 81,0x90},
+    { 82,0x40},
+    { 83,0x03},
+    { 84,0x18},
+    { 85,0x04},
+    { 86,0xE0},
+    { 87,0x7C},
+    { 88,0x1C},
+    { 89,0x05},
+    { 90,0x00},
+    { 91,0x7A},
+    { 92,0x4C},
+    { 93,0x04},
+    { 94,0xE0},
+    { 95,0x78},
+    { 96,0x10},
+    { 97,0x00},
+    { 98,0x40},
+    { 99,0x40},
+    {100,0x1C},
+    {101,0x05},
+    {102,0x00},
+    {103,0x7D},
+    {104,0x18},
+    {105,0x04},
+    {106,0xC0},
+    {107,0x36},
+    {108,0x5C},
+    {109,0x90},
+    {110,0x60},
+    {111,0x03},
+    {112,0x18},
+    {113,0x04},
+    {114,0xE0},
+    {115,0x3C},
+    {116,0x1C},
+    {117,0x05},
+    {118,0x00},
+    {119,0x3A},
+    {120,0x4C},
+    {121,0x04},
+    {122,0xE0},
+    {123,0x38},
+    {124,0x10},
+    {125,0x00},
+    {126,0x40},
+    {127,0x7F},
+    {  0,0x0B},
+    {  8,0x1C},
+    {  9,0x05},
+    { 10,0x00},
+    { 11,0x3D},
+    { 12,0x00},
+    { 13,0x00},
+    { 14,0x00},
+    { 15,0x00},
+    { 16,0x5C},
+    { 17,0x90},
+    { 18,0x40},
+    { 19,0x03},
+    { 20,0x18},
+    { 21,0x05},
+    { 22,0x20},
+    { 23,0x78},
+    { 24,0x1C},
+    { 25,0x05},
+    { 26,0x20},
+    { 27,0x7D},
+    { 28,0x1C},
+    { 29,0x05},
+    { 30,0x40},
+    { 31,0x7A},
+    { 32,0x10},
+    { 33,0x00},
+    { 34,0x40},
+    { 35,0x3F},
+    { 36,0x00},
+    { 37,0x00},
+    { 38,0x00},
+    { 39,0x00},
+    { 40,0x5C},
+    { 41,0x90},
+    { 42,0x60},
+    { 43,0x03},
+    { 44,0x18},
+    { 45,0x05},
+    { 46,0x20},
+    { 47,0x38},
+    { 48,0x1C},
+    { 49,0x05},
+    { 50,0x20},
+    { 51,0x3D},
+    { 52,0x1C},
+    { 53,0x05},
+    { 54,0x40},
+    { 55,0x3A},
+    { 56,0x10},
+    { 57,0x00},
+    { 58,0x40},
+    { 59,0x7E},
+    { 60,0x5C},
+    { 61,0x90},
+    { 62,0x40},
+    { 63,0x03},
+    { 64,0x00},
+    { 65,0x00},
+    { 66,0x00},
+    { 67,0x00},
+    { 68,0x00},
+    { 69,0x00},
+    { 70,0x00},
+    { 71,0x00},
+    { 72,0x00},
+    { 73,0x00},
+    { 74,0x00},
+    { 75,0x00},
+    { 76,0x10},
+    { 77,0x00},
+    { 78,0x40},
+    { 79,0x3E},
+    { 80,0x09},
+    { 81,0x00},
+    { 82,0x00},
+    { 83,0x05},
+    { 84,0x09},
+    { 85,0x00},
+    { 86,0x20},
+    { 87,0x02},
+    { 88,0x00},
+    { 89,0x00},
+    { 90,0x00},
+    { 91,0x00},
+    { 92,0x00},
+    { 93,0x00},
+    { 94,0x00},
+    { 95,0x00},
+    { 96,0x00},
+    { 97,0x00},
+    { 98,0x00},
+    { 99,0x00},
+    {100,0x02},
+    {101,0x00},
+    {102,0x00},
+    {103,0x00},
+    {104,0x00},
+    {105,0x00},
+    {106,0x00},
+    {107,0x00},
+};
+#define main44_miniDSP_D_reg_values_COEFF_START   0
+#define main44_miniDSP_D_reg_values_COEFF_SIZE    361
+#define main44_miniDSP_D_reg_values_INST_START    361
+#define main44_miniDSP_D_reg_values_INST_SIZE     1313
+
+/* Dummy patches*/
+
+reg_value handset_miniDSP_D_reg_values[] = {
+    {  0,0x0},
+    { 0x7F,0x50},
+    {  0,0x06},
+    { 60,0xBE},
+    { 61,0xEF},
+    { 62,0x01},
+    { 63,0x00},
+    {104,0x00},
+    {105,0x80},
+    {106,0x00},
+    {107,0x00},
+    {116,0x04},
+    {117,0x0B},
+    {118,0x78},
+    {119,0x00},
+    {  0,0x0E},
+    {124,0xBE},
+    {125,0xEF},
+    {126,0x01},
+    {127,0x00},
+    {  0,0x0F},
+    { 48,0x00},
+    { 49,0x80},
+    { 50,0x00},
+    { 51,0x00},
+    { 60,0x04},
+    { 61,0x0B},
+    { 62,0x78},
+    { 63,0x00},
+};
+reg_value handphone_miniDSP_D_reg_values[] = {
+        {  0,0x0},
+    {  0x7F,0x50},
+    {  0,0x06},
+    { 60,0xBE},
+    { 61,0xEF},
+    { 62,0x01},
+    { 63,0x00},
+    {104,0x00},
+    {105,0x80},
+    {106,0x00},
+    {107,0x00},
+    {116,0x04},
+    {117,0x0B},
+    {118,0x78},
+    {119,0x00},
+    {  0,0x0E},
+    {124,0xBE},
+    {125,0xEF},
+    {126,0x01},
+    {127,0x00},
+    {  0,0x0F},
+    { 48,0x00},
+    { 49,0x80},
+    { 50,0x00},
+    { 51,0x00},
+    { 60,0x04},
+    { 61,0x0B},
+    { 62,0x78},
+    { 63,0x00},
+};
+reg_value speaker_miniDSP_D_reg_values[] = {
+        {  0,0x0},
+    {  0x7F,0x50},
+    {  0,0x06},
+    { 60,0xBE},
+    { 61,0xEF},
+    { 62,0x01},
+    { 63,0x00},
+    {104,0x78},
+    {105,0x00},
+    {106,0x00},
+    {107,0x00},
+    {116,0x04},
+    {117,0x08},
+    {118,0x31},
+    {119,0x00},
+    {  0,0x0E},
+    {124,0xBE},
+    {125,0xEF},
+    {126,0x01},
+    {127,0x00},
+    {  0,0x0F},
+    { 48,0x78},
+    { 49,0x00},
+    { 50,0x00},
+    { 51,0x00},
+    { 60,0x04},
+    { 61,0x08},
+    { 62,0x31},
+    { 63,0x00},
+};
diff --git a/sound/soc/codecs/tlv320aic326x.c b/sound/soc/codecs/tlv320aic326x.c
new file mode 100644
index 00000000000..8bbd295a332
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x.c
@@ -0,0 +1,4528 @@
+/*
+* linux/sound/soc/codecs/tlv320aic3262.c
+*
+* Copyright (C) 2012 Texas Instruments, Inc.
+*
+* Based on sound/soc/codecs/tlv320aic3262.c
+*
+* This package is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+*
+* The TLV320AIC3262 is a flexible, low-power, low-voltage stereo audio
+* codec with digital microphone inputs and programmable outputs.
+*
+* History:
+*
+* Rev 0.1   ASoC driver support       20-01-2011
+*
+*               The AIC325x ASoC driver is ported for the codec AIC3262.
+* Rev 0.2   ASoC driver support      21-03-2011
+*               The AIC326x ASoC driver is updated abe changes.
+*
+* Rev 0.3   ASoC driver support      12.09.2011
+*               fixed the compilation issues for Whistler support
+*
+* Rev 0.4   ASoC driver support     27.09.2011
+*              The AIC326x driver ported for Nvidia cardhu.
+*
+* Rev 0.5   Modified to support Multiple ASI Ports  08-Nov-2011
+*               Driver updated to support ASI Ports of AIC3262
+*
+* Modified by Nvidia 23-Nov-2011 for K39 ASoC changes.
+*/
+
+/*
+ *****************************************************************************
+ * INCLUDES
+ *****************************************************************************
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <asm/div64.h>
+#include <sound/tlv320aic326x.h>
+#include <sound/jack.h>
+#include <linux/spi/spi.h>
+
+#include "tlv320aic326x.h"
+#include <linux/gpio.h>
+/*
+ *****************************************************************************
+ * Global Variable
+ *****************************************************************************
+ */
+static u8 aic3262_reg_ctl;
+
+#ifdef AIC3262_TiLoad
+        extern int aic3262_driver_init(struct snd_soc_codec *codec);
+#endif
+
+
+
+/* whenever aplay/arecord is run, aic3262_hw_params() function gets called.
+ * This function reprograms the clock dividers etc. this flag can be used to
+ * disable this when the clock dividers are programmed by pps config file
+ */
+static int soc_static_freq_config = 1;
+static struct aic3262_priv *aic3262_priv_data;
+static struct i2c_client *i2c_pdev;
+static struct snd_soc_codec *aic3262_codec;
+
+/*
+ *****************************************************************************
+ * Macros
+ *****************************************************************************
+ */
+
+/* ASoC Widget Control definition for a single Register based Control */
+#define SOC_SINGLE_AIC3262(xname) \
+{\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .info = __new_control_info, .get = __new_control_get,\
+        .put = __new_control_put, \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+}
+#define SOC_SINGLE_N(xname, xreg, xshift, xmax, xinvert) \
+{\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .info = n_control_info, .get = n_control_get,\
+        .put = n_control_put, \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+        .private_value =  ((unsigned long)&(struct soc_mixer_control)) \
+        {.reg = xreg, .shift = xshift, .rshift = xshift, .max = xmax, \
+        .invert = xinvert} }
+
+/* ASoC Widget Control definition for a Double Register based Control */
+
+#define SOC_DOUBLE_R_N(xname, reg_left, reg_right, xshift, xmax, xinvert) \
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+        .info = snd_soc_info_volsw_2r_n, \
+        .get = snd_soc_get_volsw_2r_n, .put = snd_soc_put_volsw_2r_n, \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
+                .max = xmax, .invert = xinvert} }
+
+#define SND_SOC_DAPM_SWITCH_N(wname, wreg, wshift, winvert) \
+{       .id = snd_soc_dapm_switch, .name = wname, .reg = wreg, .shift = wshift,\
+        .invert = winvert, .kcontrols = NULL, .num_kcontrols = 0}
+/*
+ *****************************************************************************
+ * Function Prototype
+ *****************************************************************************
+ */
+static int aic3262_set_bias_level(struct snd_soc_codec *codec,
+                                                enum snd_soc_bias_level level);
+
+static int __new_control_info(struct snd_kcontrol *kcontrol,
+                              struct snd_ctl_elem_info *uinfo);
+
+static int __new_control_get(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol);
+
+static int __new_control_put(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol);
+
+static inline int aic3262_get_divs(int mclk, int rate);
+
+static int aic3262_multi_i2s_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params,
+                                struct snd_soc_dai *dai);
+
+static int aic3262_multi_i2s_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                int clk_id, unsigned int freq, int dir);
+static int aic3262_multi_i2s_set_dai_pll(struct snd_soc_dai *codec_dai,
+                int pll_id, int source, unsigned int freq_in,
+                unsigned int freq_out);
+
+static int aic3262_multi_i2s_asi1_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt);
+
+static int aic3262_multi_i2s_asi2_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt);
+
+static int aic3262_multi_i2s_asi3_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt);
+
+static int aic3262_multi_i2s_asi1_mute(struct snd_soc_dai *dai, int mute);
+
+static int aic3262_multi_i2s_asi2_mute(struct snd_soc_dai *dai, int mute);
+
+static int aic3262_multi_i2s_asi3_mute(struct snd_soc_dai *dai, int mute);
+
+#if 0
+static const char *wclk1_pincontrol[] = {
+        "ASI1 Word Clock Input/Output", "CLKOUT output"};
+static const char *dout1_pincontrol[] = {
+        "disabled", "ASI1 data output", "gpio", "clock out",
+        "INT1", "INT2", "SAR ADC interrupt"};
+
+static const char *din1_pincontrol[] = {"disabled", "enabled"};
+
+static const char *wclk2_pincontrol[] = {
+        "diabled", "ASI1 secondary wclk", "general purpose input",
+        "general purpose output", "clkout", "INT1 interrupt",
+        "IN2 interrupt", "output digital microphone",
+        "SAR ADC interrupt", "data output for ASI1"};
+
+static const char *bclk2_pincontrol[] = {
+        "diabled", "ASI1 secondary wclk", "general purpose input",
+        "general purpose output", "clkout", "INT1 interrupt",
+        "IN2 interrupt", "output digital microphone",
+        "SAR ADC interrupt", "data output for ASI1"};
+
+static const char *dout2_pincontrol[] = {
+        "disabled", "ASI2 Data Output", "General Purpose Output",
+        "INT1 Interrupt", "INT2 Interrupt", "SAR ADC interrupt",
+        "Output for digital microphone", "Data Output for ASI1"};
+
+static const char *din2_pincontrol[] = {"disabled", "enabled"};
+
+static const char *wclk3_pincontrol[] = {
+        "Disabled", "ASI3 WCLK", "General Purpose Input",
+        "General Purpose output", "Data Output for ASI1"};
+
+static const char *bclk3_pincontrol[] = {
+        "Disabled", "ASI3 BCLK", "General Purpose Input",
+        "General Purpose output", "Data Output for ASI1"};
+
+static const char *dout3_pincontrol[] = {
+        "disabled", "ASI3 data ooutput", "General Purpose Output",
+        "ASI1 Word Clock Output", "Data Output for ASI1"};
+
+static const char *din3_pincontrol[] = {"disabled", "enabled"};
+
+static const char *clkin[] = {
+        "mclk1", "bclk1", "gpio1", "pll_clk", "bclk2", "gpi1",
+        "hf_ref_clk", "hf_osc_clk", "mclk2", "gpio2", "gpi2"};
+
+#endif
+#ifdef DAC_INDEPENDENT_VOL
+/*
+ *----------------------------------------------------------------------------
+ * Function : n_control_info
+ * Purpose  : This function is to initialize data for new control required to
+ *            program the AIC3262 registers.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int n_control_info(struct snd_kcontrol *kcontrol,
+                              struct snd_ctl_elem_info *uinfo)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        int max = mc->max;
+        unsigned int shift = mc->shift;
+        unsigned int rshift = mc->rshift;
+
+        if (max == 1)
+                uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+        else
+                uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+
+        uinfo->count = shift == rshift ? 1 : 2;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = max;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : n_control_get
+ * Purpose  : This function is to read data of new control for
+ *            program the AIC3262 registers.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int n_control_get(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        u32 val;
+        unsigned short mask, shift;
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        if (!strcmp(kcontrol->id.name, "Left DAC Volume")) {
+                mask = AIC3262_8BITS_MASK;
+                shift = 0;
+                val = snd_soc_read(codec, mc->reg);
+                ucontrol->value.integer.value[0] =
+                    (val <= 48) ? (val + 127) : (val - 129);
+        }
+        if (!strcmp(kcontrol->id.name, "Right DAC Volume")) {
+                mask = AIC3262_8BITS_MASK;
+                shift = 0;
+                val = snd_soc_read(codec, mc->reg);
+                ucontrol->value.integer.value[0] =
+                    (val <= 48) ? (val + 127) : (val - 129);
+        }
+
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_put
+ * Purpose  : new_control_put is called to pass data from user/application to
+ *            the driver.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int n_control_put(struct snd_kcontrol *kcontrol,
+                             struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        u8 val, val_mask;
+        int reg, err;
+        unsigned int invert = mc->invert;
+        int max = mc->max;
+        DBG("n_control_put\n");
+        reg = mc->reg;
+        val = ucontrol->value.integer.value[0];
+        if (invert)
+                val = max - val;
+        if (!strcmp(kcontrol->id.name, "Left DAC Volume")) {
+                DBG("LDAC\n");
+                val = (val >= 127) ? (val - 127) : (val + 129);
+                val_mask = AIC3262_8BITS_MASK;
+        }
+        if (!strcmp(kcontrol->id.name, "Right DAC Volume")) {
+                DBG("RDAC\n");
+                val = (val >= 127) ? (val - 127) : (val + 129);
+                val_mask = AIC3262_8BITS_MASK;
+        }
+
+        err = snd_soc_update_bits_locked(codec, reg, val_mask, val);
+        if (err < 0) {
+                printk(KERN_ERR "Error while updating bits\n");
+                return err;
+        }
+
+        return 0;
+}
+#endif /*#ifdef DAC_INDEPENDENT_VOL*/
+/*
+ *------------------------------------------------------------------------------
+ * snd_soc_info_volsw_2r_n - double mixer info callback
+ * @kcontrol: mixer control
+ * @uinfo: control element information
+ *
+ * Callback to provide information about a double mixer control that
+ * spans 2 codec registers.
+ *
+ * Returns 0 for success.
+ *------------------------------------------------------------------------------
+ */
+int snd_soc_info_volsw_2r_n(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_info *uinfo)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        int max = mc->max;
+
+        if (max == 1)
+                uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+        else
+                uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+
+        uinfo->count = 2;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = max;
+        return 0;
+}
+
+/*
+ *------------------------------------------------------------------------------
+ * snd_soc_get_volsw_2r_n - double mixer get callback
+ * @kcontrol: mixer control
+ * @ucontrol: control element information
+ *
+ * Callback to get the value of a double mixer control that spans 2 registers.
+ *
+ * Returns 0 for success.
+ *------------------------------------------------------------------------------
+ */
+int snd_soc_get_volsw_2r_n(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int reg = mc->reg;
+        unsigned int reg2 = mc->rreg;
+        unsigned int shift = mc->shift;
+        int max = mc->max;
+        unsigned int mask;
+        unsigned int invert = mc->invert;
+        unsigned short val, val2;
+
+        if (!strcmp(kcontrol->id.name, "PCM Playback Volume")) {
+                mask = AIC3262_8BITS_MASK;
+                shift = 0;
+        } else if (!strcmp(kcontrol->id.name, "HP Driver Gain")) {
+                mask = 0x3F;
+                shift = 0;
+        } else if (!strcmp(kcontrol->id.name, "PGA Capture Volume")) {
+                mask = 0x7F;
+                shift = 0;
+        } else if (!strcmp(kcontrol->id.name, "REC Driver Volume")) {
+                mask = 0x3F;
+                shift = 0;
+        } else if (!strcmp(kcontrol->id.name, "LO to HP Volume")) {
+                mask = 0x7F;
+                shift = 0;
+        } else if (!strcmp(kcontrol->id.name, "MA Volume")) {
+                mask = 0x7F;
+                shift = 0;
+        } else {
+                printk(KERN_ERR "Invalid kcontrol name\n");
+                return -1;
+        }
+
+        /* Read, update the corresponding Registers */
+        val = (snd_soc_read(codec, reg) >> shift) & mask;
+        val2 = (snd_soc_read(codec, reg2) >> shift) & mask;
+
+        if (!strcmp(kcontrol->id.name, "PCM Playback Volume")) {
+                ucontrol->value.integer.value[0] =
+                    (val <= 48) ? (val + 127) : (val - 129);
+                ucontrol->value.integer.value[1] =
+                    (val2 <= 48) ? (val2 + 127) : (val2 - 129);
+        } else if (!strcmp(kcontrol->id.name, "HP Driver Gain")) {
+                ucontrol->value.integer.value[0] =
+                    (val >= 57) ? (val - 57) : (val + 7);
+                ucontrol->value.integer.value[1] =
+                    (val2 >= 57) ? (val2 - 57) : (val2 + 7);
+        } else if (!strcmp(kcontrol->id.name, "PGA Capture Volume")) {
+                ucontrol->value.integer.value[0] =
+                    (val <= 40) ? (val + 24) : (val - 104);
+                ucontrol->value.integer.value[1] =
+                    (val2 <= 40) ? (val2 + 24) : (val2 - 104);
+        } else if (!strcmp(kcontrol->id.name, "REC Driver Volume")) {
+                ucontrol->value.integer.value[0] = ((val >= 0) & (val <= 29)) ?
+                                                 (val + 7) : (val - 57);
+                ucontrol->value.integer.value[1] = ((val2 >= 0) &
+                    (val2 <= 29)) ? (val2 + 7) : (val2 - 57);
+
+        } else if (!strcmp(kcontrol->id.name, "LO to HP Volume")) {
+                ucontrol->value.integer.value[0] = ((val >= 0) & (val <= 116)) ?
+                                 (val + 1) : ((val == 127) ? (0) : (117));
+                ucontrol->value.integer.value[1] = ((val2 >= 0) & (val2 <= 116))
+                                 ? (val2 + 1) : ((val2 == 127) ? (0) : (117));
+
+        } else if (!strcmp(kcontrol->id.name, "MA Volume")) {
+                ucontrol->value.integer.value[0] = (val <= 40) ?
+                                         (41 - val) : (val = 0);
+                ucontrol->value.integer.value[1] = (val2 <= 40) ?
+                                         (41 - val2) : (val2 = 0);
+        }
+
+        if (invert) {
+                ucontrol->value.integer.value[0] =
+                        max - ucontrol->value.integer.value[0];
+                ucontrol->value.integer.value[1] =
+                        max - ucontrol->value.integer.value[1];
+        }
+
+        return 0;
+}
+/*
+*-------------------------------------------------------------------------------
+* snd_soc_put_volsw_2r_n - double mixer set callback
+* @kcontrol: mixer control
+* @ucontrol: control element information
+*
+* Callback to set the value of a double mixer control that spans 2 registers.
+*
+* Returns 0 for success.
+*-------------------------------------------------------------------------------
+*/
+int snd_soc_put_volsw_2r_n(struct snd_kcontrol *kcontrol,
+        struct snd_ctl_elem_value *ucontrol)
+{
+        struct soc_mixer_control *mc =
+                (struct soc_mixer_control *)kcontrol->private_value;
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        unsigned int reg = mc->reg;
+        unsigned int reg2 = mc->rreg;
+        unsigned int shift = mc->shift;
+        int max = mc->max;
+        unsigned int mask;
+        unsigned int invert = mc->invert;
+        int err;
+        unsigned short val, val2, val_mask;
+
+        mask = 0x00FF;
+
+        val = (ucontrol->value.integer.value[0] & mask);
+        val2 = (ucontrol->value.integer.value[1] & mask);
+        if (invert) {
+                val = max - val;
+                val2 = max - val2;
+        }
+
+        /* Check for the string name of the kcontrol */
+        if (!strcmp(kcontrol->id.name, "PCM Playback Volume")) {
+                val = (val >= 127) ? (val - 127) : (val + 129);
+                val2 = (val2 >= 127) ? (val2 - 127) : (val2 + 129);
+                val_mask = AIC3262_8BITS_MASK;  /* 8 bits */
+        } else if ((!strcmp(kcontrol->id.name, "HP Driver Gain")) ||
+                   (!strcmp(kcontrol->id.name, "LO Driver Gain"))) {
+                val = (val <= 6) ? (val + 57) : (val - 7);
+                val2 = (val2 <= 6) ? (val2 + 57) : (val2 - 7);
+                val_mask = 0x3F;        /* 6 bits */
+                DBG("val=%d, val2=%d", val, val2);
+        } else if (!strcmp(kcontrol->id.name, "PGA Capture Volume")) {
+                val = (val >= 24) ? ((val <= 64) ?
+                        (val-24) : (40)) : (val + 104);
+                val2 = (val2 >= 24) ?
+                        ((val2 <= 64) ? (val2 - 24) : (40)) : (val2 + 104);
+                val_mask = 0x7F;        /* 7 bits */
+        } else if (!strcmp(kcontrol->id.name, "LO to REC Volume")) {
+
+                val = (val <= 116) ?
+                         (val % 116) : ((val == 117) ? (127) : (117));
+                val2 = (val2 <= 116) ?
+                        (val2 % 116) : ((val2 == 117) ? (127) : (117));
+                val_mask = 0x7F;
+        } else if (!strcmp(kcontrol->id.name, "REC Driver Volume")) {
+
+                val = (val <= 7) ? (val + 57) : ((val < 36) ? (val - 7) : (29));
+                val2 = (val2 <= 7) ?
+                                (val2 + 57) : ((val2 < 36) ? (val2 - 7) : (29));
+                val_mask = 0x3F;
+        } else if (!strcmp(kcontrol->id.name, "LO to HP Volume")) {
+
+                val = ((val > 0) & (val <= 117)) ?
+                         (val - 1) : ((val == 0) ? (127) : (116));
+                val2 = ((val2 > 0) & (val2 <= 117)) ?
+                         (val2 - 1) : ((val2 == 0) ? (127) : (116));
+                val_mask = 0x7F;
+        } else if (!strcmp(kcontrol->id.name, "MA Volume")) {
+
+                val = ((val <= 41) & (val > 0)) ?
+                         (41 - val) : ((val > 41) ? (val = 41) : (63));
+                val2 = ((val2 <= 41) & (val2 > 0)) ?
+                         (41 - val2) : ((val2 > 41) ? (val2 = 41) : (63));
+                val_mask = 0x7F;
+        } else {
+                printk(KERN_ERR "Invalid control name\n");
+                return -1;
+        }
+
+        val = val << shift;
+        val2 = val2 << shift;
+
+        err = snd_soc_update_bits_locked(codec, reg, val_mask, val);
+        if (err < 0)
+                return err;
+
+        err = snd_soc_update_bits_locked(codec, reg2, val_mask, val2);
+        return err;
+}
+
+static int __new_control_info(struct snd_kcontrol *kcontrol,
+                              struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+        uinfo->count = 1;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 65535;
+
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_get
+ * Purpose  : This function is to read data of new control for
+ *            program the AIC3262 registers.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int __new_control_get(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        u32 val;
+        val = snd_soc_read(codec, aic3262_reg_ctl);
+        ucontrol->value.integer.value[0] = val;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_put
+ * Purpose  : new_control_put is called to pass data from user/application to
+ *            the driver.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int __new_control_put(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 data[2];
+        int ret = 0;
+
+        u32 data_from_user = ucontrol->value.integer.value[0];
+
+        aic3262_change_book(codec, 0);
+        aic3262_reg_ctl = data[0] = (u8) ((data_from_user & 0xFF00) >> 8);
+        data[1] = (u8) ((data_from_user & 0x00FF));
+
+        if (!data[0])
+                aic3262->page_no = data[1];
+
+        DBG("reg = %d val = %x\n", data[0], data[1]);
+#if defined(LOCAL_REG_ACCESS)
+        if (codec->hw_write(codec->control_data, data, 2) != 2)
+                ret = -EIO;
+#else
+        ret = snd_soc_write(codec, data[0], data[1]);
+#endif
+        if (ret)
+                printk(KERN_ERR "Error in i2c write\n");
+
+        return ret;
+}
+
+
+/*
+ *****************************************************************************
+ * Structure Initialization
+ *****************************************************************************
+ */
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
+static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1200, 50, 0);
+static const DECLARE_TLV_DB_SCALE(spk_gain_tlv, 600, 600, 0);
+static const DECLARE_TLV_DB_SCALE(output_gain_tlv, -600, 100, 0);
+static const DECLARE_TLV_DB_SCALE(micpga_gain_tlv, 0, 50, 0);
+static const DECLARE_TLV_DB_SCALE(adc_fine_gain_tlv, -40, 10, 0);
+static const DECLARE_TLV_DB_SCALE(beep_gen_volume_tlv, -6300, 100, 0);
+
+/* Chip-level Input and Output CM Mode Controls */
+static const char *input_common_mode_text[] = {
+        "0.9v", "0.75v" };
+
+static const char *output_common_mode_text[] = {
+        "Input CM", "1.25v", "1.5v", "1.65v" };
+
+static const struct soc_enum input_cm_mode =
+        SOC_ENUM_SINGLE(CM_REG, 2, 2, input_common_mode_text);
+
+static const struct soc_enum output_cm_mode =
+        SOC_ENUM_SINGLE(CM_REG, 0, 4, output_common_mode_text);
+
+/*
+ *****************************************************************************
+ * Structure Initialization
+ *****************************************************************************
+ */
+static const struct snd_kcontrol_new aic3262_snd_controls[] = {
+        /* Output */
+#ifndef DAC_INDEPENDENT_VOL
+        /* sound new kcontrol for PCM Playback volume control */
+
+        SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
+                        DAC_LVOL, DAC_RVOL, 8,0xffffff81, 0x30, dac_vol_tlv),
+#endif
+        /*HP Driver Gain Control*/
+        SOC_DOUBLE_R_SX_TLV("HeadPhone Driver Amplifier Volume",
+                        HPL_VOL, HPR_VOL, 6, 0xfffffffa, 0xe, output_gain_tlv),
+
+        /*LO Driver Gain Control*/
+        SOC_DOUBLE_TLV("Speaker Amplifier Volume",
+                                SPK_AMP_CNTL_R4, 4, 0, 5, 0, spk_gain_tlv),
+
+        SOC_DOUBLE_R_SX_TLV("Receiver Amplifier Volume",
+        REC_AMP_CNTL_R5, RAMPR_VOL, 6, 0xfffffffa, 0x1d, output_gain_tlv),
+
+        SOC_DOUBLE_R_SX_TLV("PCM Capture Volume",
+                LADC_VOL, RADC_VOL, 7,0xffffff68, 0x24, adc_vol_tlv),
+
+
+        SOC_DOUBLE_R_TLV ("MicPGA Volume Control",
+                MICL_PGA, MICR_PGA, 0, 0x5F, 0, micpga_gain_tlv),
+        SOC_DOUBLE_TLV("PCM Capture Fine Gain Volume",
+                ADC_FINE_GAIN, 4, 0, 5, 1, adc_fine_gain_tlv),
+
+        SOC_DOUBLE("ADC channel mute", ADC_FINE_GAIN, 7, 3, 1, 0),
+
+        SOC_DOUBLE("DAC MUTE", DAC_MVOL_CONF, 2, 3, 1, 1),
+
+        /* sound new kcontrol for Programming the registers from user space */
+        SOC_SINGLE_AIC3262("Program Registers"),
+
+        SOC_SINGLE("RESET", RESET_REG, 0,1,0),
+
+        SOC_SINGLE("DAC VOL SOFT STEPPING", DAC_MVOL_CONF, 0, 2, 0),
+
+#ifdef DAC_INDEPENDENT_VOL
+        /*SOC_SINGLE_N("Left DAC Volume", DAC_LVOL, 0, 0xAF, 0),
+        SOC_SINGLE_N("Right DAC Volume", DAC_RVOL, 0, 0xAF, 0),*/
+#endif
+
+        SOC_SINGLE("DAC AUTO MUTE CONTROL", DAC_MVOL_CONF, 4, 7, 0),
+        SOC_SINGLE("RIGHT MODULATOR SETUP", DAC_MVOL_CONF, 7, 1, 0),
+
+        SOC_SINGLE("ADC Volume soft stepping", ADC_CHANNEL_POW, 0, 3, 0),
+
+        SOC_DOUBLE_R("MICPGA enable/disable",MICL_PGA,MICR_PGA,7, 1, 0),
+
+        SOC_SINGLE("Mic Bias ext independent enable", MIC_BIAS_CNTL, 7, 1, 0),
+        SOC_SINGLE("MICBIAS_EXT ON", MIC_BIAS_CNTL, 6, 1, 0),
+        SOC_SINGLE("MICBIAS EXT Power Level", MIC_BIAS_CNTL, 4, 3, 0),
+
+        SOC_SINGLE("MICBIAS_INT ON", MIC_BIAS_CNTL, 2, 1, 0),
+        SOC_SINGLE("MICBIAS INT Power Level", MIC_BIAS_CNTL, 0, 3, 0),
+
+        SOC_DOUBLE("DRC_EN_CTL", DRC_CNTL_R1, 6, 5, 1, 0),
+        SOC_SINGLE("DRC_THRESHOLD_LEVEL", DRC_CNTL_R1, 2, 7, 1),
+        SOC_SINGLE("DRC_HYSTERISIS_LEVEL", DRC_CNTL_R1, 0, 7, 0),
+
+        SOC_SINGLE("DRC_HOLD_LEVEL", DRC_CNTL_R2, 3, 0x0F, 0),
+        SOC_SINGLE("DRC_GAIN_RATE", DRC_CNTL_R2, 0, 4, 0),
+        SOC_SINGLE("DRC_ATTACK_RATE", DRC_CNTL_R3, 4, 0x0F, 1),
+        SOC_SINGLE("DRC_DECAY_RATE", DRC_CNTL_R3, 0, 0x0F, 1),
+
+        SOC_SINGLE("BEEP_GEN_EN", BEEP_CNTL_R1, 7, 1, 0),
+        SOC_DOUBLE_R("BEEP_VOL_CNTL", BEEP_CNTL_R1, BEEP_CNTL_R2, 0, 0x0F, 1),
+        SOC_SINGLE("BEEP_MAS_VOL", BEEP_CNTL_R2, 6, 3, 0),
+
+        SOC_DOUBLE_R("AGC_EN", LAGC_CNTL, RAGC_CNTL, 7, 1, 0),
+        SOC_DOUBLE_R("AGC_TARGET_LEVEL", LAGC_CNTL, RAGC_CNTL, 4, 7, 1),
+
+        SOC_DOUBLE_R("AGC_GAIN_HYSTERESIS", LAGC_CNTL, RAGC_CNTL, 0, 3, 0),
+        SOC_DOUBLE_R("AGC_HYSTERESIS", LAGC_CNTL_R2, RAGC_CNTL_R2, 6, 3, 0),
+        SOC_DOUBLE_R("AGC_NOISE_THRESHOLD", LAGC_CNTL_R2,
+                                                RAGC_CNTL_R2, 1, 31, 1),
+
+        SOC_DOUBLE_R("AGC_MAX_GAIN", LAGC_CNTL_R3, RAGC_CNTL_R3, 0, 116, 0),
+        SOC_DOUBLE_R("AGC_ATCK_TIME", LAGC_CNTL_R4, RAGC_CNTL_R4, 3, 31, 0),
+        SOC_DOUBLE_R("AGC_ATCK_SCALE_FACTOR",
+                                LAGC_CNTL_R4, RAGC_CNTL_R4, 0, 7, 0),
+
+        SOC_DOUBLE_R("AGC_DECAY_TIME", LAGC_CNTL_R5, RAGC_CNTL_R5, 3, 31, 0),
+        SOC_DOUBLE_R("AGC_DECAY_SCALE_FACTOR",
+                                LAGC_CNTL_R5, RAGC_CNTL_R5, 0, 7, 0),
+        SOC_DOUBLE_R("AGC_NOISE_DEB_TIME", LAGC_CNTL_R6,
+                                                RAGC_CNTL_R6, 0, 31, 0),
+
+        SOC_DOUBLE_R("AGC_SGL_DEB_TIME", LAGC_CNTL_R7,
+                                        RAGC_CNTL_R7, 0, 0x0F, 0),
+
+        SOC_SINGLE("DAC PRB Selection",DAC_PRB, 0, 25, 0),
+        SOC_SINGLE("HP_DEPOP", HP_DEPOP, 0, 255,0),
+        SOC_DOUBLE("IN1 LO BYPASS VOLUME" , LINE_AMP_CNTL_R2, 3, 0, 3, 1),
+        SOC_ENUM("Input CM mode", input_cm_mode),
+        SOC_ENUM("Output CM mode", output_cm_mode),
+};
+
+
+/* the sturcture contains the different values for mclk */
+static const struct aic3262_rate_divs aic3262_divs[] = {
+/*
+ * mclk, rate, p_val, pll_j, pll_d, dosr, ndac, mdac, aosr, nadc, madc, blck_N,
+ * codec_speficic_initializations
+ */
+        /* 8k rate */
+#ifdef CONFIG_MINI_DSP
+        {12000000, 8000, 1, 8, 1920, 768, 8, 2, 128, 8, 12, 4,
+                {{0, 60, 0}, {0, 61, 0} } },
+#else
+        {12000000, 8000, 1, 8, 1920, 128, 12, 8, 128, 8, 6, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {12288000, 8000, 1, 1, 3333, 128, 12, 8, 128, 8, 6, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {24000000, 8000, 1, 4, 96, 128, 12, 8, 128, 12, 8, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+#endif
+        /* 11.025k rate */
+        {12000000, 11025, 1, 1, 8816, 1024, 8, 2, 128, 8, 2, 48,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {12288000, 11025, 1, 1, 8375, 1024, 8, 2, 128, 8, 2, 48,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {24000000, 11025, 1, 3, 7632, 128, 8, 8, 128, 8, 8, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+
+        /* 16k rate */
+#ifdef CONFIG_MINI_DSP
+        {12000000, 16000, 1, 8, 1920, 384, 4, 4, 128, 4, 12, 12,
+                {{0, 60, 0}, {0, 61, 0} } },
+        {12288000, 16000, 1, 9, 0, 216, 2, 16, 72, 2, 48, 27,
+                {{0, 60, 0}, {0, 61, 0} } },
+#else
+        {12000000, 16000, 1, 8, 1920, 128, 8, 6, 128, 8, 6, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {12288000, 16000, 1, 2, 6667, 128, 8, 6, 128, 8, 6, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {24000000, 16000, 1, 4, 96, 128, 8, 6, 128, 8, 6, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+#endif
+        /* 22.05k rate */
+        {12000000, 22050, 1, 3, 7632, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {12288000, 22050, 1, 3, 675, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {24000000, 22050, 1, 3, 7632, 128, 8, 3, 128, 8, 3, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        /* 32k rate */
+        {12000000, 32000, 1, 5, 4613, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {12288000, 32000, 1, 5, 3333, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {24000000, 32000, 1, 4, 96, 128, 6, 4, 128, 6, 4, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+
+#ifdef CONFIG_MINI_DSP
+        {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4,
+                {{0, 60, 0}, {0, 61, 0} } },
+        {12288000, 44100, 1, 7, 3548, 128, 2, 8, 128, 8, 2, 4,
+                {{0, 60, 0}, {0, 61, 0} } },
+#else
+        /* 44.1k rate */
+        {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {12288000, 44100, 1, 7, 3548, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {24000000, 44100, 1, 3, 7632, 128, 4, 4, 64, 4, 4, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+#endif
+
+#ifdef CONFIG_MINI_DSP
+        {12288000, 48000, 1, 8, 52, 128, 2, 8, 128, 2, 8, 4,
+                {{0, 60, 0}, {0, 61, 0} } },
+        {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4,
+         {{0, 60, 0}, {0, 61, 0}}},
+#else
+        /* 48k rate */
+        {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {12288000, 48000, 1, 8, 52, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+        {24000000, 48000, 1, 4, 960, 128, 4, 4, 128, 4, 4, 4,
+                {{0, 60, 1}, {0, 61, 1} } },
+#endif
+
+        /*96k rate */
+        {12000000, 96000, 1, 16, 3840, 128, 8, 2, 128, 8, 2 , 4,
+                {{0, 60, 7}, {0, 61, 7} } },
+        {24000000, 96000, 1, 4, 960, 128, 4, 2, 128, 4, 2, 2,
+                {{0, 60, 7}, {0, 61, 7} } },
+        /*192k */
+        {12000000, 192000, 1, 32, 7680, 128, 8, 2, 128, 8, 2, 4,
+                {{0, 60, 17}, {0, 61, 13} } },
+        {24000000, 192000, 1, 4, 960, 128, 2, 2, 128, 2, 2, 4,
+                {{0, 60, 17}, {0, 61, 13} } },
+};
+
+
+
+/*
+*----------------------------------------------------------------------------
+* Function : aic3262_multi_i2s_dump_regs
+* Purpose  : This function is to mute or unmute the left and right DAC
+*
+*----------------------------------------------------------------------------
+*/
+static void aic3262_multi_i2s_dump_regs(struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        unsigned int counter;
+
+        DBG(KERN_INFO "#%s: Dai Active %d ASI%d REGS DUMP\n",
+                __func__, aic3262->active_count, dai->id);
+
+        aic3262_change_page(codec, 0);
+        aic3262_change_book(codec, 0);
+
+        DBG(KERN_INFO "#Page0 REGS..\n");
+        for (counter = 0; counter < 85; counter++) {
+                DBG(KERN_INFO "#%2d -> 0x%x\n", counter,
+                        snd_soc_read(codec, counter));
+        }
+
+        DBG(KERN_INFO "#Page1 REGS..\n");
+        for (counter = 128; counter < 176; counter++) {
+                DBG(KERN_INFO "#%2d -> 0x%x\n", (counter % 128),
+                        snd_soc_read(codec, counter));
+        }
+
+        DBG(KERN_INFO "#Page4 REGS..\n");
+        for (counter = 512; counter < 631; counter++) {
+                DBG(KERN_INFO "#%2d -> 0x%x\n",
+                        (counter % 128), snd_soc_read(codec, counter));
+        }
+
+        for (counter = 0; counter < MAX_ASI_COUNT; counter++) {
+                DBG(KERN_INFO "#ASI%d Frame %s @ %dHz Playback %d Record %d\n",
+                (counter + 1),
+                (aic3262->asiCtxt[counter].master == 1) ? "Master" : "Slave",
+                aic3262->asiCtxt[counter].sampling_rate,
+                aic3262->asiCtxt[counter].playback_mode,
+                aic3262->asiCtxt[counter].capture_mode);
+                DBG(KERN_INFO "#DAC Option [%d,%d] ADC Option %d WLEN %d\n\n",
+                aic3262->asiCtxt[counter].left_dac_output,
+                aic3262->asiCtxt[counter].right_dac_output,
+                aic3262->asiCtxt[counter].adc_input,
+                aic3262->asiCtxt[counter].word_len);
+        }
+        return;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_multi_i2s_mute
+ * Purpose  : This function is to mute or unmute the left and right DAC
+ *
+ *----------------------------------------------------------------------------
+ */
+static int aic3262_multi_i2s_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "#%s : mute entered with %d\n", __func__, mute);
+
+        /* If we are doing both Recording and Playback on this DAI interface,
+        * do not MUTE the Codec.
+        */
+        if (mute && (aic3262->asiCtxt[dai->id - 1].asi_active > 1)) {
+                DBG("#%s Cannot Mute the ASI%d Now..\n",
+                        __func__, dai->id);
+        } else {
+                switch (dai->id) {
+                case 1:
+                        aic3262_multi_i2s_asi1_mute(dai, mute);
+                break;
+                case 2:
+                        aic3262_multi_i2s_asi2_mute(dai, mute);
+                break;
+                case 3:
+                        aic3262_multi_i2s_asi3_mute(dai, mute);
+                break;
+                default:
+                        printk(KERN_ERR "#%s: Invalid DAI id\n", __func__);
+                        return -EINVAL;
+                }
+        }
+        DBG(KERN_INFO "#%s : mute ended\n", __func__);
+        return 0;
+}
+
+
+/*
+*----------------------------------------------------------------------------
+* Function : aic3262_multi_i2s_asi1_mute
+* Purpose  : This function is to mute or unmute the left and right DAC
+*
+*----------------------------------------------------------------------------
+*/
+static int aic3262_multi_i2s_asi1_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "#%s : mute %d started\n", __func__, mute);
+
+        if (mute && !aic3262->asiCtxt[0].port_muted ) {
+                DBG(KERN_INFO "Mute if part\n");
+
+
+        snd_soc_update_bits(codec, DAC_MVOL_CONF, DAC_LR_MUTE_MASK,DAC_LR_MUTE);
+
+                /* First check if both Playback and Recording is going on
+                * this interface.
+                */
+                if (aic3262->asiCtxt[0].asi_active > 1) {
+                        DBG("#%s Cannot Mute the ASI Now..\n", __func__);
+                } else if (!(aic3262->asiCtxt[1].playback_mode) &&
+                        !(aic3262->asiCtxt[2].playback_mode)) {
+                        /* Before Muting, please check if any other
+                        * ASI is active. if so, we cannot simply mute the
+                        * DAC and ADC Registers.
+                        */
+                DBG("#%s None of the ASI's are active now..\n", __func__);
+                        snd_soc_write(codec, DAC_MVOL_CONF,
+                                ((aic3262->dac_reg & 0xF3) | 0x0C));
+                        snd_soc_write(codec, ADC_FINE_GAIN,
+                                ((aic3262->adc_gain & 0x77) | 0x88));
+                        snd_soc_write(codec, HPL_VOL, 0xB9);
+                        snd_soc_write(codec, HPR_VOL, 0xB9);
+                        snd_soc_write(codec, REC_AMP_CNTL_R5, 0x39);
+                        snd_soc_write(codec, RAMPR_VOL, 0x39);
+                        snd_soc_write(codec, SPK_AMP_CNTL_R4, 0x00);
+                        aic3262->asiCtxt[0].port_muted = 1;
+                }
+        } else {
+                DBG(KERN_INFO "Mute else part\n");
+                snd_soc_update_bits(codec, DAC_MVOL_CONF,
+                                                DAC_LR_MUTE_MASK, 0x0);
+                snd_soc_write(codec, ADC_FINE_GAIN,(0X00 & 0x77) | 0x0);
+                aic3262_multi_i2s_dump_regs(dai);
+        }
+
+        DBG(KERN_INFO "#%s : mute %d ended\n", __func__, mute);
+
+        return 0;
+}
+
+/*
+*----------------------------------------------------------------------------
+* Function : aic3262_multi_i2s_asi2_maic3262_asi3_clk_configute
+* Purpose : This function is to mute or unmute the left and right DAC
+*
+*----------------------------------------------------------------------------
+*/
+static int aic3262_multi_i2s_asi2_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "#%s : mute %d started\n", __func__, mute);
+
+        if (mute && !aic3262->asiCtxt[1].port_muted ) {
+                DBG(KERN_INFO "Mute if part\n");
+        snd_soc_update_bits(codec, DAC_MVOL_CONF, DAC_LR_MUTE_MASK,DAC_LR_MUTE);
+
+                /* First check if both Playback and Recording is going on
+                * this interface.
+                */
+                if (aic3262->asiCtxt[1].asi_active > 1) {
+                        DBG("#%s Cannot Mute the ASI Now..\n", __func__);
+                } else if (!(aic3262->asiCtxt[0].playback_mode) &&
+                        !(aic3262->asiCtxt[2].playback_mode)) {
+                        /* Before Muting, please check if any other
+                        * ASI is active. if so, we cannot simply mute the
+                        * DAC and ADC Registers.
+                        */
+                        snd_soc_write(codec, DAC_MVOL_CONF,
+                                ((aic3262->dac_reg & 0xF3) | 0x0C));
+                        snd_soc_write(codec, ADC_FINE_GAIN,
+                                ((aic3262->adc_gain & 0x77) | 0x88));
+                        snd_soc_write(codec, HPL_VOL, 0xB9);
+                        snd_soc_write(codec, HPR_VOL, 0xB9);
+                        snd_soc_write(codec, REC_AMP_CNTL_R5, 0x39);
+                        snd_soc_write(codec, RAMPR_VOL, 0x39);
+                        snd_soc_write(codec, SPK_AMP_CNTL_R4, 0x00);
+                        aic3262->asiCtxt[1].port_muted = 1;
+                }
+        } else {
+                DBG(KERN_INFO "Mute else part\n");
+                snd_soc_update_bits(codec, DAC_MVOL_CONF,
+                                                DAC_LR_MUTE_MASK, 0x0);
+
+                /*aic3262_multi_i2s_dump_regs(dai);*/
+        }
+
+        DBG(KERN_INFO "#%s : mute %d ended\n", __func__, mute);
+
+        return 0;
+}
+
+/*
+*----------------------------------------------------------------------------
+* Function : aic3262_multi_i2s_asi3_mute
+* Purpose : This function is to mute or unmute the left and right DAC
+*
+*----------------------------------------------------------------------------
+*/
+static int aic3262_multi_i2s_asi3_mute(struct snd_soc_dai *dai, int mute)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "#%s : mute %d started\n", __func__, mute);
+
+        if (mute && !aic3262->asiCtxt[2].port_muted) {
+                DBG("Mute if part\n");
+        snd_soc_update_bits(codec, DAC_MVOL_CONF, DAC_LR_MUTE_MASK,DAC_LR_MUTE);
+
+                /* First check if both Playback and Recording is going on
+                * this interface.
+                */
+                if (aic3262->asiCtxt[2].asi_active > 1) {
+                        DBG("#%s Cannot Mute the ASI Now..\n", __func__);
+                } else if (!(aic3262->asiCtxt[0].playback_mode) &&
+                        !(aic3262->asiCtxt[1].playback_mode)) {
+                        /* Before Muting, please check if any other
+                        * ASI is active. if so, we cannot simply mute the
+                        * DAC and ADC Registers.
+                        */
+                        snd_soc_write(codec, DAC_MVOL_CONF,
+                                ((aic3262->dac_reg & 0xF3) | 0x0C));
+                        snd_soc_write(codec, ADC_FINE_GAIN,
+                                ((aic3262->adc_gain & 0x77) | 0x88));
+                        snd_soc_write(codec, HPL_VOL, 0xB9);
+                        snd_soc_write(codec, HPR_VOL, 0xB9);
+                        snd_soc_write(codec, REC_AMP_CNTL_R5, 0x39);
+                        snd_soc_write(codec, RAMPR_VOL, 0x39);
+                        snd_soc_write(codec, SPK_AMP_CNTL_R4, 0x00);
+                        aic3262->asiCtxt[2].port_muted = 1;
+                }
+        } else {
+                DBG("Mute else part\n");
+                snd_soc_update_bits(codec, DAC_MVOL_CONF,
+                                                DAC_LR_MUTE_MASK, 0x0);
+
+                /*aic3262_multi_i2s_dump_regs(dai);*/
+
+        }
+
+        DBG(KERN_INFO "#%s : mute %d ended\n", __func__, mute);
+
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_multi_i2s_set_dai_fmt
+ * Purpose  : This function is to set the DAI format
+ *
+ *----------------------------------------------------------------------------
+ */
+static int aic3262_multi_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt)
+{
+        /* Check the DAI Id and based on that switch the configuration for
+        * the Individual ASI Port.
+        */
+        switch (codec_dai->id) {
+        case 1:
+                aic3262_multi_i2s_asi1_set_dai_fmt(codec_dai, fmt);
+        break;
+        case 2:
+                aic3262_multi_i2s_asi2_set_dai_fmt(codec_dai, fmt);
+        break;
+        case 3:
+                aic3262_multi_i2s_asi3_set_dai_fmt(codec_dai, fmt);
+        break;
+        default:
+                printk(KERN_ERR
+                        "#%s: Invalid DAI interface format\n", __func__);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+
+
+/*
+*----------------------------------------------------------------------------
+* Function : aic3262_multi_i2s_asi1_set_dai_fmt
+* Purpose  : This function is to set the DAI format for ASI1 Port
+*
+*----------------------------------------------------------------------------
+*/
+static int aic3262_multi_i2s_asi1_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 iface_reg, clk_reg;
+        u8 regvalue;
+
+        DBG(KERN_INFO "%s: DAI_ID %d fmt %d\n",
+                __func__, codec_dai->id, fmt);
+
+        /* Read the B0_P4_R4 and B0_P4_R10 Registers to configure the
+        * ASI1 Bus and Clock Formats depending on the PCM Format.
+        */
+        iface_reg = snd_soc_read(codec, ASI1_BUS_FMT);
+        clk_reg   = snd_soc_read(codec, ASI1_BWCLK_CNTL_REG);
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Master..\n",
+                        __func__, codec_dai->id);
+                aic3262->asiCtxt[0].master = 1;
+                clk_reg |= (BIT5 | BIT2);       /* Codec Interface as Master */
+        break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Slave..\n",
+                        __func__, codec_dai->id);
+                clk_reg &= ~0xFC; /* Reset bits D[7:5] and D[4:2] to zero */
+                aic3262->asiCtxt[0].master = 0;
+        break;
+        case SND_SOC_DAIFMT_CBS_CFM:
+                /* new case..just for debugging */
+                DBG(KERN_INFO "%s: SND_SOC_DAIFMT_CBS_CFM\n", __func__);
+                aic3262->asiCtxt[0].master = 0;
+                clk_reg |= BIT5;        /* Only WCLK1 Output from Codec */
+                clk_reg &= ~0x1C;       /* BCLK1 Input to Codec */
+        break;
+        default:
+                printk(KERN_ERR "#%s: Invalid DAI master/slave interface\n",
+                        __func__);
+                return -EINVAL;
+        }
+        aic3262->asiCtxt[0].pcm_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for I2s Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f);
+        break;
+        case SND_SOC_DAIFMT_DSP_A:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_A Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f) | 0x20;
+        break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                iface_reg = (iface_reg & 0x1f) | 0x40;
+        break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                iface_reg = (iface_reg & 0x1f) | 0x60;
+        break;
+        case SND_SOC_DAIFMT_DSP_B:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_B Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f) | 0x80;
+                /* voice call need data offset in 1 bitclock */
+                snd_soc_write(codec, ASI1_LCH_OFFSET, 1);
+        break;
+        default:
+                printk(KERN_ERR
+                        "#%s: Invalid DAI interface format\n", __func__);
+                return -EINVAL;
+        }
+        /* Also Configure the Pin Control Registers before writing into
+        * the ASI specific Clock Control and Format Registers
+        */
+
+        /* Configure B0_P4_R65_D[5:2] to 001 This configures the
+        * WCLK1 Pin to ASI1
+        */
+        regvalue = snd_soc_read(codec, WCLK1_PIN_CNTL_REG);
+        snd_soc_write(codec, WCLK1_PIN_CNTL_REG, (regvalue | BIT2));
+
+        /* Configure B0_P4_R68_d[6:5] = 01 and B0_P4_R67_D[4:1] to 0001
+        * to ensure that the DIN1 and DOUT1 Pins are configured
+        * correctly
+        */
+        regvalue = snd_soc_read(codec, DIN1_PIN_CNTL_REG);
+        snd_soc_write(codec, DIN1_PIN_CNTL_REG, (regvalue | BIT5));
+        regvalue = snd_soc_read(codec, DOUT1_PIN_CNTL_REG);
+        snd_soc_write(codec, DOUT1_PIN_CNTL_REG, (regvalue | BIT1));
+
+        snd_soc_write(codec, ASI1_BWCLK_CNTL_REG, clk_reg);
+
+        snd_soc_write(codec, ASI1_BUS_FMT, iface_reg);
+
+        return 0;
+}
+
+
+/*
+*----------------------------------------------------------------------------
+* Function : aic3262_multi_i2s_asi2_set_dai_fmt
+* Purpose  : This function is to set the DAI format for ASI2 Port
+*
+*----------------------------------------------------------------------------
+*/
+static int aic3262_multi_i2s_asi2_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                        unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 iface_reg, clk_reg;
+        u8 regvalue;
+
+        DBG(KERN_INFO "%s: DAI_ID %d fmt %d\n",
+                __func__, codec_dai->id, fmt);
+
+        /* Read the B0_P4_R17 and B0_P4_R26 Registers to configure the
+        * ASI1 Bus and Clock Formats depending on the PCM Format.
+        */
+        iface_reg = snd_soc_read(codec, ASI2_BUS_FMT);
+        clk_reg   = snd_soc_read(codec, ASI2_BWCLK_CNTL_REG);
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Master..\n",
+                        __func__, codec_dai->id);
+                aic3262->asiCtxt[1].master = 1;
+                clk_reg |= (BIT5 | BIT2);
+        break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Slave..\n",
+                        __func__, codec_dai->id);
+
+                clk_reg &= ~0xFC;
+                aic3262->asiCtxt[1].master = 0;
+        break;
+        case SND_SOC_DAIFMT_CBS_CFM:
+                /*new case..just for debugging */
+                DBG(KERN_INFO "%s: SND_SOC_DAIFMT_CBS_CFM\n", __func__);
+                aic3262->asiCtxt[1].master = 0;
+                clk_reg |= BIT5;
+                clk_reg &= ~0x1C;
+        break;
+        default:
+                printk(KERN_ERR "#%s:Invalid DAI master/slave interface\n",
+                        __func__);
+                return -EINVAL;
+        }
+        aic3262->asiCtxt[1].pcm_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for I2S Mode..\n",
+                                __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f);
+        break;
+        case SND_SOC_DAIFMT_DSP_A:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_A Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f) | 0x20;
+        break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                iface_reg = (iface_reg & 0x1f) | 0x40;
+        break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                iface_reg = (iface_reg & 0x1f) | 0x60;
+        break;
+        case SND_SOC_DAIFMT_DSP_B:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for DSP Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f) | 0x80;
+                /* voice call need data offset in 1 bitclock */
+                snd_soc_write(codec, ASI2_LCH_OFFSET, 1);
+        break;
+        default:
+                printk(KERN_ERR "#%s:Invalid DAI interface format\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Also Configure the Pin Control Registers before writing into
+        * the ASI2 specific Clock Control and Format Registers
+        */
+
+        /* Configure B0_P4_R69_D[5:2] to 001 This configures the
+        * WCLK2 Pin to ASI2
+        */
+
+        regvalue = snd_soc_read(codec, WCLK2_PIN_CNTL_REG);
+        snd_soc_write(codec, WCLK2_PIN_CNTL_REG, (regvalue | BIT2));
+
+        regvalue = snd_soc_read(codec, BCLK2_PIN_CNTL_REG);
+        snd_soc_write(codec, BCLK2_PIN_CNTL_REG, (regvalue | BIT2));
+
+        /* Configure B0_P4_R72_d[6:5] = 01 and B0_P4_R71_D[4:1] to 0001
+         * to ensure that the DIN2 and DOUT2 Pins are configured
+         * correctly
+         */
+        regvalue = snd_soc_read(codec, DIN2_PIN_CNTL_REG);
+        snd_soc_write(codec, DIN2_PIN_CNTL_REG, (regvalue | BIT5));
+
+        regvalue = snd_soc_read(codec, DOUT2_PIN_CNTL_REG);
+        snd_soc_write(codec, DOUT2_PIN_CNTL_REG, (regvalue | BIT5 | BIT1));
+
+        snd_soc_write(codec, ASI2_BWCLK_CNTL_REG, clk_reg);
+
+        snd_soc_write(codec, ASI2_BUS_FMT, iface_reg);
+
+        return 0;
+}
+
+/*
+*----------------------------------------------------------------------------
+* Function : aic3262_multi_i2s_asi3_set_dai_fmt
+* Purpose  : This function is to set the DAI format for ASI3 Port
+*
+*----------------------------------------------------------------------------
+*/
+static int aic3262_multi_i2s_asi3_set_dai_fmt(struct snd_soc_dai *codec_dai,
+                        unsigned int fmt)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 iface_reg, clk_reg;
+        u8 regvalue;
+
+        DBG(KERN_INFO "%s: DAI_ID %d fmt %d\n",
+                __func__, codec_dai->id, fmt);
+
+        /* Read the B0_P4_R33 and B0_P4_R42 Registers to configure the
+        * ASI1 Bus and Clock Formats depending on the PCM Format.
+        */
+        iface_reg = snd_soc_read(codec, ASI3_BUS_FMT);
+        clk_reg   = snd_soc_read(codec, ASI3_BWCLK_CNTL_REG);
+
+        /* set master/slave audio interface */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Master..\n",
+                        __func__, codec_dai->id);
+                aic3262->asiCtxt[2].master = 1;
+                clk_reg |= (BIT5 | BIT2);
+        break;
+        case SND_SOC_DAIFMT_CBS_CFS:
+                DBG(KERN_INFO "#%s: Configuring ASI%d as Frame Slave..\n",
+                        __func__, codec_dai->id);
+                clk_reg &= ~0xFC;
+                aic3262->asiCtxt[2].master = 0;
+        break;
+        case SND_SOC_DAIFMT_CBS_CFM:
+                /* new case..just for debugging */
+                DBG(KERN_INFO "%s: SND_SOC_DAIFMT_CBS_CFM\n", __func__);
+                aic3262->asiCtxt[2].master = 0;
+                clk_reg |= BIT5;
+                clk_reg &= ~0x1C;
+        break;
+        default:
+                printk(KERN_ERR "Invalid DAI master/slave interface\n");
+                return -EINVAL;
+        }
+        aic3262->asiCtxt[2].pcm_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+        /* interface format */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for I2S Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f);
+        break;
+        case SND_SOC_DAIFMT_DSP_A:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for DSP_A Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f) | 0x20;
+        break;
+        case SND_SOC_DAIFMT_RIGHT_J:
+                iface_reg = (iface_reg & 0x1f) | 0x40;
+        break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                iface_reg = (iface_reg & 0x1f) | 0x60;
+        break;
+        case SND_SOC_DAIFMT_DSP_B:
+                DBG(KERN_INFO "#%s: Configuring ASI%d for DSP Mode..\n",
+                        __func__, codec_dai->id);
+                iface_reg = (iface_reg & 0x1f) | 0x80;
+                /* voice call need data offset in 1 bitclock */
+                snd_soc_write(codec, ASI3_LCH_OFFSET, 1);
+        break;
+        default:
+                printk(KERN_ERR
+                        "#%s: Invalid DAI interface format\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Also Configure the Pin Control Registers before writing into
+        * the ASI specific Clock Control and Format Registers
+        */
+        /* Configure B0_P4_R73_D[5:2] to 0001 This configures the
+        * WCLK1 Pin to ASI1
+        */
+        regvalue = snd_soc_read(codec, WCLK3_PIN_CNTL_REG);
+        snd_soc_write(codec, WCLK3_PIN_CNTL_REG, (regvalue | BIT2));
+
+        regvalue = snd_soc_read(codec, BCLK3_PIN_CNTL_REG);
+        snd_soc_write(codec, BCLK3_PIN_CNTL_REG, (regvalue | BIT2));
+
+        /* Configure B0_P4_R76_d[6:5] = 01 and B0_P4_R75_D[4:1] to 0001
+        * to ensure that the DIN1 and DOUT1 Pins are configured
+        * correctly
+        */
+        regvalue = snd_soc_read(codec, DIN3_PIN_CNTL_REG);
+        snd_soc_write(codec, DIN3_PIN_CNTL_REG, (regvalue | BIT5));
+        regvalue = snd_soc_read(codec, DOUT3_PIN_CNTL_REG);
+        snd_soc_write(codec, DOUT3_PIN_CNTL_REG, (regvalue | BIT1));
+
+        snd_soc_write(codec, ASI3_BWCLK_CNTL_REG, clk_reg);
+
+        snd_soc_write(codec, ASI3_BUS_FMT, iface_reg);
+
+        return 0;
+}
+
+/*
+ * Clock after PLL and dividers
+ */
+static int aic3262_multi_i2s_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+                int clk_id, unsigned int freq, int dir)
+{
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "#%s: DAI ID %d Freq %d Direction %d\n",
+                        __func__, codec_dai->id, freq, dir);
+        switch (freq) {
+        case AIC3262_FREQ_12000000:
+        case AIC3262_FREQ_12288000:
+        case AIC3262_FREQ_24000000:
+                aic3262->sysclk = freq;
+                return 0;
+                break;
+        }
+        printk(KERN_ERR "Invalid frequency to set DAI system clock\n");
+        return -EINVAL;
+}
+
+/*
+* aic3262_multi_i2s_set_pll
+*
+* This function is invoked as part of the PLL call-back
+* handler from the ALSA layer.
+*/
+static int aic3262_multi_i2s_set_dai_pll(struct snd_soc_dai *codec_dai,
+                int pll_id, int source, unsigned int freq_in,
+                unsigned int freq_out)
+{
+
+        printk(KERN_INFO "%s: DAI ID %d PLL_ID %d InFreq %d OutFreq %d\n",
+                __func__, pll_id, codec_dai->id, freq_in, freq_out);
+
+        return 0;
+}
+
+/*
+* aic3262_asi1_clk_config
+*
+* This function is used to configure the BCLK1, WCLK1 pins which
+* are specific to ASI1 Interface. This function just enables the
+* BCLk and WCLK  along with the miniDSP Port Control Registers.
+* However, depending on the user requirement, this function can also be
+* extended to configure the sourc for the BCLK and WCLK on a ASI basis.
+*/
+static int aic3262_asi1_clk_config(struct snd_soc_codec *codec,
+                struct snd_pcm_hw_params *params)
+{
+        u8 bclk_N_value, wclk_N_value;
+        u8 minidspD_data, minidspA_data;
+        u8 regval;
+
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "%s: Invoked\n",  __func__);
+
+        /* Configure the BCLK and WCLK Output Mux Options */
+        regval = snd_soc_read(codec, ASI1_BWCLK_OUT_CNTL);
+        regval &= ~(AIC3262_ASI_BCLK_MUX_MASK | AIC3262_ASI_WCLK_MUX_MASK);
+
+        regval |= (aic3262->asiCtxt[0].bclk_output <<
+                        AIC3262_ASI_BCLK_MUX_SHIFT);
+        regval |= aic3262->asiCtxt[0].wclk_output;
+        snd_soc_write(codec, ASI1_BWCLK_OUT_CNTL, regval);
+
+        /* Configure the corresponding miniDSP Data Ports */
+        minidspD_data = snd_soc_read(codec, MINIDSP_PORT_CNTL_REG);
+        minidspD_data &= ~(BIT5 | BIT4);
+        snd_soc_write(codec, MINIDSP_PORT_CNTL_REG, minidspD_data);
+
+        minidspA_data = snd_soc_read(codec, ASI1_ADC_INPUT_CNTL);
+        minidspA_data &= ~(BIT2 | BIT1 | BIT0);
+        minidspA_data |= aic3262->asiCtxt[0].adc_input;
+        snd_soc_write(codec, ASI1_ADC_INPUT_CNTL, minidspA_data);
+
+
+        if (aic3262->asiCtxt[0].master == 1) {
+                DBG(KERN_INFO
+                "#%s: Codec Master on ASI1 Port. Enabling BCLK WCLK Divider.\n",
+                        __func__);
+                bclk_N_value = aic3262->asiCtxt[0].bclk_div;
+                snd_soc_write(codec, ASI1_BCLK_N, (bclk_N_value | 0x80));
+
+                wclk_N_value = snd_soc_read(codec, ASI1_WCLK_N);
+                snd_soc_write(codec, ASI1_WCLK_N, (wclk_N_value | 0xA0));
+        }
+        return 0;
+
+}
+
+/*
+* aic3262_asi2_clk_config
+*
+* This function is used to configure the BCLK2, WCLK2 pins which
+* are specific to ASI2 Interface. This function just enables the
+* BCLk and WCLK  along with the miniDSP Port Control Registers.
+* However, depending on the user requirement, this function can also be
+* extended to configure the sourc for the BCLK and WCLK on a ASI basis.
+*/
+static int aic3262_asi2_clk_config(struct snd_soc_codec *codec,
+                struct snd_pcm_hw_params *params)
+{
+        u8 bclk_N_value, wclk_N_value, minidspD_data, minidspA_data;
+        u8 regval;
+
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "%s: Invoked\n",  __func__);
+
+
+        /* Configure the BCLK and WCLK Output Mux Options */
+        regval = snd_soc_read(codec, ASI2_BWCLK_OUT_CNTL);
+        regval &= ~(AIC3262_ASI_BCLK_MUX_MASK | AIC3262_ASI_WCLK_MUX_MASK);
+        regval |= (aic3262->asiCtxt[1].bclk_output <<
+                        AIC3262_ASI_BCLK_MUX_SHIFT);
+        regval |= aic3262->asiCtxt[1].wclk_output;
+
+        snd_soc_write(codec, ASI2_BWCLK_OUT_CNTL, regval);
+        /* Configure the corresponding miniDSP Data Ports */
+        minidspD_data = snd_soc_read(codec, MINIDSP_PORT_CNTL_REG);
+        minidspD_data |= (BIT2);
+        snd_soc_write(codec, MINIDSP_PORT_CNTL_REG, minidspD_data);
+
+        minidspA_data = snd_soc_read(codec, ASI2_ADC_INPUT_CNTL);
+        minidspA_data &= ~(BIT2 | BIT1 | BIT0);
+        minidspA_data |= aic3262->asiCtxt[1].adc_input;
+        snd_soc_write(codec, ASI2_ADC_INPUT_CNTL, minidspA_data);
+
+        /* NO Manual configuration of WCLK and BCLK for Master Mode.
+        * DAPM Handles all the required modifications.
+        */
+        if (aic3262->asiCtxt[1].master == 1) {
+                DBG(KERN_INFO
+                "#%s: Codec Master on ASI2 Port. Enabling BCLK WCLK Divider.\n",
+                        __func__);
+                bclk_N_value = aic3262->asiCtxt[1].bclk_div;
+                snd_soc_write(codec, ASI2_BCLK_N, (bclk_N_value | 0x80));
+
+                wclk_N_value = snd_soc_read(codec, ASI2_WCLK_N);
+                snd_soc_write(codec, ASI2_WCLK_N, (wclk_N_value | 0xA0));
+        }
+
+        return 0;
+
+}
+
+/*
+* aic3262_asi3_clk_config
+*
+* This function is used to configure the BCLK3, WCLK3 pins which
+* are specific to ASI3 Interface. This function just enables the
+* BCLk and WCLK  along with the miniDSP Port Control Registers.
+* However, depending on the user requirement, this function can also be
+* extended to configure the sourc for the BCLK and WCLK on a ASI basis.
+*/
+static int aic3262_asi3_clk_config(struct snd_soc_codec *codec,
+                struct snd_pcm_hw_params *params)
+{
+        u8 bclk_N_value, wclk_N_value, minidspD_data, minidspA_data;
+        u8 regval;
+
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "%s:\n",  __func__);
+
+
+        /* Configure the BCLK and WCLK Output Mux Options */
+        regval = snd_soc_read(codec, ASI3_BWCLK_OUT_CNTL);
+        regval &= ~(AIC3262_ASI_BCLK_MUX_MASK | AIC3262_ASI_WCLK_MUX_MASK);
+        regval |= (aic3262->asiCtxt[2].bclk_output <<
+                        AIC3262_ASI_BCLK_MUX_SHIFT);
+        regval |= aic3262->asiCtxt[2].wclk_output;
+        snd_soc_write(codec, ASI3_BWCLK_OUT_CNTL, regval);
+
+        minidspD_data = snd_soc_read(codec, MINIDSP_PORT_CNTL_REG);
+        minidspD_data |= (BIT1);
+        snd_soc_write(codec, MINIDSP_PORT_CNTL_REG, minidspD_data);
+
+        minidspA_data = snd_soc_read(codec, ASI3_ADC_INPUT_CNTL);
+        minidspA_data &= ~(BIT2 | BIT1 | BIT0);
+        minidspA_data |= aic3262->asiCtxt[2].adc_input;
+        snd_soc_write(codec, ASI3_ADC_INPUT_CNTL, minidspA_data);
+
+                if (aic3262->asiCtxt[2].master == 1) {
+                DBG(KERN_INFO
+                "#%s: Codec Master on ASI3 Port. Enabling BCLK WCLK Divider.\n",
+                        __func__);
+                bclk_N_value = aic3262->asiCtxt[2].bclk_div;
+                snd_soc_write(codec, ASI2_BCLK_N, (bclk_N_value | 0x80));
+
+                wclk_N_value = snd_soc_read(codec, ASI3_WCLK_N);
+                snd_soc_write(codec, ASI3_WCLK_N, (wclk_N_value | 0xA0));
+        }
+        return 0;
+
+}
+
+/*
+* aic3262_multi_i2s_hw_params
+*
+* This function is used to configure the individual ASI port registers
+* depending on the configuration passed on by the snd_pcm_hw_params
+* structure.
+* This function internally configures the ASI specific pins and clock
+* Control Registers.
+*/
+static int aic3262_multi_i2s_hw_params(struct snd_pcm_substream *substream,
+                        struct snd_pcm_hw_params *params,
+                        struct snd_soc_dai *dai)
+{
+        int i, j;
+        u8 data;
+        u16 regoffset = 0;
+        u8 dacpath = 0;
+        u8 adcpath = 0;
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        DBG(KERN_INFO "#%s: Invoked for ASI%d Port for %s Mode\n",
+                __func__, dai->id,
+                (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                ? "Playback" : "Record");
+
+        i = aic3262_get_divs(aic3262->sysclk, params_rate(params));
+
+        i2c_verify_book0(codec);
+
+        if (i < 0) {
+                printk(KERN_ERR "#%s: Sampling rate %d not supported\n",
+                        __func__, params_rate(params));
+                return i;
+        }
+
+        aic3262_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        /* Configure the PLL J, R D values only if none of the ASI
+        * Interfaces are Active.
+        */
+
+        if (1) {
+                DBG(KERN_INFO "#%s: None of the ASIs active yet...\n",
+                        __func__);
+                /*We will fix R value to 1 and make P & J=K.D as variable */
+                /* Setting P & R values are set to 1 and 1 at init*/
+
+                /* J value */
+                snd_soc_write(codec, PLL_J_REG, aic3262_divs[i].pll_j);
+
+                /* MSB & LSB for D value */
+
+                snd_soc_write(codec, PLL_D_MSB, (aic3262_divs[i].pll_d >> 8));
+                snd_soc_write(codec, PLL_D_LSB,
+                              (aic3262_divs[i].pll_d & AIC3262_8BITS_MASK));
+
+                /* NDAC divider value */
+                data = snd_soc_read(codec, NDAC_DIV_POW_REG);
+                DBG(KERN_INFO "# reading NDAC = %d , NDAC_DIV_POW_REG = %x\n",
+                        aic3262_divs[i].ndac, data);
+                snd_soc_write(codec, NDAC_DIV_POW_REG,
+                         ((data & 0x80)|(aic3262_divs[i].ndac)));
+                DBG(KERN_INFO "# writing NDAC = %d , NDAC_DIV_POW_REG = %x\n",
+                        aic3262_divs[i].ndac,
+                        ((data & 0x80)|(aic3262_divs[i].ndac)));
+
+                /* MDAC divider value */
+                data = snd_soc_read(codec, MDAC_DIV_POW_REG);
+                DBG(KERN_INFO "# reading MDAC = %d , MDAC_DIV_POW_REG = %x\n",
+                        aic3262_divs[i].mdac, data);
+                snd_soc_write(codec, MDAC_DIV_POW_REG,
+                        ((data & 0x80)|(aic3262_divs[i].mdac)));
+                DBG(KERN_INFO "# writing MDAC = %d , MDAC_DIV_POW_REG = %x\n",
+                aic3262_divs[i].mdac, ((data & 0x80)|(aic3262_divs[i].mdac)));
+
+                /* DOSR MSB & LSB values */
+                snd_soc_write(codec, DOSR_MSB_REG, aic3262_divs[i].dosr >> 8);
+                DBG(KERN_INFO "# writing DOSR_MSB_REG = %d\n",
+                        (aic3262_divs[i].dosr >> 8));
+                snd_soc_write(codec, DOSR_LSB_REG,
+                        aic3262_divs[i].dosr & AIC3262_8BITS_MASK);
+                DBG(KERN_INFO "# writing DOSR_LSB_REG = %d\n",
+                        (aic3262_divs[i].dosr & AIC3262_8BITS_MASK));
+
+                /* NADC divider value */
+                data = snd_soc_read(codec, NADC_DIV_POW_REG);
+                snd_soc_write(codec, NADC_DIV_POW_REG,
+                        ((data & 0x80)|(aic3262_divs[i].nadc)));
+                DBG(KERN_INFO "# writing NADC_DIV_POW_REG = %d\n",
+                        aic3262_divs[i].nadc);
+
+                /* MADC divider value */
+                data = snd_soc_read(codec, MADC_DIV_POW_REG);
+                snd_soc_write(codec, MADC_DIV_POW_REG,
+                        ((data & 0x80)|(aic3262_divs[i].madc)));
+                DBG(KERN_INFO "# writing MADC_DIV_POW_REG = %d\n",
+                        aic3262_divs[i].madc);
+
+                /* AOSR value */
+                snd_soc_write(codec, AOSR_REG, aic3262_divs[i].aosr);
+                DBG(KERN_INFO "# writing AOSR = %d\n", aic3262_divs[i].aosr);
+        } else {
+                DBG(KERN_INFO "#Atleast 1 ASI Active. Cannot Program PLL..\n");
+        }
+        /* Check for the DAI ID to know which ASI needs
+        * Configuration.
+        */
+        switch (dai->id) {
+        case 1:
+                regoffset = ASI1_BUS_FMT;
+
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                        DBG(KERN_INFO "#%s: ASI1 DAC Inputs enabled..\n",
+                                        __func__);
+                        /* Read the DAC Control Register and configure it
+                        * as per the ASIContext Structure Settings.
+                        */
+                        dacpath = snd_soc_read(codec, ASI1_DAC_OUT_CNTL);
+                        dacpath &= ~(AIC3262_ASI_LDAC_PATH_MASK |
+                                AIC3262_ASI_RDAC_PATH_MASK);
+                        dacpath |= (aic3262->asiCtxt[0].left_dac_output
+                                << AIC3262_ASI_LDAC_PATH_SHIFT);
+
+                        dacpath |= (aic3262->asiCtxt[0].right_dac_output
+                                << AIC3262_ASI_RDAC_PATH_SHIFT);
+                        snd_soc_write(codec, ASI1_DAC_OUT_CNTL, dacpath);
+
+                        aic3262->asiCtxt[0].playback_mode = 1;
+                        aic3262->asiCtxt[0].bclk_div =
+                                aic3262_divs[i].blck_N;
+                } else {
+                        /* For Recording, Configure the DOUT Pin as per
+                         * ASIContext Structure Settings.
+                         */
+                        adcpath = snd_soc_read(codec, ASI1_DATA_OUT);
+                        adcpath &= ~(AIC3262_ASI_DOUT_MASK);
+
+                        adcpath |= aic3262->asiCtxt[0].dout_option;
+                        snd_soc_write(codec, ASI1_DATA_OUT, adcpath);
+
+                        aic3262->asiCtxt[0].capture_mode = 1;
+                }
+        break;
+        case 2:
+                regoffset = ASI2_BUS_FMT;
+
+                /* Since we are configuring ASI2, please check if Playback
+                 * is expected. If so, enable ASI2 Inputs to Left and
+                 * Right DACs
+                 */
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                        DBG(KERN_INFO "#%s: ASI2 DAC Inputs enabled..\n",
+                                        __func__);
+                        /* Read the DAC Control Register and configure it
+                         * as per theASIContext Structure Settings.
+                         */
+                        dacpath = snd_soc_read(codec, ASI2_DAC_OUT_CNTL);
+                        dacpath &= ~(AIC3262_ASI_LDAC_PATH_MASK |
+                                AIC3262_ASI_RDAC_PATH_MASK);
+                        dacpath |= (aic3262->asiCtxt[1].left_dac_output
+                                << AIC3262_ASI_LDAC_PATH_SHIFT);
+
+                        dacpath |= (aic3262->asiCtxt[1].right_dac_output
+                                << AIC3262_ASI_RDAC_PATH_SHIFT);
+                        snd_soc_write(codec, ASI2_DAC_OUT_CNTL, dacpath);
+                        aic3262->asiCtxt[1].playback_mode = 1;
+
+                        aic3262->asiCtxt[1].bclk_div =
+                                aic3262_divs[i].blck_N;
+                } else {
+                        /* For Recording, Configure the DOUT Pin as per
+                         * ASIContext Structure Settings.
+                         */
+                        adcpath = snd_soc_read(codec, ASI2_DATA_OUT);
+                        adcpath &= ~(AIC3262_ASI_DOUT_MASK);
+                        adcpath |= aic3262->asiCtxt[1].dout_option;
+                        snd_soc_write(codec, ASI2_DATA_OUT, adcpath);
+
+                        aic3262->asiCtxt[1].capture_mode = 1;
+                }
+        break;
+        case 3:
+                regoffset = ASI3_BUS_FMT;
+                /* Since we are configuring ASI3, please check if Playback
+                * is expected. If so, enable ASI3 Inputs to Left and
+                * Right DACs
+                */
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                        DBG(KERN_INFO "#%s:ASI3 DAC Inputs enabled.\n",
+                                __func__);
+                        /* Read the DAC Control Register and configure
+                        * it as per the ASIContext Structure Settings.
+                        */
+                        dacpath = snd_soc_read(codec, ASI3_DAC_OUT_CNTL);
+                        dacpath &= ~(AIC3262_ASI_LDAC_PATH_MASK |
+                                        AIC3262_ASI_RDAC_PATH_MASK);
+                        dacpath |= (aic3262->asiCtxt[2].left_dac_output
+                                        << AIC3262_ASI_LDAC_PATH_SHIFT);
+                        dacpath |= (aic3262->asiCtxt[2].right_dac_output
+                                << AIC3262_ASI_RDAC_PATH_SHIFT);
+                        snd_soc_write(codec,
+                                ASI3_DAC_OUT_CNTL, dacpath);
+
+                        aic3262->asiCtxt[2].playback_mode = 1;
+
+                        aic3262->asiCtxt[2].bclk_div =
+                                aic3262_divs[i].blck_N;
+                } else {
+                        /* For Recording, Configure the DOUT Pin as per
+                         * ASIContext Structure Settings.
+                         */
+                        adcpath &= ~(AIC3262_ASI_DOUT_MASK);
+                        adcpath |= aic3262->asiCtxt[2].dout_option;
+                        snd_soc_write(codec, ASI3_DATA_OUT, adcpath);
+
+                        aic3262->asiCtxt[2].capture_mode = 1;
+                }
+        break;
+        default:
+                printk(KERN_ERR "Invalid Dai ID %d in %s",
+                        dai->id, __func__);
+        break;
+        }
+        DBG(KERN_INFO "#%s: Reading Pg %d Reg %d for Bus Format Control.\n",
+                __func__, (regoffset/128),  (regoffset % 128));
+
+        /* Read the correspondig ASI DAI Interface Register */
+        data = snd_soc_read(codec, regoffset);
+
+        data = data & 0xe7;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                DBG(KERN_INFO "#%s: Configuring ASI%d S16_LE Fmt..\n",
+                        __func__, dai->id);
+                data = data | 0x00;
+                aic3262->asiCtxt[dai->id - 1].word_len = 16;
+        break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                data |= (0x08);
+                aic3262->asiCtxt[dai->id - 1].word_len = 20;
+        break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                DBG(KERN_INFO "#%s: Configuring ASI%d S24_LE Fmt..\n",
+                        __func__, dai->id);
+                data |= (0x10);
+                aic3262->asiCtxt[dai->id - 1].word_len = 24;
+        break;
+        case SNDRV_PCM_FORMAT_S32_LE:
+                DBG(KERN_INFO "#%s: Configuring ASI%d S32_LE Fmt..\n",
+                        __func__, dai->id);
+                data |= (0x18);
+                aic3262->asiCtxt[dai->id - 1].word_len = 32;
+        break;
+        }
+
+        /* configure the respective Registers for the above configuration */
+        snd_soc_write(codec, regoffset, data);
+
+        for (j = 0; j < NO_FEATURE_REGS; j++) {
+                snd_soc_write(codec,
+                        aic3262_divs[i].codec_specific_regs[j].reg_offset,
+                        aic3262_divs[i].codec_specific_regs[j].reg_val);
+        }
+
+        /* Enable the PLL, MDAC, NDAC, NADC, MADC and BCLK Dividers */
+        aic3262_set_bias_level(codec, SND_SOC_BIAS_ON);
+
+        /* Based on the DAI ID we enable the corresponding pins related to the
+        * ASI Port.
+        */
+        switch (dai->id) {
+        case 1:
+                aic3262_asi1_clk_config(codec, params);
+        break;
+        case 2:
+                aic3262_asi2_clk_config(codec, params);
+        break;
+        case 3:
+                aic3262_asi3_clk_config(codec, params);
+        break;
+        default:
+                printk(KERN_ERR "Invalid Dai ID %d in %s",
+                        dai->id, __func__);
+        break;
+        }
+        /* Depending on the DAI->ID update the local Flags */
+        aic3262->asiCtxt[dai->id - 1].asi_active++;
+        aic3262->asiCtxt[dai->id - 1].sampling_rate = params_rate(params);
+        /* Update the active_count flag */
+        aic3262->active_count++;
+
+        return 0;
+}
+
+/*
+*
+* aic3262_multi_i2s_hw_free
+*
+* This function is used to configure the Codec after the usage is completed.
+* We can use this function to disable the DAC and ADC specific inputs from the
+* individual ASI Ports of the Audio Codec.
+*/
+static int aic3262_multi_i2s_shutdown(struct snd_pcm_substream *substream,
+                        struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        u8 value;
+        u8 dacpath;
+        u8 adcpath;
+        u16 dacregoffset = 0;
+        u16 adcregoffset = 0;
+
+        DBG(KERN_INFO "#%s: ASI%d Port for %s Mode\n",
+                __func__, dai->id,
+                (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+                "Playback" : "Record");
+
+        /* Check if this function was already executed earlier for the same
+        * ASI Port
+        */
+        if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) &&
+                (aic3262->asiCtxt[dai->id - 1].playback_mode == 0)) {
+                DBG(KERN_INFO "#%s: Function Already Executed. Exiting..\n",
+                        __func__);
+                goto err;
+        } else if ((substream->stream != SNDRV_PCM_STREAM_PLAYBACK) &&
+                (aic3262->asiCtxt[dai->id - 1].capture_mode == 0)) {
+                DBG(KERN_INFO "#%s: Function Already Executed. Exiting..\n",
+                        __func__);
+                goto err;
+        }
+
+        switch (dai->id) {
+        case 1:
+                /* In case we are Frame Master on this Interface, Switch off
+                * the Bit Clock Divider and Word Clock Dividers
+                */
+                if (aic3262->asiCtxt[0].master == 1) {
+                        /* Also check if either Playback or Recording is still
+                        * going on this ASI Interface
+                        */
+
+                        value = snd_soc_read(codec, ASI1_BCLK_N);
+                        snd_soc_write(codec, ASI1_BCLK_N, (value & 0x7f));
+
+                        value = snd_soc_read(codec, ASI1_WCLK_N);
+                        snd_soc_write(codec, ASI1_WCLK_N, (value & 0x7f));
+                }
+
+                dacregoffset = ASI1_DAC_OUT_CNTL;
+                adcregoffset = ASI1_ADC_INPUT_CNTL;
+        break;
+        case 2:
+                /* In case we are Frame Master on this Interface, Switch off
+                * the Bit Clock Divider and Word Clock Dividers
+                */
+                if (aic3262->asiCtxt[1].master == 1) {
+                        value = snd_soc_read(codec, ASI2_BCLK_N);
+                        snd_soc_write(codec, ASI2_BCLK_N, (value & 0x7f));
+
+                        value = snd_soc_read(codec, ASI2_WCLK_N);
+                        snd_soc_write(codec, ASI2_WCLK_N, (value & 0x7f));
+                }
+                dacregoffset = ASI2_DAC_OUT_CNTL;
+                adcregoffset = ASI2_ADC_INPUT_CNTL;
+        break;
+        case 3:
+                /* In case we are Frame Master on this Interface, Switch off
+                * the Bit Clock Divider and Word Clock Dividers
+                */
+                if (aic3262->asiCtxt[2].master == 1) {
+                        value = snd_soc_read(codec, ASI3_BCLK_N);
+                        snd_soc_write(codec, ASI3_BCLK_N, (value & 0x7f));
+
+                        value = snd_soc_read(codec, ASI3_WCLK_N);
+                        snd_soc_write(codec, ASI3_WCLK_N, (value & 0x7f));
+                }
+                dacregoffset = ASI3_DAC_OUT_CNTL;
+                adcregoffset = ASI3_ADC_INPUT_CNTL;
+        break;
+        default:
+                printk(KERN_ERR "#%s: Invalid dai id\n", __func__);
+        }
+        /* If this was a Playback Stream Stop, then only
+        * switch off the DAC Inputs
+        */
+        if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) &&
+                (dacregoffset != 0)) {
+                DBG(KERN_INFO "#%s: Disabling Pg %d Reg %d DAC Inputs ..\n",
+                        __func__, (dacregoffset/128), (dacregoffset % 128));
+
+                dacpath = snd_soc_read(codec, dacregoffset);
+                snd_soc_write(codec, dacregoffset, (dacpath & ~(BIT6 | BIT4)));
+
+                aic3262->asiCtxt[dai->id - 1].playback_mode = 0;
+        } else {
+                /* Switch off the ADC Input Control Registers here */
+                DBG(KERN_INFO "#%s: Disabling Pg %d Reg %d for ADC Inputs..\n",
+                        __func__, (adcregoffset/128), (adcregoffset % 128));
+
+                adcpath =  snd_soc_read(codec, adcregoffset);
+                snd_soc_write(codec, adcregoffset,
+                        (adcpath & ~(BIT2 | BIT1 | BIT0)));
+
+                aic3262->asiCtxt[dai->id - 1].capture_mode = 0;
+        }
+
+        /* If we were configured in mono PCM Mode earlier, then reset the
+        * Left Channel and Right Channel offset Registers here.
+        */
+        switch (dai->id) {
+        case 1:
+                if (aic3262->asiCtxt[0].pcm_format == SND_SOC_DAIFMT_DSP_B) {
+                        snd_soc_write(codec, ASI1_LCH_OFFSET, 0x00);
+                        snd_soc_write(codec, ASI1_RCH_OFFSET, 0x00);
+                }
+        break;
+        case 2:
+                if (aic3262->asiCtxt[1].pcm_format == SND_SOC_DAIFMT_DSP_B) {
+                        snd_soc_write(codec, ASI2_LCH_OFFSET, 0x00);
+                        snd_soc_write(codec, ASI2_RCH_OFFSET, 0x00);
+                }
+
+        break;
+        case 3:
+                if (aic3262->asiCtxt[2].pcm_format == SND_SOC_DAIFMT_DSP_B) {
+                        snd_soc_write(codec, ASI3_LCH_OFFSET, 0x00);
+                        snd_soc_write(codec, ASI3_RCH_OFFSET, 0x00);
+                }
+        break;
+        }
+        /* Depending on the DAI->ID update the asi_active Flags */
+        if (aic3262->asiCtxt[dai->id - 1].asi_active) {
+                aic3262->asiCtxt[dai->id - 1].asi_active--;
+
+                /* Update the active_count flag */
+                if (aic3262->active_count)
+                        aic3262->active_count--;
+        }
+err:
+        return 0;
+}
+
+
+/*
+*
+* aic3262_multi_i2s_set_clkdiv
+*
+*/
+static int aic3262_multi_i2s_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
+{
+        int value;
+        struct snd_soc_codec *codec = codec_dai->codec;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+
+        value = snd_soc_read(codec, div_id);
+        snd_soc_write(codec, div_id, (value | div));
+
+        printk(KERN_INFO "#%s: DAI ID %d Page %d Register %d Divider_Val %d Final_Value 0x%x\n",
+                        __func__, codec_dai->id, (div_id /128), (div_id%128), div,
+                        (value | div));
+
+        /* Store the Clock Divider inside the Private Structure */
+        switch(codec_dai->id) {
+        case 1:
+                if (div_id == ASI1_BCLK_N)
+                aic3262->asiCtxt[0].bclk_div = div;
+                if (div_id == ASI1_WCLK_N)
+                aic3262->asiCtxt[0].wclk_div = div;
+        break;
+        case 2:
+                if (div_id == ASI2_BCLK_N)
+                aic3262->asiCtxt[1].bclk_div = div;
+                if (div_id == ASI2_WCLK_N)
+                aic3262->asiCtxt[1].wclk_div = div;
+        break;
+        case 3:
+                if (div_id == ASI3_BCLK_N)
+                aic3262->asiCtxt[2].bclk_div = div;
+                if (div_id == ASI3_WCLK_N)
+                aic3262->asiCtxt[2].wclk_div = div;
+        break;
+        }
+        return 0;
+}
+
+
+/*
+ *----------------------------------------------------------------------------
+ * @struct  snd_soc_codec_dai |
+ *          It is SoC Codec DAI structure which has DAI capabilities viz.,
+ *          playback and capture, DAI runtime information viz. state of DAI
+ *                      and pop wait state, and DAI private data.
+ *          The AIC3262 rates ranges from 8k to 192k
+ *          The PCM bit format supported are 16, 20, 24 and 32 bits
+ *----------------------------------------------------------------------------
+ */
+struct snd_soc_dai_ops aic3262_multi_i2s_dai_ops = {
+        .hw_params      = aic3262_multi_i2s_hw_params,
+        .digital_mute   = aic3262_multi_i2s_mute,
+        .set_fmt        = aic3262_multi_i2s_set_dai_fmt,
+        .set_pll        = aic3262_multi_i2s_set_dai_pll,
+        .set_sysclk     = aic3262_multi_i2s_set_dai_sysclk,
+        .shutdown        = aic3262_multi_i2s_shutdown,
+        .set_clkdiv      = aic3262_multi_i2s_set_clkdiv,
+};
+
+
+static struct snd_soc_dai_driver tlv320aic3262_dai[] = {
+/* AIC3262 ASI1 DAI */
+{
+        .name = "aic3262-asi1",
+        .id = 1,
+        .playback = {
+                .stream_name = "ASI1 Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AIC3262_RATES,
+                .formats = AIC3262_FORMATS},
+        .capture = { /* dummy for fast DAI switching */
+                .stream_name = "ASI1 Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AIC3262_RATES,
+                .formats = AIC3262_FORMATS},
+        .ops = &aic3262_multi_i2s_dai_ops,
+},
+/* AIC3262 ASI2 DAI */
+{
+        .name = "aic3262-asi2",
+        .id = 2,
+        .playback = {
+                .stream_name = "ASI2 Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AIC3262_RATES,
+                .formats = AIC3262_FORMATS,},
+        .capture = {
+                .stream_name = "ASI2 Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AIC3262_RATES,
+                .formats = AIC3262_FORMATS,},
+        .ops = &aic3262_multi_i2s_dai_ops,
+
+},
+/* AIC3262 ASI3 DAI  */
+{
+        .name = "aic3262-asi3",
+        .id = 3,
+        .playback = {
+                .stream_name = "ASI3 Playback",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AIC3262_RATES,
+                .formats = AIC3262_FORMATS, },
+        .capture = {
+                .stream_name = "ASI3 Capture",
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = AIC3262_RATES,
+                .formats = AIC3262_FORMATS, },
+        .ops = &aic3262_multi_i2s_dai_ops,
+
+},
+};
+
+/*
+ *****************************************************************************
+ * Initializations
+ *****************************************************************************
+ */
+/*
+ * AIC3262 register cache
+ * We are caching the registers here.
+ * There is no point in caching the reset register.
+ *
+ * NOTE: In AIC3262, there are 127 registers supported in both page0 and page1
+ *       The following table contains the page0 and page 1 and page 3
+ *       registers values.
+ */
+static const u8 aic3262_reg[AIC3262_CACHEREGNUM] = {
+        0x00, 0x00, 0x10, 0x00, /* 0 */
+        0x03, 0x40, 0x11, 0x08, /* 4 */
+        0x00, 0x00, 0x00, 0x82, /* 8 */
+        0x88, 0x00, 0x80, 0x02, /* 12 */
+        0x00, 0x08, 0x01, 0x01, /* 16 */
+        0x80, 0x01, 0x00, 0x04, /* 20 */
+        0x00, 0x00, 0x01, 0x00, /* 24 */
+        0x00, 0x00, 0x01, 0x00, /* 28 */
+        0x00, 0x00, 0x00, 0x00, /* 32 */
+        0x00, 0x00, 0x00, 0x00, /* 36 */
+        0x00, 0x00, 0x00, 0x00, /* 40 */
+        0x00, 0x00, 0x00, 0x00, /* 44 */
+        0x00, 0x00, 0x00, 0x00, /* 48 */
+        0x00, 0x42, 0x02, 0x02, /* 52 */
+        0x42, 0x02, 0x02, 0x02, /* 56 */
+        0x00, 0x00, 0x00, 0x01, /* 60 */
+        0x01, 0x00, 0x14, 0x00, /* 64 */
+        0x0C, 0x00, 0x00, 0x00, /* 68 */
+        0x00, 0x00, 0x00, 0xEE, /* 72 */
+        0x10, 0xD8, 0x10, 0xD8, /* 76 */
+        0x00, 0x00, 0x88, 0x00, /* 80 */
+        0x00, 0x00, 0x00, 0x00, /* 84 */
+        0x7F, 0x00, 0x00, 0x00, /* 88 */
+        0x00, 0x00, 0x00, 0x00, /* 92 */
+        0x7F, 0x00, 0x00, 0x00, /* 96 */
+        0x00, 0x00, 0x00, 0x00, /* 100 */
+        0x00, 0x00, 0x00, 0x00, /* 104 */
+        0x00, 0x00, 0x00, 0x00, /* 108 */
+        0x00, 0x00, 0x00, 0x00, /* 112 */
+        0x00, 0x00, 0x00, 0x00, /* 116 */
+        0x00, 0x00, 0x00, 0x00, /* 120 */
+        0x00, 0x00, 0x00, 0x00, /* 124 - PAGE0 Registers(127) ends here */
+        0x01, 0x00, 0x08, 0x00, /* 128, PAGE1-0 */
+        0x00, 0x00, 0x00, 0x00, /* 132, PAGE1-4 */
+        0x00, 0x00, 0x00, 0x10, /* 136, PAGE1-8 */
+        0x00, 0x00, 0x00, 0x00, /* 140, PAGE1-12 */
+        0x40, 0x40, 0x40, 0x40, /* 144, PAGE1-16 */
+        0x00, 0x00, 0x00, 0x00, /* 148, PAGE1-20 */
+        0x00, 0x00, 0x00, 0x00, /* 152, PAGE1-24 */
+        0x00, 0x00, 0x00, 0x00, /* 156, PAGE1-28 */
+        0x00, 0x00, 0x00, 0x00, /* 160, PAGE1-32 */
+        0x00, 0x00, 0x00, 0x00, /* 164, PAGE1-36 */
+        0x00, 0x00, 0x00, 0x00, /* 168, PAGE1-40 */
+        0x00, 0x00, 0x00, 0x00, /* 172, PAGE1-44 */
+        0x00, 0x00, 0x00, 0x00, /* 176, PAGE1-48 */
+        0x00, 0x00, 0x00, 0x00, /* 180, PAGE1-52 */
+        0x00, 0x00, 0x00, 0x80, /* 184, PAGE1-56 */
+        0x80, 0x00, 0x00, 0x00, /* 188, PAGE1-60 */
+        0x00, 0x00, 0x00, 0x00, /* 192, PAGE1-64 */
+        0x00, 0x00, 0x00, 0x00, /* 196, PAGE1-68 */
+        0x00, 0x00, 0x00, 0x00, /* 200, PAGE1-72 */
+        0x00, 0x00, 0x00, 0x00, /* 204, PAGE1-76 */
+        0x00, 0x00, 0x00, 0x00, /* 208, PAGE1-80 */
+        0x00, 0x00, 0x00, 0x00, /* 212, PAGE1-84 */
+        0x00, 0x00, 0x00, 0x00, /* 216, PAGE1-88 */
+        0x00, 0x00, 0x00, 0x00, /* 220, PAGE1-92 */
+        0x00, 0x00, 0x00, 0x00, /* 224, PAGE1-96 */
+        0x00, 0x00, 0x00, 0x00, /* 228, PAGE1-100 */
+        0x00, 0x00, 0x00, 0x00, /* 232, PAGE1-104 */
+        0x00, 0x00, 0x00, 0x00, /* 236, PAGE1-108 */
+        0x00, 0x00, 0x00, 0x00, /* 240, PAGE1-112 */
+        0x00, 0x00, 0x00, 0x00, /* 244, PAGE1-116 */
+        0x00, 0x00, 0x00, 0x00, /* 248, PAGE1-120 */
+        0x00, 0x00, 0x00, 0x00, /* 252, PAGE1-124 Page 1 Registers Ends Here */
+        0x00, 0x00, 0x00, 0x00, /* 256, PAGE2-0  */
+        0x00, 0x00, 0x00, 0x00, /* 260, PAGE2-4  */
+        0x00, 0x00, 0x00, 0x00, /* 264, PAGE2-8  */
+        0x00, 0x00, 0x00, 0x00, /* 268, PAGE2-12 */
+        0x00, 0x00, 0x00, 0x00, /* 272, PAGE2-16 */
+        0x00, 0x00, 0x00, 0x00, /* 276, PAGE2-20 */
+        0x00, 0x00, 0x00, 0x00, /* 280, PAGE2-24 */
+        0x00, 0x00, 0x00, 0x00, /* 284, PAGE2-28 */
+        0x00, 0x00, 0x00, 0x00, /* 288, PAGE2-32 */
+        0x00, 0x00, 0x00, 0x00, /* 292, PAGE2-36 */
+        0x00, 0x00, 0x00, 0x00, /* 296, PAGE2-40 */
+        0x00, 0x00, 0x00, 0x00, /* 300, PAGE2-44 */
+        0x00, 0x00, 0x00, 0x00, /* 304, PAGE2-48 */
+        0x00, 0x00, 0x00, 0x00, /* 308, PAGE2-52 */
+        0x00, 0x00, 0x00, 0x00, /* 312, PAGE2-56 */
+        0x00, 0x00, 0x00, 0x00, /* 316, PAGE2-60 */
+        0x00, 0x00, 0x00, 0x00, /* 320, PAGE2-64 */
+        0x00, 0x00, 0x00, 0x00, /* 324, PAGE2-68 */
+        0x00, 0x00, 0x00, 0x00, /* 328, PAGE2-72 */
+        0x00, 0x00, 0x00, 0x00, /* 332, PAGE2-76 */
+        0x00, 0x00, 0x00, 0x00, /* 336, PAGE2-80 */
+        0x00, 0x00, 0x00, 0x00, /* 340, PAGE2-84 */
+        0x00, 0x00, 0x00, 0x00, /* 344, PAGE2-88 */
+        0x00, 0x00, 0x00, 0x00, /* 348, PAGE2-92 */
+        0x00, 0x00, 0x00, 0x00, /* 352, PAGE2-96 */
+        0x00, 0x00, 0x00, 0x00, /* 356, PAGE2-100 */
+        0x00, 0x00, 0x00, 0x00, /* 360, PAGE2-104 */
+        0x00, 0x00, 0x00, 0x00, /* 364, PAGE2-108 */
+        0x00, 0x00, 0x00, 0x00, /* 368, PAGE2-112*/
+        0x00, 0x00, 0x00, 0x00, /* 372, PAGE2-116*/
+        0x00, 0x00, 0x00, 0x00, /* 376, PAGE2-120*/
+        0x00, 0x00, 0x00, 0x00, /* 380, PAGE2-124 Page 2 Registers Ends Here */
+        0x00, 0x00, 0x00, 0x00, /* 384, PAGE3-0  */
+        0x00, 0x00, 0x00, 0x00, /* 388, PAGE3-4  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-8  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-12  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-16  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-20  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-24  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-28  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-32  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-36  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-40  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-44  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-48  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-52  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-56  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-60  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-64  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE3-68  */
+        0x00, 0x00, 0x00, 0x00, /* 328, PAGE3-72 */
+        0x00, 0x00, 0x00, 0x00, /* 332, PAGE3-76 */
+        0x00, 0x00, 0x00, 0x00, /* 336, PAGE3-80 */
+        0x00, 0x00, 0x00, 0x00, /* 340, PAGE3-84 */
+        0x00, 0x00, 0x00, 0x00, /* 344, PAGE3-88 */
+        0x00, 0x00, 0x00, 0x00, /* 348, PAGE3-92 */
+        0x00, 0x00, 0x00, 0x00, /* 352, PAGE3-96 */
+        0x00, 0x00, 0x00, 0x00, /* 356, PAGE3-100 */
+        0x00, 0x00, 0x00, 0x00, /* 360, PAGE3-104 */
+        0x00, 0x00, 0x00, 0x00, /* 364, PAGE3-108 */
+        0x00, 0x00, 0x00, 0x00, /* 368, PAGE3-112*/
+        0x00, 0x00, 0x00, 0x00, /* 372, PAGE3-116*/
+        0x00, 0x00, 0x00, 0x00, /* 376, PAGE3-120*/
+        0x00, 0x00, 0x00, 0x00, /* 380, PAGE3-124 Page 3 Registers Ends Here */
+        0x00, 0x00, 0x00, 0x00, /* 384, PAGE4-0  */
+        0x00, 0x00, 0x00, 0x00, /* 388, PAGE4-4  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-8  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-12  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-16  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-20  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-24  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-28  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-32  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-36  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-40  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-44  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-48  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-52  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-56  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-60  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-64  */
+        0x00, 0x00, 0x00, 0x00, /* 392, PAGE4-68  */
+        0x00, 0x00, 0x00, 0x00, /* 328, PAGE4-72 */
+        0x00, 0x00, 0x00, 0x00, /* 332, PAGE4-76 */
+        0x00, 0x00, 0x00, 0x00, /* 336, PAGE4-80 */
+        0x00, 0x00, 0x00, 0x00, /* 340, PAGE4-84 */
+        0x00, 0x00, 0x00, 0x00, /* 344, PAGE4-88 */
+        0x00, 0x00, 0x00, 0x00, /* 348, PAGE4-92 */
+        0x00, 0x00, 0x00, 0x00, /* 352, PAGE4-96 */
+        0x00, 0x00, 0x00, 0x00, /* 356, PAGE4-100 */
+        0x00, 0x00, 0x00, 0x00, /* 360, PAGE4-104 */
+        0x00, 0x00, 0x00, 0x00, /* 364, PAGE4-108 */
+        0x00, 0x00, 0x00, 0x00, /* 368, PAGE4-112*/
+        0x00, 0x00, 0x00, 0x00, /* 372, PAGE4-116*/
+        0x00, 0x00, 0x00, 0x00, /* 376, PAGE4-120*/
+        0x00, 0x00, 0x00, 0x00, /* 380, PAGE4-124 Page 2 Registers Ends Here */
+
+};
+
+/*
+ *------------------------------------------------------------------------------
+ * aic3262 initialization data
+ * This structure initialization contains the initialization required for
+ * AIC326x.
+ * These registers values (reg_val) are written into the respective AIC3262
+ * register offset (reg_offset) to  initialize AIC326x.
+ * These values are used in aic3262_init() function only.
+ *------------------------------------------------------------------------------
+ */
+static const struct aic3262_configs aic3262_reg_init[] = {
+        /* CLOCKING */
+
+        {0, RESET_REG, 1},
+        {0, RESET_REG, 0},
+
+        {0, PASI_DAC_DP_SETUP,  0xc0},  /*DAC */
+        {0, DAC_MVOL_CONF,  0x00},      /*DAC un-muted*/
+        /* set default volumes */
+        {0, DAC_LVOL, 0x01},
+        {0, DAC_RVOL, 0x01},
+        {0, HPL_VOL,  0x80},
+        {0, HPR_VOL,  0x80},
+        {0, SPK_AMP_CNTL_R2, 0x14},
+        {0, SPK_AMP_CNTL_R3, 0x14},
+        {0, SPK_AMP_CNTL_R4, 0x33},
+        {0, REC_AMP_CNTL_R5, 0x82},
+        {0, RAMPR_VOL, 20},
+        {0, RAMP_CNTL_R1, 70},
+        {0, RAMP_CNTL_R2, 70},
+
+        /* DRC Defaults */
+        {0, DRC_CNTL_R1, 0x6c},
+        {0, DRC_CNTL_R2, 16},
+
+        /* DEPOP SETTINGS */
+        {0, HP_DEPOP, 0x14},
+        {0, RECV_DEPOP, 0x14},
+
+        {0, POWER_CONF, 0x00},   /* Disconnecting AVDD-DVD weak link*/
+        {0, REF_PWR_DLY, 0x01},
+        {0, CM_REG, 0x00},      /*CM - default*/
+        {0, LDAC_PTM, 0},       /*LDAC_PTM - default*/
+        {0, RDAC_PTM, 0},       /*RDAC_PTM - default*/
+        {0, HP_CTL, 0x30},      /*HP output percentage - at 75%*/
+        {0, LADC_VOL, 0x01},    /*LADC volume*/
+        {0, RADC_VOL, 0x01},    /*RADC volume*/
+
+        {0, DAC_ADC_CLKIN_REG, 0x33},   /*DAC ADC CLKIN*/
+        {0, PLL_CLKIN_REG, 0x00},       /*PLL CLKIN*/
+        {0, PLL_PR_POW_REG, 0x11},      /*PLL Power=0-down, P=1, R=1 vals*/
+        {0, 0x3d, 1},
+
+        {0, LMIC_PGA_PIN, 0x0}, /*IN1_L select - - 10k -LMICPGA_P*/
+        {0, LMIC_PGA_MIN, 0x40},        /*CM to LMICPGA-M*/
+        {0, RMIC_PGA_PIN, 0x0}, /*IN1_R select - - 10k -RMIC_PGA_P*/
+        {0, RMIC_PGA_MIN, 0x0}, /*CM to RMICPGA_M*/
+        {0, MIC_PWR_DLY , 33},  /*LMIC-PGA-POWERUP-DELAY - default*/
+        {0, REF_PWR_DLY, 1},    /*FIXMELATER*/
+
+
+        {0, ADC_CHANNEL_POW, 0x0}, /*ladc, radc ON , SOFT STEP disabled*/
+        {0, ADC_FINE_GAIN, 0x00},   /*ladc - unmute, radc - unmute*/
+        {0, MICL_PGA, 0x3f},
+        {0, MICR_PGA, 0x3f},
+        /*controls MicBias ext power based on B0_P1_R51_D6*/
+        {0, MIC_BIAS_CNTL, 0x80},
+        /*   ASI1 Configuration */
+        {0, ASI1_BUS_FMT, 0},
+        {0, ASI1_BWCLK_CNTL_REG, 0x00},         /* originaly 0x24*/
+        {0, ASI1_BCLK_N_CNTL, 1},
+        {0, ASI1_BCLK_N, 0x04},
+
+        {0, MA_CNTL, 0},                        /* Mixer Amp disabled */
+        {0, LINE_AMP_CNTL_R2, 0x00},            /* Line Amp Cntl disabled */
+
+        /* ASI2 Configuration */
+        {0, ASI2_BUS_FMT, 0},
+        {0, ASI2_BCLK_N_CNTL, 0x01},
+        {0, ASI2_BCLK_N, 0x04},
+        {0, ASI2_BWCLK_OUT_CNTL, 0x20},
+
+        {0, BEEP_CNTL_R1, 0x05},
+        {0, BEEP_CNTL_R2, 0x04},
+
+        /* Interrupt config for headset detection */
+        {0,HEADSET_TUNING1_REG,0x7f},
+        {0, INT1_CNTL, 0x40},
+        /*{0, TIMER_REG, 0x8c},*/
+        {0, INT_FMT, 0x40},
+        {0, GPIO1_IO_CNTL, 0x14},
+        {0, HP_DETECT, 0x96},
+
+#if defined(CONFIG_MINI_DSP)
+        {0, 60, 0},
+        {0, 61, 0},
+        /* Added the below set of values after consulting the miniDSP
+         * Program Section Array
+         */
+        {0, MINIDSP_ACCESS_CTRL, 0x00},
+#endif
+
+
+};
+
+static int reg_init_size =
+        sizeof(aic3262_reg_init) / sizeof(struct aic3262_configs);
+
+static const unsigned int adc_ma_tlv[] = {
+TLV_DB_RANGE_HEAD(4),
+        0, 29, TLV_DB_SCALE_ITEM(-1450, 500, 0),
+        30, 35, TLV_DB_SCALE_ITEM(-2060, 1000, 0),
+        36, 38, TLV_DB_SCALE_ITEM(-2660, 2000, 0),
+        39, 40, TLV_DB_SCALE_ITEM(-3610, 5000, 0),
+};
+static const DECLARE_TLV_DB_SCALE(lo_hp_tlv, -7830, 50, 0);
+
+static const struct snd_kcontrol_new mal_pga_mixer_controls[] = {
+        SOC_DAPM_SINGLE("IN1L Switch", MA_CNTL, 5, 1, 0),
+        SOC_DAPM_SINGLE_TLV("Left MicPGA Volume", LADC_PGA_MAL_VOL, 0,
+                                                        0x3f, 1, adc_ma_tlv),
+
+};
+
+static const struct snd_kcontrol_new mar_pga_mixer_controls[] = {
+        SOC_DAPM_SINGLE("IN1R Switch", MA_CNTL, 4, 1, 0),
+        SOC_DAPM_SINGLE_TLV("Right MicPGA Volume", RADC_PGA_MAR_VOL, 0,
+                                                        0x3f, 1, adc_ma_tlv),
+};
+
+/* Left HPL Mixer */
+static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("MAL Switch", HP_AMP_CNTL_R1, 7, 1, 0),
+        SOC_DAPM_SINGLE("LDAC Switch", HP_AMP_CNTL_R1, 5, 1, 0),
+        SOC_DAPM_SINGLE_TLV("LOL-B1 Volume", HP_AMP_CNTL_R2, 0,
+                                                        0x7f, 1, lo_hp_tlv),
+};
+
+/* Right HPR Mixer */
+static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE_TLV("LOR-B1 Volume", HP_AMP_CNTL_R3, 0,
+                                                        0x7f, 1, lo_hp_tlv),
+        SOC_DAPM_SINGLE("LDAC Switch", HP_AMP_CNTL_R1,   2, 1, 0),
+        SOC_DAPM_SINGLE("RDAC Switch", HP_AMP_CNTL_R1, 4, 1, 0),
+        SOC_DAPM_SINGLE("MAR Switch", HP_AMP_CNTL_R1, 6, 1, 0),
+};
+
+/* Left LOL Mixer */
+static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("MAL Switch", LINE_AMP_CNTL_R2, 7, 1, 0),
+        SOC_DAPM_SINGLE("IN1L-B Switch", LINE_AMP_CNTL_R2, 3, 1,0),
+        SOC_DAPM_SINGLE("LDAC Switch", LINE_AMP_CNTL_R1, 7, 1, 0),
+        SOC_DAPM_SINGLE("RDAC Switch", LINE_AMP_CNTL_R1, 5, 1, 0),
+};
+
+/* Right LOR Mixer */
+static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("LOL Switch", LINE_AMP_CNTL_R1, 2, 1, 0),
+        SOC_DAPM_SINGLE("RDAC Switch", LINE_AMP_CNTL_R1, 6, 1, 0),
+        SOC_DAPM_SINGLE("MAR Switch", LINE_AMP_CNTL_R2, 6, 1, 0),
+        SOC_DAPM_SINGLE("IN1R-B Switch", LINE_AMP_CNTL_R2, 0, 1,0),
+};
+
+/* Left SPKL Mixer */
+static const struct snd_kcontrol_new spkl_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE("MAL Switch", SPK_AMP_CNTL_R1, 7, 1, 0),
+        SOC_DAPM_SINGLE_TLV("LOL Volume", SPK_AMP_CNTL_R2, 0, 0x7f,0,
+                                                                lo_hp_tlv),
+        SOC_DAPM_SINGLE("SPR_IN Switch", SPK_AMP_CNTL_R1, 2, 1, 0),
+};
+
+/* Right SPKR Mixer */
+static const struct snd_kcontrol_new spkr_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE_TLV("LOR Volume", SPK_AMP_CNTL_R3, 0, 0x7f, 0,
+                                                                lo_hp_tlv),
+        SOC_DAPM_SINGLE("MAR Switch", SPK_AMP_CNTL_R1, 6, 1, 0),
+};
+
+/* REC Mixer */
+static const struct snd_kcontrol_new rec_output_mixer_controls[] = {
+        SOC_DAPM_SINGLE_TLV("LOL-B2 Volume", RAMP_CNTL_R1, 0, 0x7f,0,
+                                                        lo_hp_tlv),
+        SOC_DAPM_SINGLE_TLV("IN1L Volume", IN1L_SEL_RM, 0, 0x7f, 1, lo_hp_tlv),
+        SOC_DAPM_SINGLE_TLV("IN1R Volume", IN1R_SEL_RM, 0, 0x7f, 1, lo_hp_tlv),
+        SOC_DAPM_SINGLE_TLV("LOR-B2 Volume", RAMP_CNTL_R2, 0,0x7f, 0,lo_hp_tlv),
+};
+
+/* Left Input Mixer */
+static const struct snd_kcontrol_new left_input_mixer_controls[] = {
+        SOC_DAPM_SINGLE("IN1L Switch", LMIC_PGA_PIN, 6, 1, 0),
+        SOC_DAPM_SINGLE("IN2L Switch", LMIC_PGA_PIN, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN3L Switch", LMIC_PGA_PIN, 2, 1, 0),
+        SOC_DAPM_SINGLE("IN4L Switch", LMIC_PGA_PM_IN4, 5, 1, 0),
+        SOC_DAPM_SINGLE("IN1R Switch", LMIC_PGA_PIN, 0, 1, 0),
+        SOC_DAPM_SINGLE("IN2R Switch", LMIC_PGA_MIN, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN3R Switch", LMIC_PGA_MIN, 2, 1, 0),
+        SOC_DAPM_SINGLE("IN4R Switch", LMIC_PGA_PM_IN4, 4, 1, 0),
+        SOC_DAPM_SINGLE("CM2L Switch", LMIC_PGA_MIN, 0, 1, 0),
+        SOC_DAPM_SINGLE("CM1L Switch", LMIC_PGA_MIN, 6, 1, 0),
+};
+
+/* Right Input Mixer */
+static const struct snd_kcontrol_new right_input_mixer_controls[] = {
+        SOC_DAPM_SINGLE("IN1R Switch", RMIC_PGA_PIN, 6, 1, 0),
+        SOC_DAPM_SINGLE("IN2R Switch", RMIC_PGA_PIN, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN3R Switch", RMIC_PGA_PIN, 2, 1, 0),
+        SOC_DAPM_SINGLE("IN4R Switch", RMIC_PGA_PM_IN4, 5, 1, 0),
+        SOC_DAPM_SINGLE("IN2L Switch", RMIC_PGA_PIN, 0, 1, 0),
+        SOC_DAPM_SINGLE("IN1L Switch", RMIC_PGA_MIN, 4, 1, 0),
+        SOC_DAPM_SINGLE("IN3L Switch", RMIC_PGA_MIN, 2, 1, 0),
+        SOC_DAPM_SINGLE("IN4L Switch", RMIC_PGA_PM_IN4, 4, 1, 0),
+        SOC_DAPM_SINGLE("CM1R Switch", RMIC_PGA_MIN, 6, 1, 0),
+        SOC_DAPM_SINGLE("CM2R Switch", RMIC_PGA_MIN, 0, 1, 0),
+};
+
+
+static const char *asi1lin_text[] = {
+        "Off", "ASI1 Left In","ASI1 Right In","ASI1 MonoMix In"
+};
+
+SOC_ENUM_SINGLE_DECL(asi1lin_enum, ASI1_DAC_OUT_CNTL, 6, asi1lin_text);
+
+static const struct snd_kcontrol_new asi1lin_control =
+        SOC_DAPM_ENUM("ASI1LIN Route", asi1lin_enum);
+
+
+static const char *asi1rin_text[] = {
+        "Off", "ASI1 Right In","ASI1 Left In","ASI1 MonoMix In"
+};
+
+SOC_ENUM_SINGLE_DECL(asi1rin_enum, ASI1_DAC_OUT_CNTL, 4, asi1rin_text);
+
+static const struct snd_kcontrol_new asi1rin_control =
+        SOC_DAPM_ENUM("ASI1RIN Route", asi1rin_enum);
+
+static const char *asi2lin_text[] = {
+        "Off", "ASI2 Left In","ASI2 Right In","ASI2 MonoMix In"
+};
+
+SOC_ENUM_SINGLE_DECL(asi2lin_enum, ASI2_DAC_OUT_CNTL, 6, asi2lin_text);
+static const struct snd_kcontrol_new asi2lin_control =
+        SOC_DAPM_ENUM("ASI2LIN Route", asi2lin_enum);
+
+static const char *asi2rin_text[] = {
+        "Off", "ASI2 Right In","ASI2 Left In","ASI2 MonoMix In"
+};
+
+
+SOC_ENUM_SINGLE_DECL(asi2rin_enum, ASI2_DAC_OUT_CNTL, 4, asi2rin_text);
+
+static const struct snd_kcontrol_new asi2rin_control =
+        SOC_DAPM_ENUM("ASI2RIN Route", asi2rin_enum);
+
+static const char *asi3lin_text[] = {
+        "Off", "ASI3 Left In","ASI3 Right In","ASI3 MonoMix In"
+};
+
+
+SOC_ENUM_SINGLE_DECL(asi3lin_enum, ASI3_DAC_OUT_CNTL, 6, asi3lin_text);
+static const struct snd_kcontrol_new asi3lin_control =
+                        SOC_DAPM_ENUM("ASI3LIN Route", asi3lin_enum);
+
+
+static const char *asi3rin_text[] = {
+        "Off", "ASI3 Right In","ASI3 Left In","ASI3 MonoMix In"
+};
+
+
+SOC_ENUM_SINGLE_DECL(asi3rin_enum, ASI3_DAC_OUT_CNTL, 4, asi3rin_text);
+static const struct snd_kcontrol_new asi3rin_control =
+        SOC_DAPM_ENUM("ASI3RIN Route", asi3rin_enum);
+
+
+static const char *dacminidspin1_text[] = {
+        "ASI1 In", "ASI2 In","ASI3 In","ADC MiniDSP Out"
+};
+
+SOC_ENUM_SINGLE_DECL(dacminidspin1_enum, MINIDSP_PORT_CNTL_REG, 4, dacminidspin1_text);
+static const struct snd_kcontrol_new dacminidspin1_control =
+        SOC_DAPM_ENUM("DAC MiniDSP IN1 Route", dacminidspin1_enum);
+
+static const char *dacminidspin2_text[] = {
+        "ASI1 In", "ASI2 In","ASI3 In"
+};
+
+//static const struct soc_enum dacminidspin1_enum =
+//       SOC_ENUM_SINGLE(MINIDSP_DATA_PORT_CNTL, 5, 2, dacminidspin1_text);
+SOC_ENUM_SINGLE_DECL(dacminidspin2_enum, MINIDSP_PORT_CNTL_REG, 2, dacminidspin2_text);
+
+static const struct snd_kcontrol_new dacminidspin2_control =
+        SOC_DAPM_ENUM("DAC MiniDSP IN2 Route", dacminidspin2_enum);
+
+static const char *dacminidspin3_text[] = {
+        "ASI1 In", "ASI2 In","ASI3 In"
+};
+
+//static const struct soc_enum dacminidspin1_enum =
+//       SOC_ENUM_SINGLE(MINIDSP_DATA_PORT_CNTL, 5, 2, dacminidspin1_text);
+SOC_ENUM_SINGLE_DECL(dacminidspin3_enum, MINIDSP_PORT_CNTL_REG, 0, dacminidspin3_text);
+
+static const struct snd_kcontrol_new dacminidspin3_control =
+SOC_DAPM_ENUM("DAC MiniDSP IN3 Route", dacminidspin3_enum);
+
+static const char *asi1out_text[] = {
+        "Off",
+        "ASI1 Out",
+        "ASI1In Bypass",
+        "ASI2In Bypass",
+        "ASI3In Bypass",
+};
+SOC_ENUM_SINGLE_DECL(asi1out_enum, ASI1_ADC_INPUT_CNTL, 0, asi1out_text);
+static const struct snd_kcontrol_new asi1out_control =
+        SOC_DAPM_ENUM("ASI1OUT Route", asi1out_enum);
+
+static const char *asi2out_text[] = {
+        "Off",
+        "ASI1 Out",
+        "ASI1In Bypass",
+        "ASI2In Bypass",
+        "ASI3In Bypass",
+        "ASI2 Out",
+};
+SOC_ENUM_SINGLE_DECL(asi2out_enum, ASI2_ADC_INPUT_CNTL, 0, asi2out_text);
+static const struct snd_kcontrol_new asi2out_control =
+        SOC_DAPM_ENUM("ASI2OUT Route", asi2out_enum);
+static const char *asi3out_text[] = {
+        "Off",
+        "ASI1 Out",
+        "ASI1In Bypass",
+        "ASI2In Bypass",
+        "ASI3In Bypass",
+        "ASI3 Out",
+};
+SOC_ENUM_SINGLE_DECL(asi3out_enum, ASI3_ADC_INPUT_CNTL, 0, asi3out_text);
+static const struct snd_kcontrol_new asi3out_control =
+        SOC_DAPM_ENUM("ASI3OUT Route", asi3out_enum);
+
+static const char *asi1bclk_text[] = {
+        "DAC_CLK",
+        "DAC_MOD_CLK",
+        "ADC_CLK",
+        "ADC_MOD_CLK",
+};
+
+SOC_ENUM_SINGLE_DECL(asi1bclk_enum, ASI1_BCLK_N_CNTL, 0, asi1bclk_text);
+static const struct snd_kcontrol_new asi1bclk_control =
+        SOC_DAPM_ENUM("ASI1_BCLK Route", asi1bclk_enum);
+
+static const char *asi2bclk_text[] = {
+        "DAC_CLK",
+        "DAC_MOD_CLK",
+        "ADC_CLK",
+        "ADC_MOD_CLK",
+};
+SOC_ENUM_SINGLE_DECL(asi2bclk_enum, ASI2_BCLK_N_CNTL, 0, asi2bclk_text);
+static const struct snd_kcontrol_new asi2bclk_control =
+        SOC_DAPM_ENUM("ASI2_BCLK Route", asi2bclk_enum);
+static const char *asi3bclk_text[] = {
+        "DAC_CLK",
+        "DAC_MOD_CLK",
+        "ADC_CLK",
+        "ADC_MOD_CLK",
+};
+SOC_ENUM_SINGLE_DECL(asi3bclk_enum, ASI3_BCLK_N_CNTL, 0, asi3bclk_text);
+static const struct snd_kcontrol_new asi3bclk_control =
+        SOC_DAPM_ENUM("ASI3_BCLK Route", asi3bclk_enum);
+
+static int aic326x_hp_event(struct snd_soc_dapm_widget *w,
+                struct snd_kcontrol *kcontrol, int event)
+{
+        return 0;
+}
+static int pll_power_on_event(struct snd_soc_dapm_widget *w,
+        struct snd_kcontrol *kcontrol, int event)
+{
+        if (event == SND_SOC_DAPM_POST_PMU)
+        {
+                mdelay(10);
+        }
+        return 0;
+}
+
+static int polling_loop(struct snd_soc_codec *codec, unsigned int reg,
+                        int mask, int on_off)
+{
+        unsigned int counter, status;
+
+        counter = 0;
+        switch(on_off) {
+                case 0: /*off*/
+                        do {
+                                status = snd_soc_read(codec, reg);
+                                counter++;
+                        } while ((counter < 500) && ((status & mask) == mask));
+                break;
+                case 1: /*on*/
+                        do {
+                                status = snd_soc_read(codec, reg);
+                                counter++;
+                        } while ((counter < 500) && ((status & mask) != mask));
+                break;
+                default:
+                        printk("%s: unknown arguement\n", __func__);
+                        break;
+        }
+
+        printk("%s: exiting with count value %d \n", __func__, counter);
+        if(counter >= 500)
+                return -1;
+        return 0;
+}
+
+int poll_dac(struct snd_soc_codec *codec, int left_right, int on_off)
+{
+        int ret = 0;
+
+        aic3262_change_page(codec, 0);
+        aic3262_change_book(codec, 0);
+
+        switch(on_off) {
+
+                case 0:/*power off polling*/
+                        /*DAC power polling logic*/
+                        switch(left_right) {
+                                case 0: /*left dac polling*/
+                                        ret = polling_loop(codec, DAC_FLAG_R1, LDAC_POW_FLAG_MASK, 0);
+                                        break;
+                                case 1:/*right dac polling*/
+                                        ret = polling_loop(codec, DAC_FLAG_R1, RDAC_POW_FLAG_MASK, 0);
+                                        break;
+                        }
+                        break;
+                case 1:/*power on polling*/
+                        /*DAC power polling logic*/
+                        switch(left_right) {
+                                case 0: /*left dac polling*/
+                                        ret = polling_loop(codec, DAC_FLAG_R1, LDAC_POW_FLAG_MASK, 1);
+                                        break;
+                                case 1:/*right dac polling*/
+                                        ret = polling_loop(codec, DAC_FLAG_R1, RDAC_POW_FLAG_MASK, 1);
+                                        break;
+                        }
+                break;
+                default:
+                        printk("%s:unknown arguement\n", __func__);
+                        break;
+                }
+        if(ret)
+                printk("%s: power %s %s failure", __func__, left_right?"right":"left", on_off?"on":"off");
+        return ret;
+}
+
+int poll_adc(struct snd_soc_codec *codec, int left_right, int on_off)
+{
+        int ret = 0;
+
+        aic3262_change_page(codec, 0);
+        aic3262_change_book(codec, 0);
+
+        switch(on_off) {
+
+                case 0:/*power off polling*/
+                        /*DAC power polling logic*/
+                        switch(left_right) {
+                                case 0: /*left dac polling*/
+                                        ret = polling_loop(codec, ADC_FLAG_R1, LADC_POW_FLAG_MASK, 0);
+                                        break;
+                                case 1:/*right dac polling*/
+                                        ret = polling_loop(codec, ADC_FLAG_R1, RADC_POW_FLAG_MASK, 0);
+                                        break;
+        }
+                        break;
+                case 1:/*power on polling*/
+                        /*DAC power polling logic*/
+                        switch(left_right) {
+                                case 0: /*left dac polling*/
+                                        ret = polling_loop(codec, ADC_FLAG_R1, LADC_POW_FLAG_MASK, 1);
+                                        break;
+                                case 1:/*right dac polling*/
+                                        ret = polling_loop(codec, ADC_FLAG_R1, RADC_POW_FLAG_MASK, 1);
+                                        break;
+                }
+                        break;
+                default:
+                        printk("%s:unknown arguement\n", __func__);
+                        break;
+        }
+
+        if(ret)
+                printk("%s: power %s %s failure", __func__, left_right?"right":"left", on_off?"on":"off");
+        return ret;
+}
+
+static int  slave_dac_event(struct snd_soc_dapm_widget *w,
+                               struct snd_kcontrol *kcontrol, int event)
+
+{
+        struct snd_soc_codec *codec = w->codec;
+
+        if (event & SND_SOC_DAPM_POST_PMU) {
+                /* Poll for DAC Power-up first */
+                poll_dac(codec, 0, 1);
+                poll_dac(codec, 1, 1);
+        }
+
+        if (event & SND_SOC_DAPM_POST_PMD) {
+                poll_dac(codec, 0, 0);
+                poll_dac(codec, 1, 0);
+        }
+        return 0;
+}
+
+
+static int  slave_adc_event(struct snd_soc_dapm_widget *w,
+                               struct snd_kcontrol *kcontrol, int event)
+
+{
+        struct snd_soc_codec *codec = w->codec;
+
+        if (event & SND_SOC_DAPM_POST_PMU) {
+
+                /* Poll for ADC Power-up first */
+                poll_adc(codec, 0, 1);
+                poll_adc(codec, 1, 1);
+        }
+
+
+        if (event & SND_SOC_DAPM_POST_PMD) {
+                poll_adc(codec, 0, 0);
+                poll_adc(codec, 1, 0);
+        }
+
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget aic3262_dapm_widgets[] = {
+        /* TODO: Can we switch these off ? */
+        SND_SOC_DAPM_AIF_IN("ASI1IN", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_IN("ASI2IN", "ASI2 Playback", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_IN("ASI3IN", "ASI3 Playback", 0, SND_SOC_NOPM, 0, 0),
+
+
+        SND_SOC_DAPM_DAC_E("Left DAC", NULL, PASI_DAC_DP_SETUP, 7, 0,
+                        slave_dac_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
+                        SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_DAC_E("Right DAC", NULL, PASI_DAC_DP_SETUP, 6, 0,
+                        slave_dac_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
+                        SND_SOC_DAPM_PRE_PMD),
+
+        /* dapm widget (path domain) for HPL Output Mixer */
+        SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
+                 &hpl_output_mixer_controls[0],
+                ARRAY_SIZE(hpl_output_mixer_controls)),
+
+        /* dapm widget (path domain) for HPR Output Mixer */
+        SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
+                        &hpr_output_mixer_controls[0],
+                        ARRAY_SIZE(hpr_output_mixer_controls)),
+
+
+        SND_SOC_DAPM_PGA_E("HPL Driver", HP_AMP_CNTL_R1, 1, 0, NULL, 0,
+                                aic326x_hp_event, SND_SOC_DAPM_POST_PMU),
+        SND_SOC_DAPM_PGA_E("HPR Driver", HP_AMP_CNTL_R1, 0, 0, NULL, 0,
+                                aic326x_hp_event, SND_SOC_DAPM_POST_PMU),
+
+
+        /* dapm widget (path domain) for LOL Output Mixer */
+        SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
+                        &lol_output_mixer_controls[0],
+                        ARRAY_SIZE(lol_output_mixer_controls)),
+
+        /* dapm widget (path domain) for LOR Output Mixer mixer */
+        SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
+                        &lor_output_mixer_controls[0],
+                        ARRAY_SIZE(lor_output_mixer_controls)),
+
+        SND_SOC_DAPM_PGA("LOL Driver", LINE_AMP_CNTL_R1, 1, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("LOR Driver", LINE_AMP_CNTL_R1, 0, 0, NULL, 0),
+
+
+        /* dapm widget (path domain) for SPKL Output Mixer */
+        SND_SOC_DAPM_MIXER("SPKL Output Mixer", SND_SOC_NOPM, 0, 0,
+                        &spkl_output_mixer_controls[0],
+                        ARRAY_SIZE(spkl_output_mixer_controls)),
+
+        /* dapm widget (path domain) for SPKR Output Mixer */
+        SND_SOC_DAPM_MIXER("SPKR Output Mixer", SND_SOC_NOPM, 0, 0,
+                        &spkr_output_mixer_controls[0],
+                        ARRAY_SIZE(spkr_output_mixer_controls)),
+
+        SND_SOC_DAPM_PGA("SPKL Driver", SPK_AMP_CNTL_R1, 1, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("SPKR Driver", SPK_AMP_CNTL_R1, 0, 0, NULL, 0),
+
+
+        /* dapm widget (path domain) for SPKR Output Mixer */
+        SND_SOC_DAPM_MIXER("REC Output Mixer", SND_SOC_NOPM, 0, 0,
+                        &rec_output_mixer_controls[0],
+                        ARRAY_SIZE(rec_output_mixer_controls)),
+
+        SND_SOC_DAPM_PGA("RECP Driver", REC_AMP_CNTL_R5, 7, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("RECM Driver", REC_AMP_CNTL_R5, 6, 0, NULL, 0),
+
+
+        SND_SOC_DAPM_MUX("ASI1LIN Route",
+                SND_SOC_NOPM, 0, 0, &asi1lin_control),
+        SND_SOC_DAPM_MUX("ASI1RIN Route",
+                SND_SOC_NOPM, 0, 0, &asi1rin_control),
+        SND_SOC_DAPM_MUX("ASI2LIN Route",
+                SND_SOC_NOPM, 0, 0, &asi2lin_control),
+        SND_SOC_DAPM_MUX("ASI2RIN Route",
+                SND_SOC_NOPM, 0, 0, &asi2rin_control),
+        SND_SOC_DAPM_MUX("ASI3LIN Route",
+                SND_SOC_NOPM, 0, 0, &asi3lin_control),
+        SND_SOC_DAPM_MUX("ASI3RIN Route",
+                SND_SOC_NOPM, 0, 0, &asi3rin_control),
+
+        SND_SOC_DAPM_PGA("ASI1LIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI1RIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI2LIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI2RIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI3LIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI3RIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("ASI1LOUT", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI1ROUT", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI2LOUT", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI2ROUT", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI3LOUT", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI3ROUT", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        SND_SOC_DAPM_PGA("ASI1MonoMixIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI2MonoMixIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI3MonoMixIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+        /* TODO: Can we switch the ASIxIN off? */
+        SND_SOC_DAPM_PGA("ASI1IN Port", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI2IN Port", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ASI3IN Port", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+
+        SND_SOC_DAPM_MUX("DAC MiniDSP IN1 Route",
+                        SND_SOC_NOPM, 0, 0, &dacminidspin1_control),
+SND_SOC_DAPM_MUX("DAC MiniDSP IN2 Route",
+                        SND_SOC_NOPM, 0, 0, &dacminidspin2_control),
+        SND_SOC_DAPM_MUX("DAC MiniDSP IN3 Route",
+                        SND_SOC_NOPM, 0, 0, &dacminidspin3_control),
+
+        SND_SOC_DAPM_PGA("CM", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("CM1L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("CM2L", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("CM1R", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("CM2R", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+        /* TODO: Can we switch these off ? */
+        SND_SOC_DAPM_AIF_OUT("ASI1OUT","ASI1 Capture", 0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("ASI2OUT", "ASI2 Capture",0, SND_SOC_NOPM, 0, 0),
+        SND_SOC_DAPM_AIF_OUT("ASI3OUT", "ASI3 Capture",0, SND_SOC_NOPM, 0, 0),
+
+        SND_SOC_DAPM_MUX("ASI1OUT Route",
+                SND_SOC_NOPM, 0, 0, &asi1out_control),
+        SND_SOC_DAPM_MUX("ASI2OUT Route",
+                SND_SOC_NOPM, 0, 0, &asi2out_control),
+        SND_SOC_DAPM_MUX("ASI3OUT Route",
+                SND_SOC_NOPM, 0, 0, &asi3out_control),
+
+        /* TODO: Will be used during MINIDSP programming */
+        /* TODO: Can we switch them off? */
+        SND_SOC_DAPM_PGA("ADC MiniDSP OUT1", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ADC MiniDSP OUT2", SND_SOC_NOPM, 0, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("ADC MiniDSP OUT3", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+
+
+        SND_SOC_DAPM_ADC_E("Left ADC", NULL, ADC_CHANNEL_POW, 7, 0,
+                        slave_adc_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
+                        SND_SOC_DAPM_PRE_PMD),
+        SND_SOC_DAPM_ADC_E("Right ADC", NULL, ADC_CHANNEL_POW, 6, 0,
+                        slave_adc_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD |
+                        SND_SOC_DAPM_PRE_PMD),
+
+        SND_SOC_DAPM_PGA("Left MicPGA",MICL_PGA, 7, 1, NULL, 0),
+        SND_SOC_DAPM_PGA("Right MicPGA",MICR_PGA, 7, 1, NULL, 0),
+
+        SND_SOC_DAPM_PGA("MAL PGA", MA_CNTL, 3, 0, NULL, 0),
+        SND_SOC_DAPM_PGA("MAR PGA", MA_CNTL, 2, 0, NULL, 0),
+
+
+        /* dapm widget for MAL PGA Mixer*/
+        SND_SOC_DAPM_MIXER("MAL PGA Mixer", SND_SOC_NOPM, 0, 0,
+                         &mal_pga_mixer_controls[0],
+                         ARRAY_SIZE(mal_pga_mixer_controls)),
+
+        /* dapm widget for MAR PGA Mixer*/
+        SND_SOC_DAPM_MIXER("MAR PGA Mixer", SND_SOC_NOPM, 0, 0,
+                        &mar_pga_mixer_controls[0],
+                        ARRAY_SIZE(mar_pga_mixer_controls)),
+
+        /* dapm widget for Left Input Mixer*/
+        SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
+                        &left_input_mixer_controls[0],
+                        ARRAY_SIZE(left_input_mixer_controls)),
+
+        /* dapm widget for Right Input Mixer*/
+        SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
+                        &right_input_mixer_controls[0],
+                        ARRAY_SIZE(right_input_mixer_controls)),
+
+
+        SND_SOC_DAPM_OUTPUT("HPL"),
+        SND_SOC_DAPM_OUTPUT("HPR"),
+        SND_SOC_DAPM_OUTPUT("LOL"),
+        SND_SOC_DAPM_OUTPUT("LOR"),
+        SND_SOC_DAPM_OUTPUT("SPKL"),
+        SND_SOC_DAPM_OUTPUT("SPKR"),
+        SND_SOC_DAPM_OUTPUT("RECP"),
+        SND_SOC_DAPM_OUTPUT("RECM"),
+
+        SND_SOC_DAPM_INPUT("IN1L"),
+        SND_SOC_DAPM_INPUT("IN2L"),
+        SND_SOC_DAPM_INPUT("IN3L"),
+        SND_SOC_DAPM_INPUT("IN4L"),
+        SND_SOC_DAPM_INPUT("IN1R"),
+        SND_SOC_DAPM_INPUT("IN2R"),
+        SND_SOC_DAPM_INPUT("IN3R"),
+        SND_SOC_DAPM_INPUT("IN4R"),
+
+
+        SND_SOC_DAPM_MICBIAS("Mic Bias Ext", MIC_BIAS_CNTL, 6, 0),
+        SND_SOC_DAPM_MICBIAS("Mic Bias Int", MIC_BIAS_CNTL, 2, 0),
+
+        SND_SOC_DAPM_SUPPLY("PLLCLK",PLL_PR_POW_REG,7,0,pll_power_on_event,
+                                                SND_SOC_DAPM_POST_PMU),
+        SND_SOC_DAPM_SUPPLY("DACCLK",NDAC_DIV_POW_REG,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("CODEC_CLK_IN",SND_SOC_NOPM,0,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("DAC_MOD_CLK",MDAC_DIV_POW_REG,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ADCCLK",NADC_DIV_POW_REG,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK",MADC_DIV_POW_REG,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ASI1_BCLK",ASI1_BCLK_N,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ASI1_WCLK",ASI1_WCLK_N,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ASI2_BCLK",ASI2_BCLK_N,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ASI2_WCLK",ASI2_WCLK_N,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ASI3_BCLK",ASI3_BCLK_N,7,0, NULL, 0),
+        SND_SOC_DAPM_SUPPLY("ASI3_WCLK",ASI3_WCLK_N,7,0, NULL, 0),
+        SND_SOC_DAPM_MUX("ASI1_BCLK Route",
+                SND_SOC_NOPM, 0, 0, &asi1bclk_control),
+        SND_SOC_DAPM_MUX("ASI2_BCLK Route", SND_SOC_NOPM, 0, 0, &asi2bclk_control),
+        SND_SOC_DAPM_MUX("ASI3_BCLK Route", SND_SOC_NOPM, 0, 0, &asi3bclk_control),
+};
+
+static const struct snd_soc_dapm_route aic3262_dapm_routes[] ={
+        /* TODO: Do we need only DACCLK for ASIIN's and ADCCLK for ASIOUT??? */
+        /* Clock portion */
+        {"CODEC_CLK_IN", NULL, "PLLCLK"},
+        {"DACCLK", NULL, "CODEC_CLK_IN"},
+        {"ADCCLK", NULL, "CODEC_CLK_IN"},
+        {"DAC_MOD_CLK", NULL, "DACCLK"},
+#ifdef AIC3262_SYNC_MODE
+        {"ADC_MOD_CLK", NULL,"DACCLK"},
+#else
+        {"ADC_MOD_CLK", NULL, "ADCCLK"},
+#endif
+
+        {"ASI1_BCLK Route","DAC_CLK","DACCLK"},
+        {"ASI1_BCLK Route","DAC_MOD_CLK","DAC_MOD_CLK"},
+        {"ASI1_BCLK Route","ADC_CLK","ADCCLK"},
+        {"ASI1_BCLK Route","ADC_MOD_CLK","ADC_MOD_CLK"},
+
+        {"ASI2_BCLK Route","DAC_CLK","DACCLK"},
+        {"ASI2_BCLK Route","DAC_MOD_CLK","DAC_MOD_CLK"},
+        {"ASI2_BCLK Route","ADC_CLK","ADCCLK"},
+        {"ASI2_BCLK Route","ADC_MOD_CLK","ADC_MOD_CLK"},
+
+        {"ASI3_BCLK Route","DAC_CLK","DACCLK"},
+        {"ASI3_BCLK Route","DAC_MOD_CLK","DAC_MOD_CLK"},
+        {"ASI3_BCLK Route","ADC_CLK","ADCCLK"},
+        {"ASI3_BCLK Route","ADC_MOD_CLK","ADC_MOD_CLK"},
+
+        {"ASI1_BCLK", NULL, "ASI1_BCLK Route"},
+        {"ASI2_BCLK", NULL, "ASI2_BCLK Route"},
+        {"ASI3_BCLK", NULL, "ASI3_BCLK Route"},
+
+
+        {"ASI1IN", NULL , "PLLCLK"},
+        {"ASI1IN", NULL , "DACCLK"},
+        {"ASI1IN", NULL , "ADCCLK"},
+        {"ASI1IN", NULL , "DAC_MOD_CLK"},
+        {"ASI1IN", NULL , "ADC_MOD_CLK"},
+
+        {"ASI1OUT", NULL , "PLLCLK"},
+        {"ASI1OUT", NULL , "DACCLK"},
+        {"ASI1OUT", NULL , "ADCCLK"},
+        {"ASI1OUT", NULL , "DAC_MOD_CLK"},
+        {"ASI1OUT", NULL , "ADC_MOD_CLK"},
+#ifdef AIC3262_ASI1_MASTER
+        {"ASI1IN", NULL , "ASI1_BCLK"},
+        {"ASI1OUT", NULL , "ASI1_BCLK"},
+        {"ASI1IN", NULL , "ASI1_WCLK"},
+        {"ASI1OUT", NULL , "ASI1_WCLK"},
+#else
+
+#endif
+
+        {"ASI2IN", NULL , "PLLCLK"},
+        {"ASI2IN", NULL , "DACCLK"},
+        {"ASI2IN", NULL , "ADCCLK"},
+        {"ASI2IN", NULL , "DAC_MOD_CLK"},
+        {"ASI2IN", NULL , "ADC_MOD_CLK"},
+
+        {"ASI2OUT", NULL , "PLLCLK"},
+        {"ASI2OUT", NULL , "DACCLK"},
+        {"ASI2OUT", NULL , "ADCCLK"},
+        {"ASI2OUT", NULL , "DAC_MOD_CLK"},
+        {"ASI2OUT", NULL , "ADC_MOD_CLK"},
+
+#ifdef AIC3262_ASI2_MASTER
+        {"ASI2IN", NULL , "ASI2_BCLK"},
+        {"ASI2OUT", NULL , "ASI2_BCLK"},
+        {"ASI2IN", NULL , "ASI2_WCLK"},
+        {"ASI2OUT", NULL , "ASI2_WCLK"},
+#else
+
+#endif
+        {"ASI3IN", NULL , "PLLCLK"},
+        {"ASI3IN", NULL , "DACCLK"},
+        {"ASI3IN", NULL , "ADCCLK"},
+        {"ASI3IN", NULL , "DAC_MOD_CLK"},
+        {"ASI3IN", NULL , "ADC_MOD_CLK"},
+
+
+        {"ASI3OUT", NULL , "PLLCLK"},
+        {"ASI3OUT", NULL , "DACCLK"},
+        {"ASI3OUT", NULL , "ADCCLK"},
+        {"ASI3OUT", NULL , "DAC_MOD_CLK"},
+        {"ASI3OUT", NULL , "ADC_MOD_CLK"},
+
+#ifdef AIC3262_ASI3_MASTER
+        {"ASI3IN", NULL , "ASI3_BCLK"},
+        {"ASI3OUT", NULL , "ASI3_BCLK"},
+        {"ASI3IN", NULL , "ASI3_WCLK"},
+        {"ASI3OUT", NULL , "ASI3_WCLK"},
+#else
+#endif
+
+/* Playback (DAC) Portion */
+        {"HPL Output Mixer","LDAC Switch","Left DAC"},
+        {"HPL Output Mixer","MAL Switch","MAL PGA"},
+        {"HPL Output Mixer","LOL-B1 Volume","LOL"},
+
+        {"HPR Output Mixer","LOR-B1 Volume","LOR"},
+        {"HPR Output Mixer","LDAC Switch","Left DAC"},
+        {"HPR Output Mixer","RDAC Switch","Right DAC"},
+        {"HPR Output Mixer","MAR Switch","MAR PGA"},
+
+        {"HPL Driver",NULL,"HPL Output Mixer"},
+        {"HPR Driver",NULL,"HPR Output Mixer"},
+
+        {"HPL",NULL,"HPL Driver"},
+        {"HPR",NULL,"HPR Driver"},
+
+        {"LOL Output Mixer","MAL Switch","MAL PGA"},
+        {"LOL Output Mixer","IN1L-B Switch","IN1L"},
+        {"LOL Output Mixer","LDAC Switch","Left DAC"},
+        {"LOL Output Mixer","RDAC Switch","Right DAC"},
+
+        {"LOR Output Mixer","LOL Switch","LOL"},
+        {"LOR Output Mixer","RDAC Switch","Right DAC"},
+        {"LOR Output Mixer","MAR Switch","MAR PGA"},
+        {"LOR Output Mixer","IN1R-B Switch","IN1R"},
+
+        {"LOL Driver",NULL,"LOL Output Mixer"},
+        {"LOR Driver",NULL,"LOR Output Mixer"},
+
+        {"LOL",NULL,"LOL Driver"},
+        {"LOR",NULL,"LOR Driver"},
+
+        {"REC Output Mixer","LOL-B2 Volume","LOL"},
+        {"REC Output Mixer","IN1L Volume","IN1L"},
+        {"REC Output Mixer","IN1R Volume","IN1R"},
+        {"REC Output Mixer","LOR-B2 Volume","LOR"},
+
+        {"RECP Driver",NULL,"REC Output Mixer"},
+        {"RECM Driver",NULL,"REC Output Mixer"},
+
+        {"RECP",NULL,"RECP Driver"},
+        {"RECM",NULL,"RECM Driver"},
+
+        {"SPKL Output Mixer","MAL Switch","MAL PGA"},
+        {"SPKL Output Mixer","LOL Volume","LOL"},
+        {"SPKL Output Mixer","SPR_IN Switch","SPKR Output Mixer"},
+
+        {"SPKR Output Mixer", "LOR Volume","LOR"},
+        {"SPKR Output Mixer", "MAR Switch","MAR PGA"},
+
+
+        {"SPKL Driver",NULL,"SPKL Output Mixer"},
+        {"SPKR Driver",NULL,"SPKR Output Mixer"},
+
+        {"SPKL",NULL,"SPKL Driver"},
+        {"SPKR",NULL,"SPKR Driver"},
+/* ASI Input routing */
+        {"ASI1LIN", NULL, "ASI1IN"},
+        {"ASI1RIN", NULL, "ASI1IN"},
+        {"ASI2LIN", NULL, "ASI2IN"},
+        {"ASI2RIN", NULL, "ASI2IN"},
+        {"ASI3LIN", NULL, "ASI3IN"},
+        {"ASI3RIN", NULL, "ASI3IN"},
+
+        {"ASI1MonoMixIN", NULL, "ASI1IN"},
+        {"ASI2MonoMixIN", NULL, "ASI2IN"},
+        {"ASI3MonoMixIN", NULL, "ASI3IN"},
+
+        {"ASI1LIN Route","ASI1 Left In","ASI1LIN"},
+        {"ASI1LIN Route","ASI1 Right In","ASI1RIN"},
+        {"ASI1LIN Route","ASI1 MonoMix In","ASI1MonoMixIN"},
+
+        {"ASI1RIN Route", "ASI1 Right In","ASI1RIN"},
+        {"ASI1RIN Route","ASI1 Left In","ASI1LIN"},
+        {"ASI1RIN Route","ASI1 MonoMix In","ASI1MonoMixIN"},
+
+
+        {"ASI2LIN Route","ASI2 Left In","ASI2LIN"},
+        {"ASI2LIN Route","ASI2 Right In","ASI2RIN"},
+        {"ASI2LIN Route","ASI2 MonoMix In","ASI2MonoMixIN"},
+
+        {"ASI2RIN Route","ASI2 Right In","ASI2RIN"},
+        {"ASI2RIN Route","ASI2 Left In","ASI2LIN"},
+        {"ASI2RIN Route","ASI2 MonoMix In","ASI2MonoMixIN"},
+
+
+        {"ASI3LIN Route","ASI3 Left In","ASI3LIN"},
+        {"ASI3LIN Route","ASI3 Right In","ASI3RIN"},
+        {"ASI3LIN Route","ASI3 MonoMix In","ASI3MonoMixIN"},
+
+        {"ASI3RIN Route","ASI3 Right In","ASI3RIN"},
+        {"ASI3RIN Route","ASI3 Left In","ASI3LIN"},
+        {"ASI3RIN Route","ASI3 MonoMix In","ASI3MonoMixIN"},
+
+        {"ASI1IN Port", NULL, "ASI1LIN Route"},
+        {"ASI1IN Port", NULL, "ASI1RIN Route"},
+        {"ASI2IN Port", NULL, "ASI2LIN Route"},
+        {"ASI2IN Port", NULL, "ASI2RIN Route"},
+        {"ASI3IN Port", NULL, "ASI3LIN Route"},
+        {"ASI3IN Port", NULL, "ASI3RIN Route"},
+
+        {"DAC MiniDSP IN1 Route", "ASI1 In","ASI1IN Port"},
+        {"DAC MiniDSP IN1 Route","ASI2 In","ASI2IN Port"},
+        {"DAC MiniDSP IN1 Route","ASI3 In","ASI3IN Port"},
+        {"DAC MiniDSP IN1 Route","ADC MiniDSP Out","ADC MiniDSP OUT1"},
+
+        {"DAC MiniDSP IN2 Route","ASI1 In","ASI1IN Port"},
+        {"DAC MiniDSP IN2 Route","ASI2 In","ASI2IN Port"},
+        {"DAC MiniDSP IN2 Route","ASI3 In","ASI3IN Port"},
+
+        {"DAC MiniDSP IN3 Route","ASI1 In","ASI1IN Port"},
+        {"DAC MiniDSP IN3 Route","ASI2 In","ASI2IN Port"},
+        {"DAC MiniDSP IN3 Route","ASI3 In","ASI3IN Port"},
+
+        {"Left DAC", "NULL", "DAC MiniDSP IN1 Route"},
+        {"Right DAC", "NULL", "DAC MiniDSP IN1 Route"},
+
+        {"Left DAC", "NULL","DAC MiniDSP IN2 Route"},
+        {"Right DAC", "NULL","DAC MiniDSP IN2 Route"},
+
+        {"Left DAC", "NULL","DAC MiniDSP IN3 Route"},
+        {"Right DAC", "NULL","DAC MiniDSP IN3 Route"},
+
+
+/* Mixer Amplifier */
+
+        {"MAL PGA Mixer", "IN1L Switch","IN1L"},
+        {"MAL PGA Mixer", "Left MicPGA Volume","Left MicPGA"},
+
+        {"MAL PGA", NULL, "MAL PGA Mixer"},
+
+
+        {"MAR PGA Mixer", "IN1R Switch","IN1R"},
+        {"MAR PGA Mixer", "Right MicPGA Volume","Right MicPGA"},
+
+        {"MAR PGA", NULL, "MAR PGA Mixer"},
+
+
+/* Capture (ADC) portions */
+        /* Left Positive PGA input */
+        {"Left Input Mixer","IN1L Switch","IN1L"},
+        {"Left Input Mixer","IN2L Switch","IN2L"},
+        {"Left Input Mixer","IN3L Switch","IN3L"},
+        {"Left Input Mixer","IN4L Switch","IN4L"},
+        {"Left Input Mixer","IN1R Switch","IN1R"},
+        /* Left Negative PGA input */
+        {"Left Input Mixer","IN2R Switch","IN2R"},
+        {"Left Input Mixer","IN3R Switch","IN3R"},
+        {"Left Input Mixer","IN4R Switch","IN4R"},
+        {"Left Input Mixer","CM2L Switch","CM2L"},
+        {"Left Input Mixer","CM1L Switch","CM1L"},
+
+        /* Right Positive PGA Input */
+        {"Right Input Mixer","IN1R Switch","IN1R"},
+        {"Right Input Mixer","IN2R Switch","IN2R"},
+        {"Right Input Mixer","IN3R Switch","IN3R"},
+        {"Right Input Mixer","IN4R Switch","IN4R"},
+        {"Right Input Mixer","IN2L Switch","IN2L"},
+
+        /* Right Negative PGA Input */
+        {"Right Input Mixer","IN1L Switch","IN1L"},
+        {"Right Input Mixer","IN3L Switch","IN3L"},
+        {"Right Input Mixer","IN4L Switch","IN4L"},
+        {"Right Input Mixer","CM1R Switch","CM1R"},
+        {"Right Input Mixer","CM2R Switch","CM2R"},
+
+        {"CM1L", NULL, "CM"},
+        {"CM2L", NULL, "CM"},
+        {"CM1R", NULL, "CM"},
+        {"CM2R", NULL, "CM"},
+
+        {"Left MicPGA",NULL,"Left Input Mixer"},
+        {"Right MicPGA",NULL,"Right Input Mixer"},
+
+        {"Left ADC", NULL, "Left MicPGA"},
+        {"Right ADC", NULL, "Right MicPGA"},
+
+/* ASI Output Routing */
+        {"ADC MiniDSP OUT1", NULL, "Left ADC"},
+        {"ADC MiniDSP OUT1", NULL, "Right ADC"},
+        {"ADC MiniDSP OUT2", NULL, "Left ADC"},
+        {"ADC MiniDSP OUT2", NULL, "Right ADC"},
+        {"ADC MiniDSP OUT3", NULL, "Left ADC"},
+        {"ADC MiniDSP OUT3", NULL, "Right ADC"},
+
+        {"ASI1OUT Route", "ASI1 Out","ADC MiniDSP OUT1"},// Port 1
+        {"ASI1OUT Route", "ASI1In Bypass","ASI1IN Port"},
+        {"ASI1OUT Route", "ASI2In Bypass","ASI2IN Port"},
+        {"ASI1OUT Route", "ASI3In Bypass","ASI3IN Port"},
+
+        {"ASI2OUT Route", "ASI1 Out","ADC MiniDSP OUT1"},// Port 1
+        {"ASI2OUT Route", "ASI1In Bypass","ASI1IN Port"},
+        {"ASI2OUT Route", "ASI2In Bypass","ASI2IN Port"},
+        {"ASI2OUT Route", "ASI3In Bypass","ASI3IN Port"},
+        {"ASI2OUT Route", "ASI2 Out","ADC MiniDSP OUT2"},// Port 2
+
+        {"ASI3OUT Route", "ASI1 Out","ADC MiniDSP OUT1"},// Port 1
+        {"ASI3OUT Route", "ASI1In Bypass","ASI1IN Port"},
+        {"ASI3OUT Route", "ASI2In Bypass","ASI2IN Port"},
+        {"ASI3OUT Route", "ASI3In Bypass","ASI3IN Port"},
+        {"ASI3OUT Route", "ASI3 Out","ADC MiniDSP OUT3"},// Port 3
+
+        {"ASI1OUT",NULL,"ASI1OUT Route"},
+        {"ASI2OUT",NULL,"ASI2OUT Route"},
+        {"ASI3OUT",NULL,"ASI3OUT Route"},
+
+};
+
+
+#define AIC3262_DAPM_ROUTE_NUM (sizeof(aic3262_dapm_routes)/sizeof(struct snd_soc_dapm_route))
+
+/*
+ *****************************************************************************
+ * Function Definitions
+ *****************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_change_page
+ * Purpose  : This function is to switch between page 0 and page 1.
+ *
+ *----------------------------------------------------------------------------
+ */
+int aic3262_change_page(struct snd_soc_codec *codec, u8 new_page)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 data[2];
+        int ret = 0;
+
+        data[0] = 0;
+        data[1] = new_page;
+        aic3262->page_no = new_page;
+
+#if defined(LOCAL_REG_ACCESS)
+        if (codec->hw_write(codec->control_data, data, 2) != 2)
+                ret = -EIO;
+#else
+        ret = snd_soc_write(codec, data[0], data[1]);
+#endif
+        if (ret)
+                printk(KERN_ERR "Error in changing page to %d\n", new_page);
+
+        /*DBG("# Changing page to %d\r\n", new_page);*/
+
+        return ret;
+}
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_change_book
+ * Purpose  : This function is to switch between books
+ *
+ *----------------------------------------------------------------------------
+ */
+int aic3262_change_book(struct snd_soc_codec *codec, u8 new_book)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 data[2];
+        int ret = 0;
+
+        data[0] = 0x7F;
+        data[1] = new_book;
+        aic3262->book_no = new_book;
+
+        ret = aic3262_change_page(codec, 0);
+        if (ret)
+                return ret;
+
+#if defined(LOCAL_REG_ACCESS)
+        if (codec->hw_write(codec->control_data, data, 2) != 2)
+                ret = -EIO;
+#else
+        ret = snd_soc_write(codec, data[0], data[1]);
+#endif
+        if (ret)
+                printk(KERN_ERR "Error in changing Book\n");
+
+        /*DBG("# Changing book to %d\r\n", new_book);*/
+
+        return ret;
+}
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_write_reg_cache
+ * Purpose  : This function is to write aic3262 register cache
+ *
+ *----------------------------------------------------------------------------
+ */
+void aic3262_write_reg_cache(struct snd_soc_codec *codec,
+                                           u16 reg, u8 value)
+{
+#if defined(EN_REG_CACHE)
+        u8 *cache = codec->reg_cache;
+
+        if (reg >= AIC3262_CACHEREGNUM)
+                return;
+
+        if (cache)
+                cache[reg] = value;
+#endif
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_read
+ * Purpose  : This function is to read the aic3262 register space.
+ *
+ *----------------------------------------------------------------------------
+ */
+
+u8 aic3262_read(struct snd_soc_codec *codec, u16 reg)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 value;
+        u8 page = reg / 128;
+        u16 *cache = codec->reg_cache;
+        u16 cmd;
+        u8 buffer[2];
+        int rc;
+        reg = reg % 128;
+
+        if (reg >= AIC3262_CACHEREGNUM) {
+                return 0;
+        }
+
+        if (aic3262->control_type == SND_SOC_I2C) {
+                if (aic3262->page_no != page) {
+                aic3262_change_page(codec, page);
+                }
+                i2c_master_send(codec->control_data, (char *)&reg, 1);
+                i2c_master_recv(codec->control_data, &value, 1);
+                /*DBG("r %2x %02x\r\n", reg, value); */
+        } else if (aic3262->control_type == SND_SOC_SPI) {
+                u16 value;
+
+                /* Do SPI transfer; first 16bits are command; remaining is
+                 * register contents */
+                cmd = AIC3262_READ_COMMAND_WORD(reg);
+                buffer[0] = (cmd >> 8) & 0xff;
+                buffer[1] = cmd & 0xff;
+                //rc = spi_write_then_read(aic3262->spi, buffer, 2, buffer, 2);
+
+                if (rc) {
+                        dev_err(&aic3262->spi->dev, "AIC26 reg read error\n");
+                        return -EIO;
+                }
+                value = (buffer[0] << 8) | buffer[1];
+        } else {
+                printk(KERN_ERR "Unknown Interface Type in aic3262_read\n");
+        }
+
+        /* Update the cache before returning with the value */
+        cache[reg] = value;
+        return value;
+
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_write
+ * Purpose  : This function is to write to the aic3262 register space.
+ *
+ *----------------------------------------------------------------------------
+ */
+int aic3262_write(struct snd_soc_codec *codec, u16 reg, u8 value)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 data[2];
+        u8 page;
+        int ret = 0;
+
+        page = reg / 128;
+        data[AIC3262_REG_OFFSET_INDEX] = reg % 128;
+        if (aic3262->page_no != page)
+                aic3262_change_page(codec, page);
+
+        /* data is
+         *   D15..D8 aic3262 register offset
+         *   D7...D0 register data
+         */
+        data[AIC3262_REG_DATA_INDEX] = value & AIC3262_8BITS_MASK;
+#if defined(EN_REG_CACHE)
+        if ((page >= 0) & (page <= 4))
+                aic3262_write_reg_cache(codec, reg, value);
+
+#endif
+        if (!data[AIC3262_REG_OFFSET_INDEX]) {
+                /* if the write is to reg0 update aic3262->page_no */
+                aic3262->page_no = value;
+        }
+
+        /*DBG("w %2x %02x\r\n",
+                data[AIC3262_REG_OFFSET_INDEX], data[AIC3262_REG_DATA_INDEX]);*/
+
+#if defined(LOCAL_REG_ACCESS)
+        if (codec->hw_write(codec->control_data, data, 2) != 2)
+                ret = -EIO;
+#else
+        ret = snd_soc_write(codec, data[AIC3262_REG_OFFSET_INDEX],
+                        data[AIC3262_REG_DATA_INDEX]);
+#endif
+        if (ret)
+                printk(KERN_ERR "Error in i2c write\n");
+
+        return ret;
+}
+
+/*
+ *------------------------------------------------------------------------------
+ * Function : aic3262_write__
+ * Purpose  : This function is to write to the aic3262 register space.
+ *            (low level).
+ *------------------------------------------------------------------------------
+ */
+
+int aic3262_write__(struct i2c_client *client, const char *buf, int count)
+{
+        u8 data[3];
+        int ret;
+        data[0] = *buf;
+        data[1] = *(buf+1);
+        data[2] = *(buf+2);
+        /*DBG("w %2x %02x\r\n",
+                data[AIC3262_REG_OFFSET_INDEX], data[AIC3262_REG_DATA_INDEX]);*/
+        ret = i2c_master_send(client, data, 2);
+        if (ret < 2) {
+                printk(
+                KERN_ERR "I2C write Error : bytes written = %d\n\n", ret);
+                return -EIO;
+        }
+
+        return ret;
+}
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_reset_cache
+ * Purpose  : This function is to reset the cache.
+ *----------------------------------------------------------------------------
+ */
+int aic3262_reset_cache(struct snd_soc_codec *codec)
+{
+#if defined(EN_REG_CACHE)
+        if (codec->reg_cache) {
+                memcpy(codec->reg_cache, aic3262_reg, sizeof(aic3262_reg));
+                return 0;
+        }
+
+        codec->reg_cache = kmemdup(aic3262_reg,
+                        sizeof(aic3262_reg), GFP_KERNEL);
+        if (!codec->reg_cache) {
+                printk(KERN_ERR "aic32x4: kmemdup failed\n");
+                return -ENOMEM;
+        }
+#endif
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_get_divs
+ * Purpose  : This function is to get required divisor from the "aic3262_divs"
+ *            table.
+ *
+ *----------------------------------------------------------------------------
+ */
+static inline int aic3262_get_divs(int mclk, int rate)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(aic3262_divs); i++) {
+                if ((aic3262_divs[i].rate == rate)
+                    && (aic3262_divs[i].mclk == mclk)) {
+                        DBG(KERN_INFO "#%s: Found Entry %d in Clock_Array\n",
+                                __func__, i);
+                        return i;
+                }
+        }
+        printk(KERN_ERR "Master clock and sample rate is not supported\n");
+        return -EINVAL;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_add_widgets
+ * Purpose  : This function is to add the dapm widgets
+ *            The following are the main widgets supported
+ *                # Left DAC to Left Outputs
+ *                # Right DAC to Right Outputs
+ *                # Left Inputs to Left ADC
+ *                # Right Inputs to Right ADC
+ *
+ *----------------------------------------------------------------------------
+ */
+static int aic3262_add_widgets(struct snd_soc_codec *codec)
+{
+        int ret;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+#ifndef AIC3262_MULTI_I2S
+        int i;
+        for (i = 0; i < ARRAY_SIZE(aic3262_dapm_widgets); i++)
+                ret = snd_soc_dapm_new_control(dapm, &aic3262_dapm_widgets[i]);
+#else
+        ret = snd_soc_dapm_new_controls(dapm, aic3262_dapm_widgets,
+                        ARRAY_SIZE(aic3262_dapm_widgets));
+        if (ret != 0) {
+                printk(KERN_ERR "#%s: Unable to add DAPM Controls. Err %d\n",
+                                 __func__, ret);
+        }
+#endif
+        /* set up audio path interconnects */
+        DBG("#Completed adding new dapm widget controls size=%d\n",
+                ARRAY_SIZE(aic3262_dapm_widgets));
+        snd_soc_dapm_add_routes(dapm, aic3262_dapm_routes,
+                                ARRAY_SIZE(aic3262_dapm_routes));
+        DBG("#Completed adding DAPM routes\n");
+        snd_soc_dapm_new_widgets(dapm);
+        DBG("#Completed updating dapm\n");
+        return 0;
+}
+/*
+ *----------------------------------------------------------------------------
+ * Function : reg_def_conf
+ * Purpose  : This function is to reset the codec book 0 registers
+ *
+ *----------------------------------------------------------------------------
+ */
+int reg_def_conf(struct snd_soc_codec *codec)
+{
+        int i = 0, ret;
+        DBG(KERN_INFO "#%s: Invoked..\n", __func__);
+
+        ret = aic3262_change_page(codec, 0);
+        if (ret != 0)
+                return ret;
+
+        ret = aic3262_change_book(codec, 0);
+        if (ret != 0)
+                return ret;
+
+        /* Configure the Codec with the default Initialization Values */
+        for (i = 0; i < reg_init_size; i++) {
+                ret = snd_soc_write(codec, aic3262_reg_init[i].reg_offset,
+                        aic3262_reg_init[i].reg_val);
+                if (ret)
+                        break;
+        }
+        DBG(KERN_INFO "#%s: Done..\n", __func__);
+        return ret;
+}
+
+/*
+ * i2c_verify_book0
+ *
+ * This function is used to dump the values of the Book 0 Pages.
+ */
+int i2c_verify_book0(struct snd_soc_codec *codec)
+{
+        int i, j, k = 0;
+        u8 val1;
+
+        DBG("starting i2c_verify\n");
+        DBG("Resetting page to 0\n");
+        aic3262_change_book(codec, 0);
+        for (j = 0; j < 3; j++) {
+                if (j == 0) {
+                        aic3262_change_page(codec, 0);
+                        k = 0;
+                }
+                if (j == 1) {
+                        aic3262_change_page(codec, 1);
+                        k = 1;
+                }
+                /*
+                if (j == 2) {
+                        aic3262_change_page(codec, 4);
+                        k = 4;
+                }*/
+                for (i = 0; i <= 127; i++) {
+#if defined(LOCAL_REG_ACCESS)
+                        val1 = i2c_smbus_read_byte_data(codec->control_data, i);
+#else
+                        val1 = snd_soc_read(codec, i);
+#endif
+                        /* printk("[%d][%d]=[0x%2x]\n",k,i,val1); */
+                }
+        }
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_set_bias_level
+ * Purpose  : This function is to get triggered when dapm events occurs.
+ *
+ *----------------------------------------------------------------------------
+ */
+
+static int aic3262_set_bias_level(struct snd_soc_codec *codec,
+                        enum snd_soc_bias_level level)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 value;
+        switch (level) {
+                /* full On */
+        case SND_SOC_BIAS_ON:
+
+                /* all power is driven by DAPM system */
+                dev_dbg(codec->dev, "set_bias_on\n");
+                break;
+
+                /* partial On */
+        case SND_SOC_BIAS_PREPARE:
+
+                dev_dbg(codec->dev, "set_bias_prepare\n");
+
+                break;
+
+        /* Off, with power */
+        case SND_SOC_BIAS_STANDBY:
+                /*
+                 * all power is driven by DAPM system,
+                 * so output power is safe if bypass was set
+                 */
+                 dev_dbg(codec->dev, "set_bias_stby\n");
+
+                break;
+        /* Off, without power */
+        case SND_SOC_BIAS_OFF:
+                 dev_dbg(codec->dev, "set_bias_off\n");
+
+                break;
+        }
+        codec->dapm.bias_level=level;
+
+        return 0;
+}
+
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_suspend
+ * Purpose  : This function is to suspend the AIC3262 driver.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int aic3262_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        DBG(KERN_INFO "#%s: Invoked..\n", __func__);
+        if (aic3262)
+                disable_irq(aic3262->irq);
+
+        aic3262_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_resume
+ * Purpose  : This function is to resume the AIC3262 driver
+ *
+ *----------------------------------------------------------------------------
+ */
+static int aic3262_resume(struct snd_soc_codec *codec)
+{
+        int i;
+        u8 data[2];
+        int ret = 0;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u8 *cache = codec->reg_cache;
+        DBG(KERN_INFO "#%s: Invoked..\n", __func__);
+
+        ret = aic3262_change_page(codec, 0);
+        if (ret)
+                return ret;
+#if defined(EN_REG_CACHE)
+        /* Sync reg_cache with the hardware */
+        for (i = 0; i < ARRAY_SIZE(aic3262_reg); i++) {
+                data[0] = i % 128;
+                data[1] = cache[i];
+#if defined(LOCAL_REG_ACCESS)
+                codec->hw_write(codec->control_data, data, 2);
+#else
+                ret = snd_soc_write(codec, data[0], data[1]);
+                if (ret)
+                        break;
+#endif
+        }
+#endif
+        if (!ret) {
+                aic3262_change_page(codec, 0);
+                aic3262_set_bias_level(codec, SND_SOC_BIAS_ON);
+
+                if (aic3262)
+                        enable_irq(aic3262->irq);
+        }
+        return ret;
+}
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_hw_read
+ * Purpose  : This is a low level harware read function.
+ *
+ *----------------------------------------------------------------------------
+ */
+unsigned int aic3262_hw_read(struct snd_soc_codec *codec, unsigned int count)
+{
+        struct i2c_client *client = codec->control_data;
+        unsigned int buf;
+
+        if (count > (sizeof(unsigned int)))
+                return 0;
+
+        i2c_master_recv(client, (char *)&buf, count);
+        return buf;
+}
+
+/*
+* aic3262_jack_handler
+*
+* This function is called from the Interrupt Handler
+* to check the status of the AIC3262 Registers related to Headset Detection
+*/
+static irqreturn_t aic3262_jack_handler(int irq, void *data)
+{
+        struct snd_soc_codec *codec = data;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        unsigned int value;
+        unsigned int micbits, hsbits = 0;
+        DBG(KERN_INFO "%s++\n", __func__);
+
+        aic3262_change_page(codec, 0);
+
+        /* Read the Jack Status Register*/
+        value = snd_soc_read(codec, STICKY_FLAG2);
+        DBG(KERN_INFO "reg44 0x%x\n", value);
+
+
+        value = snd_soc_read(codec, INT_FLAG2);
+        DBG(KERN_INFO "reg46 0x%x\n", value);
+
+        value = snd_soc_read(codec, DAC_FLAG_R1);
+        DBG(KERN_INFO "reg37 0x%x\n", value);
+
+        micbits = value & DAC_FLAG_MIC_MASKBITS;
+        DBG(KERN_INFO "micbits 0x%x\n", micbits);
+
+        hsbits = value & DAC_FLAG_HS_MASKBITS;
+        DBG(KERN_INFO "hsbits 0x%x\n", hsbits);
+
+
+        /* No Headphone or Headset*/
+        if (!micbits && !hsbits) {
+                DBG(KERN_INFO "no headset/headphone\n");
+                snd_soc_jack_report(aic3262->headset_jack,
+                                0, SND_JACK_HEADSET);
+        }
+
+        /* Headphone Detected */
+        if ((micbits == DAC_FLAG_R1_NOMIC) || (hsbits)) {
+                DBG(KERN_INFO "headphone\n");
+                snd_soc_jack_report(aic3262->headset_jack,
+                                SND_JACK_HEADPHONE, SND_JACK_HEADSET);
+        }
+
+        /* Headset Detected - only with capless */
+        if (micbits == DAC_FLAG_R1_MIC) {
+                DBG(KERN_INFO "headset\n");
+                snd_soc_jack_report(aic3262->headset_jack,
+                                SND_JACK_HEADSET, SND_JACK_HEADSET);
+        }
+        DBG(KERN_INFO "%s--\n", __func__);
+        return IRQ_HANDLED;
+}
+
+/*
+* aic326x_headset_detect
+*
+* Call-back function called to check the status of Headset Pin.
+*/
+int aic326x_headset_detect(struct snd_soc_codec *codec,
+        struct snd_soc_jack *jack, int jack_type)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        aic3262->headset_jack = jack;
+        /*Enable the Headset Interrupts*/
+        snd_soc_write(codec, INT1_CNTL, 0x80);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(aic326x_headset_detect);
+
+int aic326x_headset_button_init(struct snd_soc_codec *codec,
+        struct snd_soc_jack *jack, int jack_type)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        aic3262->button_dev = input_allocate_device();
+        aic3262->button_dev->name = "aic326x_headset_button";
+       aic3262->button_dev->phys = "codec/input0";
+        aic3262->button_dev->dev.parent = snd_card_get_device_link(codec->card->snd_card);
+        input_set_capability(aic3262->button_dev, EV_KEY, KEY_MEDIA);
+
+        if (input_register_device(aic3262->button_dev))
+        {
+           printk( "Unable to register input device headset button");
+        }
+
+        aic3262_jack_handler(aic3262->irq, codec);
+        return 0;
+}
+#ifdef AIC3262_MULTI_I2S
+/*
+* aic3262_asi_default_config
+*
+* This function is used to perform the default pin configurations for
+* the functionalities which are specific to each ASI Port of the AIC3262
+* Audio Codec Chipset. The user is encouraged to change these values
+* if required on their platforms.
+*/
+static void aic3262_asi_default_config(struct snd_soc_codec *codec)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u16 counter;
+
+        DBG(KERN_INFO
+                "#%s: Invoked. Will Config ASI Registers to Defaults..\n",
+                        __func__);
+        for (counter = 0; counter < MAX_ASI_COUNT; counter++) {
+                aic3262->asiCtxt[counter].asi_active = 0;
+                aic3262->asiCtxt[counter].bclk_div = 1;
+                aic3262->asiCtxt[counter].wclk_div = 1;
+                aic3262->asiCtxt[counter].port_muted = 1;
+                aic3262->asiCtxt[counter].bclk_div_option =
+                        BDIV_CLKIN_DAC_MOD_CLK;
+                aic3262->asiCtxt[counter].offset1 = 0;
+                aic3262->asiCtxt[counter].offset2 = 0;
+        }
+        /* ASI1 Defaults */
+        aic3262->asiCtxt[0].bclk_output = ASI1_BCLK_DIVIDER_OUTPUT;
+        aic3262->asiCtxt[0].wclk_output = GENERATED_DAC_FS;
+        aic3262->asiCtxt[0].left_dac_output  = DAC_PATH_LEFT;
+        aic3262->asiCtxt[0].right_dac_output = DAC_PATH_LEFT;
+        aic3262->asiCtxt[0].adc_input        = ADC_PATH_MINIDSP_1;
+        aic3262->asiCtxt[0].dout_option      = ASI_OUTPUT;
+
+        /* ASI2 Defaults */
+        aic3262->asiCtxt[1].bclk_output = ASI2_BCLK_DIVIDER_OUTPUT;
+        aic3262->asiCtxt[1].wclk_output = GENERATED_DAC_FS;
+        aic3262->asiCtxt[1].left_dac_output  = DAC_PATH_LEFT;
+        aic3262->asiCtxt[1].right_dac_output = DAC_PATH_LEFT;
+        aic3262->asiCtxt[1].adc_input        = ADC_PATH_MINIDSP_2;
+        aic3262->asiCtxt[1].dout_option      = ASI_OUTPUT;
+
+        /* ASI3 Defaults */
+        aic3262->asiCtxt[2].bclk_output = ASI3_BCLK_DIVIDER_OUTPUT;
+        aic3262->asiCtxt[2].wclk_output = GENERATED_DAC_FS;
+        aic3262->asiCtxt[2].left_dac_output  = DAC_PATH_LEFT;
+        aic3262->asiCtxt[2].right_dac_output = DAC_PATH_LEFT;
+        aic3262->asiCtxt[2].adc_input        = ADC_PATH_MINIDSP_3;
+        aic3262->asiCtxt[2].dout_option      = ASI2_INPUT;
+        return;
+}
+
+#endif /* #ifdef AIC3262_MULTI_I2S */
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_probe
+ * Purpose  : This is first driver function called by the SoC core driver.
+ *
+ *----------------------------------------------------------------------------
+ */
+
+static int aic3262_probe(struct snd_soc_codec *codec)
+{
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        int ret = 0;
+
+        DBG(KERN_INFO "#%s: Invoked..\n", __func__);
+
+#if defined(EN_REG_CACHE)
+        codec->reg_cache =
+                kmemdup(aic3262_reg, sizeof(aic3262_reg), GFP_KERNEL);
+
+        if (!codec->reg_cache) {
+                printk(KERN_ERR "aic3262: kmemdup failed\n");
+                return -ENOMEM;
+        }
+#else
+        /* Setting cache bypass - not to overwrite the cache registers,
+        Codec registers have 4 pages which is not handled in the common
+        cache code properly - bypass it in write value and save it
+        using separate call*/
+        codec->cache_bypass = 1;
+#endif
+
+#if defined(LOCAL_REG_ACCESS)
+        codec->control_data = aic3262->control_data;
+        codec->hw_write = (hw_write_t) aic3262_write__;
+        codec->hw_read = aic3262_hw_read;
+#else
+        ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+                return ret;
+        }
+#endif
+        ret = reg_def_conf(codec);
+        if (ret != 0) {
+                printk(KERN_ERR "Failed to init TI codec: %d\n", ret);
+                return ret;
+        }
+
+        if (aic3262->irq) {
+                /* audio interrupt */
+                ret = request_threaded_irq(aic3262->irq, NULL,
+                                aic3262_jack_handler,
+                                IRQF_TRIGGER_FALLING,
+                                "tlv320aic3262", codec);
+                if (ret) {
+                        printk(KERN_INFO "#%s: IRQ Registration failed..[%d]",
+                                        __func__, ret);
+                        dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
+                        return ret;
+                } else
+                        DBG(KERN_INFO
+                                "#%s: irq Registration for IRQ %d done..\n",
+                                        __func__, aic3262->irq);
+        } else {
+                DBG(KERN_INFO "#%s: I2C IRQ Configuration is Wrong. \
+                        Please check it..\n", __func__);
+        }
+
+        aic3262_asi_default_config(codec);
+
+        /* off, with power on */
+        aic3262_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+        ret = snd_soc_add_controls(codec, aic3262_snd_controls,
+                                        ARRAY_SIZE(aic3262_snd_controls));
+        if(ret)
+        {
+                printk(KERN_INFO "%s failed\n", __func__);
+        }
+
+        aic3262_add_widgets(codec);
+        /*TODO*/
+        snd_soc_write(codec, MIC_BIAS_CNTL, 0x66);
+
+#ifdef AIC3262_TiLoad
+        ret = aic3262_driver_init(codec);
+        if (ret < 0)
+                printk(KERN_ERR
+        "\nAIC3262 CODEC: aic3262_probe :TiLoad Initialization failed\n");
+#endif
+
+
+#ifdef CONFIG_MINI_DSP
+        /* Program MINI DSP for ADC and DAC */
+        aic3262_minidsp_program(codec);
+        aic3262_add_minidsp_controls(codec);
+        aic3262_change_book(codec, 0x0);
+#endif
+
+#ifdef MULTIBYTE_CONFIG_SUPPORT
+        aic3262_add_multiconfig_controls(codec);
+#endif
+
+        DBG(KERN_INFO "#%s: done..\n", __func__);
+        return ret;
+}
+
+
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_remove
+ * Purpose  : to remove aic3262 soc device
+ *
+ *----------------------------------------------------------------------------
+ */
+static int aic3262_remove(struct snd_soc_codec *codec)
+{
+
+        /* power down chip */
+        aic3262_set_bias_level(codec, SND_SOC_BIAS_OFF);
+
+        return 0;
+}
+
+
+/*
+ *----------------------------------------------------------------------------
+ * @struct  snd_soc_codec_device |
+ *          This structure is soc audio codec device sturecute which pointer
+ *          to basic functions aic3262_probe(), aic3262_remove(),
+ *          aic3262_suspend() and aic3262_resume()
+ *----------------------------------------------------------------------------
+ */
+static struct snd_soc_codec_driver soc_codec_dev_aic3262 = {
+        .probe = aic3262_probe,
+        .remove = aic3262_remove,
+        .suspend = aic3262_suspend,
+        .resume = aic3262_resume,
+        .set_bias_level = aic3262_set_bias_level,
+#if defined(LOCAL_REG_ACCESS)
+        .read = aic3262_read,
+        .write = aic3262_write,
+#endif
+#if !defined(EN_REG_CACHE)
+        .reg_cache_size = ARRAY_SIZE(aic3262_reg),
+        .reg_word_size = sizeof(u8),
+        .reg_cache_default = aic3262_reg,
+#endif
+};
+
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_codec_probe
+ * Purpose  : This function attaches the i2c client and initializes
+ *                              AIC3262 CODEC.
+ *            NOTE:
+ *            This function is called from i2c core when the I2C address is
+ *            valid.
+ *            If the i2c layer weren't so broken, we could pass this kind of
+ *            data around
+ *
+ *----------------------------------------------------------------------------
+ */
+static __devinit int aic3262_codec_probe(struct i2c_client *i2c,
+                        const struct i2c_device_id *id)
+{
+        int ret;
+
+        struct aic3262_priv *aic3262;
+
+        DBG(KERN_INFO "#%s: Entered\n", __func__);
+
+        aic3262 = kzalloc(sizeof(struct aic3262_priv), GFP_KERNEL);
+
+        if (!aic3262) {
+                printk(KERN_ERR "#%s: Unable to Allocate Priv struct..\n",
+                        __func__);
+                return -ENOMEM;
+        }
+
+        i2c_set_clientdata(i2c, aic3262);
+#if defined(LOCAL_REG_ACCESS)
+        aic3262->control_data = i2c;
+#endif
+        aic3262->control_type = SND_SOC_I2C;
+        aic3262->irq = i2c->irq;
+        aic3262->pdata = i2c->dev.platform_data;
+
+        /* The Configuration Support will be by default to 3 which
+        * holds the MAIN Patch Configuration.
+        */
+        aic3262->current_dac_config[0] = -1;
+        aic3262->current_dac_config[1] = -1;
+        aic3262->current_adc_config[0] = -1;
+        aic3262->current_adc_config[1] = -1;
+
+        aic3262->mute_codec = 1;
+
+        aic3262->page_no = 0;
+        aic3262->book_no = 0;
+        aic3262->active_count = 0;
+        aic3262->dac_clkin_option = 3;
+        aic3262->adc_clkin_option = 3;
+
+        ret = snd_soc_register_codec(&i2c->dev,
+                &soc_codec_dev_aic3262,
+                tlv320aic3262_dai, ARRAY_SIZE(tlv320aic3262_dai));
+
+        if (ret < 0)
+                kfree(aic3262);
+        DBG(KERN_INFO "#%s: Done ret %d\n", __func__, ret);
+        return ret;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_i2c_remove
+ * Purpose  : This function removes the i2c client and uninitializes
+ *                              AIC3262 CODEC.
+ *            NOTE:
+ *            This function is called from i2c core
+ *            If the i2c layer weren't so broken, we could pass this kind of
+ *            data around
+ *
+ *----------------------------------------------------------------------------
+ */
+static __devexit int aic3262_i2c_remove(struct i2c_client *i2c)
+{
+        snd_soc_unregister_codec(&i2c->dev);
+        kfree(i2c_get_clientdata(i2c));
+        return 0;
+}
+
+static const struct i2c_device_id tlv320aic3262_id[] = {
+        {"aic3262-codec", 0},
+        {}
+};
+MODULE_DEVICE_TABLE(i2c, tlv320aic3262_id);
+
+static struct i2c_driver tlv320aic3262_i2c_driver = {
+        .driver = {
+                .name = "aic3262-codec",
+                .owner = THIS_MODULE,
+        },
+        .probe = aic3262_codec_probe,
+        .remove = __devexit_p(aic3262_i2c_remove),
+        .id_table = tlv320aic3262_id,
+};
+#endif /*#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)*/
+
+#if defined(CONFIG_SPI_MASTER)
+static int aic3262_spi_write(struct spi_device *spi, const char *data, int len)
+{
+        struct spi_transfer t;
+        struct spi_message m;
+        u8 msg[2];
+
+        if (len <= 0)
+                return 0;
+
+        msg[0] = data[0];
+        msg[1] = data[1];
+
+        spi_message_init(&m);
+        memset(&t, 0, (sizeof t));
+        t.tx_buf = &msg[0];
+        t.len = len;
+
+        spi_message_add_tail(&t, &m);
+        spi_sync(spi, &m);
+
+        return len;
+}
+
+/*
+ * This function forces any delayed work to be queued and run.
+ */
+static int run_delayed_work(struct delayed_work *dwork)
+{
+        int ret;
+
+        /* cancel any work waiting to be queued. */
+        ret = cancel_delayed_work(dwork);
+
+        /* if there was any work waiting then we run it now and
+         * wait for it's completion */
+        if (ret) {
+                schedule_delayed_work(dwork, 0);
+                flush_scheduled_work();
+        }
+        return ret;
+}
+static int __devinit aic3262_spi_probe(struct spi_device *spi)
+{
+        int ret;
+        struct snd_soc_codec *codec;
+        struct aic3262_priv *aic3262;
+        printk(KERN_INFO "%s entering\n",__func__);
+        aic3262 = kzalloc(sizeof(struct aic3262_priv), GFP_KERNEL);
+
+        if (!aic3262) {
+                printk(KERN_ERR "#%s: Unable to Allocate Priv struct..\n",
+                        __func__);
+                return -ENOMEM;
+        }
+        codec = &aic3262->codec;
+        codec->control_data = spi;
+        aic3262->control_type = SND_SOC_SPI;
+        codec->hw_write = (hw_write_t)aic3262_spi_write;
+        codec->dev = &spi->dev;
+
+        aic3262->pdata = spi->dev.platform_data;
+
+        /* The Configuration Support will be by default to 3 which
+        * holds the MAIN Patch Configuration.
+        */
+        aic3262->current_dac_config[0] = -1;
+        aic3262->current_dac_config[1] = -1;
+        aic3262->current_adc_config[0] = -1;
+        aic3262->current_adc_config[1] = -1;
+
+        aic3262->mute_codec = 1;
+
+        aic3262->page_no = 0;
+        aic3262->book_no = 0;
+        aic3262->active_count = 0;
+        aic3262->dac_clkin_option = 3;
+        aic3262->adc_clkin_option = 3;
+        dev_set_drvdata(&spi->dev, aic3262);
+        spi_set_drvdata(spi, aic3262);
+        ret = snd_soc_register_codec(&spi->dev,
+                &soc_codec_dev_aic3262,
+                tlv320aic3262_dai, ARRAY_SIZE(tlv320aic3262_dai));
+
+        if (ret < 0) {
+                printk(KERN_INFO "%s codec registeration failed\n",__func__);
+                kfree(aic3262);
+        }
+        else {
+                printk(KERN_INFO "%s registered\n",__func__);
+        }
+        printk(KERN_INFO "#%s: Done ret %d\n", __func__, ret);
+        return ret;
+}
+
+static int __devexit aic3262_spi_remove(struct spi_device *spi)
+{
+        struct aic3262_priv *aic3262 = dev_get_drvdata(&spi->dev);
+        aic3262_set_bias_level(&aic3262->codec, SND_SOC_BIAS_OFF);
+        snd_soc_unregister_codec(&spi->dev);
+        kfree(aic3262);
+        aic3262_codec = NULL;
+        return 0;
+
+}
+
+static struct spi_driver aic3262_spi_driver = {
+        .driver = {
+                .name   = "aic3262-codec",
+                .bus    = &spi_bus_type,
+                .owner  = THIS_MODULE,
+        },
+        .probe          = aic3262_spi_probe,
+        .remove         = __devexit_p(aic3262_spi_remove),
+};
+#endif
+static int __init tlv320aic3262_modinit(void)
+{
+        int ret = 0;
+        printk(KERN_INFO "In %s\n",__func__);
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        ret = i2c_add_driver(&tlv320aic3262_i2c_driver);
+        if (ret != 0)
+                printk(KERN_ERR "Failed to register aic326x i2c driver %d\n",
+                        ret);
+#endif
+#if defined(CONFIG_SPI_MASTER)
+        printk(KERN_INFO "Inside config_spi_master\n");
+        ret = spi_register_driver(&aic3262_spi_driver);
+        if (ret != 0)
+                printk(KERN_ERR "Failed to register aic3262 SPI driver: %d\n", ret);
+#endif
+        return ret;
+
+}
+
+module_init(tlv320aic3262_modinit);
+
+static void __exit tlv320aic3262_exit(void)
+{
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+        i2c_del_driver(&tlv320aic3262_i2c_driver);
+#endif
+}
+module_exit(tlv320aic3262_exit);
+
+MODULE_DESCRIPTION("ASoC TLV320AIC3262 codec driver");
+MODULE_AUTHOR("Barani Prashanth<gvbarani@mistralsolutions.com>");
+MODULE_AUTHOR("Ravindra<ravindra@mistralsolutions.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/tlv320aic326x.h b/sound/soc/codecs/tlv320aic326x.h
new file mode 100644
index 00000000000..a31cc9eca5c
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x.h
@@ -0,0 +1,684 @@
+/*
+ * linux/sound/soc/codecs/tlv320aic3262.h
+ *
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * History:
+ *  Rev 0.1   ASoC driver support          20-01-2011
+ *
+ * The AIC3262 ASoC driver is ported for the codec AIC3262.
+ *
+ */
+
+#ifndef _TLV320AIC3262_H
+#define _TLV320AIC3262_H
+#include <linux/input.h>
+#define AUDIO_NAME "aic3262"
+#define AIC3262_VERSION "1.1"
+
+//#define AIC3262_ASI2_MASTER 1
+
+/* Enable this macro allow for different ASI formats */
+/*#define ASI_MULTI_FMT*/
+#undef ASI_MULTI_FMT
+
+#define  INT_FLAG2_BUTTN_PRESSBIT 0x20
+
+/* Enable register caching on write */
+#define EN_REG_CACHE 1
+
+#define MULTIBYTE_CONFIG_SUPPORT
+
+/*Setting all codec reg/write locally*/
+/* This definition is added as the snd_ direct call are
+result some issue with cache. Common code doesnot support
+page, so fix that before commenting this line*/
+#define LOCAL_REG_ACCESS 1
+
+/* Macro to enable the inclusion of tiload kernel driver */
+#define AIC3262_TiLoad
+
+
+/* Macro enables or disables support for miniDSP in the driver */
+/* Enable the AIC3262_TiLoad macro first before enabling these macros */
+#define CONFIG_MINI_DSP
+/*#undef CONFIG_MINI_DSP*/
+
+/* Enable or disable controls to have Input routing*/
+/*#define FULL_IN_CNTL */
+#undef FULL_IN_CNTL
+/* AIC3262 supported sample rate are 8k to 192k */
+#define AIC3262_RATES   SNDRV_PCM_RATE_8000_192000
+
+/* AIC3262 supports the word formats 16bits, 20bits, 24bits and 32 bits */
+#define AIC3262_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
+                         | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+#define AIC3262_FREQ_12000000 12000000
+#define AIC3262_FREQ_12288000 12288000
+#define AIC3262_FREQ_24000000 24000000
+
+/* Macro for enabling the Multi_I2S Support in Driver */
+#define AIC3262_MULTI_I2S       1
+
+/* Driver Debug Messages Enabled */
+//#define DEBUG
+
+#ifdef DEBUG
+        #define DBG(x...)       printk(x)
+#else
+        #define DBG(x...)
+#endif
+
+/*Select the below macro to decide on the DAC master volume controls.
+ *2 independent or one combined
+ */
+/*#define DAC_INDEPENDENT_VOL*/
+#undef DAC_INDEPENDENT_VOL
+
+/* Audio data word length = 16-bits (default setting) */
+#define AIC3262_WORD_LEN_16BITS         0x00
+#define AIC3262_WORD_LEN_20BITS         0x01
+#define AIC3262_WORD_LEN_24BITS         0x02
+#define AIC3262_WORD_LEN_32BITS         0x03
+
+/* sink: name of target widget */
+#define AIC3262_WIDGET_NAME     0
+/* control: mixer control name */
+#define AIC3262_CONTROL_NAME
+/* source: name of source name */
+#define AIC3262_SOURCE_NAME     2
+
+/* D15..D8 aic3262 register offset */
+#define AIC3262_REG_OFFSET_INDEX    0
+/* D7...D0 register data */
+#define AIC3262_REG_DATA_INDEX      1
+
+/* Serial data bus uses I2S mode (Default mode) */
+#define AIC3262_I2S_MODE                0x00
+#define AIC3262_DSP_MODE                0x01
+#define AIC3262_RIGHT_JUSTIFIED_MODE    0x02
+#define AIC3262_LEFT_JUSTIFIED_MODE     0x03
+
+/* 8 bit mask value */
+#define AIC3262_8BITS_MASK           0xFF
+
+/* shift value for CLK_REG_3 register */
+#define CLK_REG_3_SHIFT                 6
+/* shift value for DAC_OSR_MSB register */
+#define DAC_OSR_MSB_SHIFT               4
+
+/* number of codec specific register for configuration */
+#define NO_FEATURE_REGS                 2
+
+/* Total number of ASI Ports */
+#define MAX_ASI_COUNT                   3
+
+
+/* AIC3262 register space */
+/* Updated from 256 to support Page 3 registers */
+#define AIC3262_CACHEREGNUM             1024
+#define BIT7             (0x01 << 7)
+#define BIT6             (0x01 << 6)
+#define BIT5             (0x01 << 5)
+#define BIT4             (0x01 << 4)
+#define BIT3             (0x01 << 3)
+#define BIT2             (0x01 << 2)
+#define BIT1             (0x01 << 1)
+#define BIT0             (0x01 << 0)
+
+#define DAC_FLAG_MIC_MASKBITS   0x30
+#define DAC_FLAG_HS_MASKBITS    0x03
+#define DAC_FLAG_R1_NOJACK      0
+#define DAC_FLAG_R1_NOMIC       (0x1 << 4)
+#define DAC_FLAG_R1_MIC         (0x3 << 4)
+#define DAC_FLAG_R1_NOHS        0
+#define DAC_FLAG_R1_MONOHS      1
+#define DAC_FLAG_R1_STEREOHS    2
+
+/*mask patterns for DAC and ADC polling logic*/
+#define LDAC_POW_FLAG_MASK      0x80
+#define RDAC_POW_FLAG_MASK      0x08
+#define LADC_POW_FLAG_MASK      0x40
+#define RADC_POW_FLAG_MASK      0x04
+
+/* ****************** Book 0 Registers **************************************/
+
+/* ****************** Page 0 Registers **************************************/
+
+#define PAGE_SEL_REG            0
+#define RESET_REG               1
+#define DAC_ADC_CLKIN_REG       4
+#define PLL_CLKIN_REG           5
+#define PLL_CLK_RANGE_REG       5
+#define PLL_PR_POW_REG          6
+#define PLL_J_REG               7
+#define PLL_D_MSB               8
+#define PLL_D_LSB               9
+#define PLL_CKIN_DIV            10
+
+#define NDAC_DIV_POW_REG        11
+#define MDAC_DIV_POW_REG        12
+#define DOSR_MSB_REG            13
+#define DOSR_LSB_REG            14
+
+#define NADC_DIV_POW_REG        18
+#define MADC_DIV_POW_REG        19
+#define AOSR_REG                20
+#define CLKOUT_MUX              21
+#define CLKOUT_MDIV_VAL         22
+#define TIMER_REG               23
+
+#define LF_CLK_CNTL             24
+#define HF_CLK_CNTL_R1          25
+#define HF_CLK_CNTL_R2          26
+#define HF_CLK_CNTL_R3          27
+#define HF_CLK_CNTL_R4          28
+#define HF_CLK_TRIM_R1          29
+#define HF_CLK_TRIM_R2          30
+#define HF_CLK_TRIM_R3          31
+#define HF_CLK_TRIM_R4          32
+#define ADC_FLAG_R1             36
+#define DAC_FLAG_R1             37
+#define DAC_FLAG_R2             38
+
+#define STICKY_FLAG1            42
+#define INT_FLAG1               43
+#define STICKY_FLAG2            44
+#define STICKY_FLAG3            45
+#define INT_FLAG2               46
+#define INT1_CNTL               48
+#define INT2_CNTL               49
+#define INT_FMT                 51
+
+#define DAC_PRB                 60
+#define ADC_PRB                 61
+#define PASI_DAC_DP_SETUP       63
+#define DAC_MVOL_CONF           64
+#define DAC_LVOL                65
+#define DAC_RVOL                66
+#define HP_DETECT               67
+#define DRC_CNTL_R1             68
+#define DRC_CNTL_R2             69
+#define DRC_CNTL_R3             70
+#define BEEP_CNTL_R1            71
+#define BEEP_CNTL_R2            72
+
+#define ADC_CHANNEL_POW         81
+#define ADC_FINE_GAIN           82
+#define LADC_VOL                83
+#define RADC_VOL                84
+#define ADC_PHASE               85
+
+#define LAGC_CNTL               86
+#define LAGC_CNTL_R2            87
+#define LAGC_CNTL_R3            88
+#define LAGC_CNTL_R4            89
+#define LAGC_CNTL_R5            90
+#define LAGC_CNTL_R6            91
+#define LAGC_CNTL_R7            92
+#define LAGC_CNTL_R8            93
+
+#define RAGC_CNTL               94
+#define RAGC_CNTL_R2            95
+#define RAGC_CNTL_R3            96
+#define RAGC_CNTL_R4            97
+#define RAGC_CNTL_R5            98
+#define RAGC_CNTL_R6            99
+#define RAGC_CNTL_R7            100
+#define RAGC_CNTL_R8            101
+#define MINIDSP_ACCESS_CTRL     121
+/* ****************** Page 1 Registers **************************************/
+#define PAGE_1                  128
+
+#define POWER_CONF              (PAGE_1 + 1)
+#define LDAC_PTM                (PAGE_1 + 3)
+#define RDAC_PTM                (PAGE_1 + 4)
+#define CM_REG                  (PAGE_1 + 8)
+#define HP_CTL                  (PAGE_1 + 9)
+#define HP_DEPOP                (PAGE_1 + 11)
+#define RECV_DEPOP              (PAGE_1 + 12)
+#define MA_CNTL                 (PAGE_1 + 17)
+#define LADC_PGA_MAL_VOL        (PAGE_1 + 18)
+#define RADC_PGA_MAR_VOL        (PAGE_1 + 19)
+
+
+#define LINE_AMP_CNTL_R1        (PAGE_1 + 22)
+#define LINE_AMP_CNTL_R2        (PAGE_1 + 23)
+
+#define HP_AMP_CNTL_R1          (PAGE_1 + 27)
+#define HP_AMP_CNTL_R2          (PAGE_1 + 28)
+#define HP_AMP_CNTL_R3          (PAGE_1 + 29)
+
+#define HPL_VOL                 (PAGE_1 + 31)
+#define HPR_VOL                 (PAGE_1 + 32)
+#define INT1_SEL_L              (PAGE_1 + 34)
+#define RAMP_CNTL_R1            (PAGE_1 + 36)
+#define RAMP_CNTL_R2            (PAGE_1 + 37)
+//#define INT1_SEL_RM           (PAGE_1 + 39)
+#define IN1L_SEL_RM             (PAGE_1 + 39)
+#define IN1R_SEL_RM             (PAGE_1 + 39)
+
+#define REC_AMP_CNTL_R5         (PAGE_1 + 40)
+#define RAMPR_VOL               (PAGE_1 + 41)
+#define RAMP_TIME_CNTL          (PAGE_1 + 42)
+#define SPK_AMP_CNTL_R1         (PAGE_1 + 45)
+#define SPK_AMP_CNTL_R2         (PAGE_1 + 46)
+#define SPK_AMP_CNTL_R3         (PAGE_1 + 47)
+#define SPK_AMP_CNTL_R4         (PAGE_1 + 48)
+#define MIC_BIAS_CNTL           (PAGE_1 + 51)
+
+#define LMIC_PGA_PIN            (PAGE_1 + 52)
+#define LMIC_PGA_PM_IN4         (PAGE_1 + 53)
+#define LMIC_PGA_MIN            (PAGE_1 + 54)
+#define RMIC_PGA_PIN            (PAGE_1 + 55)
+#define RMIC_PGA_PM_IN4         (PAGE_1 + 56)
+#define RMIC_PGA_MIN            (PAGE_1 + 57)
+/* MIC PGA Gain Registers */
+#define MICL_PGA                (PAGE_1 + 59)
+#define MICR_PGA                (PAGE_1 + 60)
+#define HEADSET_TUNING1_REG     (PAGE_1 + 119)
+#define HEADSET_TUNING2_REG     (PAGE_1 + 120)
+#define MIC_PWR_DLY             (PAGE_1 + 121)
+#define REF_PWR_DLY             (PAGE_1 + 122)
+
+/* ****************** Page 4 Registers **************************************/
+#define PAGE_4                  512
+#define ASI1_BUS_FMT            (PAGE_4 + 1)
+#define ASI1_LCH_OFFSET         (PAGE_4 + 2)
+#define ASI1_RCH_OFFSET         (PAGE_4 + 3)
+#define ASI1_CHNL_SETUP         (PAGE_4 + 4)
+#define ASI1_MULTI_CH_SETUP_R1  (PAGE_4 + 5)
+#define ASI1_MULTI_CH_SETUP_R2  (PAGE_4 + 6)
+#define ASI1_ADC_INPUT_CNTL     (PAGE_4 + 7)
+#define ASI1_DAC_OUT_CNTL       (PAGE_4 + 8)
+#define ASI1_ADC_OUT_TRISTATE   (PAGE_4 + 9)
+#define ASI1_BWCLK_CNTL_REG     (PAGE_4 + 10)
+#define ASI1_BCLK_N_CNTL        (PAGE_4 + 11)
+#define ASI1_BCLK_N             (PAGE_4 + 12)
+#define ASI1_WCLK_N             (PAGE_4 + 13)
+#define ASI1_BWCLK_OUT_CNTL     (PAGE_4 + 14)
+#define ASI1_DATA_OUT           (PAGE_4 + 15)
+#define ASI2_BUS_FMT            (PAGE_4 + 17)
+#define ASI2_LCH_OFFSET         (PAGE_4 + 18)
+#define ASI2_RCH_OFFSET         (PAGE_4 + 19)
+#define ASI2_ADC_INPUT_CNTL     (PAGE_4 + 23)
+#define ASI2_DAC_OUT_CNTL       (PAGE_4 + 24)
+#define ASI2_BWCLK_CNTL_REG     (PAGE_4 + 26)
+#define ASI2_BCLK_N_CNTL        (PAGE_4 + 27)
+#define ASI2_BCLK_N             (PAGE_4 + 28)
+#define ASI2_WCLK_N             (PAGE_4 + 29)
+#define ASI2_BWCLK_OUT_CNTL     (PAGE_4 + 30)
+#define ASI2_DATA_OUT           (PAGE_4 + 31)
+#define ASI3_BUS_FMT            (PAGE_4 + 33)
+#define ASI3_LCH_OFFSET         (PAGE_4 + 34)
+#define ASI3_RCH_OFFSET         (PAGE_4 + 35)
+#define ASI3_ADC_INPUT_CNTL     (PAGE_4 + 39)
+#define ASI3_DAC_OUT_CNTL       (PAGE_4 + 40)
+#define ASI3_BWCLK_CNTL_REG     (PAGE_4 + 42)
+#define ASI3_BCLK_N_CNTL        (PAGE_4 + 43)
+#define ASI3_BCLK_N             (PAGE_4 + 44)
+#define ASI3_WCLK_N             (PAGE_4 + 45)
+#define ASI3_BWCLK_OUT_CNTL     (PAGE_4 + 46)
+#define ASI3_DATA_OUT           (PAGE_4 + 47)
+#define WCLK1_PIN_CNTL_REG      (PAGE_4 + 65)
+#define DOUT1_PIN_CNTL_REG      (PAGE_4 + 67)
+#define DIN1_PIN_CNTL_REG       (PAGE_4 + 68)
+#define WCLK2_PIN_CNTL_REG      (PAGE_4 + 69)
+#define BCLK2_PIN_CNTL_REG      (PAGE_4 + 70)
+#define DOUT2_PIN_CNTL_REG      (PAGE_4 + 71)
+#define DIN2_PIN_CNTL_REG       (PAGE_4 + 72)
+#define WCLK3_PIN_CNTL_REG      (PAGE_4 + 73)
+#define BCLK3_PIN_CNTL_REG      (PAGE_4 + 74)
+#define DOUT3_PIN_CNTL_REG      (PAGE_4 + 75)
+#define DIN3_PIN_CNTL_REG       (PAGE_4 + 76)
+#define MCLK2_PIN_CNTL_REG      (PAGE_4 + 82)
+#define GPIO1_IO_CNTL           (PAGE_4 + 86)
+#define GPIO2_IO_CNTL           (PAGE_4 + 87)
+#define GPI1_EN                 (PAGE_4 + 91)
+#define GPO2_EN                 (PAGE_4 + 92)
+#define GPO1_PIN_CNTL           (PAGE_4 + 96)
+#define MINIDSP_PORT_CNTL_REG   (PAGE_4 + 118)
+
+/****************************************************************************
+* Mixer control  related #defines
+***************************************************************************
+*/
+#define WCLK1_ENUM            0
+#define DOUT1_ENUM            1
+#define DIN1_ENUM             2
+#define WCLK2_ENUM            3
+#define BCLK2_ENUM            4
+#define DOUT2_ENUM            5
+#define DIN2_ENUM             6
+#define WCLK3_ENUM            7
+#define BCLK3_ENUM            8
+#define DOUT3_ENUM            9
+#define DIN3_ENUM             10
+#define CLKIN_ENUM            11
+/*
+*****************************************************************************
+* Enumeration Definitions
+*****************************************************************************
+*/
+/* The below enumeration lists down all the possible inputs to the
+* the PLL of the AIC3262. The Private structure will hold a member
+* of this Enumeration Type.
+*/
+enum AIC3262_PLL_OPTION {
+        PLL_CLKIN_MCLK1 = 0,    /* 0000: (Device Pin) */
+        PLL_CLKIN_BLKC1,        /* 0001: (Device Pin) */
+        PLL_CLKIN_GPIO1,        /* 0010: (Device Pin)*/
+        PLL_CLKIN_DIN1,         /* 0011: (Device Pin)*/
+        PLL_CLKIN_BCLK2,        /* 0100: (Device Pin)*/
+        PLL_CLKIN_GPI1,         /* 0101: (Device Pin)*/
+        PLL_CLKIN_HF_REF_CLK,   /* 0110: (Device Pin)*/
+        PLL_CLKIN_GPIO2,        /* 0111: (Device Pin)*/
+        PLL_CLKIN_GPI2,         /* 1000: (Device Pin)*/
+        PLL_CLKIN_MCLK2         /* 1001: (Device Pin)*/
+};
+
+/* ASI Specific Bit Clock Divider Input Options.
+* Please refer to Page 4 Reg 11, Reg 27 and Reg 43
+*/
+enum ASI_BDIV_CLKIN_OPTION {
+        BDIV_CLKIN_DAC_CLK = 0,         /* 00 DAC_CLK     */
+        BDIV_CLKIN_DAC_MOD_CLK,         /* 01 DAC_MOD_CLK */
+        BDIV_CLKIN_ADC_CLK,             /* 02 ADC_CLK     */
+        BDIV_CLKIN_ADC_MOD_CLK          /* 03 ADC_MOD_CLK */
+};
+
+/* ASI Specific Bit Clock Output Mux Options.
+* Please refer to Page 4 Reg 14, Reg 30 and Reg 46
+* Please note that we are not handling the Reserved
+* cases here.
+*/
+enum ASI_BCLK_OPTION {
+        ASI1_BCLK_DIVIDER_OUTPUT = 0,   /* 00 ASI1 Bit Clock Divider Output */
+        ASI1_BCLK_INPUT,                /* 01 ASI1 Bit Clock Input */
+        ASI2_BCLK_DIVIDER_OUTPUT,       /* 02 ASI2 Bit Clock Divider Output  */
+        ASI2_BCLK_INPUT,                /* 03 ASI2 Bit Clock Input */
+        ASI3_BCLK_DIVIDER_OUTPUT,       /* 04 ASI3 Bit Clock Divider Output  */
+        ASI3_BBCLK_INPUT                /* 05 ASi3 Bit Clock Input */
+};
+
+/* Above bits are to be configured after Shifting 4 bits */
+#define AIC3262_ASI_BCLK_MUX_SHIFT      4
+#define AIC3262_ASI_BCLK_MUX_MASK       (BIT6 | BIT5 | BIT4)
+#define AIC3262_ASI_WCLK_MUX_MASK       (BIT2 | BIT1 | BIT0)
+
+/* ASI Specific Word Clock Output Mux Options */
+enum ASI_WCLK_OPTION {
+        GENERATED_DAC_FS = 0,           /* 00 WCLK = DAC_FS */
+        GENERATED_ADC_FS = 1,           /* 01 WCLK = ADC_FS */
+        ASI1_WCLK_DIV_OUTPUT = 2,       /* 02 WCLK = ASI1 WCLK_DIV_OUT */
+        ASI1_WCLK_INPUT      = 3,       /* 03 WCLK = ASI1 WCLK Input   */
+        ASI2_WCLK_DIV_OUTPUT = 4,       /* 04 WCLK = ASI2 WCLK_DIV_OUT */
+        ASI2_WCLK_INPUT      = 5,       /* 05 WCLK = ASI2 WCLK Input   */
+        ASI3_WCLK_DIV_OUTPUT = 6,       /* 06 WCLK = ASI3 WCLK_DIV_OUT */
+        ASI3_WCLK_INPUT      = 7        /* 07 WCLK = ASI3 WCLK Input   */
+};
+
+/* ASI DAC Output Control Options */
+enum ASI_DAC_OUTPUT_OPTION {
+        DAC_PATH_OFF = 0,       /* 00 DAC Datapath Off */
+        DAC_PATH_LEFT,          /* 01 DAC Datapath left Data */
+        DAC_PATH_RIGHT,         /* 02 DAC Datapath Right Data */
+};
+
+#define AIC3262_READ_COMMAND_WORD(addr)   ((1 << 15) | (addr << 5))
+#define AIC3262_WRITE_COMMAND_WORD(addr)  ((0 << 15) | (addr << 5))
+
+/* Shift the above options by so many bits */
+#define AIC3262_ASI_LDAC_PATH_SHIFT     6
+#define AIC3262_ASI_LDAC_PATH_MASK      (BIT5 | BIT4)
+#define AIC3262_ASI_RDAC_PATH_SHIFT     4
+#define AIC3262_ASI_RDAC_PATH_MASK      (BIT7 | BIT6)
+
+
+#define DAC_LR_MUTE_MASK        0xc
+#define DAC_LR_MUTE             0xc
+#define ENABLE_CLK_MASK         0x80
+#define ENABLE_CLK              0x80
+
+/* ASI specific ADC Input Control Options */
+enum ASI_ADC_INPUT_OPTION {
+        ADC_PATH_OFF = 0,       /* 00 ASI Digital Output Disabled */
+        ADC_PATH_MINIDSP_1,     /* 01 ASI Digital O/P from miniDSP_A(L1,R1) */
+        ADC_PATH_ASI1,          /* 02 ASI Digital Output from ASI1 */
+        ADC_PATH_ASI2,          /* 03 ASI Digital Output from ASI2 */
+        ADC_PATH_ASI3,          /* 04 ASI Digital Output from ASI3 */
+        ADC_PATH_MINIDSP_2,     /* 05 ASI Digital O/P from miniDSP_A(L2,R2) */
+        ADC_PATH_MINIDSP_3      /* 05 ASI Digital O/P from miniDSP_A(L3,R3) */
+};
+
+/* ASI Specific DOUT Pin Options */
+enum ASI_DOUT_OPTION {
+        ASI_OUTPUT = 0,         /* 00 Default ASI Output */
+        ASI1_INPUT,             /* 01 ASI1 Data Input    */
+        ASI2_INPUT,             /* 02 ASI2 Data Input    */
+        ASI3_INPUT              /* 03 ASI3 Data Input    */
+};
+
+#define AIC3262_ASI_DOUT_MASK   (BIT1 | BIT0)
+
+/*
+ *****************************************************************************
+ * Structures Definitions
+ *****************************************************************************
+ */
+#define AIC3262_MULTI_ASI_ACTIVE(x) (((x)->asiCtxt[0].asi_active) || \
+                        ((x)->asiCtxt[1].asi_active) || \
+                        ((x)->asiCtxt[2].asi_active))
+
+/*
+*----------------------------------------------------------------------------
+* @struct  aic3262_setup_data |
+*          i2c specific data setup for AIC3262.
+* @field   unsigned short |i2c_address |
+*          Unsigned short for i2c address.
+*----------------------------------------------------------------------------
+*/
+        struct aic3262_setup_data {
+        unsigned short i2c_address;
+};
+
+/*
+*----------------------------------------------------------------------------
+* @struct aic3262_asi_data
+*       ASI specific data stored for each ASI Interface
+*
+*
+*---------------------------------------------------------------------------
+*/
+struct aic3262_asi_data {
+        u8 asi_active;                                  /* ASI Active Flag */
+        u8 master;                                      /* Frame Master */
+        u32 sampling_rate;                              /* Sampling Rate */
+        enum ASI_BDIV_CLKIN_OPTION bclk_div_option;     /* BCLK DIV Mux Option*/
+        enum ASI_BCLK_OPTION    bclk_output;            /* BCLK Output Option*/
+        enum ASI_WCLK_OPTION    wclk_output;            /* WCLK Output Option*/
+        u8                      bclk_div;               /* BCLK Divider */
+        u8                      wclk_div;               /* WCLK Divider */
+        enum ASI_DAC_OUTPUT_OPTION left_dac_output;     /* LDAC Path */
+        enum ASI_DAC_OUTPUT_OPTION right_dac_output;    /* RDAC Path */
+        enum ASI_ADC_INPUT_OPTION  adc_input;           /* ADC Input Control */
+        enum ASI_DOUT_OPTION    dout_option;            /* DOUT Option */
+        u8                      playback_mode;          /* Playback Selected */
+        u8                      capture_mode;           /* Record Selected */
+        u8                      port_muted;             /* ASI Muted */
+        u8                      pcm_format;             /* PCM Format */
+        u8                      word_len;               /* Word Length */
+        u8                      offset1;                /* Left Ch offset */
+        u8                      offset2;                /* Right Ch Offset */
+};
+
+/*
+*----------------------------------------------------------------------------
+* @struct  aic3262_priv |
+*          AIC3262 priviate data structure to set the system clock, mode and
+*          page number.
+* @field   u32 | sysclk |
+*          system clock
+* @field   s32 | master |
+*          master/slave mode setting for AIC3262
+* @field   u8 | book_no |
+*          book number.
+* @field   u8 | page_no |
+*          page number. Here, page 0 and page 1 are used.
+*----------------------------------------------------------------------------
+*/
+struct aic3262_priv {
+        enum snd_soc_control_type control_type;
+        struct aic326x_pdata *pdata;
+        struct snd_soc_codec codec;
+        u32 sysclk;
+        s32 master;
+        u8 book_no;
+        u8 page_no;
+        u8 process_flow;
+        u8 mute_codec;
+        u8 stream_status;
+        u32 active_count;
+        int current_dac_config[MAX_ASI_COUNT];
+        int current_adc_config[MAX_ASI_COUNT];
+        int current_config;
+        struct aic3262_asi_data asiCtxt[MAX_ASI_COUNT];
+        enum AIC3262_PLL_OPTION aic3262_pllclkin_option;
+        u8 dac_clkin_option;
+        u8 adc_clkin_option;
+        int irq;
+        u8 dac_reg;
+        u8 adc_gain;
+        u8 hpl;
+        u8 hpr;
+        u8 rec_amp;
+        u8 rampr;
+        u8 spk_amp;
+        struct spi_device *spi;
+        struct snd_soc_jack *headset_jack;
+        struct input_dev *button_dev;
+        int codec_audio_mode;
+#if defined(LOCAL_REG_ACCESS)
+        void *control_data;
+#endif
+};
+
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_configs |
+ *          AIC3262 initialization data which has register offset and register
+ *          value.
+ * @field   u8 | book_no |
+ *          AIC3262 Book Number Offsets required for initialization..
+ * @field   u16 | reg_offset |
+ *          AIC3262 Register offsets required for initialization..
+ * @field   u8 | reg_val |
+ *          value to set the AIC3262 register to initialize the AIC3262.
+ *----------------------------------------------------------------------------
+ */
+struct aic3262_configs {
+        u8 book_no;
+        u16 reg_offset;
+        u8  reg_val;
+};
+
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_rate_divs |
+ *          Setting up the values to get different freqencies
+ * @field   u32 | mclk |
+ *          Master clock
+ * @field   u32 | rate |
+ *          sample rate
+ * @field   u8 | p_val |
+ *          value of p in PLL
+ * @field   u32 | pll_j |
+ *          value for pll_j
+ * @field   u32 | pll_d |
+ *          value for pll_d
+ * @field   u32 | dosr |
+ *          value to store dosr
+ * @field   u32 | ndac |
+ *          value for ndac
+ * @field   u32 | mdac |
+ *          value for mdac
+ * @field   u32 | aosr |
+ *          value for aosr
+ * @field   u32 | nadc |
+ *          value for nadc
+ * @field   u32 | madc |
+ *          value for madc
+ * @field   u32 | blck_N |
+ *          value for block N
+ * @field   u32 | aic3262_configs |
+ *          configurations for aic3262 register value
+ *----------------------------------------------------------------------------
+ */
+struct aic3262_rate_divs {
+        u32 mclk;
+        u32 rate;
+        u8 p_val;
+        u8 pll_j;
+        u16 pll_d;
+        u16 dosr;
+        u8 ndac;
+        u8 mdac;
+        u8 aosr;
+        u8 nadc;
+        u8 madc;
+        u8 blck_N;
+        struct aic3262_configs codec_specific_regs[NO_FEATURE_REGS];
+};
+
+/*
+*****************************************************************************
+* EXTERN DECLARATIONS
+*****************************************************************************
+*/
+/*
+ *----------------------------------------------------------------------------
+ * @func  aic326x_headset_detect
+ *      This function help to setup the needed registers to
+ *      enable the headset detection
+ *
+ */
+extern int aic326x_headset_detect(struct snd_soc_codec *codec,
+        struct snd_soc_jack *jack, int jack_type);
+extern int aic326x_headset_button_init(struct snd_soc_codec *codec,
+        struct snd_soc_jack *jack, int jack_type);
+
+extern u8 aic3262_read(struct snd_soc_codec *codec, u16 reg);
+extern u16 aic3262_read_2byte(struct snd_soc_codec *codec, u16 reg);
+extern int aic3262_reset_cache(struct snd_soc_codec *codec);
+extern int aic3262_change_page(struct snd_soc_codec *codec, u8 new_page);
+extern int aic3262_write(struct snd_soc_codec *codec, u16 reg, u8 value);
+extern void aic3262_write_reg_cache(struct snd_soc_codec *codec,
+                                    u16 reg, u8 value);
+extern int aic3262_change_book(struct snd_soc_codec *codec, u8 new_book);
+extern int reg_def_conf(struct snd_soc_codec *codec);
+extern int i2c_verify_book0(struct snd_soc_codec *codec);
+extern int poll_dac(struct snd_soc_codec *codec, int left_right, int on_off);
+extern int poll_adc(struct snd_soc_codec *codec, int left_right, int on_off);
+
+#ifdef CONFIG_MINI_DSP
+extern int aic3262_minidsp_program(struct snd_soc_codec *codec);
+extern int aic3262_add_minidsp_controls(struct snd_soc_codec *codec);
+#endif
+
+
+#ifdef MULTIBYTE_CONFIG_SUPPORT
+extern int aic3262_add_multiconfig_controls(struct snd_soc_codec *codec);
+#endif
+
+#endif                          /* _TLV320AIC3262_H */
+
diff --git a/sound/soc/codecs/tlv320aic326x_mini-dsp.c b/sound/soc/codecs/tlv320aic326x_mini-dsp.c
new file mode 100644
index 00000000000..6d55abb4dac
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x_mini-dsp.c
@@ -0,0 +1,1796 @@
+/*
+ * linux/sound/soc/codecs/tlv320aic326x_mini-dsp.c
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * The TLV320AIC3262 is a flexible, low-power, low-voltage stereo audio
+ * codec with digital microphone inputs and programmable outputs.
+ *
+ * History:
+ *
+ * Rev 0.1   Added the miniDSP Support   01-03-2011
+ *
+ * Rev 0.2   Updated the code-base for miniDSP switching and
+ *       mux control update.    21-03-2011
+ *
+ * Rev 0.3   Updated the code-base to support Multi-Configuration feature
+ *                 of PPS GDE
+ */
+
+/*
+ *****************************************************************************
+ * INCLUDES
+ *****************************************************************************
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/types.h>
+#include <linux/kdev_t.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <sound/soc.h>
+#include <sound/core.h>
+#include <sound/soc-dapm.h>
+#include <sound/control.h>
+#include <linux/time.h>         /* For timing computations */
+#include "tlv320aic326x.h"
+#include "tlv320aic326x_mini-dsp.h"
+
+#include "base_main_Rate48_pps_driver.h"
+#include "second_rate_pps_driver.h"
+//#include "one_mic_aec_nc_latest.h"
+#ifdef CONFIG_MINI_DSP
+
+#ifdef REG_DUMP_MINIDSP
+static void aic3262_dump_page(struct i2c_client *i2c, u8 page);
+#endif
+
+/*
+ *****************************************************************************
+ * LOCAL STATIC DECLARATIONS
+ *****************************************************************************
+ */
+static int m_control_info(struct snd_kcontrol *kcontrol,
+                                  struct snd_ctl_elem_info *uinfo);
+static int m_control_get(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol);
+static int m_control_put(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol);
+
+/*
+ *****************************************************************************
+ * MINIDSP RELATED GLOBALS
+ *****************************************************************************
+ */
+/* The below variable is used to maintain the I2C Transactions
+ * to be carried out during miniDSP switching.
+ */
+ #if 1
+minidsp_parser_data dsp_parse_data[MINIDSP_PARSER_ARRAY_SIZE*2];
+
+struct i2c_msg i2c_transaction[MINIDSP_PARSER_ARRAY_SIZE * 2];
+/* Total count of I2C Messages are stored in the i2c_count */
+int i2c_count;
+
+/* The below array is used to store the burst array for I2C Multibyte
+ * Operations
+ */
+minidsp_i2c_page i2c_page_array[MINIDSP_PARSER_ARRAY_SIZE];
+int i2c_page_count;
+#else
+minidsp_parser_data dsp_parse_data;
+
+struct i2c_msg i2c_transaction;
+/* Total count of I2C Messages are stored in the i2c_count */
+int i2c_count;
+
+/* The below array is used to store the burst array for I2C Multibyte
+ * Operations
+ */
+minidsp_i2c_page i2c_page_array;
+int i2c_page_count;
+#endif
+
+/* kcontrol structure used to register with ALSA Core layer */
+static struct snd_kcontrol_new snd_mux_controls[MAX_MUX_CONTROLS];
+
+/* mode variables */
+static int amode;
+static int dmode;
+
+/* k-control macros used for miniDSP related Kcontrols */
+#define SOC_SINGLE_VALUE_M(xmax, xinvert) \
+        ((unsigned long)&(struct soc_mixer_control) \
+        {.max = xmax, \
+        .invert = xinvert})
+#define SOC_SINGLE_M(xname, max, invert) \
+{\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .info = m_control_info, .get = m_control_get,\
+        .put = m_control_put, \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+        .private_value = SOC_SINGLE_VALUE_M(max, invert) }
+#define SOC_SINGLE_AIC3262_M(xname) \
+{\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .info = m_control_info, .get = m_control_get,\
+        .put = m_control_put, \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+}
+
+/*
+ * aic3262_minidsp_controls
+ *
+ * Contains the list of the Kcontrol macros required for modifying the
+ * miniDSP behavior at run-time.
+ */
+static const struct snd_kcontrol_new aic3262_minidsp_controls[] = {
+        SOC_SINGLE_AIC3262_M("Minidsp mode") ,
+        SOC_SINGLE_AIC3262_M("ADC Adaptive mode Enable") ,
+        SOC_SINGLE_AIC3262_M("DAC Adaptive mode Enable") ,
+        SOC_SINGLE_AIC3262_M("Dump Regs Book0") ,
+        SOC_SINGLE_AIC3262_M("Verify minidsp program") ,
+};
+
+#ifdef REG_DUMP_MINIDSP
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_dump_page
+ * Purpose  : Read and display one codec register page, for debugging purpose
+ *----------------------------------------------------------------------------
+ */
+static void aic3262_dump_page(struct i2c_client *i2c, u8 page)
+{
+        int i;
+        u8 data;
+        u8 test_page_array[256];
+
+        aic3262_change_page(codec, page);
+
+        data = 0x0;
+
+        i2c_master_send(i2c, data, 1);
+        i2c_master_recv(i2c, test_page_array, 128);
+
+        DBG("\n------- MINI_DSP PAGE %d DUMP --------\n", page);
+        for (i = 0; i < 128; i++)
+                DBG(KERN_INFO " [ %d ] = 0x%x\n", i, test_page_array[i]);
+
+}
+#endif
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : update_kcontrols
+ * Purpose  : Given the miniDSP process flow, this function reads the
+ *                      corresponding Page Numbers and then performs I2C Read for those
+ *                      Pages.
+ *----------------------------------------------------------------------------
+ */
+void update_kcontrols(struct snd_soc_codec *codec, int process_flow)
+{
+        int i, val1, array_size;
+        char **knames;
+        control *cntl;
+
+#if 0
+        if (process_flow == 1) {
+                knames = Second_Rate_MUX_control_names;
+                cntl = Second_Rate_MUX_controls;
+                array_size = ARRAY_SIZE(Second_Rate_MUX_controls);
+        } else {
+#endif
+                knames = main44_MUX_control_names;
+                cntl = main44_MUX_controls;
+                array_size = ARRAY_SIZE(main44_MUX_controls);
+//      }
+
+        DBG(KERN_INFO "%s: ARRAY_SIZE = %d\tmode=%d\n", __func__,
+                        array_size, process_flow);
+        for (i = 0; i < array_size; i++) {
+                aic3262_change_book(codec, cntl[i].control_book);
+                aic3262_change_page(codec, cntl[i].control_page);
+                val1 = i2c_smbus_read_byte_data(codec->control_data,
+                                cntl[i].control_base);
+                snd_mux_controls[i].private_value = 0;
+        }
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : byte_i2c_array_transfer
+ * Purpose  : Function used only for debugging purpose. This function will
+ *                      be used while switching miniDSP Modes register by register.
+ *                      This needs to be used only during development.
+ *-----------------------------------------------------------------------------
+ */
+ #if 1
+int byte_i2c_array_transfer(struct snd_soc_codec *codec,
+                                reg_value *program_ptr,
+                                int size)
+{
+        int j;
+        u8 buf[3];
+
+        for (j = 0; j < size; j++) {
+                /* Check if current Reg offset is zero */
+                if (program_ptr[j].reg_off == 0) {
+                        /* Check for the Book Change Request */
+                        if ((j < (size - 1)) &&
+                                (program_ptr[j+1].reg_off == 127)) {
+                                aic3262_change_book(codec,
+                                        program_ptr[j+1].reg_val);
+                        /* Increment for loop counter across Book Change */
+                                j++;
+                                continue;
+                }
+                /* Check for the Page Change Request in Current book */
+                aic3262_change_page(codec, program_ptr[j].reg_val);
+                continue;
+                }
+
+                buf[AIC3262_REG_OFFSET_INDEX] = program_ptr[j].reg_off % 128;
+                buf[AIC3262_REG_DATA_INDEX] =
+                                program_ptr[j].reg_val & AIC3262_8BITS_MASK;
+
+                if (codec->hw_write(codec->control_data, buf, 2) != 2) {
+                        printk(KERN_ERR "Error in i2c write\n");
+                        return -EIO;
+                }
+        }
+        aic3262_change_book(codec, 0);
+        return 0;
+}
+
+#else
+int byte_i2c_array_transfer(struct snd_soc_codec *codec,
+                                reg_value *program_ptr,
+                                int size)
+{
+        int j;
+        u8 buf[3];
+        printk(KERN_INFO "%s: started with array size %d\n", __func__, size);
+        for (j = 0; j < size; j++) {
+                /* Check if current Reg offset is zero */
+                buf[AIC3262_REG_OFFSET_INDEX] = program_ptr[j].reg_off % 128;
+                buf[AIC3262_REG_DATA_INDEX] =
+                                program_ptr[j].reg_val & AIC3262_8BITS_MASK;
+
+                if (codec->hw_write(codec->control_data, buf, 2) != 2) {
+                        printk(KERN_ERR "Error in i2c write\n");
+                        return -EIO;
+                }
+        }
+        printk(KERN_INFO "%s: ended\n", __func__);
+        return 0;
+}
+#endif
+/*
+ *----------------------------------------------------------------------------
+ * Function : byte_i2c_array_read
+ * Purpose  : This function is used to perform Byte I2C Read. This is used
+ *                      only for debugging purposes to read back the Codec Page
+ *                      Registers after miniDSP Configuration.
+ *----------------------------------------------------------------------------
+ */
+int byte_i2c_array_read(struct snd_soc_codec *codec,
+                        reg_value *program_ptr, int size)
+{
+        int j;
+        u8 val1;
+        u8 cur_page = 0;
+        u8 cur_book = 0;
+        for (j = 0; j < size; j++) {
+                /* Check if current Reg offset is zero */
+                if (program_ptr[j].reg_off == 0) {
+                        /* Check for the Book Change Request */
+                        if ((j < (size - 1)) &&
+                                (program_ptr[j+1].reg_off == 127)) {
+                                aic3262_change_book(codec,
+                                        program_ptr[j+1].reg_val);
+                                cur_book = program_ptr[j+1].reg_val;
+                        /* Increment for loop counter across Book Change */
+                                j++;
+                                continue;
+                        }
+                        /* Check for the Page Change Request in Current book */
+                        aic3262_change_page(codec, program_ptr[j].reg_val);
+                        cur_page = program_ptr[j].reg_val;
+                        continue;
+                }
+
+                val1 = i2c_smbus_read_byte_data(codec->control_data,
+                                program_ptr[j].reg_off);
+                if (val1 < 0)
+                        printk(KERN_ERR "Error in smbus read\n");
+
+                if(val1 != program_ptr[j].reg_val)
+                        /*printk(KERN_INFO "mismatch [%d][%d][%d] = %x %x\n",
+                        cur_book, cur_page, program_ptr[j].reg_off, val1, program_ptr[j].reg_val);*/
+                DBG(KERN_INFO "[%d][%d][%d]= %x\n",
+                        cur_book, cur_page, program_ptr[j].reg_off, val1);
+        }
+        aic3262_change_book(codec, 0);
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : minidsp_get_burst
+ * Purpose  : Format one I2C burst for transfer from mini dsp program array.
+ *                      This function will parse the program array and get next burst
+ *                      data for doing an I2C bulk transfer.
+ *----------------------------------------------------------------------------
+ */
+static void
+minidsp_get_burst(reg_value *program_ptr,
+                                int program_size,
+                                minidsp_parser_data *parse_data)
+{
+        int index = parse_data->current_loc;
+        int burst_write_count = 0;
+
+        /*DBG("GET_BURST: start\n");*/
+        /* check if first location is page register, and populate page addr */
+        if (program_ptr[index].reg_off == 0) {
+                if ((index < (program_size - 1)) &&
+                        (program_ptr[index+1].reg_off == 127)) {
+                        parse_data->book_change = 1;
+                        parse_data->book_no = program_ptr[index+1].reg_val;
+                        index += 2;
+                        goto finish_out;
+
+                }
+                parse_data->page_num = program_ptr[index].reg_val;
+                parse_data->burst_array[burst_write_count++] =
+                        program_ptr[index].reg_off;
+                parse_data->burst_array[burst_write_count++] =
+                        program_ptr[index].reg_val;
+                index++;
+                goto finish_out;
+        }
+
+        parse_data->burst_array[burst_write_count++] =
+                        program_ptr[index].reg_off;
+        parse_data->burst_array[burst_write_count++] =
+                        program_ptr[index].reg_val;
+        index++;
+
+        for (; index < program_size; index++) {
+                if (program_ptr[index].reg_off !=
+                                (program_ptr[index - 1].reg_off + 1))
+                        break;
+                else
+                        parse_data->burst_array[burst_write_count++] =
+                                program_ptr[index].reg_val;
+
+        }
+finish_out:
+        parse_data->burst_size = burst_write_count;
+        if (index == program_size)
+                /* parsing completed */
+                parse_data->current_loc = MINIDSP_PARSING_END;
+        else
+                parse_data->current_loc = index;
+        /*DBG("GET_BURST: end\n");*/
+}
+/*
+ *----------------------------------------------------------------------------
+ * Function : minidsp_i2c_multibyte_transfer
+ * Purpose  : Function used to perform multi-byte I2C Writes. Used to configure
+ *                      the miniDSP Pages.
+ *----------------------------------------------------------------------------
+ */
+ #if 1
+int
+minidsp_i2c_multibyte_transfer(struct snd_soc_codec *codec,
+                                        reg_value *program_ptr,
+                                        int program_size)
+{
+        struct i2c_client *client = codec->control_data;
+
+        minidsp_parser_data parse_data;
+        int count = 0;
+
+#ifdef DEBUG_MINIDSP_LOADING
+        int i = 0, j = 0;
+#endif
+        /* point the current location to start of program array */
+        parse_data.current_loc = 0;
+        parse_data.page_num = 0;
+        parse_data.book_change = 0;
+        parse_data.book_no = 0;
+
+        DBG(KERN_INFO "size is : %d", program_size);
+        do {
+                do {
+                        /* Get first burst data */
+                        minidsp_get_burst(program_ptr, program_size,
+                                        &parse_data);
+                        if (parse_data.book_change == 1)
+                                break;
+                        dsp_parse_data[count] = parse_data;
+
+                        i2c_transaction[count].addr = client->addr;
+                        i2c_transaction[count].flags =
+                                client->flags & I2C_M_TEN;
+                        i2c_transaction[count].len =
+                                dsp_parse_data[count].burst_size;
+                        i2c_transaction[count].buf =
+                                dsp_parse_data[count].burst_array;
+
+#ifdef DEBUG_MINIDSP_LOADING
+                        DBG(KERN_INFO
+                        "i: %d\taddr: %d\tflags: %d\tlen: %d\tbuf:",
+                        i, client->addr, client->flags & I2C_M_TEN,
+                        dsp_parse_data[count].burst_size);
+
+                        for (j = 0; j <= dsp_parse_data[count].burst_size; j++)
+                                DBG(KERN_INFO "%x ",
+                                        dsp_parse_data[i].burst_array[j]);
+
+                        DBG(KERN_INFO "\n\n");
+                        i++;
+#endif
+
+                        count++;
+                        /* Proceed to the next burst reg_addr_incruence */
+                } while (parse_data.current_loc != MINIDSP_PARSING_END);
+
+                if (count > 0) {
+                        if (i2c_transfer(client->adapter,
+                                i2c_transaction, count) != count) {
+                                printk(KERN_ERR "Write burst i2c data error!\n");
+                        }
+                }
+                if (parse_data.book_change == 1) {
+                        aic3262_change_book(codec, parse_data.book_no);
+                        parse_data.book_change = 0;
+                }
+        } while (parse_data.current_loc != MINIDSP_PARSING_END);
+        aic3262_change_book(codec, 0);
+        return 0;
+}
+#else
+int
+minidsp_i2c_multibyte_transfer(struct snd_soc_codec *codec,
+                                        reg_value *program_ptr,
+                                        int program_size)
+{
+        struct i2c_client *client = codec->control_data;
+
+        minidsp_parser_data parse_data;
+        int count = 1;
+
+#ifdef DEBUG_MINIDSP_LOADING
+        int i = 0, j = 0;
+#endif
+        /* point the current location to start of program array */
+        parse_data.current_loc = 0;
+        parse_data.page_num = 0;
+        parse_data.book_change = 0;
+        parse_data.book_no = 0;
+
+        DBG(KERN_INFO "size is : %d", program_size);
+
+        do {
+                /* Get first burst data */
+                minidsp_get_burst(program_ptr, program_size,
+                                &parse_data);
+
+                dsp_parse_data = parse_data;
+
+                i2c_transaction.addr = client->addr;
+                i2c_transaction.flags =
+                        client->flags & I2C_M_TEN;
+                i2c_transaction.len =
+                        dsp_parse_data.burst_size;
+                i2c_transaction.buf =
+                        dsp_parse_data.burst_array;
+
+#ifdef DEBUG_MINIDSP_LOADING
+                        DBG(KERN_INFO
+                        "i: %d\taddr: %d\tflags: %d\tlen: %d\tbuf:",
+                        i, client->addr, client->flags & I2C_M_TEN,
+                        dsp_parse_data.burst_size);
+
+                        for (j = 0; j <= dsp_parse_data.burst_size; j++)
+                                printk( "%x ",
+                                        dsp_parse_data.burst_array[j]);
+
+                        DBG(KERN_INFO "\n\n");
+                        i++;
+#endif
+
+                if (i2c_transfer(client->adapter,
+                        &i2c_transaction, count) != count) {
+                        printk(KERN_ERR "Write burst i2c data error!\n");
+                }
+                if (parse_data.book_change == 1) {
+                        aic3262_change_book(codec, parse_data.book_no);
+                        parse_data.book_change = 0;
+                }
+                /* Proceed to the next burst reg_addr_incruence */
+        } while (parse_data.current_loc != MINIDSP_PARSING_END);
+
+        return 0;
+}
+#endif
+/*
+* Process_Flow Structure
+* Structure used to maintain the mapping of each PFW like the miniDSP_A
+* miniDSP_D array values and sizes. It also contains information about
+* the patches required for each patch.
+*/
+struct process_flow{
+        int init_size;
+        reg_value *miniDSP_init;
+        int A_size;
+        reg_value *miniDSP_A_values;
+        int D_size;
+        reg_value *miniDSP_D_values;
+        int post_size;
+        reg_value *miniDSP_post;
+        struct minidsp_config {
+                int a_patch_size;
+                reg_value *a_patch;
+                int d_patch_size;
+                reg_value *d_patch;
+        } configs[MAXCONFIG];
+
+} miniDSP_programs[]  = {
+        {
+        ARRAY_SIZE(main44_REG_Section_init_program), main44_REG_Section_init_program,
+        ARRAY_SIZE(main44_miniDSP_A_reg_values),main44_miniDSP_A_reg_values,
+        ARRAY_SIZE(main44_miniDSP_D_reg_values),main44_miniDSP_D_reg_values,
+        ARRAY_SIZE(main44_REG_Section_post_program),main44_REG_Section_post_program,
+        {
+
+                { 0, 0, 0, 0},
+                { 0, 0, 0, 0},
+                { 0, 0, 0, 0},
+                { 0, 0, 0, 0},
+
+
+        },
+},
+        {
+        ARRAY_SIZE(base_speaker_SRS_REG_init_Section_program),base_speaker_SRS_REG_init_Section_program,
+        ARRAY_SIZE(base_speaker_SRS_miniDSP_A_reg_values),base_speaker_SRS_miniDSP_A_reg_values,
+        ARRAY_SIZE(base_speaker_SRS_miniDSP_D_reg_values),base_speaker_SRS_miniDSP_D_reg_values,
+        ARRAY_SIZE(base_speaker_SRS_REG_post_Section_program),base_speaker_SRS_REG_post_Section_program,
+
+        {
+                        {0, 0,  ARRAY_SIZE(SRS_ON_miniDSP_D_reg_values), SRS_ON_miniDSP_D_reg_values},
+                        {0, 0,  ARRAY_SIZE(SRS_OFF_miniDSP_D_reg_values),SRS_OFF_miniDSP_D_reg_values},
+                        {0, 0, 0, 0},
+                        {0, 0, 0, 0},
+                },
+},
+#if 0
+        {ARRAY_SIZE(spkr_srs_REG_Section_init_program),spkr_srs_REG_Section_init_program,
+        ARRAY_SIZE(spkr_srs_miniDSP_A_reg_values),spkr_srs_miniDSP_A_reg_values,
+        ARRAY_SIZE(spkr_srs_miniDSP_D_reg_values),spkr_srs_miniDSP_D_reg_values,
+        ARRAY_SIZE(spkr_srs_REG_Section_post_program),spkr_srs_REG_Section_post_program,
+        {
+                { 0, 0, 0, 0},
+                { 0, 0, 0, 0},
+                { 0, 0, 0, 0},
+                { 0, 0, 0, 0},
+
+        },
+},
+#endif
+};
+
+int
+set_minidsp_mode(struct snd_soc_codec *codec, int new_mode, int new_config)
+{
+
+        if (codec == NULL) {
+        printk(KERN_INFO "%s codec is NULL\n",__func__);
+        }
+        struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        struct process_flow *  pflows = &miniDSP_programs[new_mode];
+        u8 reg63, reg81, pll_pow, ndac_pow, mdac_pow, nadc_pow, madc_pow;
+
+        u8 adc_status,dac_status;
+        u8 reg, val;
+        u8 shift;
+        volatile u16 counter;
+
+        int (*ptransfer)(struct snd_soc_codec *codec,
+                                reg_value *program_ptr,
+                                int size);
+
+        printk("%s:New Switch mode = %d New Config= %d\n", __func__, new_mode,new_config);
+        if (new_mode >= ARRAY_SIZE(miniDSP_programs))
+                return 0; //  error condition
+                if (new_config > MAXCONFIG)
+                        return 0;
+#ifndef MULTIBYTE_I2C
+                ptransfer = byte_i2c_array_transfer;
+#else
+                ptransfer = minidsp_i2c_multibyte_transfer;
+#endif
+        if (new_mode !=  aic326x->process_flow) {
+
+                printk("== From PFW %d to PFW %d==\n", aic326x->process_flow , new_mode);
+
+                /* Change to book 0 page 0 and turn off the DAC and snd_soc_dapm_disable_piADC,
+                * while turning them down, poll for the power down completion.
+                */
+                   aic3262_change_page(codec, 0);
+                   aic3262_change_book(codec, 0);
+
+#if 0
+                reg63 = aic3262_read(codec, PASI_DAC_DP_SETUP);
+                aic3262_write(codec, PASI_DAC_DP_SETUP, (reg63 & ~0xC0));/*dac power down*/
+                mdelay (5);
+                counter = 0;
+                reg = DAC_FLAG_R1;
+
+                  dac_status = aic3262_read(codec, reg);
+
+                do {
+                        dac_status = snd_soc_read(codec, reg);
+                        counter++;struct snd_soc_dapm_context *dapm
+                        mdelay(5);
+                } while ((counter < 200) && ((dac_status & 0x88) == 1));
+                printk (KERN_INFO  "#%s: Polled Register %d Bits set 0x%X counter %d\n",
+                                __func__, reg, dac_status, counter);snd_soc_dapm_disable_pi
+                struct snd_soc_dapm_context *dapm
+                   reg81= aic3262_read(codec, ADC_CHANNEL_POW);
+                aic3262_write(codec, ADC_CHANNEL_POW, (reg81 & ~0xC0));/*adc power down*/
+                mdelay (5);
+
+                adc_status=aic3262_read(codec,ADC_FLAG_R1);
+                counter = 0;
+                reg = ADC_FLAG_R1;
+                do {
+                        adc_status = snd_soc_read(codec, reg);
+                        counter++;
+                        mdelay(5);
+                } while ((counter < 200) && ((adc_status & 0x44) == 1));
+
+                printk (KERN_INFO  "#%s: Polled Register %d Bits set 0x%X counter %d\n",
+                                __func__, reg, adc_status, counter);
+
+                dac_status = snd_soc_read(codec, DAC_FLAG_R1);
+                adc_status = snd_soc_read (codec, ADC_FLAG_R1);
+
+                printk (KERN_INFO "#%s: Initial DAC_STATUS 0x%x ADC_STATUS 0x%X\n",
+                        __func__, dac_status, adc_status);
+
+#endif
+                /* Instead of hard-coding the switching off DAC and ADC, we will use the DAPM
+                * to switch off the Playback Paths and the ADC
+                */
+                snd_soc_dapm_disable_pin( dapm, "Headphone Jack");
+                snd_soc_dapm_disable_pin( dapm, "EarPiece");
+                snd_soc_dapm_disable_pin( dapm, "Int Spk");
+                snd_soc_dapm_disable_pin( dapm, "SPK out");
+                snd_soc_dapm_disable_pin( dapm, "Line Out");
+
+                snd_soc_dapm_disable_pin( dapm, "Mic Jack");
+                snd_soc_dapm_disable_pin( dapm, "Linein");
+                snd_soc_dapm_disable_pin( dapm, "Int Mic");
+
+                //snd_soc_dapm_disable_pin (codec, "Left DAC");
+                //snd_soc_dapm_disable_pin (codec, "Right DAC");
+                //snd_soc_dapm_disable_pin (codec, "Left ADC");
+                //snd_soc_dapm_disable_pin (codec, "Right ADC");
+                snd_soc_dapm_sync(dapm);
+                mdelay(10);
+
+                mdac_pow = aic3262_read(codec, MDAC_DIV_POW_REG);
+                aic3262_write(codec, MDAC_DIV_POW_REG, (mdac_pow & ~0x80));/*mdac power down*/
+                mdelay(5);
+                nadc_pow = aic3262_read(codec, MADC_DIV_POW_REG);
+                aic3262_write(codec, MADC_DIV_POW_REG, (nadc_pow & ~0x80));/*madc power down*/
+                mdelay(5);
+                pll_pow = aic3262_read(codec, PLL_PR_POW_REG);
+                aic3262_write(codec, PLL_PR_POW_REG, (pll_pow & ~0x80));/*pll power down*/
+                mdelay(5);
+                ndac_pow = aic3262_read(codec, NDAC_DIV_POW_REG);
+                aic3262_write(codec, NDAC_DIV_POW_REG, (ndac_pow & ~0x80)); /*ndac power down*/
+                mdelay(5);
+
+                dac_status = snd_soc_read(codec, DAC_FLAG_R1);
+                adc_status = snd_soc_read (codec, ADC_FLAG_R1);
+
+                printk (KERN_INFO "#%s: Before Switching DAC_STATUS 0x%x ADC_STATUS 0x%X\n",
+                        __func__, dac_status, adc_status);
+
+                mdelay (10);
+                ptransfer(codec, pflows->miniDSP_init,             pflows->init_size);
+                   ptransfer(codec, pflows->miniDSP_A_values,  pflows->A_size);
+                   ptransfer(codec, pflows->miniDSP_D_values,  pflows->D_size);
+                   ptransfer(codec, pflows->miniDSP_post,                pflows->post_size);
+
+
+                aic326x->process_flow = new_mode;
+
+                aic3262_change_page(codec, 0);
+                        aic3262_change_book(codec, 0);
+#if 0
+
+                /* After the miniDSP Programming is completed, power up the DAC and ADC
+                * and poll for its power up operation.
+                */
+
+                aic3262_write(codec, PASI_DAC_DP_SETUP, reg63);/*reverting the old DAC values */
+                mdelay(5);
+
+                /* Poll for DAC Power-up first */
+                /* For DAC Power-up and Power-down event, we will poll for
+                * Book0 Page0 Register 37
+                */
+                reg = DAC_FLAG_R1;
+                counter = 0;
+                do {
+                        dac_status = snd_soc_read(codec, reg);
+                        counter++;
+                        mdelay(5);
+                } while ((counter < 200) && ((dac_status & 0x88) == 0));
+
+                printk (KERN_INFO  "#%s: Polled Register %d Bits set 0x%X counter %d\n",
+                                __func__, reg, dac_status, counter);
+
+                aic3262_write(codec, ADC_CHANNEL_POW, reg81);/*reverting the old ADC values*/
+                mdelay (5);
+                /* For ADC Power-up and Power-down event, we will poll for
+                * Book0 Page0 Register 36
+                */
+                reg = ADC_FLAG_R1;
+                counter = 0;
+                do {
+                        adc_status = snd_soc_read(codec, reg);
+                        counter++;
+                        mdelay(5);
+                } while ((counter < 200) && ((adc_status & 0x44) == 0));
+
+                printk (KERN_INFO  "#%s: Polled Register %d Bits set 0x%X counter %d\n",
+                                __func__, reg, adc_status, counter);
+                aic3262_write(codec, PLL_PR_POW_REG, pll_pow);/*reverting the old pll values*/
+                mdelay(10);
+
+                aic3262_write(codec, MDAC_DIV_POW_REG, mdac_pow);/*reverting the old mdac values*/
+                mdelay(5);
+                aic3262_write(codec, MADC_DIV_POW_REG, madc_pow);/*reverting the old madc values*/
+                mdelay(5);
+                aic3262_write(codec, NDAC_DIV_POW_REG, ndac_pow);/*reverting the old ndac values*/
+                mdelay(5);
+
+                /*if (new_config == 0) {
+                        aic326x->current_config = 0;
+                        return 0;
+                }
+                aic326x->current_config =  -1;*/
+
+                //aic3262_change_book(codec, 0);
+                //aic3262_change_page(codec, 0);
+#endif
+        }
+
+#ifdef MULTICONFIG_SUPPORT
+        if (new_config < 0 )
+                return 0; // No configs supported in this pfw
+        if (new_config == aic326x->current_config)
+                return 0;
+           if (pflows->configs[new_config].a_patch_size || pflows->configs[new_config].d_patch_size)
+                minidsp_multiconfig(codec,
+                        pflows->configs[new_config].a_patch, pflows->configs[new_config].a_patch_size,
+                        pflows->configs[new_config].d_patch,  pflows->configs[new_config].d_patch_size);
+#endif
+
+        aic326x->current_config = new_config;
+        aic3262_change_book( codec, 0);
+
+        DBG(KERN_INFO "%s: switch mode finished\n", __func__);
+        return 0;
+}
+
+/*
+ * i2c_verify
+ *
+ * Function used to validate the contents written into the miniDSP
+ * pages after miniDSP Configuration.
+*/
+int i2c_verify(struct snd_soc_codec *codec)
+{
+
+        DBG(KERN_INFO "#%s: Invoked.. Resetting to page 0\n", __func__);
+
+        aic3262_change_book(codec, 0);
+        DBG(KERN_INFO "#Reading reg_section_init_program\n");
+
+        byte_i2c_array_read(codec, main44_REG_Section_init_program,
+                ARRAY_SIZE(main44_REG_Section_init_program));
+
+        DBG(KERN_INFO "#Reading minidsp_A_reg_values\n");
+        byte_i2c_array_read(codec, main44_miniDSP_A_reg_values,
+                (main44_miniDSP_A_reg_values_COEFF_SIZE +
+                 main44_miniDSP_A_reg_values_INST_SIZE));
+
+        DBG(KERN_INFO "#Reading minidsp_D_reg_values\n");
+        byte_i2c_array_read(codec, main44_miniDSP_D_reg_values,
+                (main44_miniDSP_D_reg_values_COEFF_SIZE +
+                 main44_miniDSP_D_reg_values_INST_SIZE));
+
+        DBG(KERN_INFO "#Reading reg_section_post_program\n");
+        byte_i2c_array_read(codec, main44_REG_Section_post_program,
+                ARRAY_SIZE(main44_REG_Section_post_program));
+
+        aic3262_change_book(codec, 0);
+
+        DBG(KERN_INFO "i2c_verify completed\n");
+        return 0;
+}
+
+
+int change_codec_power_status(struct snd_soc_codec * codec, int off_restore, int power_mask)
+{
+        int minidsp_power_mask;
+        u8 dac_status;
+        u8 adc_status;
+
+        minidsp_power_mask = 0;
+
+        aic3262_change_page (codec, 0);
+        aic3262_change_book (codec, 0);
+
+
+        switch (off_restore) {
+
+                case 0: /* Power-off the Codec */
+                        dac_status = snd_soc_read (codec, DAC_FLAG_R1);
+
+                        if(dac_status & 0x88) {
+                                minidsp_power_mask |= 0x1;
+                                snd_soc_update_bits(codec, PASI_DAC_DP_SETUP, 0xC0, 0x0);
+
+                                poll_dac(codec, 0x0, 0x0);
+                                poll_dac(codec, 0x1, 0x0);
+                        }
+
+                        adc_status = snd_soc_read (codec, ADC_FLAG_R1);
+
+                        if(adc_status & 0x44) {
+                                minidsp_power_mask |= 0x2;
+                                snd_soc_update_bits(codec, ADC_CHANNEL_POW, 0xC0, 0x0);
+
+                                poll_adc(codec, 0x0, 0x0);
+                                poll_adc(codec, 0x1, 0x0);
+                        }
+                break;
+                case 1: /* For Restoring Codec to Previous Power State */
+
+                        if(power_mask & 0x1) {
+
+                                snd_soc_update_bits(codec, PASI_DAC_DP_SETUP, 0xC0, 0xC0);
+
+                                poll_dac(codec, 0x0, 0x1);
+                                poll_dac(codec, 0x1, 0x1);
+                        }
+
+                        if(power_mask & 0x2) {
+
+                                snd_soc_update_bits(codec, ADC_CHANNEL_POW, 0xC0, 0xC0);
+
+                                poll_adc(codec, 0x0, 0x1);
+                                poll_adc(codec, 0x1, 0x1);
+                        }
+                break;
+                default:
+                        printk(KERN_ERR "#%s: Unknown Power State Requested..\n",
+                                __func__);
+        }
+
+        return minidsp_power_mask;
+
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function  : boot_minidsp
+ * Purpose  : for laoding the default minidsp mode for the first time .
+ *----------------------------------------------------------------------------
+ */
+int
+boot_minidsp(struct snd_soc_codec *codec, int new_mode)
+{
+        struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
+        struct process_flow *  pflows = &miniDSP_programs[new_mode];
+        int minidsp_stat;
+
+        int (*ptransfer)(struct snd_soc_codec *codec,
+                                reg_value *program_ptr,
+                                int size);
+
+        DBG("%s: switch  mode start\n", __func__);
+        if (new_mode >= ARRAY_SIZE(miniDSP_programs))
+                return 0; //  error condition
+        if (new_mode == aic326x->process_flow)
+                return 0;
+
+
+#ifndef MULTIBYTE_I2C
+        ptransfer = byte_i2c_array_transfer;
+#else
+        ptransfer = minidsp_i2c_multibyte_transfer;
+#endif
+
+        minidsp_stat = change_codec_power_status (codec, 0x0, 0x3);
+
+        ptransfer(codec, pflows->miniDSP_init,             pflows->init_size);
+        ptransfer(codec, pflows->miniDSP_A_values,  pflows->A_size);
+        ptransfer(codec, pflows->miniDSP_D_values,  pflows->D_size);
+        ptransfer(codec, pflows->miniDSP_post,           pflows->post_size);
+
+        aic326x->process_flow = new_mode;
+
+        change_codec_power_status(codec, 1, minidsp_stat);
+
+        aic3262_change_page( codec,0);
+        aic3262_change_book( codec,0);
+
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : aic3262_minidsp_program
+ * Purpose  : Program mini dsp for AIC3262 codec chip. This routine is
+ *              called from the aic3262 codec driver, if mini dsp programming
+ *              is enabled.
+ *----------------------------------------------------------------------------
+ */
+int aic3262_minidsp_program(struct snd_soc_codec *codec)
+{
+        struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
+        DBG(KERN_INFO "#AIC3262: programming mini dsp\n");
+
+#if defined(PROGRAM_MINI_DSP_first)
+        #ifdef DEBUG
+        DBG("#Verifying book 0\n");
+        i2c_verify_book0(codec);
+#endif
+        aic3262_change_book(codec, 0);
+        boot_minidsp(codec, 1);
+        aic326x->process_flow = 0;
+        aic3262_change_book(codec, 0);
+#ifdef DEBUG
+        DBG("#verifying book 0\n");
+        i2c_verify_book0(codec);
+#endif
+#endif
+#if defined(PROGRAM_MINI_DSP_second)
+#ifdef DEBUG
+        DBG("#Verifying book 0\n");
+        aic3262_change_book(codec, 0);
+#endif
+        boot_minidsp(codec, 0);
+        aic326x->process_flow = 1;
+#ifdef DEBUG
+        DBG("#verifying book 0\n");
+        aic3262_change_book(codec, 0);
+#endif
+#endif
+        return 0;
+}
+/*
+ *----------------------------------------------------------------------------
+ * Function : m_control_info
+ * Purpose  : This function is to initialize data for new control required to
+ *                      program the AIC3262 registers.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int m_control_info(struct snd_kcontrol *kcontrol,
+                                  struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->count = 1;
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 1;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : m_control_get
+ * Purpose  : This function is to read data of new control for
+ *                      program the AIC3262 registers.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int m_control_get(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+        u32 val;
+        u8 val1;
+
+        if (!strcmp(kcontrol->id.name, "Minidsp mode")) {
+                val = aic3262->process_flow;
+                ucontrol->value.integer.value[0] = val;
+                DBG(KERN_INFO "control get : mode=%d\n", aic3262->process_flow);
+        }
+        if (!strcmp(kcontrol->id.name, "DAC Adaptive mode Enable")) {
+                aic3262_change_book(codec, 80);
+                val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
+                ucontrol->value.integer.value[0] = ((val1>>1)&0x01);
+                DBG(KERN_INFO "control get : mode=%d\n", aic3262->process_flow);
+                aic3262_change_book(codec,0);
+        }
+        if (!strcmp(kcontrol->id.name, "ADC Adaptive mode Enable")) {
+                aic3262_change_book(codec, 40);
+                val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
+                ucontrol->value.integer.value[0] = ((val1>>1)&0x01);
+                DBG(KERN_INFO "control get : mode=%d\n", dmode);
+                aic3262_change_book(codec,0);
+        }
+
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : m_new_control_put
+ * Purpose  : new_control_put is called to pass data from user/application to
+ *                      the driver.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int m_control_put(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        u32 val;
+        u8 val1;
+        int mode = aic3262->process_flow;
+
+        DBG("n_control_put\n");
+        val = ucontrol->value.integer.value[0];
+        if (!strcmp(kcontrol->id.name, "Minidsp mode")) {
+                DBG(KERN_INFO "\nMini dsp put\n mode = %d, val=%d\n",
+                        aic3262->process_flow, val);
+                if (val != mode) {
+                        if (aic3262->mute_codec == 1) {
+                                i2c_verify_book0(codec);
+                                aic3262_change_book(codec, 0);
+                                boot_minidsp(codec, val);
+
+                                aic3262_change_book(codec, 0);
+                                i2c_verify_book0(codec);
+        /*                      update_kcontrols(codec, val);*/
+                        } else {
+                                printk(KERN_ERR
+                        " Cant Switch Processflows, Playback in progress");
+                        }
+                }
+        }
+
+        if (!strcmp(kcontrol->id.name, "DAC Adaptive mode Enable")) {
+                DBG(KERN_INFO "\nMini dsp put\n mode = %d, val=%d\n",
+                        aic3262->process_flow, val);
+                if (val != amode) {
+                        aic3262_change_book(codec, 80);
+                        val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
+                        aic3262_write(codec, 1, (val1&0xfb)|(val<<1));
+                        aic3262_change_book(codec,0);
+                }
+                amode = val;
+        }
+
+        if (!strcmp(kcontrol->id.name, "ADC Adaptive mode Enable")) {
+                DBG(KERN_INFO "\nMini dsp put\n mode = %d, val=%d\n",
+                        aic3262->process_flow, val);
+                if (val != dmode) {
+                        aic3262_change_book(codec, 40);
+                        val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
+                        aic3262_write(codec, 1, (val1&0xfb)|(val<<1));
+                        aic3262_change_book(codec,0);
+                }
+                dmode = val;
+        }
+
+        if (!strcmp(kcontrol->id.name, "Dump Regs Book0"))
+                i2c_verify_book0(codec);
+
+#if 0
+        if (!strcmp(kcontrol->id.name, "Verify minidsp program")) {
+
+                if (mode == 0) {
+                        DBG("Current mod=%d\nVerifying minidsp_D_regs", mode);
+                        byte_i2c_array_read(codec,  main44_miniDSP_D_reg_values,
+                                (main44_miniDSP_D_reg_values_COEFF_SIZE +
+                                main44_miniDSP_D_reg_values_INST_SIZE));
+                } else {
+                        byte_i2c_array_read(codec,
+                                Second_Rate_miniDSP_A_reg_values,
+                                (Second_Rate_miniDSP_A_reg_values_COEFF_SIZE +
+                                Second_Rate_miniDSP_A_reg_values_INST_SIZE));
+                        byte_i2c_array_read(codec,
+                                Second_Rate_miniDSP_D_reg_values,
+                                (Second_Rate_miniDSP_D_reg_values_COEFF_SIZE +
+                                Second_Rate_miniDSP_D_reg_values_INST_SIZE));
+                }
+        }
+#endif
+        DBG("\nmode = %d\n", mode);
+        return mode;
+}
+
+/************************** MUX CONTROL section *****************************/
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_info_minidsp_mux
+ * Purpose  : info routine for mini dsp mux control amixer kcontrols
+ *----------------------------------------------------------------------------
+ */
+static int __new_control_info_minidsp_mux(struct snd_kcontrol *kcontrol,
+                                          struct snd_ctl_elem_info *uinfo)
+{
+        int index,index2;
+        int ret_val = -1;
+
+
+        for (index = 0; index < ARRAY_SIZE(main44_MUX_controls); index++) {
+                if (strstr(kcontrol->id.name, main44_MUX_control_names[index]))
+                        break;
+        }
+        if (index < ARRAY_SIZE(main44_MUX_controls))
+                {
+                uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+                uinfo->count = 1;
+                uinfo->value.integer.min = MIN_MUX_CTRL;
+                uinfo->value.integer.max = MAX_MUX_CTRL;
+                ret_val = 0;
+        }
+
+        #if 1
+        else{
+                printk(" The second rate kcontrol id name is====== %s\n",kcontrol->id.name);
+
+
+        for (index2 = 0; index < ARRAY_SIZE(base_speaker_SRS_MUX_controls); index2++) {
+                if (strstr(kcontrol->id.name, base_speaker_SRS_MUX_control_names[index2]))
+                        break;
+                }
+                if (index < ARRAY_SIZE(base_speaker_SRS_MUX_controls))
+                {
+                uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+                uinfo->count = 1;
+                uinfo->value.integer.min = MIN_MUX_CTRL;
+                uinfo->value.integer.max = MAX_MUX_CTRL;
+                ret_val = 0;
+                }
+        }
+
+        #endif
+
+        return ret_val;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_get_minidsp_mux
+ *
+ * Purpose  : get routine for  mux control amixer kcontrols,
+ *   read current register values to user.
+ *   Used for for mini dsp 'MUX control' amixer controls.
+ *----------------------------------------------------------------------------
+ */
+static int __new_control_get_minidsp_mux(struct snd_kcontrol *kcontrol,
+                                         struct snd_ctl_elem_value *ucontrol)
+{
+
+        ucontrol->value.integer.value[0] = kcontrol->private_value;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_put_minidsp_mux
+ *
+ * Purpose  : put routine for amixer kcontrols, write user values to registers
+ *                      values. Used for for mini dsp 'MUX control' amixer controls.
+ *----------------------------------------------------------------------------
+ */
+static int __new_control_put_minidsp_mux(struct snd_kcontrol *kcontrol,
+                                        struct snd_ctl_elem_value *ucontrol)
+{
+        u8 data[MUX_CTRL_REG_SIZE + 1];
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        int index = 1;
+        int user_value = ucontrol->value.integer.value[0];
+        struct i2c_client *i2c;
+        u8 value[2], swap_reg_pre, swap_reg_post;
+        u8 page;
+        int ret_val = -1, array_size;
+        control *array;
+        char **array_names;
+        char *control_name, *control_name1, *control_name2;
+        struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
+        i2c = codec->control_data;
+
+
+
+        if (aic326x->process_flow == 0) {
+                DBG("#the current process flow is %d", aic326x->process_flow);
+                array = main44_MUX_controls;
+                array_size = ARRAY_SIZE(main44_MUX_controls);
+                array_names = main44_MUX_control_names;
+                control_name = "Stereo_Mux_TwoToOne_1";
+                control_name1 = "Mono_Mux_1_1";
+                }
+
+#if 0
+
+                /* Configure only for process flow  1 controls */
+                if (strcmp(kcontrol->id.name, control_name) &&
+                        strcmp(kcontrol->id.name, control_name1))
+                        return 0;
+        } else {
+                array = Second_Rate_MUX_controls;
+                array_size = ARRAY_SIZE(Second_Rate_MUX_controls);
+                array_names = Second_Rate_MUX_control_names;
+                control_name = "Stereo_Mux_TwoToOne_1_Second";
+                control_name1 = "Mono_Mux_1_Second";
+                control_name2 = "Mono_Mux_4_Second";
+
+                /* Configure only for process flow 2 controls */
+                if (strcmp(kcontrol->id.name, control_name1) &&
+                        strcmp(kcontrol->id.name, control_name2))
+                        return 0;
+        }
+
+#endif
+
+        page = array[index].control_page;
+
+        DBG("#user value = 0x%x\n", user_value);
+        for (index = 0; index < array_size; index++) {
+                if (strstr(kcontrol->id.name, array_names[index]))
+                        break;
+        }
+        if (index < array_size) {
+                DBG(KERN_INFO "#Index %d Changing to Page %d\n", index,
+                        array[index].control_page);
+
+                aic3262_change_book(codec,
+                                        array[index].control_book);
+                aic3262_change_page(codec,
+                                        array[index].control_page);
+
+                if (!strcmp(array_names[index], control_name)) {
+                        if (user_value > 0) {
+                                data[1] = 0x00;
+                                data[2] = 0x00;
+                                data[3] = 0x00;
+                        } else {
+                                data[1] = 0xFF;
+                                data[2] = 0xFf;
+                                data[3] = 0xFF;
+                        }
+                } else {
+                        if (user_value > 0) {
+                                data[1] =
+                                        (u8) ((user_value >> 16) &
+                                                  AIC3262_8BITS_MASK);
+                                data[2] =
+                                        (u8) ((user_value >> 8) &
+                                                  AIC3262_8BITS_MASK);
+                                data[3] =
+                                        (u8)((user_value) & AIC3262_8BITS_MASK);
+                        }
+                }
+                /* start register address */
+                data[0] = array[index].control_base;
+
+                DBG(KERN_INFO
+                "#Writing %d %d %d \r\n", data[0], data[1], data[2]);
+
+                ret_val = i2c_master_send(i2c, data, MUX_CTRL_REG_SIZE + 1);
+
+                if (ret_val != MUX_CTRL_REG_SIZE + 1)
+                        printk(KERN_ERR "i2c_master_send transfer failed\n");
+                else {
+                        /* store the current level */
+                        kcontrol->private_value = user_value;
+                        ret_val = 0;
+                        /* Enable adaptive filtering for ADC/DAC */
+                }
+
+                /* Perform a BUFFER SWAP Command. Check if we are currently not
+                 * in Page 8, if so, swap to Page 8 first
+                 */
+
+                value[0] = 1;
+
+                if (i2c_master_send(i2c, value, 1) != 1)
+                        printk(KERN_ERR "Can not write register address\n");
+
+                /* Read the Value of the Page 8 Register 1 which controls the
+                   Adaptive Switching Mode */
+                if (i2c_master_recv(i2c, value, 1) != 1)
+                        printk(KERN_ERR "Can not read codec registers\n");
+
+                swap_reg_pre = value[0];
+                /* Write the Register bit updates */
+                value[1] = value[0] | 1;
+                value[0] = 1;
+
+                if (i2c_master_send(i2c, value, 2) != 2)
+                        printk(KERN_ERR "Can not write register address\n");
+
+                value[0] = 1;
+                /* verify buffer swap */
+                if (i2c_master_send(i2c, value, 1) != 1)
+                        printk(KERN_ERR "Can not write register address\n");
+
+                /* Read the Value of the Page 8 Register 1 which controls the
+                   Adaptive Switching Mode */
+                if (i2c_master_recv(i2c, &swap_reg_post, 1) != 1)
+                        printk(KERN_ERR "Can not read codec registers\n");
+
+                if ((swap_reg_pre == 4 && swap_reg_post == 6)
+                        || (swap_reg_pre == 6 && swap_reg_post == 4))
+                        DBG("Buffer swap success\n");
+                else
+                        printk(KERN_ERR
+                        "Buffer swap...FAILED\nswap_reg_pre=%x, \
+                        swap_reg_post=%x\n", swap_reg_pre, swap_reg_post);
+
+        }
+        /* update the new buffer value in the old, just swapped out buffer */
+        aic3262_change_book(codec, array[index].control_book);
+        aic3262_change_page(codec, array[index].control_page);
+        ret_val = i2c_master_send(i2c, data, MUX_CTRL_REG_SIZE + 1);
+        ret_val = 0;
+
+        aic3262_change_book(codec, 0);
+        return ret_val;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : minidsp_mux_ctrl_mixer_controls
+ *
+ * Purpose  : Add amixer kcontrols for mini dsp mux controls,
+ *----------------------------------------------------------------------------
+ */
+static int minidsp_mux_ctrl_mixer_controls(struct snd_soc_codec *codec,
+                                                int size, control *cntl,
+                                                char **name)
+{
+        int i, err;
+        int val1;
+
+        printk("%d mixer controls for mini dsp MUX\n", size);
+        if (size) {
+                for (i = 0; i < size; i++) {
+
+                        snd_mux_controls[i].name = name[i];
+                        snd_mux_controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+                        snd_mux_controls[i].access =
+                                SNDRV_CTL_ELEM_ACCESS_READWRITE;
+                        snd_mux_controls[i].info =
+                                __new_control_info_minidsp_mux;
+                        snd_mux_controls[i].get = __new_control_get_minidsp_mux;
+                        snd_mux_controls[i].put = __new_control_put_minidsp_mux;
+                        /*
+                         *  TBD: read volume reg and update the index number
+                         */
+                        aic3262_change_book(codec, cntl[i].control_book);
+                        aic3262_change_page(codec, cntl[i].control_page);
+                        val1 = i2c_smbus_read_byte_data(codec->control_data,
+                                        cntl[i].control_base);
+                        DBG(KERN_INFO "Control data %x\n", val1);
+                        /*
+                        if( val1 >= 0 )
+                                snd_mux_controls[i].private_value = val1;
+                        else
+                                snd_mux_controls[i].private_value = 0;
+                        */
+                        DBG(KERN_INFO
+                                "the value of amixer control mux=%d", val1);
+                        if (val1 >= 0 && val1 != 255)
+                                snd_mux_controls[i].private_value = val1;
+                        else
+                                snd_mux_controls[i].private_value = 0;
+
+                        snd_mux_controls[i].count = 0;
+
+                        err = snd_ctl_add(codec->card->snd_card,
+                                snd_ctl_new1(&snd_mux_controls[i],
+                                                   codec));
+                        if (err < 0)
+                                printk(KERN_ERR
+                                        "%s:Invalid control %s\n", __FILE__,
+                                        snd_mux_controls[i].name);
+                }
+        }
+        return 0;
+}
+
+/*-------------------------  Volume Controls  -----------------------*/
+static int volume_lite_table[] = {
+
+        0x00000D, 0x00000E, 0x00000E, 0x00000F,
+        0x000010, 0x000011, 0x000012, 0x000013,
+        0x000015, 0x000016, 0x000017, 0x000018,
+        0x00001A, 0x00001C, 0x00001D, 0x00001F,
+        0x000021, 0x000023, 0x000025, 0x000027,
+        0x000029, 0x00002C, 0x00002F, 0x000031,
+        0x000034, 0x000037, 0x00003B, 0x00003E,
+        0x000042, 0x000046, 0x00004A, 0x00004F,
+        0x000053, 0x000058, 0x00005D, 0x000063,
+        0x000069, 0x00006F, 0x000076, 0x00007D,
+        0x000084, 0x00008C, 0x000094, 0x00009D,
+        0x0000A6, 0x0000B0, 0x0000BB, 0x0000C6,
+        0x0000D2, 0x0000DE, 0x0000EB, 0x0000F9,
+        0x000108, 0x000118, 0x000128, 0x00013A,
+        0x00014D, 0x000160, 0x000175, 0x00018B,
+        0x0001A3, 0x0001BC, 0x0001D6, 0x0001F2,
+        0x000210, 0x00022F, 0x000250, 0x000273,
+        0x000298, 0x0002C0, 0x0002E9, 0x000316,
+        0x000344, 0x000376, 0x0003AA, 0x0003E2,
+        0x00041D, 0x00045B, 0x00049E, 0x0004E4,
+        0x00052E, 0x00057C, 0x0005D0, 0x000628,
+        0x000685, 0x0006E8, 0x000751, 0x0007C0,
+        0x000836, 0x0008B2, 0x000936, 0x0009C2,
+        0x000A56, 0x000AF3, 0x000B99, 0x000C49,
+        0x000D03, 0x000DC9, 0x000E9A, 0x000F77,
+        0x001062, 0x00115A, 0x001262, 0x001378,
+        0x0014A0, 0x0015D9, 0x001724, 0x001883,
+        0x0019F7, 0x001B81, 0x001D22, 0x001EDC,
+        0x0020B0, 0x0022A0, 0x0024AD, 0x0026DA,
+        0x002927, 0x002B97, 0x002E2D, 0x0030E9,
+        0x0033CF, 0x0036E1, 0x003A21, 0x003D93,
+        0x004139, 0x004517, 0x00492F, 0x004D85,
+        0x00521D, 0x0056FA, 0x005C22, 0x006197,
+        0x006760, 0x006D80, 0x0073FD, 0x007ADC,
+        0x008224, 0x0089DA, 0x009205, 0x009AAC,
+        0x00A3D7, 0x00B7D4, 0x00AD8C, 0x00C2B9,
+        0x00CE43, 0x00DA7B, 0x00E76E, 0x00F524,
+        0x0103AB, 0x01130E, 0x01235A, 0x01349D,
+        0x0146E7, 0x015A46, 0x016ECA, 0x018486,
+        0x019B8C, 0x01B3EE, 0x01CDC3, 0x01E920,
+        0x02061B, 0x0224CE, 0x024553, 0x0267C5,
+        0x028C42, 0x02B2E8, 0x02DBD8, 0x030736,
+        0x033525, 0x0365CD, 0x039957, 0x03CFEE,
+        0x0409C2, 0x044703, 0x0487E5, 0x04CCA0,
+        0x05156D, 0x05628A, 0x05B439, 0x060ABF,
+        0x066666, 0x06C77B, 0x072E50, 0x079B3D,
+        0x080E9F, 0x0888D7, 0x090A4D, 0x09936E,
+        0x0A24B0, 0x0ABE8D, 0x0B6188, 0x0C0E2B,
+        0x0CC509, 0x0D86BD, 0x0E53EB, 0x0F2D42,
+        0x101379, 0x110754, 0x1209A3, 0x131B40,
+        0x143D13, 0x157012, 0x16B543, 0x180DB8,
+        0x197A96, 0x1AFD13, 0x1C9676, 0x1E481C,
+        0x201373, 0x21FA02, 0x23FD66, 0x261F54,
+        0x28619A, 0x2AC625, 0x2D4EFB, 0x2FFE44,
+        0x32D646, 0x35D96B, 0x390A41, 0x3C6B7E,
+        0x400000, 0x43CAD0, 0x47CF26, 0x4C106B,
+        0x50923B, 0x55586A, 0x5A6703, 0x5FC253,
+        0x656EE3, 0x6B7186, 0x71CF54, 0x788DB4,
+        0x7FB260,
+};
+
+static struct snd_kcontrol_new snd_vol_controls[MAX_VOLUME_CONTROLS];
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_info_main44_minidsp_volume
+ * Purpose  : info routine for volumeLite amixer kcontrols
+ *----------------------------------------------------------------------------
+ */
+
+static int
+__new_control_info_minidsp_volume(struct snd_kcontrol *kcontrol,
+                                  struct snd_ctl_elem_info *uinfo)
+{
+        int index, index8;
+        int ret_val = -1;
+
+        for (index = 0; index < ARRAY_SIZE(main44_VOLUME_controls); index++) {
+                if (strstr
+                        (kcontrol->id.name, main44_VOLUME_control_names[index]))
+                        break;
+        }
+
+        for (index8 = 0; index8 < ARRAY_SIZE(base_speaker_SRS_VOLUME_controls);
+                        index8++) {
+                if (strstr
+                        (kcontrol->id.name,
+                        base_speaker_SRS_VOLUME_control_names[index]))
+                        break;
+        }
+
+        if ((index < ARRAY_SIZE(main44_VOLUME_controls))
+
+                || (index8 < ARRAY_SIZE(base_speaker_SRS_VOLUME_controls))) {
+                uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+                uinfo->count = 1;
+                uinfo->value.integer.min = MIN_VOLUME;
+                uinfo->value.integer.max = MAX_VOLUME;
+                ret_val = 0;
+        }
+        return ret_val;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_get_main44_minidsp_vol
+ * Purpose  : get routine for amixer kcontrols, read current register
+ *               values. Used for for mini dsp 'VolumeLite' amixer controls.
+ *----------------------------------------------------------------------------
+ */
+static int
+__new_control_get_minidsp_volume(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        ucontrol->value.integer.value[0] = kcontrol->private_value;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : __new_control_put_main44_minidsp_volume
+ * Purpose  : put routine for amixer kcontrols, write user values to registers
+ *              values. Used for for mini dsp 'VolumeLite' amixer controls.
+ *----------------------------------------------------------------------------
+ */
+static int
+__new_control_put_minidsp_volume(struct snd_kcontrol *kcontrol,
+                                 struct snd_ctl_elem_value *ucontrol)
+{
+        u8 data[4];
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        int user_value = ucontrol->value.integer.value[0];
+        struct i2c_client *i2c = codec->control_data;
+        int ret_val = -1;
+        int coeff;
+        u8 value[2], swap_reg_pre, swap_reg_post;
+        struct aic3262_priv *aic3262 = snd_soc_codec_get_drvdata(codec);
+
+        control *volume_controls = NULL;
+        printk(KERN_INFO "user value = 0x%x\n", user_value);
+
+        if (aic3262->process_flow == 0)
+                volume_controls = main44_VOLUME_controls;
+
+        else
+                volume_controls = base_speaker_SRS_VOLUME_controls;
+
+
+        aic3262_change_book(codec, volume_controls->control_book);
+        aic3262_change_page(codec, volume_controls->control_page);
+
+        coeff = volume_lite_table[user_value << 1];
+
+        data[1] = (u8) ((coeff >> 16) & AIC3262_8BITS_MASK);
+        data[2] = (u8) ((coeff >> 8) & AIC3262_8BITS_MASK);
+        data[3] = (u8) ((coeff) & AIC3262_8BITS_MASK);
+
+        /* Start register address */
+        data[0] = volume_controls->control_base;
+        ret_val = i2c_master_send(i2c, data, VOLUME_REG_SIZE + 1);
+        if (ret_val != VOLUME_REG_SIZE + 1)
+                printk(KERN_ERR "i2c_master_send transfer failed\n");
+        else {
+                /* store the current level */
+                kcontrol->private_value = user_value;
+                ret_val = 0;
+        }
+        /* Initiate buffer swap */
+        value[0] = 1;
+
+        if (i2c_master_send(i2c, value, 1) != 1)
+                printk(KERN_ERR "Can not write register address\n");
+
+        /* Read the Value of the Page 8 Register 1 which controls the
+           Adaptive Switching Mode */
+        if (i2c_master_recv(i2c, value, 1) != 1)
+                printk(KERN_ERR "Can not read codec registers\n");
+
+        swap_reg_pre = value[0];
+        /* Write the Register bit updates */
+        value[1] = value[0] | 1;
+        value[0] = 1;
+        if (i2c_master_send(i2c, value, 2) != 2)
+                printk(KERN_ERR "Can not write register address\n");
+
+        value[0] = 1;
+        /* verify buffer swap */
+        if (i2c_master_send(i2c, value, 1) != 1)
+                printk(KERN_ERR "Can not write register address\n");
+
+        /* Read the Value of the Page 8 Register 1 which controls the
+           Adaptive Switching Mode */
+        if (i2c_master_recv(i2c, &swap_reg_post, 1) != 1)
+                printk(KERN_ERR "Can not read codec registers\n");
+
+        if ((swap_reg_pre == 4 && swap_reg_post == 6)
+                || (swap_reg_pre == 6 && swap_reg_post == 4))
+                DBG("Buffer swap success\n");
+        else
+                DBG("Buffer swap...FAILED\nswap_reg_pre=%x, swap_reg_post=%x\n",
+                         swap_reg_pre, swap_reg_post);
+
+        /* update the new buffer value in the old, just swapped out buffer */
+        aic3262_change_book(codec, volume_controls->control_book);
+        aic3262_change_page(codec, volume_controls->control_page);
+        i2c_master_send(i2c, data, MUX_CTRL_REG_SIZE + 1);
+
+        aic3262_change_book(codec, 0);
+
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : minidsp_volume_main44_mixer_controls
+ * Purpose  : Add amixer kcontrols for mini dsp volume Lite controls,
+ *----------------------------------------------------------------------------
+ */
+static int minidsp_volume_mixer_controls(struct snd_soc_codec *codec)
+{
+        int i, err, no_volume_controls;
+        static char volume_control_name[MAX_VOLUME_CONTROLS][40];
+
+        /*        ADD first process volume controls        */
+        no_volume_controls = ARRAY_SIZE(main44_VOLUME_controls);
+
+        printk(KERN_INFO " %d mixer controls for mini dsp 'volumeLite'\n",
+                no_volume_controls);
+
+        if (no_volume_controls) {
+
+                for (i = 0; i < no_volume_controls; i++) {
+                        strcpy(volume_control_name[i],
+                                   main44_VOLUME_control_names[i]);
+                        strcat(volume_control_name[i], VOLUME_KCONTROL_NAME);
+
+                        printk(KERN_ERR "Volume controls: %s\n",
+                                volume_control_name[i]);
+
+                        snd_vol_controls[i].name = volume_control_name[i];
+                        snd_vol_controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+                        snd_vol_controls[i].access =
+                                SNDRV_CTL_ELEM_ACCESS_READWRITE;
+                        snd_vol_controls[i].info =
+                                __new_control_info_minidsp_volume;
+                        snd_vol_controls[i].get =
+                                __new_control_get_minidsp_volume;
+                        snd_vol_controls[i].put =
+                                __new_control_put_minidsp_volume;
+                        /*
+                         *        TBD: read volume reg and update the index number
+                         */
+                        snd_vol_controls[i].private_value = 0;
+                        snd_vol_controls[i].count = 0;
+
+                        err = snd_ctl_add(codec->card->snd_card,
+                                          snd_ctl_new1(&snd_vol_controls[i],
+                                                           codec));
+                        if (err < 0) {
+                                printk(KERN_ERR
+                                        "%s:Invalid control %s\n", __FILE__,
+                                        snd_vol_controls[i].name);
+                        }
+                }
+        }
+
+
+        /*        ADD second process volume controls      */
+        no_volume_controls = ARRAY_SIZE(base_speaker_SRS_VOLUME_controls);
+
+        printk(KERN_ERR " %d mixer controls for mini dsp 'volumeLite'\n",
+                no_volume_controls);
+
+        if (no_volume_controls) {
+
+                for (i = 0; i < no_volume_controls; i++) {
+                        strcpy(volume_control_name[i],
+                                   base_speaker_SRS_VOLUME_control_names[i]);
+                        strcat(volume_control_name[i], VOLUME_KCONTROL_NAME);
+
+                        printk(KERN_ERR "Volume controls: %s\n",
+                                volume_control_name[i]);
+
+                        snd_vol_controls[i].name = volume_control_name[i];
+                        snd_vol_controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+                        snd_vol_controls[i].access =
+                                SNDRV_CTL_ELEM_ACCESS_READWRITE;
+                        snd_vol_controls[i].info =
+                                __new_control_info_minidsp_volume;
+                        snd_vol_controls[i].get =
+                                __new_control_get_minidsp_volume;
+                        snd_vol_controls[i].put =
+                                __new_control_put_minidsp_volume;
+                        /*
+                         *        TBD: read volume reg and update the index number
+                         */
+                        snd_vol_controls[i].private_value = 0;
+                        snd_vol_controls[i].count = 0;
+
+                        err = snd_ctl_add(codec->card->snd_card,
+                                          snd_ctl_new1(&snd_vol_controls[i],
+                                                           codec));
+                        if (err < 0) {
+                                printk(KERN_ERR
+                                        "%s:Invalid control %s\n", __FILE__,
+                                           snd_vol_controls[i].name);
+                        }
+                }
+        }
+
+        return 0;
+}
+
+/*
+ *--------------------------------------------------------------------------
+ * Function : aic3262_add_minidsp_controls
+ * Purpose :  Configures the AMIXER Control Interfaces that can be exercised by
+ *                      the user at run-time. Utilizes the  the snd_adaptive_controls[]
+ *                      array to specify two run-time controls.
+ *---------------------------------------------------------------------------
+ */
+int aic3262_add_minidsp_controls(struct snd_soc_codec *codec)
+{
+#ifdef ADD_MINI_DSP_CONTROLS
+        int i, err, no_mux_controls,no_mux_controls1;
+        /* add mode k control */
+        for (i = 0; i < ARRAY_SIZE(aic3262_minidsp_controls); i++) {
+                err = snd_ctl_add(codec->card->snd_card,
+                snd_ctl_new1(&aic3262_minidsp_controls[i], codec));
+                if (err < 0) {
+                        printk(KERN_ERR "Invalid control\n");
+                        return err;
+                }
+        }
+
+
+        /* add mux controls */
+        no_mux_controls = ARRAY_SIZE(main44_MUX_controls);
+        minidsp_mux_ctrl_mixer_controls(codec, no_mux_controls,
+                main44_MUX_controls, main44_MUX_control_names);
+
+
+        no_mux_controls1 = ARRAY_SIZE(base_speaker_SRS_MUX_controls);
+        minidsp_mux_ctrl_mixer_controls(codec, no_mux_controls1,
+                base_speaker_SRS_MUX_controls, base_speaker_SRS_MUX_control_names);
+
+
+        /* add volume controls*/
+        minidsp_volume_mixer_controls(codec);
+#endif /* ADD_MINI_DSP_CONTROLS */
+        return 0;
+}
+
+MODULE_DESCRIPTION("ASoC TLV320AIC3262 miniDSP driver");
+MODULE_AUTHOR("Y Preetam Sashank Reddy <preetam@mistralsolutions.com>");
+MODULE_LICENSE("GPL");
+#endif /* End of CONFIG_MINI_DSP */
diff --git a/sound/soc/codecs/tlv320aic326x_mini-dsp.h b/sound/soc/codecs/tlv320aic326x_mini-dsp.h
new file mode 100644
index 00000000000..bebb12fa680
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x_mini-dsp.h
@@ -0,0 +1,128 @@
+/*
+ * linux/sound/soc/codecs/tlv320aic3262_mini-dsp.h
+ *
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * History:
+ * Rev 0.1   Added the multiconfig support     17-08-2011
+ *
+ * Rev 0.2   Migrated for aic3262 nVidia
+ *        21-10-2011
+ */
+
+#ifndef _TLV320AIC3262_MINI_DSP_H
+#define _TLV320AIC3262_MINI_DSP_H
+
+/* defines */
+
+#define MAXCONFIG 4
+
+//#define DEBUG_MINIDSP_LOADING
+
+/* Select the functionalities to be used in mini dsp module */
+#define PROGRAM_MINI_DSP_first
+//#define PROGRAM_MINI_DSP_second
+#define PROGRAM_CODEC_REG_SECTIONS
+#define ADD_MINI_DSP_CONTROLS
+
+/* use the following macros to select between burst and byte mode of i2c
+ * Byte mode uses standard read & write as provides debugging information if enabled
+ * if enabled.
+ * Multibyte should be used for production codes where performance is priority
+ */
+//#define MULTIBYTE_I2C
+#undef MULTIBYTE_I2C
+
+typedef struct {
+        u8 reg_off;
+        u8 reg_val;
+} reg_value;
+
+/*CONTROL LOCATIONS*/
+typedef struct {
+        u8 control_book;        /*coefficient book location*/
+        u8 control_page;        /*coefficient page location*/
+        u8 control_base;        /*coefficient base address within page*/
+        u8 control_mute_flag;   /*non-zero means muting required*/
+        u8 control_string_index;        /*string table index*/
+} control;
+
+/* volume ranges from -110db to 6db
+ * amixer controls does not accept negative values
+ * Therefore we are normalizing values to start from value 0
+ * value 0 corresponds to -110db and 116 to 6db
+ */
+#define MAX_VOLUME_CONTROLS                             2
+#define MIN_VOLUME                                      0
+#define MAX_VOLUME                                      116
+#define VOLUME_REG_SIZE                                 3       /*  3 bytes */
+#define VOLUME_KCONTROL_NAME                    "(0=-110dB, 116=+6dB)"
+
+#define FILT_CTL_NAME_ADC       "ADC adaptive filter(0=Disable, 1=Enable)"
+#define FILT_CTL_NAME_DAC       "DAC adaptive filter(0=Disable, 1=Enable)"
+#define COEFF_CTL_NAME_ADC      "ADC coeff Buffer(0=Buffer A, 1=Buffer B)"
+#define COEFF_CTL_NAME_DAC      "DAC coeff Buffer(0=Buffer A, 1=Buffer B)"
+
+#define BUFFER_PAGE_ADC                                 0x8
+#define BUFFER_PAGE_DAC                                 0x2c
+
+#define ADAPTIVE_MAX_CONTROLS                   4
+
+/*
+ * MUX controls,  3 bytes of control data.
+ */
+#define MAX_MUX_CONTROLS                        2
+#define MIN_MUX_CTRL                            0
+#define MAX_MUX_CTRL                            2
+#define MUX_CTRL_REG_SIZE                       3       /*  3 bytes */
+
+#define MINIDSP_PARSING_START                   0
+#define MINIDSP_PARSING_END                     (-1)
+
+#define CODEC_REG_DONT_IGNORE                   0
+#define CODEC_REG_IGNORE                        1
+
+#define CODEC_REG_PRE_INIT              0
+#define CODEC_REG_POST_INIT             1
+#define INIT_SEQ_DELIMITER              255     /* Delimiter register */
+#define DELIMITER_COUNT                 2       /* 2 delimiter entries */
+
+/* Parser info structure */
+typedef struct {
+        char page_num;
+        char burst_array[129];
+        int burst_size;
+        int current_loc;
+        int book_change;CONFIG_MINI_DSP
+        u8 book_no;
+} minidsp_parser_data;
+
+/* I2c Page Change Structure */
+typedef struct {
+        char burst_array[4];
+} minidsp_i2c_page;
+
+/* This macro defines the total size of the miniDSP parser arrays
+ * that the driver will maintain as a data backup.
+ * The total memory requirement will be around
+ * sizeof(minidsp_parser_data) * 48 = 138 * 32 = 4416 bytes
+ */
+#define MINIDSP_PARSER_ARRAY_SIZE           200
+
+extern int
+minidsp_i2c_multibyte_transfer(struct snd_soc_codec *, reg_value *, int);
+extern int byte_i2c_array_transfer(struct snd_soc_codec *, reg_value *, int);
+extern void minidsp_multiconfig(struct snd_soc_codec *,reg_value *, int ,reg_value *, int );
+extern int reg_def_conf(struct snd_soc_codec *);
+
+#endif
diff --git a/sound/soc/codecs/tlv320aic326x_minidsp_config.c b/sound/soc/codecs/tlv320aic326x_minidsp_config.c
new file mode 100644
index 00000000000..e34ffbe2ca8
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic326x_minidsp_config.c
@@ -0,0 +1,495 @@
+/*
+ * linux/sound/soc/codecs/tlv320aic326x_minidsp_config.c
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * The TLV320AIC3262 is a flexible, low-power, low-voltage stereo audio
+ * codec with digital microphone inputs and programmable outputs.
+ *
+ * History:
+ *
+ * Rev 0.1   Added the multiconfig support           17-08-2011
+ *
+ * Rev 0.2   Migrated for aic3262 nVidia
+ *           21-10-2011
+ */
+
+/*
+ *****************************************************************************
+ * INCLUDES
+ *****************************************************************************
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/types.h>
+#include <linux/kdev_t.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <sound/soc.h>
+#include <sound/core.h>
+#include <sound/soc-dapm.h>
+#include <sound/control.h>
+#include <linux/time.h>         /* For timing computations */
+#include "tlv320aic326x.h"
+#include "tlv320aic326x_mini-dsp.h"
+
+#if 0
+#include "Patch_base_jazz_Rate48_pps_driver.h"
+#include "Patch_base_main_Rate48_pps_driver.h"
+#include "Patch_base_pop_Rate48_pps_driver.h"
+#include "Patch_base_rock_Rate48_pps_driver.h"
+#endif
+
+#ifdef CONFIG_MINI_DSP
+
+#define MAX_CONFIG_D_ARRAYS 4
+#define MAX_CONFIG_A_ARRAYS 0
+#define MAX_CONFIG_ARRAYS   4
+#define MINIDSP_DMODE 0
+#define MINIDSP_AMODE 1
+
+/*
+ *****************************************************************************
+ * LOCAL STATIC DECLARATIONS
+ *****************************************************************************
+ */
+static int multibyte_coeff_change(struct snd_soc_codec *codec, int);
+
+static int m_control_get(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol);
+static int m_control_put(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol);
+
+/* k-control macros used for miniDSP related Kcontrols */
+#define SOC_SINGLE_VALUE_M(xmax, xinvert) \
+        ((unsigned long)&(struct soc_mixer_control) \
+        {.max = xmax, \
+        .invert = xinvert})
+#define SOC_SINGLE_M(xname, max, invert) \
+{\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .info = m_control_info, .get = m_control_get,\
+        .put = m_control_put, \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+        .private_value = SOC_SINGLE_VALUE_M(max, invert) }
+#define SOC_SINGLE_AIC3262_M(xname) \
+{\
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+        .info = m_control_info, .get = m_control_get,\
+        .put = m_control_put, \
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+}
+
+
+/* The Multi-Configurations generated through PPS GDE has been
+ * named as Rock, Pop, Jazz and Main. These were the Configurations
+ * that were used while testing this AUdio Driver. If the user
+ * creates Process-flow with different names, it is advised to
+ * modify the names present in the below array.
+ */
+static const char *multi_config_support_DAC[] = {
+        "ROCK",
+        "POP",
+        "JAZZ",
+        "MAIN",
+};
+
+/* SOC_ENUM Declaration and kControl for switching Configurations
+ * at run-time.
+ */
+static const struct soc_enum aic3262_enum =
+        SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(multi_config_support_DAC),
+                        multi_config_support_DAC);
+
+static const struct snd_kcontrol_new aic3262_minidsp_controls1[] = {
+
+        SOC_ENUM_EXT("Multiconfig support for DAC",
+                aic3262_enum, m_control_get, m_control_put),
+
+};
+
+
+/*
+ * multibyte_config
+ *
+ * This structure has been devised to maintain information about each
+ * configuration provided with the PPS GDE Processflow. For each
+ * configuration, the Driver needs to know where the starting offset
+ * of the Coefficient change, Total Size of Coefficients being affected,
+ * and the Instruction Sizes.
+ * This has to be replicated for both miniDSP_A and miniDSP_D
+ */
+
+#if 0
+struct multibyte_config {
+        reg_value *regs;
+        unsigned int d_coeff_start;
+        unsigned int d_coeff_size;
+        unsigned int d_inst_start;
+        unsigned int d_inst_size;
+        unsigned int a_coeff_start;
+        unsigned int a_coeff_size;
+        unsigned int a_inst_start;
+        unsigned int a_inst_size;
+} config_array[][2][MAX_CONFIG_ARRAYS] = {
+        /* Process flow 1 */
+        {
+                {
+                        /* DAC */
+                        {rock_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
+                        {pop_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
+                        {jazz_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
+                        {main_D_reg_values, 0, 67, 67, 0, 0, 0, 0, 0},
+                },
+                /* ADC */
+                {},
+        },
+
+        /* Process flow 2 */
+        {
+#if 0
+                {
+                        {main, 0, 0, 0, 0, 0, 0, 0, 0},
+                        {pop, 0, 0, 0, 0, 0, 0, 0, 0},
+                        {jazz, 0, 0, 0, 0, 0, 0, 0, 0},
+                        {rock, 0, 0, 0, 0, 0, 0, 0, 0},
+                },
+                /* ADC */
+                {},
+#endif
+        },
+};
+
+#else
+struct multibyte_config {
+        reg_value *regs;
+        unsigned int d_coeff_start;
+        unsigned int d_coeff_size;
+        unsigned int d_inst_start;
+        unsigned int d_inst_size;
+        unsigned int a_coeff_start;
+        unsigned int a_coeff_size;
+        unsigned int a_inst_start;
+        unsigned int a_inst_size;
+} config_array[][2][MAX_CONFIG_ARRAYS] = {
+        /* Process flow 1 */
+        {
+                {
+                        /* DAC */
+                                {},
+                },
+                /* ADC */
+                {},
+        },
+
+        /* Process flow 2 */
+        {
+#if 0
+                {
+                        {main, 0, 0, 0, 0, 0, 0, 0, 0},
+                        {pop, 0, 0, 0, 0, 0, 0, 0, 0},
+                        {jazz, 0, 0, 0, 0, 0, 0, 0, 0},
+                        {rock, 0, 0, 0, 0, 0, 0, 0, 0},
+                },
+                /* ADC */
+                {},
+#endif
+        },
+};
+#endif
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : m_control_get
+ * Purpose  : This function is to read data of new control for
+ *            program the AIC3262 registers.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int m_control_get(struct snd_kcontrol *kcontrol,
+                         struct snd_ctl_elem_value *ucontrol)
+{
+
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
+        u32 val = 0;
+        u32 mode = aic326x->process_flow;
+
+
+        if (!strcmp(kcontrol->id.name, "Multiconfig support for DAC"))
+                val = aic326x->current_dac_config[mode];
+        else if (!strcmp(kcontrol->id.name, "Multiconfig support for ADC"))
+                val = aic326x->current_adc_config[mode];
+
+
+        ucontrol->value.integer.value[0] = val;
+        return 0;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function : m_new_control_put
+ * Purpose  : new_control_put is called to pass data from user/application to
+ *            the driver.
+ *
+ *----------------------------------------------------------------------------
+ */
+static int m_control_put(struct snd_kcontrol *kcontrol,
+                         struct snd_ctl_elem_value *ucontrol)
+{
+        struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+        struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
+        u32 val;
+        u8 value;
+        int pf = aic326x->process_flow;
+        struct multibyte_config *array;
+
+        val = ucontrol->value.integer.value[0];
+        if (!strcmp(kcontrol->id.name, "Multiconfig support for DAC")) {
+                if (aic326x->process_flow == MINIDSP_DMODE) {
+                        if (val > MAX_CONFIG_D_ARRAYS) {
+                                dev_err(codec->dev, "Value not in range\n");
+                                return -1;
+                        }
+
+                        value = aic3262_read(codec, ADC_CHANNEL_POW);
+                        value = aic3262_read(codec, PASI_DAC_DP_SETUP);
+
+                        array = &config_array[pf][MINIDSP_DMODE][val];
+                        minidsp_i2c_multibyte_transfer(codec,
+                                array->regs,
+                                (array->d_inst_size + array->d_coeff_size));
+
+
+                        /*coefficent buffer change*/
+                        multibyte_coeff_change(codec, 0x50);
+
+                        minidsp_i2c_multibyte_transfer(codec,
+                                array->regs,
+                                (array->d_inst_size + array->d_coeff_size));
+
+
+
+                        value = aic3262_read(codec, ADC_CHANNEL_POW);
+                        value = aic3262_read(codec, PASI_DAC_DP_SETUP);
+                }
+                aic326x->current_dac_config[pf] = val;
+
+        } else {
+                if (aic326x->process_flow == MINIDSP_AMODE) {
+                        if (val > MAX_CONFIG_A_ARRAYS) {
+                                dev_err(codec->dev, "Value not in range\n");
+                                return -1;
+                        }
+                        array = &config_array[pf][MINIDSP_AMODE][val];
+                        minidsp_i2c_multibyte_transfer(codec,
+                                array->regs,
+                                (array->a_inst_size + array->a_coeff_size));
+                }
+                aic326x->current_adc_config[pf] = val;
+        }
+        return val;
+}
+
+
+/*
+ *--------------------------------------------------------------------------
+ * Function : aic3262_add_multiconfig_controls
+ * Purpose :  Configures the AMIXER Control Interfaces that can be exercised by
+ *            the user at run-time. Utilizes the  the snd_adaptive_controls[]
+ *            array to specify two run-time controls.
+ *---------------------------------------------------------------------------
+ */
+int aic3262_add_multiconfig_controls(struct snd_soc_codec *codec)
+{
+        int i, err;
+
+        DBG(KERN_INFO
+                "#%s: Invoked to add controls for Multi-Configuration\n",
+                __func__);
+
+        /* add mode k control */
+        for (i = 0; i < ARRAY_SIZE(aic3262_minidsp_controls1); i++) {
+                err = snd_ctl_add(codec->card->snd_card,
+                                snd_ctl_new1(&aic3262_minidsp_controls1[i],
+                                codec));
+                if (err < 0) {
+                        printk(KERN_ERR
+                        "Cannot add controls for mulibyte configuration\n");
+                        return err;
+                }
+        }
+        DBG(KERN_INFO "#%s: Completed control addition.\n", __func__);
+        return 0;
+}
+
+/*
+ *--------------------------------------------------------------------------
+ * Function : minidsp_multiconfig
+ * Purpose :  Function which is invoked when user changes the configuration
+ *            at run-time. Internally configures/switches both
+ *            miniDSP_D and miniDSP_A Coefficient arrays.
+ *---------------------------------------------------------------------------
+ */
+void minidsp_multiconfig(struct snd_soc_codec *codec,
+                                                                        reg_value *a_patch, int a_size,
+                                                                        reg_value *d_patch, int d_size)
+{
+        struct aic3262_priv *aic326x = snd_soc_codec_get_drvdata(codec);
+        int val1,val2;
+        int adc_status,dac_status;
+        int (*ptransfer)(struct snd_soc_codec *codec,
+                                reg_value *program_ptr,
+                                int size);
+
+printk("======in the config_multiconfiguration function==== \n");
+#ifndef MULTIBYTE_I2C
+                ptransfer = byte_i2c_array_transfer;
+#else
+                ptransfer = minidsp_i2c_multibyte_transfer;
+#endif
+        //DBG(KERN_INFO "#%s: Invoked for miniDSP Mode %d\n", __func__, mode);
+
+        adc_status=aic3262_read(codec,ADC_FLAG_R1);
+        printk("ADC STATUS = %x", adc_status);
+
+        dac_status=aic3262_read(codec,DAC_FLAG_R1);
+        printk("DAC STATUS = %x", dac_status);
+
+        #if 0
+        /* Switching off the adaptive filtering for loading the patch file*/
+        aic3262_change_book(codec, 40);
+        val1 = i2c_smbus_read_byte_data(codec->control_data, 1);
+        aic3262_write(codec, 1, (val1&0xfb));
+
+        aic3262_change_book(codec, 80);
+        val2 = i2c_smbus_read_byte_data(codec->control_data, 1);
+        aic3262_write(codec, 1, (val2&0xfb));
+
+        #endif
+
+        /*apply patches to both pages (mirrored coeffs). this works when DSP are stopped*/
+        /* to apply patches when DSPs are runnig, the 'buffer swap' has to be executed, which is
+            done in the buffer swap section below*/
+
+        if (a_size)
+                ptransfer       (codec, a_patch, a_size);
+        if (d_size)
+                ptransfer       (codec, d_patch, d_size);
+
+
+                /*swap buffers for both a&d only if DSPs are running*/
+              if((dac_status & 0x80) || (dac_status & 0x8))
+              {
+                   multibyte_coeff_change(codec, 0x50);/*swap DSP D Buffer*/
+                   if (d_size)
+                   ptransfer(codec, d_patch, d_size); /*apply patch after swapping buffer*/
+              }
+
+              if((adc_status & 0x40) || (adc_status & 0x4))
+              {
+                  multibyte_coeff_change(codec, 0x28);/*swap DSP A Buffer*/
+                  if (a_size)
+                  ptransfer(codec, a_patch, a_size); /*apply patch after swapping buffer*/
+              }
+
+        #if 0
+        if (a_size)
+                ptransfer       (codec, a_patch, a_size);
+        if (d_size)
+                ptransfer       (codec, d_patch, d_size);
+        #endif
+
+
+        return ;
+}
+
+/*
+ *--------------------------------------------------------------------------
+ * Function : config_multibyte_for_mode
+ * Purpose :  Function which is invoked when user changes the configuration
+ *            at run-time. Internally configures/switches both
+ *            miniDSP_D and miniDSP_A Coefficient arrays.
+ *---------------------------------------------------------------------------
+ */
+static int multibyte_coeff_change(struct snd_soc_codec *codec, int bk)
+{
+
+        u8 value[2], swap_reg_pre, swap_reg_post;
+        struct i2c_client *i2c;
+        i2c = codec->control_data;
+
+        aic3262_change_book(codec, bk);
+        aic3262_change_page(codec, 0);
+
+        value[0] = 1;
+
+        if (i2c_master_send(i2c, value, 1) != 1)
+                printk(KERN_ERR "Can not write register address\n");
+        else {
+                /* Read the Value of the Page 8 Register 1 which controls the
+                   Adaptive Switching Mode */
+                if (i2c_master_recv(i2c, value, 1) != 1) {
+                        printk(KERN_ERR "Can not read codec registers\n");
+                        goto err;
+                }
+                swap_reg_pre = value[0];
+
+                /* Write the Register bit updates */
+                value[1] = value[0] | 1;
+                value[0] = 1;
+
+                if (i2c_master_send(i2c, value, 2) != 2) {
+                        printk(KERN_ERR "Can not write register address\n");
+                        goto err;
+                }
+              /*before verifying for buffer_swap, make sure we give one
+              frame delay, because the buffer swap happens at the end of the frame */
+              mdelay(5);
+                value[0] = 1;
+                /* verify buffer swap */
+                if (i2c_master_send(i2c, value, 1) != 1)
+                        printk(KERN_ERR "Can not write register address\n");
+
+                /* Read the Value of the Page 8 Register 1 which controls the
+                   Adaptive Switching Mode */
+                if (i2c_master_recv(i2c, &swap_reg_post, 1) != 1)
+                        printk(KERN_ERR "Can not read codec registers\n");
+
+                if ((swap_reg_pre == 4 && swap_reg_post == 6)
+                        || (swap_reg_pre == 6 && swap_reg_post == 4))
+                        printk(KERN_INFO "Buffer swap success\n");
+                else
+                        printk(KERN_ERR
+                        "Buffer swap...FAILED\nswap_reg_pre=%x, swap_reg_post=%x\n",
+                        swap_reg_pre, swap_reg_post);
+
+                aic3262_change_book(codec, 0x00);
+        }
+
+err:
+        return 0;
+}
+
+
+
+#endif
+
+MODULE_DESCRIPTION("ASoC AIC3262 miniDSP multi-configuration");
+MODULE_AUTHOR("Barani Prashanth <gvbarani@mistralsolutions.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8994-tables.c b/sound/soc/codecs/wm8994-tables.c
new file mode 100644
index 00000000000..a87adbd05ee
--- /dev/null
+++ b/sound/soc/codecs/wm8994-tables.c
@@ -0,0 +1,3147 @@
+#include "wm8994.h"
+
+const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = {
+        { 0xFFFF, 0xFFFF }, /* R0     - Software Reset */
+        { 0x3B37, 0x3B37 }, /* R1     - Power Management (1) */
+        { 0x6BF0, 0x6BF0 }, /* R2     - Power Management (2) */
+        { 0x3FF0, 0x3FF0 }, /* R3     - Power Management (3) */
+        { 0x3F3F, 0x3F3F }, /* R4     - Power Management (4) */
+        { 0x3F0F, 0x3F0F }, /* R5     - Power Management (5) */
+        { 0x003F, 0x003F }, /* R6     - Power Management (6) */
+        { 0x0000, 0x0000 }, /* R7 */
+        { 0x0000, 0x0000 }, /* R8 */
+        { 0x0000, 0x0000 }, /* R9 */
+        { 0x0000, 0x0000 }, /* R10 */
+        { 0x0000, 0x0000 }, /* R11 */
+        { 0x0000, 0x0000 }, /* R12 */
+        { 0x0000, 0x0000 }, /* R13 */
+        { 0x0000, 0x0000 }, /* R14 */
+        { 0x0000, 0x0000 }, /* R15 */
+        { 0x0000, 0x0000 }, /* R16 */
+        { 0x0000, 0x0000 }, /* R17 */
+        { 0x0000, 0x0000 }, /* R18 */
+        { 0x0000, 0x0000 }, /* R19 */
+        { 0x0000, 0x0000 }, /* R20 */
+        { 0x01C0, 0x01C0 }, /* R21    - Input Mixer (1) */
+        { 0x0000, 0x0000 }, /* R22 */
+        { 0x0000, 0x0000 }, /* R23 */
+        { 0x00DF, 0x01DF }, /* R24    - Left Line Input 1&2 Volume */
+        { 0x00DF, 0x01DF }, /* R25    - Left Line Input 3&4 Volume */
+        { 0x00DF, 0x01DF }, /* R26    - Right Line Input 1&2 Volume */
+        { 0x00DF, 0x01DF }, /* R27    - Right Line Input 3&4 Volume */
+        { 0x00FF, 0x01FF }, /* R28    - Left Output Volume */
+        { 0x00FF, 0x01FF }, /* R29    - Right Output Volume */
+        { 0x0077, 0x0077 }, /* R30    - Line Outputs Volume */
+        { 0x0030, 0x0030 }, /* R31    - HPOUT2 Volume */
+        { 0x00FF, 0x01FF }, /* R32    - Left OPGA Volume */
+        { 0x00FF, 0x01FF }, /* R33    - Right OPGA Volume */
+        { 0x007F, 0x007F }, /* R34    - SPKMIXL Attenuation */
+        { 0x017F, 0x017F }, /* R35    - SPKMIXR Attenuation */
+        { 0x003F, 0x003F }, /* R36    - SPKOUT Mixers */
+        { 0x003F, 0x003F }, /* R37    - ClassD */
+        { 0x00FF, 0x01FF }, /* R38    - Speaker Volume Left */
+        { 0x00FF, 0x01FF }, /* R39    - Speaker Volume Right */
+        { 0x00FF, 0x00FF }, /* R40    - Input Mixer (2) */
+        { 0x01B7, 0x01B7 }, /* R41    - Input Mixer (3) */
+        { 0x01B7, 0x01B7 }, /* R42    - Input Mixer (4) */
+        { 0x01C7, 0x01C7 }, /* R43    - Input Mixer (5) */
+        { 0x01C7, 0x01C7 }, /* R44    - Input Mixer (6) */
+        { 0x01FF, 0x01FF }, /* R45    - Output Mixer (1) */
+        { 0x01FF, 0x01FF }, /* R46    - Output Mixer (2) */
+        { 0x0FFF, 0x0FFF }, /* R47    - Output Mixer (3) */
+        { 0x0FFF, 0x0FFF }, /* R48    - Output Mixer (4) */
+        { 0x0FFF, 0x0FFF }, /* R49    - Output Mixer (5) */
+        { 0x0FFF, 0x0FFF }, /* R50    - Output Mixer (6) */
+        { 0x0038, 0x0038 }, /* R51    - HPOUT2 Mixer */
+        { 0x0077, 0x0077 }, /* R52    - Line Mixer (1) */
+        { 0x0077, 0x0077 }, /* R53    - Line Mixer (2) */
+        { 0x03FF, 0x03FF }, /* R54    - Speaker Mixer */
+        { 0x00C1, 0x00C1 }, /* R55    - Additional Control */
+        { 0x00F0, 0x00F0 }, /* R56    - AntiPOP (1) */
+        { 0x01EF, 0x01EF }, /* R57    - AntiPOP (2) */
+        { 0x00FF, 0x00FF }, /* R58    - MICBIAS */
+        { 0x000F, 0x000F }, /* R59    - LDO 1 */
+        { 0x0007, 0x0007 }, /* R60    - LDO 2 */
+        { 0xFFFF, 0xFFFF }, /* R61 */
+        { 0xFFFF, 0xFFFF }, /* R62 */
+        { 0x0000, 0x0000 }, /* R63 */
+        { 0x0000, 0x0000 }, /* R64 */
+        { 0x0000, 0x0000 }, /* R65 */
+        { 0x0000, 0x0000 }, /* R66 */
+        { 0x0000, 0x0000 }, /* R67 */
+        { 0x0000, 0x0000 }, /* R68 */
+        { 0x0000, 0x0000 }, /* R69 */
+        { 0x0000, 0x0000 }, /* R70 */
+        { 0x0000, 0x0000 }, /* R71 */
+        { 0x0000, 0x0000 }, /* R72 */
+        { 0x0000, 0x0000 }, /* R73 */
+        { 0x0000, 0x0000 }, /* R74 */
+        { 0x0000, 0x0000 }, /* R75 */
+        { 0x8000, 0x8000 }, /* R76    - Charge Pump (1) */
+        { 0x0000, 0x0000 }, /* R77 */
+        { 0x0000, 0x0000 }, /* R78 */
+        { 0x0000, 0x0000 }, /* R79 */
+        { 0x0000, 0x0000 }, /* R80 */
+        { 0x0301, 0x0301 }, /* R81    - Class W (1) */
+        { 0x0000, 0x0000 }, /* R82 */
+        { 0x0000, 0x0000 }, /* R83 */
+        { 0x333F, 0x333F }, /* R84    - DC Servo (1) */
+        { 0x0FEF, 0x0FEF }, /* R85    - DC Servo (2) */
+        { 0x0000, 0x0000 }, /* R86 */
+        { 0xFFFF, 0xFFFF }, /* R87    - DC Servo (4) */
+        { 0x0333, 0x0000 }, /* R88    - DC Servo Readback */
+        { 0x0000, 0x0000 }, /* R89 */
+        { 0x0000, 0x0000 }, /* R90 */
+        { 0x0000, 0x0000 }, /* R91 */
+        { 0x0000, 0x0000 }, /* R92 */
+        { 0x0000, 0x0000 }, /* R93 */
+        { 0x0000, 0x0000 }, /* R94 */
+        { 0x0000, 0x0000 }, /* R95 */
+        { 0x00EE, 0x00EE }, /* R96    - Analogue HP (1) */
+        { 0x0000, 0x0000 }, /* R97 */
+        { 0x0000, 0x0000 }, /* R98 */
+        { 0x0000, 0x0000 }, /* R99 */
+        { 0x0000, 0x0000 }, /* R100 */
+        { 0x0000, 0x0000 }, /* R101 */
+        { 0x0000, 0x0000 }, /* R102 */
+        { 0x0000, 0x0000 }, /* R103 */
+        { 0x0000, 0x0000 }, /* R104 */
+        { 0x0000, 0x0000 }, /* R105 */
+        { 0x0000, 0x0000 }, /* R106 */
+        { 0x0000, 0x0000 }, /* R107 */
+        { 0x0000, 0x0000 }, /* R108 */
+        { 0x0000, 0x0000 }, /* R109 */
+        { 0x0000, 0x0000 }, /* R110 */
+        { 0x0000, 0x0000 }, /* R111 */
+        { 0x0000, 0x0000 }, /* R112 */
+        { 0x0000, 0x0000 }, /* R113 */
+        { 0x0000, 0x0000 }, /* R114 */
+        { 0x0000, 0x0000 }, /* R115 */
+        { 0x0000, 0x0000 }, /* R116 */
+        { 0x0000, 0x0000 }, /* R117 */
+        { 0x0000, 0x0000 }, /* R118 */
+        { 0x0000, 0x0000 }, /* R119 */
+        { 0x0000, 0x0000 }, /* R120 */
+        { 0x0000, 0x0000 }, /* R121 */
+        { 0x0000, 0x0000 }, /* R122 */
+        { 0x0000, 0x0000 }, /* R123 */
+        { 0x0000, 0x0000 }, /* R124 */
+        { 0x0000, 0x0000 }, /* R125 */
+        { 0x0000, 0x0000 }, /* R126 */
+        { 0x0000, 0x0000 }, /* R127 */
+        { 0x0000, 0x0000 }, /* R128 */
+        { 0x0000, 0x0000 }, /* R129 */
+        { 0x0000, 0x0000 }, /* R130 */
+        { 0x0000, 0x0000 }, /* R131 */
+        { 0x0000, 0x0000 }, /* R132 */
+        { 0x0000, 0x0000 }, /* R133 */
+        { 0x0000, 0x0000 }, /* R134 */
+        { 0x0000, 0x0000 }, /* R135 */
+        { 0x0000, 0x0000 }, /* R136 */
+        { 0x0000, 0x0000 }, /* R137 */
+        { 0x0000, 0x0000 }, /* R138 */
+        { 0x0000, 0x0000 }, /* R139 */
+        { 0x0000, 0x0000 }, /* R140 */
+        { 0x0000, 0x0000 }, /* R141 */
+        { 0x0000, 0x0000 }, /* R142 */
+        { 0x0000, 0x0000 }, /* R143 */
+        { 0x0000, 0x0000 }, /* R144 */
+        { 0x0000, 0x0000 }, /* R145 */
+        { 0x0000, 0x0000 }, /* R146 */
+        { 0x0000, 0x0000 }, /* R147 */
+        { 0x0000, 0x0000 }, /* R148 */
+        { 0x0000, 0x0000 }, /* R149 */
+        { 0x0000, 0x0000 }, /* R150 */
+        { 0x0000, 0x0000 }, /* R151 */
+        { 0x0000, 0x0000 }, /* R152 */
+        { 0x0000, 0x0000 }, /* R153 */
+        { 0x0000, 0x0000 }, /* R154 */
+        { 0x0000, 0x0000 }, /* R155 */
+        { 0x0000, 0x0000 }, /* R156 */
+        { 0x0000, 0x0000 }, /* R157 */
+        { 0x0000, 0x0000 }, /* R158 */
+        { 0x0000, 0x0000 }, /* R159 */
+        { 0x0000, 0x0000 }, /* R160 */
+        { 0x0000, 0x0000 }, /* R161 */
+        { 0x0000, 0x0000 }, /* R162 */
+        { 0x0000, 0x0000 }, /* R163 */
+        { 0x0000, 0x0000 }, /* R164 */
+        { 0x0000, 0x0000 }, /* R165 */
+        { 0x0000, 0x0000 }, /* R166 */
+        { 0x0000, 0x0000 }, /* R167 */
+        { 0x0000, 0x0000 }, /* R168 */
+        { 0x0000, 0x0000 }, /* R169 */
+        { 0x0000, 0x0000 }, /* R170 */
+        { 0x0000, 0x0000 }, /* R171 */
+        { 0x0000, 0x0000 }, /* R172 */
+        { 0x0000, 0x0000 }, /* R173 */
+        { 0x0000, 0x0000 }, /* R174 */
+        { 0x0000, 0x0000 }, /* R175 */
+        { 0x0000, 0x0000 }, /* R176 */
+        { 0x0000, 0x0000 }, /* R177 */
+        { 0x0000, 0x0000 }, /* R178 */
+        { 0x0000, 0x0000 }, /* R179 */
+        { 0x0000, 0x0000 }, /* R180 */
+        { 0x0000, 0x0000 }, /* R181 */
+        { 0x0000, 0x0000 }, /* R182 */
+        { 0x0000, 0x0000 }, /* R183 */
+        { 0x0000, 0x0000 }, /* R184 */
+        { 0x0000, 0x0000 }, /* R185 */
+        { 0x0000, 0x0000 }, /* R186 */
+        { 0x0000, 0x0000 }, /* R187 */
+        { 0x0000, 0x0000 }, /* R188 */
+        { 0x0000, 0x0000 }, /* R189 */
+        { 0x0000, 0x0000 }, /* R190 */
+        { 0x0000, 0x0000 }, /* R191 */
+        { 0x0000, 0x0000 }, /* R192 */
+        { 0x0000, 0x0000 }, /* R193 */
+        { 0x0000, 0x0000 }, /* R194 */
+        { 0x0000, 0x0000 }, /* R195 */
+        { 0x0000, 0x0000 }, /* R196 */
+        { 0x0000, 0x0000 }, /* R197 */
+        { 0x0000, 0x0000 }, /* R198 */
+        { 0x0000, 0x0000 }, /* R199 */
+        { 0x0000, 0x0000 }, /* R200 */
+        { 0x0000, 0x0000 }, /* R201 */
+        { 0x0000, 0x0000 }, /* R202 */
+        { 0x0000, 0x0000 }, /* R203 */
+        { 0x0000, 0x0000 }, /* R204 */
+        { 0x0000, 0x0000 }, /* R205 */
+        { 0x0000, 0x0000 }, /* R206 */
+        { 0x0000, 0x0000 }, /* R207 */
+        { 0xFFFF, 0xFFFF }, /* R208 */
+        { 0xFFFF, 0xFFFF }, /* R209 */
+        { 0xFFFF, 0xFFFF }, /* R210 */
+        { 0x0000, 0x0000 }, /* R211 */
+        { 0x0000, 0x0000 }, /* R212 */
+        { 0x0000, 0x0000 }, /* R213 */
+        { 0x0000, 0x0000 }, /* R214 */
+        { 0x0000, 0x0000 }, /* R215 */
+        { 0x0000, 0x0000 }, /* R216 */
+        { 0x0000, 0x0000 }, /* R217 */
+        { 0x0000, 0x0000 }, /* R218 */
+        { 0x0000, 0x0000 }, /* R219 */
+        { 0x0000, 0x0000 }, /* R220 */
+        { 0x0000, 0x0000 }, /* R221 */
+        { 0x0000, 0x0000 }, /* R222 */
+        { 0x0000, 0x0000 }, /* R223 */
+        { 0x0000, 0x0000 }, /* R224 */
+        { 0x0000, 0x0000 }, /* R225 */
+        { 0x0000, 0x0000 }, /* R226 */
+        { 0x0000, 0x0000 }, /* R227 */
+        { 0x0000, 0x0000 }, /* R228 */
+        { 0x0000, 0x0000 }, /* R229 */
+        { 0x0000, 0x0000 }, /* R230 */
+        { 0x0000, 0x0000 }, /* R231 */
+        { 0x0000, 0x0000 }, /* R232 */
+        { 0x0000, 0x0000 }, /* R233 */
+        { 0x0000, 0x0000 }, /* R234 */
+        { 0x0000, 0x0000 }, /* R235 */
+        { 0x0000, 0x0000 }, /* R236 */
+        { 0x0000, 0x0000 }, /* R237 */
+        { 0x0000, 0x0000 }, /* R238 */
+        { 0x0000, 0x0000 }, /* R239 */
+        { 0x0000, 0x0000 }, /* R240 */
+        { 0x0000, 0x0000 }, /* R241 */
+        { 0x0000, 0x0000 }, /* R242 */
+        { 0x0000, 0x0000 }, /* R243 */
+        { 0x0000, 0x0000 }, /* R244 */
+        { 0x0000, 0x0000 }, /* R245 */
+        { 0x0000, 0x0000 }, /* R246 */
+        { 0x0000, 0x0000 }, /* R247 */
+        { 0x0000, 0x0000 }, /* R248 */
+        { 0x0000, 0x0000 }, /* R249 */
+        { 0x0000, 0x0000 }, /* R250 */
+        { 0x0000, 0x0000 }, /* R251 */
+        { 0x0000, 0x0000 }, /* R252 */
+        { 0x0000, 0x0000 }, /* R253 */
+        { 0x0000, 0x0000 }, /* R254 */
+        { 0x0000, 0x0000 }, /* R255 */
+        { 0x000F, 0x0000 }, /* R256   - Chip Revision */
+        { 0x0074, 0x0074 }, /* R257   - Control Interface */
+        { 0x0000, 0x0000 }, /* R258 */
+        { 0x0000, 0x0000 }, /* R259 */
+        { 0x0000, 0x0000 }, /* R260 */
+        { 0x0000, 0x0000 }, /* R261 */
+        { 0x0000, 0x0000 }, /* R262 */
+        { 0x0000, 0x0000 }, /* R263 */
+        { 0x0000, 0x0000 }, /* R264 */
+        { 0x0000, 0x0000 }, /* R265 */
+        { 0x0000, 0x0000 }, /* R266 */
+        { 0x0000, 0x0000 }, /* R267 */
+        { 0x0000, 0x0000 }, /* R268 */
+        { 0x0000, 0x0000 }, /* R269 */
+        { 0x0000, 0x0000 }, /* R270 */
+        { 0x0000, 0x0000 }, /* R271 */
+        { 0x807F, 0x837F }, /* R272   - Write Sequencer Ctrl (1) */
+        { 0x017F, 0x0000 }, /* R273   - Write Sequencer Ctrl (2) */
+        { 0x0000, 0x0000 }, /* R274 */
+        { 0x0000, 0x0000 }, /* R275 */
+        { 0x0000, 0x0000 }, /* R276 */
+        { 0x0000, 0x0000 }, /* R277 */
+        { 0x0000, 0x0000 }, /* R278 */
+        { 0x0000, 0x0000 }, /* R279 */
+        { 0x0000, 0x0000 }, /* R280 */
+        { 0x0000, 0x0000 }, /* R281 */
+        { 0x0000, 0x0000 }, /* R282 */
+        { 0x0000, 0x0000 }, /* R283 */
+        { 0x0000, 0x0000 }, /* R284 */
+        { 0x0000, 0x0000 }, /* R285 */
+        { 0x0000, 0x0000 }, /* R286 */
+        { 0x0000, 0x0000 }, /* R287 */
+        { 0x0000, 0x0000 }, /* R288 */
+        { 0x0000, 0x0000 }, /* R289 */
+        { 0x0000, 0x0000 }, /* R290 */
+        { 0x0000, 0x0000 }, /* R291 */
+        { 0x0000, 0x0000 }, /* R292 */
+        { 0x0000, 0x0000 }, /* R293 */
+        { 0x0000, 0x0000 }, /* R294 */
+        { 0x0000, 0x0000 }, /* R295 */
+        { 0x0000, 0x0000 }, /* R296 */
+        { 0x0000, 0x0000 }, /* R297 */
+        { 0x0000, 0x0000 }, /* R298 */
+        { 0x0000, 0x0000 }, /* R299 */
+        { 0x0000, 0x0000 }, /* R300 */
+        { 0x0000, 0x0000 }, /* R301 */
+        { 0x0000, 0x0000 }, /* R302 */
+        { 0x0000, 0x0000 }, /* R303 */
+        { 0x0000, 0x0000 }, /* R304 */
+        { 0x0000, 0x0000 }, /* R305 */
+        { 0x0000, 0x0000 }, /* R306 */
+        { 0x0000, 0x0000 }, /* R307 */
+        { 0x0000, 0x0000 }, /* R308 */
+        { 0x0000, 0x0000 }, /* R309 */
+        { 0x0000, 0x0000 }, /* R310 */
+        { 0x0000, 0x0000 }, /* R311 */
+        { 0x0000, 0x0000 }, /* R312 */
+        { 0x0000, 0x0000 }, /* R313 */
+        { 0x0000, 0x0000 }, /* R314 */
+        { 0x0000, 0x0000 }, /* R315 */
+        { 0x0000, 0x0000 }, /* R316 */
+        { 0x0000, 0x0000 }, /* R317 */
+        { 0x0000, 0x0000 }, /* R318 */
+        { 0x0000, 0x0000 }, /* R319 */
+        { 0x0000, 0x0000 }, /* R320 */
+        { 0x0000, 0x0000 }, /* R321 */
+        { 0x0000, 0x0000 }, /* R322 */
+        { 0x0000, 0x0000 }, /* R323 */
+        { 0x0000, 0x0000 }, /* R324 */
+        { 0x0000, 0x0000 }, /* R325 */
+        { 0x0000, 0x0000 }, /* R326 */
+        { 0x0000, 0x0000 }, /* R327 */
+        { 0x0000, 0x0000 }, /* R328 */
+        { 0x0000, 0x0000 }, /* R329 */
+        { 0x0000, 0x0000 }, /* R330 */
+        { 0x0000, 0x0000 }, /* R331 */
+        { 0x0000, 0x0000 }, /* R332 */
+        { 0x0000, 0x0000 }, /* R333 */
+        { 0x0000, 0x0000 }, /* R334 */
+        { 0x0000, 0x0000 }, /* R335 */
+        { 0x0000, 0x0000 }, /* R336 */
+        { 0x0000, 0x0000 }, /* R337 */
+        { 0x0000, 0x0000 }, /* R338 */
+        { 0x0000, 0x0000 }, /* R339 */
+        { 0x0000, 0x0000 }, /* R340 */
+        { 0x0000, 0x0000 }, /* R341 */
+        { 0x0000, 0x0000 }, /* R342 */
+        { 0x0000, 0x0000 }, /* R343 */
+        { 0x0000, 0x0000 }, /* R344 */
+        { 0x0000, 0x0000 }, /* R345 */
+        { 0x0000, 0x0000 }, /* R346 */
+        { 0x0000, 0x0000 }, /* R347 */
+        { 0x0000, 0x0000 }, /* R348 */
+        { 0x0000, 0x0000 }, /* R349 */
+        { 0x0000, 0x0000 }, /* R350 */
+        { 0x0000, 0x0000 }, /* R351 */
+        { 0x0000, 0x0000 }, /* R352 */
+        { 0x0000, 0x0000 }, /* R353 */
+        { 0x0000, 0x0000 }, /* R354 */
+        { 0x0000, 0x0000 }, /* R355 */
+        { 0x0000, 0x0000 }, /* R356 */
+        { 0x0000, 0x0000 }, /* R357 */
+        { 0x0000, 0x0000 }, /* R358 */
+        { 0x0000, 0x0000 }, /* R359 */
+        { 0x0000, 0x0000 }, /* R360 */
+        { 0x0000, 0x0000 }, /* R361 */
+        { 0x0000, 0x0000 }, /* R362 */
+        { 0x0000, 0x0000 }, /* R363 */
+        { 0x0000, 0x0000 }, /* R364 */
+        { 0x0000, 0x0000 }, /* R365 */
+        { 0x0000, 0x0000 }, /* R366 */
+        { 0x0000, 0x0000 }, /* R367 */
+        { 0x0000, 0x0000 }, /* R368 */
+        { 0x0000, 0x0000 }, /* R369 */
+        { 0x0000, 0x0000 }, /* R370 */
+        { 0x0000, 0x0000 }, /* R371 */
+        { 0x0000, 0x0000 }, /* R372 */
+        { 0x0000, 0x0000 }, /* R373 */
+        { 0x0000, 0x0000 }, /* R374 */
+        { 0x0000, 0x0000 }, /* R375 */
+        { 0x0000, 0x0000 }, /* R376 */
+        { 0x0000, 0x0000 }, /* R377 */
+        { 0x0000, 0x0000 }, /* R378 */
+        { 0x0000, 0x0000 }, /* R379 */
+        { 0x0000, 0x0000 }, /* R380 */
+        { 0x0000, 0x0000 }, /* R381 */
+        { 0x0000, 0x0000 }, /* R382 */
+        { 0x0000, 0x0000 }, /* R383 */
+        { 0x0000, 0x0000 }, /* R384 */
+        { 0x0000, 0x0000 }, /* R385 */
+        { 0x0000, 0x0000 }, /* R386 */
+        { 0x0000, 0x0000 }, /* R387 */
+        { 0x0000, 0x0000 }, /* R388 */
+        { 0x0000, 0x0000 }, /* R389 */
+        { 0x0000, 0x0000 }, /* R390 */
+        { 0x0000, 0x0000 }, /* R391 */
+        { 0x0000, 0x0000 }, /* R392 */
+        { 0x0000, 0x0000 }, /* R393 */
+        { 0x0000, 0x0000 }, /* R394 */
+        { 0x0000, 0x0000 }, /* R395 */
+        { 0x0000, 0x0000 }, /* R396 */
+        { 0x0000, 0x0000 }, /* R397 */
+        { 0x0000, 0x0000 }, /* R398 */
+        { 0x0000, 0x0000 }, /* R399 */
+        { 0x0000, 0x0000 }, /* R400 */
+        { 0x0000, 0x0000 }, /* R401 */
+        { 0x0000, 0x0000 }, /* R402 */
+        { 0x0000, 0x0000 }, /* R403 */
+        { 0x0000, 0x0000 }, /* R404 */
+        { 0x0000, 0x0000 }, /* R405 */
+        { 0x0000, 0x0000 }, /* R406 */
+        { 0x0000, 0x0000 }, /* R407 */
+        { 0x0000, 0x0000 }, /* R408 */
+        { 0x0000, 0x0000 }, /* R409 */
+        { 0x0000, 0x0000 }, /* R410 */
+        { 0x0000, 0x0000 }, /* R411 */
+        { 0x0000, 0x0000 }, /* R412 */
+        { 0x0000, 0x0000 }, /* R413 */
+        { 0x0000, 0x0000 }, /* R414 */
+        { 0x0000, 0x0000 }, /* R415 */
+        { 0x0000, 0x0000 }, /* R416 */
+        { 0x0000, 0x0000 }, /* R417 */
+        { 0x0000, 0x0000 }, /* R418 */
+        { 0x0000, 0x0000 }, /* R419 */
+        { 0x0000, 0x0000 }, /* R420 */
+        { 0x0000, 0x0000 }, /* R421 */
+        { 0x0000, 0x0000 }, /* R422 */
+        { 0x0000, 0x0000 }, /* R423 */
+        { 0x0000, 0x0000 }, /* R424 */
+        { 0x0000, 0x0000 }, /* R425 */
+        { 0x0000, 0x0000 }, /* R426 */
+        { 0x0000, 0x0000 }, /* R427 */
+        { 0x0000, 0x0000 }, /* R428 */
+        { 0x0000, 0x0000 }, /* R429 */
+        { 0x0000, 0x0000 }, /* R430 */
+        { 0x0000, 0x0000 }, /* R431 */
+        { 0x0000, 0x0000 }, /* R432 */
+        { 0x0000, 0x0000 }, /* R433 */
+        { 0x0000, 0x0000 }, /* R434 */
+        { 0x0000, 0x0000 }, /* R435 */
+        { 0x0000, 0x0000 }, /* R436 */
+        { 0x0000, 0x0000 }, /* R437 */
+        { 0x0000, 0x0000 }, /* R438 */
+        { 0x0000, 0x0000 }, /* R439 */
+        { 0x0000, 0x0000 }, /* R440 */
+        { 0x0000, 0x0000 }, /* R441 */
+        { 0x0000, 0x0000 }, /* R442 */
+        { 0x0000, 0x0000 }, /* R443 */
+        { 0x0000, 0x0000 }, /* R444 */
+        { 0x0000, 0x0000 }, /* R445 */
+        { 0x0000, 0x0000 }, /* R446 */
+        { 0x0000, 0x0000 }, /* R447 */
+        { 0x0000, 0x0000 }, /* R448 */
+        { 0x0000, 0x0000 }, /* R449 */
+        { 0x0000, 0x0000 }, /* R450 */
+        { 0x0000, 0x0000 }, /* R451 */
+        { 0x0000, 0x0000 }, /* R452 */
+        { 0x0000, 0x0000 }, /* R453 */
+        { 0x0000, 0x0000 }, /* R454 */
+        { 0x0000, 0x0000 }, /* R455 */
+        { 0x0000, 0x0000 }, /* R456 */
+        { 0x0000, 0x0000 }, /* R457 */
+        { 0x0000, 0x0000 }, /* R458 */
+        { 0x0000, 0x0000 }, /* R459 */
+        { 0x0000, 0x0000 }, /* R460 */
+        { 0x0000, 0x0000 }, /* R461 */
+        { 0x0000, 0x0000 }, /* R462 */
+        { 0x0000, 0x0000 }, /* R463 */
+        { 0x0000, 0x0000 }, /* R464 */
+        { 0x0000, 0x0000 }, /* R465 */
+        { 0x0000, 0x0000 }, /* R466 */
+        { 0x0000, 0x0000 }, /* R467 */
+        { 0x0000, 0x0000 }, /* R468 */
+        { 0x0000, 0x0000 }, /* R469 */
+        { 0x0000, 0x0000 }, /* R470 */
+        { 0x0000, 0x0000 }, /* R471 */
+        { 0x0000, 0x0000 }, /* R472 */
+        { 0x0000, 0x0000 }, /* R473 */
+        { 0x0000, 0x0000 }, /* R474 */
+        { 0x0000, 0x0000 }, /* R475 */
+        { 0x0000, 0x0000 }, /* R476 */
+        { 0x0000, 0x0000 }, /* R477 */
+        { 0x0000, 0x0000 }, /* R478 */
+        { 0x0000, 0x0000 }, /* R479 */
+        { 0x0000, 0x0000 }, /* R480 */
+        { 0x0000, 0x0000 }, /* R481 */
+        { 0x0000, 0x0000 }, /* R482 */
+        { 0x0000, 0x0000 }, /* R483 */
+        { 0x0000, 0x0000 }, /* R484 */
+        { 0x0000, 0x0000 }, /* R485 */
+        { 0x0000, 0x0000 }, /* R486 */
+        { 0x0000, 0x0000 }, /* R487 */
+        { 0x0000, 0x0000 }, /* R488 */
+        { 0x0000, 0x0000 }, /* R489 */
+        { 0x0000, 0x0000 }, /* R490 */
+        { 0x0000, 0x0000 }, /* R491 */
+        { 0x0000, 0x0000 }, /* R492 */
+        { 0x0000, 0x0000 }, /* R493 */
+        { 0x0000, 0x0000 }, /* R494 */
+        { 0x0000, 0x0000 }, /* R495 */
+        { 0x0000, 0x0000 }, /* R496 */
+        { 0x0000, 0x0000 }, /* R497 */
+        { 0x0000, 0x0000 }, /* R498 */
+        { 0x0000, 0x0000 }, /* R499 */
+        { 0x0000, 0x0000 }, /* R500 */
+        { 0x0000, 0x0000 }, /* R501 */
+        { 0x0000, 0x0000 }, /* R502 */
+        { 0x0000, 0x0000 }, /* R503 */
+        { 0x0000, 0x0000 }, /* R504 */
+        { 0x0000, 0x0000 }, /* R505 */
+        { 0x0000, 0x0000 }, /* R506 */
+        { 0x0000, 0x0000 }, /* R507 */
+        { 0x0000, 0x0000 }, /* R508 */
+        { 0x0000, 0x0000 }, /* R509 */
+        { 0x0000, 0x0000 }, /* R510 */
+        { 0x0000, 0x0000 }, /* R511 */
+        { 0x001F, 0x001F }, /* R512   - AIF1 Clocking (1) */
+        { 0x003F, 0x003F }, /* R513   - AIF1 Clocking (2) */
+        { 0x0000, 0x0000 }, /* R514 */
+        { 0x0000, 0x0000 }, /* R515 */
+        { 0x001F, 0x001F }, /* R516   - AIF2 Clocking (1) */
+        { 0x003F, 0x003F }, /* R517   - AIF2 Clocking (2) */
+        { 0x0000, 0x0000 }, /* R518 */
+        { 0x0000, 0x0000 }, /* R519 */
+        { 0x001F, 0x001F }, /* R520   - Clocking (1) */
+        { 0x0777, 0x0777 }, /* R521   - Clocking (2) */
+        { 0x0000, 0x0000 }, /* R522 */
+        { 0x0000, 0x0000 }, /* R523 */
+        { 0x0000, 0x0000 }, /* R524 */
+        { 0x0000, 0x0000 }, /* R525 */
+        { 0x0000, 0x0000 }, /* R526 */
+        { 0x0000, 0x0000 }, /* R527 */
+        { 0x00FF, 0x00FF }, /* R528   - AIF1 Rate */
+        { 0x00FF, 0x00FF }, /* R529   - AIF2 Rate */
+        { 0x000F, 0x0000 }, /* R530   - Rate Status */
+        { 0x0000, 0x0000 }, /* R531 */
+        { 0x0000, 0x0000 }, /* R532 */
+        { 0x0000, 0x0000 }, /* R533 */
+        { 0x0000, 0x0000 }, /* R534 */
+        { 0x0000, 0x0000 }, /* R535 */
+        { 0x0000, 0x0000 }, /* R536 */
+        { 0x0000, 0x0000 }, /* R537 */
+        { 0x0000, 0x0000 }, /* R538 */
+        { 0x0000, 0x0000 }, /* R539 */
+        { 0x0000, 0x0000 }, /* R540 */
+        { 0x0000, 0x0000 }, /* R541 */
+        { 0x0000, 0x0000 }, /* R542 */
+        { 0x0000, 0x0000 }, /* R543 */
+        { 0x0007, 0x0007 }, /* R544   - FLL1 Control (1) */
+        { 0x3F77, 0x3F77 }, /* R545   - FLL1 Control (2) */
+        { 0xFFFF, 0xFFFF }, /* R546   - FLL1 Control (3) */
+        { 0x7FEF, 0x7FEF }, /* R547   - FLL1 Control (4) */
+        { 0x1FDB, 0x1FDB }, /* R548   - FLL1 Control (5) */
+        { 0x0000, 0x0000 }, /* R549 */
+        { 0x0000, 0x0000 }, /* R550 */
+        { 0x0000, 0x0000 }, /* R551 */
+        { 0x0000, 0x0000 }, /* R552 */
+        { 0x0000, 0x0000 }, /* R553 */
+        { 0x0000, 0x0000 }, /* R554 */
+        { 0x0000, 0x0000 }, /* R555 */
+        { 0x0000, 0x0000 }, /* R556 */
+        { 0x0000, 0x0000 }, /* R557 */
+        { 0x0000, 0x0000 }, /* R558 */
+        { 0x0000, 0x0000 }, /* R559 */
+        { 0x0000, 0x0000 }, /* R560 */
+        { 0x0000, 0x0000 }, /* R561 */
+        { 0x0000, 0x0000 }, /* R562 */
+        { 0x0000, 0x0000 }, /* R563 */
+        { 0x0000, 0x0000 }, /* R564 */
+        { 0x0000, 0x0000 }, /* R565 */
+        { 0x0000, 0x0000 }, /* R566 */
+        { 0x0000, 0x0000 }, /* R567 */
+        { 0x0000, 0x0000 }, /* R568 */
+        { 0x0000, 0x0000 }, /* R569 */
+        { 0x0000, 0x0000 }, /* R570 */
+        { 0x0000, 0x0000 }, /* R571 */
+        { 0x0000, 0x0000 }, /* R572 */
+        { 0x0000, 0x0000 }, /* R573 */
+        { 0x0000, 0x0000 }, /* R574 */
+        { 0x0000, 0x0000 }, /* R575 */
+        { 0x0007, 0x0007 }, /* R576   - FLL2 Control (1) */
+        { 0x3F77, 0x3F77 }, /* R577   - FLL2 Control (2) */
+        { 0xFFFF, 0xFFFF }, /* R578   - FLL2 Control (3) */
+        { 0x7FEF, 0x7FEF }, /* R579   - FLL2 Control (4) */
+        { 0x1FDB, 0x1FDB }, /* R580   - FLL2 Control (5) */
+        { 0x0000, 0x0000 }, /* R581 */
+        { 0x0000, 0x0000 }, /* R582 */
+        { 0x0000, 0x0000 }, /* R583 */
+        { 0x0000, 0x0000 }, /* R584 */
+        { 0x0000, 0x0000 }, /* R585 */
+        { 0x0000, 0x0000 }, /* R586 */
+        { 0x0000, 0x0000 }, /* R587 */
+        { 0x0000, 0x0000 }, /* R588 */
+        { 0x0000, 0x0000 }, /* R589 */
+        { 0x0000, 0x0000 }, /* R590 */
+        { 0x0000, 0x0000 }, /* R591 */
+        { 0x0000, 0x0000 }, /* R592 */
+        { 0x0000, 0x0000 }, /* R593 */
+        { 0x0000, 0x0000 }, /* R594 */
+        { 0x0000, 0x0000 }, /* R595 */
+        { 0x0000, 0x0000 }, /* R596 */
+        { 0x0000, 0x0000 }, /* R597 */
+        { 0x0000, 0x0000 }, /* R598 */
+        { 0x0000, 0x0000 }, /* R599 */
+        { 0x0000, 0x0000 }, /* R600 */
+        { 0x0000, 0x0000 }, /* R601 */
+        { 0x0000, 0x0000 }, /* R602 */
+        { 0x0000, 0x0000 }, /* R603 */
+        { 0x0000, 0x0000 }, /* R604 */
+        { 0x0000, 0x0000 }, /* R605 */
+        { 0x0000, 0x0000 }, /* R606 */
+        { 0x0000, 0x0000 }, /* R607 */
+        { 0x0000, 0x0000 }, /* R608 */
+        { 0x0000, 0x0000 }, /* R609 */
+        { 0x0000, 0x0000 }, /* R610 */
+        { 0x0000, 0x0000 }, /* R611 */
+        { 0x0000, 0x0000 }, /* R612 */
+        { 0x0000, 0x0000 }, /* R613 */
+        { 0x0000, 0x0000 }, /* R614 */
+        { 0x0000, 0x0000 }, /* R615 */
+        { 0x0000, 0x0000 }, /* R616 */
+        { 0x0000, 0x0000 }, /* R617 */
+        { 0x0000, 0x0000 }, /* R618 */
+        { 0x0000, 0x0000 }, /* R619 */
+        { 0x0000, 0x0000 }, /* R620 */
+        { 0x0000, 0x0000 }, /* R621 */
+        { 0x0000, 0x0000 }, /* R622 */
+        { 0x0000, 0x0000 }, /* R623 */
+        { 0x0000, 0x0000 }, /* R624 */
+        { 0x0000, 0x0000 }, /* R625 */
+        { 0x0000, 0x0000 }, /* R626 */
+        { 0x0000, 0x0000 }, /* R627 */
+        { 0x0000, 0x0000 }, /* R628 */
+        { 0x0000, 0x0000 }, /* R629 */
+        { 0x0000, 0x0000 }, /* R630 */
+        { 0x0000, 0x0000 }, /* R631 */
+        { 0x0000, 0x0000 }, /* R632 */
+        { 0x0000, 0x0000 }, /* R633 */
+        { 0x0000, 0x0000 }, /* R634 */
+        { 0x0000, 0x0000 }, /* R635 */
+        { 0x0000, 0x0000 }, /* R636 */
+        { 0x0000, 0x0000 }, /* R637 */
+        { 0x0000, 0x0000 }, /* R638 */
+        { 0x0000, 0x0000 }, /* R639 */
+        { 0x0000, 0x0000 }, /* R640 */
+        { 0x0000, 0x0000 }, /* R641 */
+        { 0x0000, 0x0000 }, /* R642 */
+        { 0x0000, 0x0000 }, /* R643 */
+        { 0x0000, 0x0000 }, /* R644 */
+        { 0x0000, 0x0000 }, /* R645 */
+        { 0x0000, 0x0000 }, /* R646 */
+        { 0x0000, 0x0000 }, /* R647 */
+        { 0x0000, 0x0000 }, /* R648 */
+        { 0x0000, 0x0000 }, /* R649 */
+        { 0x0000, 0x0000 }, /* R650 */
+        { 0x0000, 0x0000 }, /* R651 */
+        { 0x0000, 0x0000 }, /* R652 */
+        { 0x0000, 0x0000 }, /* R653 */
+        { 0x0000, 0x0000 }, /* R654 */
+        { 0x0000, 0x0000 }, /* R655 */
+        { 0x0000, 0x0000 }, /* R656 */
+        { 0x0000, 0x0000 }, /* R657 */
+        { 0x0000, 0x0000 }, /* R658 */
+        { 0x0000, 0x0000 }, /* R659 */
+        { 0x0000, 0x0000 }, /* R660 */
+        { 0x0000, 0x0000 }, /* R661 */
+        { 0x0000, 0x0000 }, /* R662 */
+        { 0x0000, 0x0000 }, /* R663 */
+        { 0x0000, 0x0000 }, /* R664 */
+        { 0x0000, 0x0000 }, /* R665 */
+        { 0x0000, 0x0000 }, /* R666 */
+        { 0x0000, 0x0000 }, /* R667 */
+        { 0x0000, 0x0000 }, /* R668 */
+        { 0x0000, 0x0000 }, /* R669 */
+        { 0x0000, 0x0000 }, /* R670 */
+        { 0x0000, 0x0000 }, /* R671 */
+        { 0x0000, 0x0000 }, /* R672 */
+        { 0x0000, 0x0000 }, /* R673 */
+        { 0x0000, 0x0000 }, /* R674 */
+        { 0x0000, 0x0000 }, /* R675 */
+        { 0x0000, 0x0000 }, /* R676 */
+        { 0x0000, 0x0000 }, /* R677 */
+        { 0x0000, 0x0000 }, /* R678 */
+        { 0x0000, 0x0000 }, /* R679 */
+        { 0x0000, 0x0000 }, /* R680 */
+        { 0x0000, 0x0000 }, /* R681 */
+        { 0x0000, 0x0000 }, /* R682 */
+        { 0x0000, 0x0000 }, /* R683 */
+        { 0x0000, 0x0000 }, /* R684 */
+        { 0x0000, 0x0000 }, /* R685 */
+        { 0x0000, 0x0000 }, /* R686 */
+        { 0x0000, 0x0000 }, /* R687 */
+        { 0x0000, 0x0000 }, /* R688 */
+        { 0x0000, 0x0000 }, /* R689 */
+        { 0x0000, 0x0000 }, /* R690 */
+        { 0x0000, 0x0000 }, /* R691 */
+        { 0x0000, 0x0000 }, /* R692 */
+        { 0x0000, 0x0000 }, /* R693 */
+        { 0x0000, 0x0000 }, /* R694 */
+        { 0x0000, 0x0000 }, /* R695 */
+        { 0x0000, 0x0000 }, /* R696 */
+        { 0x0000, 0x0000 }, /* R697 */
+        { 0x0000, 0x0000 }, /* R698 */
+        { 0x0000, 0x0000 }, /* R699 */
+        { 0x0000, 0x0000 }, /* R700 */
+        { 0x0000, 0x0000 }, /* R701 */
+        { 0x0000, 0x0000 }, /* R702 */
+        { 0x0000, 0x0000 }, /* R703 */
+        { 0x0000, 0x0000 }, /* R704 */
+        { 0x0000, 0x0000 }, /* R705 */
+        { 0x0000, 0x0000 }, /* R706 */
+        { 0x0000, 0x0000 }, /* R707 */
+        { 0x0000, 0x0000 }, /* R708 */
+        { 0x0000, 0x0000 }, /* R709 */
+        { 0x0000, 0x0000 }, /* R710 */
+        { 0x0000, 0x0000 }, /* R711 */
+        { 0x0000, 0x0000 }, /* R712 */
+        { 0x0000, 0x0000 }, /* R713 */
+        { 0x0000, 0x0000 }, /* R714 */
+        { 0x0000, 0x0000 }, /* R715 */
+        { 0x0000, 0x0000 }, /* R716 */
+        { 0x0000, 0x0000 }, /* R717 */
+        { 0x0000, 0x0000 }, /* R718 */
+        { 0x0000, 0x0000 }, /* R719 */
+        { 0x0000, 0x0000 }, /* R720 */
+        { 0x0000, 0x0000 }, /* R721 */
+        { 0x0000, 0x0000 }, /* R722 */
+        { 0x0000, 0x0000 }, /* R723 */
+        { 0x0000, 0x0000 }, /* R724 */
+        { 0x0000, 0x0000 }, /* R725 */
+        { 0x0000, 0x0000 }, /* R726 */
+        { 0x0000, 0x0000 }, /* R727 */
+        { 0x0000, 0x0000 }, /* R728 */
+        { 0x0000, 0x0000 }, /* R729 */
+        { 0x0000, 0x0000 }, /* R730 */
+        { 0x0000, 0x0000 }, /* R731 */
+        { 0x0000, 0x0000 }, /* R732 */
+        { 0x0000, 0x0000 }, /* R733 */
+        { 0x0000, 0x0000 }, /* R734 */
+        { 0x0000, 0x0000 }, /* R735 */
+        { 0x0000, 0x0000 }, /* R736 */
+        { 0x0000, 0x0000 }, /* R737 */
+        { 0x0000, 0x0000 }, /* R738 */
+        { 0x0000, 0x0000 }, /* R739 */
+        { 0x0000, 0x0000 }, /* R740 */
+        { 0x0000, 0x0000 }, /* R741 */
+        { 0x0000, 0x0000 }, /* R742 */
+        { 0x0000, 0x0000 }, /* R743 */
+        { 0x0000, 0x0000 }, /* R744 */
+        { 0x0000, 0x0000 }, /* R745 */
+        { 0x0000, 0x0000 }, /* R746 */
+        { 0x0000, 0x0000 }, /* R747 */
+        { 0x0000, 0x0000 }, /* R748 */
+        { 0x0000, 0x0000 }, /* R749 */
+        { 0x0000, 0x0000 }, /* R750 */
+        { 0x0000, 0x0000 }, /* R751 */
+        { 0x0000, 0x0000 }, /* R752 */
+        { 0x0000, 0x0000 }, /* R753 */
+        { 0x0000, 0x0000 }, /* R754 */
+        { 0x0000, 0x0000 }, /* R755 */
+        { 0x0000, 0x0000 }, /* R756 */
+        { 0x0000, 0x0000 }, /* R757 */
+        { 0x0000, 0x0000 }, /* R758 */
+        { 0x0000, 0x0000 }, /* R759 */
+        { 0x0000, 0x0000 }, /* R760 */
+        { 0x0000, 0x0000 }, /* R761 */
+        { 0x0000, 0x0000 }, /* R762 */
+        { 0x0000, 0x0000 }, /* R763 */
+        { 0x0000, 0x0000 }, /* R764 */
+        { 0x0000, 0x0000 }, /* R765 */
+        { 0x0000, 0x0000 }, /* R766 */
+        { 0x0000, 0x0000 }, /* R767 */
+        { 0xE1F8, 0xE1F8 }, /* R768   - AIF1 Control (1) */
+        { 0xCD1F, 0xCD1F }, /* R769   - AIF1 Control (2) */
+        { 0xF000, 0xF000 }, /* R770   - AIF1 Master/Slave */
+        { 0x01F0, 0x01F0 }, /* R771   - AIF1 BCLK */
+        { 0x0FFF, 0x0FFF }, /* R772   - AIF1ADC LRCLK */
+        { 0x0FFF, 0x0FFF }, /* R773   - AIF1DAC LRCLK */
+        { 0x0003, 0x0003 }, /* R774   - AIF1DAC Data */
+        { 0x0003, 0x0003 }, /* R775   - AIF1ADC Data */
+        { 0x0000, 0x0000 }, /* R776 */
+        { 0x0000, 0x0000 }, /* R777 */
+        { 0x0000, 0x0000 }, /* R778 */
+        { 0x0000, 0x0000 }, /* R779 */
+        { 0x0000, 0x0000 }, /* R780 */
+        { 0x0000, 0x0000 }, /* R781 */
+        { 0x0000, 0x0000 }, /* R782 */
+        { 0x0000, 0x0000 }, /* R783 */
+        { 0xF1F8, 0xF1F8 }, /* R784   - AIF2 Control (1) */
+        { 0xFD1F, 0xFD1F }, /* R785   - AIF2 Control (2) */
+        { 0xF000, 0xF000 }, /* R786   - AIF2 Master/Slave */
+        { 0x01F0, 0x01F0 }, /* R787   - AIF2 BCLK */
+        { 0x0FFF, 0x0FFF }, /* R788   - AIF2ADC LRCLK */
+        { 0x0FFF, 0x0FFF }, /* R789   - AIF2DAC LRCLK */
+        { 0x0003, 0x0003 }, /* R790   - AIF2DAC Data */
+        { 0x0003, 0x0003 }, /* R791   - AIF2ADC Data */
+        { 0x0000, 0x0000 }, /* R792 */
+        { 0x0000, 0x0000 }, /* R793 */
+        { 0x0000, 0x0000 }, /* R794 */
+        { 0x0000, 0x0000 }, /* R795 */
+        { 0x0000, 0x0000 }, /* R796 */
+        { 0x0000, 0x0000 }, /* R797 */
+        { 0x0000, 0x0000 }, /* R798 */
+        { 0x0000, 0x0000 }, /* R799 */
+        { 0x0000, 0x0000 }, /* R800 */
+        { 0x0000, 0x0000 }, /* R801 */
+        { 0x0000, 0x0000 }, /* R802 */
+        { 0x0000, 0x0000 }, /* R803 */
+        { 0x0000, 0x0000 }, /* R804 */
+        { 0x0000, 0x0000 }, /* R805 */
+        { 0x0000, 0x0000 }, /* R806 */
+        { 0x0000, 0x0000 }, /* R807 */
+        { 0x0000, 0x0000 }, /* R808 */
+        { 0x0000, 0x0000 }, /* R809 */
+        { 0x0000, 0x0000 }, /* R810 */
+        { 0x0000, 0x0000 }, /* R811 */
+        { 0x0000, 0x0000 }, /* R812 */
+        { 0x0000, 0x0000 }, /* R813 */
+        { 0x0000, 0x0000 }, /* R814 */
+        { 0x0000, 0x0000 }, /* R815 */
+        { 0x0000, 0x0000 }, /* R816 */
+        { 0x0000, 0x0000 }, /* R817 */
+        { 0x0000, 0x0000 }, /* R818 */
+        { 0x0000, 0x0000 }, /* R819 */
+        { 0x0000, 0x0000 }, /* R820 */
+        { 0x0000, 0x0000 }, /* R821 */
+        { 0x0000, 0x0000 }, /* R822 */
+        { 0x0000, 0x0000 }, /* R823 */
+        { 0x0000, 0x0000 }, /* R824 */
+        { 0x0000, 0x0000 }, /* R825 */
+        { 0x0000, 0x0000 }, /* R826 */
+        { 0x0000, 0x0000 }, /* R827 */
+        { 0x0000, 0x0000 }, /* R828 */
+        { 0x0000, 0x0000 }, /* R829 */
+        { 0x0000, 0x0000 }, /* R830 */
+        { 0x0000, 0x0000 }, /* R831 */
+        { 0x0000, 0x0000 }, /* R832 */
+        { 0x0000, 0x0000 }, /* R833 */
+        { 0x0000, 0x0000 }, /* R834 */
+        { 0x0000, 0x0000 }, /* R835 */
+        { 0x0000, 0x0000 }, /* R836 */
+        { 0x0000, 0x0000 }, /* R837 */
+        { 0x0000, 0x0000 }, /* R838 */
+        { 0x0000, 0x0000 }, /* R839 */
+        { 0x0000, 0x0000 }, /* R840 */
+        { 0x0000, 0x0000 }, /* R841 */
+        { 0x0000, 0x0000 }, /* R842 */
+        { 0x0000, 0x0000 }, /* R843 */
+        { 0x0000, 0x0000 }, /* R844 */
+        { 0x0000, 0x0000 }, /* R845 */
+        { 0x0000, 0x0000 }, /* R846 */
+        { 0x0000, 0x0000 }, /* R847 */
+        { 0x0000, 0x0000 }, /* R848 */
+        { 0x0000, 0x0000 }, /* R849 */
+        { 0x0000, 0x0000 }, /* R850 */
+        { 0x0000, 0x0000 }, /* R851 */
+        { 0x0000, 0x0000 }, /* R852 */
+        { 0x0000, 0x0000 }, /* R853 */
+        { 0x0000, 0x0000 }, /* R854 */
+        { 0x0000, 0x0000 }, /* R855 */
+        { 0x0000, 0x0000 }, /* R856 */
+        { 0x0000, 0x0000 }, /* R857 */
+        { 0x0000, 0x0000 }, /* R858 */
+        { 0x0000, 0x0000 }, /* R859 */
+        { 0x0000, 0x0000 }, /* R860 */
+        { 0x0000, 0x0000 }, /* R861 */
+        { 0x0000, 0x0000 }, /* R862 */
+        { 0x0000, 0x0000 }, /* R863 */
+        { 0x0000, 0x0000 }, /* R864 */
+        { 0x0000, 0x0000 }, /* R865 */
+        { 0x0000, 0x0000 }, /* R866 */
+        { 0x0000, 0x0000 }, /* R867 */
+        { 0x0000, 0x0000 }, /* R868 */
+        { 0x0000, 0x0000 }, /* R869 */
+        { 0x0000, 0x0000 }, /* R870 */
+        { 0x0000, 0x0000 }, /* R871 */
+        { 0x0000, 0x0000 }, /* R872 */
+        { 0x0000, 0x0000 }, /* R873 */
+        { 0x0000, 0x0000 }, /* R874 */
+        { 0x0000, 0x0000 }, /* R875 */
+        { 0x0000, 0x0000 }, /* R876 */
+        { 0x0000, 0x0000 }, /* R877 */
+        { 0x0000, 0x0000 }, /* R878 */
+        { 0x0000, 0x0000 }, /* R879 */
+        { 0x0000, 0x0000 }, /* R880 */
+        { 0x0000, 0x0000 }, /* R881 */
+        { 0x0000, 0x0000 }, /* R882 */
+        { 0x0000, 0x0000 }, /* R883 */
+        { 0x0000, 0x0000 }, /* R884 */
+        { 0x0000, 0x0000 }, /* R885 */
+        { 0x0000, 0x0000 }, /* R886 */
+        { 0x0000, 0x0000 }, /* R887 */
+        { 0x0000, 0x0000 }, /* R888 */
+        { 0x0000, 0x0000 }, /* R889 */
+        { 0x0000, 0x0000 }, /* R890 */
+        { 0x0000, 0x0000 }, /* R891 */
+        { 0x0000, 0x0000 }, /* R892 */
+        { 0x0000, 0x0000 }, /* R893 */
+        { 0x0000, 0x0000 }, /* R894 */
+        { 0x0000, 0x0000 }, /* R895 */
+        { 0x0000, 0x0000 }, /* R896 */
+        { 0x0000, 0x0000 }, /* R897 */
+        { 0x0000, 0x0000 }, /* R898 */
+        { 0x0000, 0x0000 }, /* R899 */
+        { 0x0000, 0x0000 }, /* R900 */
+        { 0x0000, 0x0000 }, /* R901 */
+        { 0x0000, 0x0000 }, /* R902 */
+        { 0x0000, 0x0000 }, /* R903 */
+        { 0x0000, 0x0000 }, /* R904 */
+        { 0x0000, 0x0000 }, /* R905 */
+        { 0x0000, 0x0000 }, /* R906 */
+        { 0x0000, 0x0000 }, /* R907 */
+        { 0x0000, 0x0000 }, /* R908 */
+        { 0x0000, 0x0000 }, /* R909 */
+        { 0x0000, 0x0000 }, /* R910 */
+        { 0x0000, 0x0000 }, /* R911 */
+        { 0x0000, 0x0000 }, /* R912 */
+        { 0x0000, 0x0000 }, /* R913 */
+        { 0x0000, 0x0000 }, /* R914 */
+        { 0x0000, 0x0000 }, /* R915 */
+        { 0x0000, 0x0000 }, /* R916 */
+        { 0x0000, 0x0000 }, /* R917 */
+        { 0x0000, 0x0000 }, /* R918 */
+        { 0x0000, 0x0000 }, /* R919 */
+        { 0x0000, 0x0000 }, /* R920 */
+        { 0x0000, 0x0000 }, /* R921 */
+        { 0x0000, 0x0000 }, /* R922 */
+        { 0x0000, 0x0000 }, /* R923 */
+        { 0x0000, 0x0000 }, /* R924 */
+        { 0x0000, 0x0000 }, /* R925 */
+        { 0x0000, 0x0000 }, /* R926 */
+        { 0x0000, 0x0000 }, /* R927 */
+        { 0x0000, 0x0000 }, /* R928 */
+        { 0x0000, 0x0000 }, /* R929 */
+        { 0x0000, 0x0000 }, /* R930 */
+        { 0x0000, 0x0000 }, /* R931 */
+        { 0x0000, 0x0000 }, /* R932 */
+        { 0x0000, 0x0000 }, /* R933 */
+        { 0x0000, 0x0000 }, /* R934 */
+        { 0x0000, 0x0000 }, /* R935 */
+        { 0x0000, 0x0000 }, /* R936 */
+        { 0x0000, 0x0000 }, /* R937 */
+        { 0x0000, 0x0000 }, /* R938 */
+        { 0x0000, 0x0000 }, /* R939 */
+        { 0x0000, 0x0000 }, /* R940 */
+        { 0x0000, 0x0000 }, /* R941 */
+        { 0x0000, 0x0000 }, /* R942 */
+        { 0x0000, 0x0000 }, /* R943 */
+        { 0x0000, 0x0000 }, /* R944 */
+        { 0x0000, 0x0000 }, /* R945 */
+        { 0x0000, 0x0000 }, /* R946 */
+        { 0x0000, 0x0000 }, /* R947 */
+        { 0x0000, 0x0000 }, /* R948 */
+        { 0x0000, 0x0000 }, /* R949 */
+        { 0x0000, 0x0000 }, /* R950 */
+        { 0x0000, 0x0000 }, /* R951 */
+        { 0x0000, 0x0000 }, /* R952 */
+        { 0x0000, 0x0000 }, /* R953 */
+        { 0x0000, 0x0000 }, /* R954 */
+        { 0x0000, 0x0000 }, /* R955 */
+        { 0x0000, 0x0000 }, /* R956 */
+        { 0x0000, 0x0000 }, /* R957 */
+        { 0x0000, 0x0000 }, /* R958 */
+        { 0x0000, 0x0000 }, /* R959 */
+        { 0x0000, 0x0000 }, /* R960 */
+        { 0x0000, 0x0000 }, /* R961 */
+        { 0x0000, 0x0000 }, /* R962 */
+        { 0x0000, 0x0000 }, /* R963 */
+        { 0x0000, 0x0000 }, /* R964 */
+        { 0x0000, 0x0000 }, /* R965 */
+        { 0x0000, 0x0000 }, /* R966 */
+        { 0x0000, 0x0000 }, /* R967 */
+        { 0x0000, 0x0000 }, /* R968 */
+        { 0x0000, 0x0000 }, /* R969 */
+        { 0x0000, 0x0000 }, /* R970 */
+        { 0x0000, 0x0000 }, /* R971 */
+        { 0x0000, 0x0000 }, /* R972 */
+        { 0x0000, 0x0000 }, /* R973 */
+        { 0x0000, 0x0000 }, /* R974 */
+        { 0x0000, 0x0000 }, /* R975 */
+        { 0x0000, 0x0000 }, /* R976 */
+        { 0x0000, 0x0000 }, /* R977 */
+        { 0x0000, 0x0000 }, /* R978 */
+        { 0x0000, 0x0000 }, /* R979 */
+        { 0x0000, 0x0000 }, /* R980 */
+        { 0x0000, 0x0000 }, /* R981 */
+        { 0x0000, 0x0000 }, /* R982 */
+        { 0x0000, 0x0000 }, /* R983 */
+        { 0x0000, 0x0000 }, /* R984 */
+        { 0x0000, 0x0000 }, /* R985 */
+        { 0x0000, 0x0000 }, /* R986 */
+        { 0x0000, 0x0000 }, /* R987 */
+        { 0x0000, 0x0000 }, /* R988 */
+        { 0x0000, 0x0000 }, /* R989 */
+        { 0x0000, 0x0000 }, /* R990 */
+        { 0x0000, 0x0000 }, /* R991 */
+        { 0x0000, 0x0000 }, /* R992 */
+        { 0x0000, 0x0000 }, /* R993 */
+        { 0x0000, 0x0000 }, /* R994 */
+        { 0x0000, 0x0000 }, /* R995 */
+        { 0x0000, 0x0000 }, /* R996 */
+        { 0x0000, 0x0000 }, /* R997 */
+        { 0x0000, 0x0000 }, /* R998 */
+        { 0x0000, 0x0000 }, /* R999 */
+        { 0x0000, 0x0000 }, /* R1000 */
+        { 0x0000, 0x0000 }, /* R1001 */
+        { 0x0000, 0x0000 }, /* R1002 */
+        { 0x0000, 0x0000 }, /* R1003 */
+        { 0x0000, 0x0000 }, /* R1004 */
+        { 0x0000, 0x0000 }, /* R1005 */
+        { 0x0000, 0x0000 }, /* R1006 */
+        { 0x0000, 0x0000 }, /* R1007 */
+        { 0x0000, 0x0000 }, /* R1008 */
+        { 0x0000, 0x0000 }, /* R1009 */
+        { 0x0000, 0x0000 }, /* R1010 */
+        { 0x0000, 0x0000 }, /* R1011 */
+        { 0x0000, 0x0000 }, /* R1012 */
+        { 0x0000, 0x0000 }, /* R1013 */
+        { 0x0000, 0x0000 }, /* R1014 */
+        { 0x0000, 0x0000 }, /* R1015 */
+        { 0x0000, 0x0000 }, /* R1016 */
+        { 0x0000, 0x0000 }, /* R1017 */
+        { 0x0000, 0x0000 }, /* R1018 */
+        { 0x0000, 0x0000 }, /* R1019 */
+        { 0x0000, 0x0000 }, /* R1020 */
+        { 0x0000, 0x0000 }, /* R1021 */
+        { 0x0000, 0x0000 }, /* R1022 */
+        { 0x0000, 0x0000 }, /* R1023 */
+        { 0x00FF, 0x01FF }, /* R1024  - AIF1 ADC1 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1025  - AIF1 ADC1 Right Volume */
+        { 0x00FF, 0x01FF }, /* R1026  - AIF1 DAC1 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1027  - AIF1 DAC1 Right Volume */
+        { 0x00FF, 0x01FF }, /* R1028  - AIF1 ADC2 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1029  - AIF1 ADC2 Right Volume */
+        { 0x00FF, 0x01FF }, /* R1030  - AIF1 DAC2 Left Volume */
+        { 0x00FF, 0x01FF }, /* R1031  - AIF1 DAC2 Right Volume */
+        { 0x0000, 0x0000 }, /* R1032 */
+        { 0x0000, 0x0000 }, /* R1033 */
+        { 0x0000, 0x0000 }, /* R1034 */
+        { 0x0000, 0x0000 }, /* R1035 */
+        { 0x0000, 0x0000 }, /* R1036 */
+        { 0x0000, 0x0000 }, /* R1037 */
+        { 0x0000, 0x0000 }, /* R1038 */
+        { 0x0000, 0x0000 }, /* R1039 */
+        { 0xF800, 0xF800 }, /* R1040  - AIF1 ADC1 Filters */
+        { 0x7800, 0x7800 }, /* R1041  - AIF1 ADC2 Filters */
+        { 0x0000, 0x0000 }, /* R1042 */
+        { 0x0000, 0x0000 }, /* R1043 */
+        { 0x0000, 0x0000 }, /* R1044 */
+        { 0x0000, 0x0000 }, /* R1045 */
+        { 0x0000, 0x0000 }, /* R1046 */
+        { 0x0000, 0x0000 }, /* R1047 */
+        { 0x0000, 0x0000 }, /* R1048 */
+        { 0x0000, 0x0000 }, /* R1049 */
+        { 0x0000, 0x0000 }, /* R1050 */
+        { 0x0000, 0x0000 }, /* R1051 */
+        { 0x0000, 0x0000 }, /* R1052 */
+        { 0x0000, 0x0000 }, /* R1053 */
+        { 0x0000, 0x0000 }, /* R1054 */
+        { 0x0000, 0x0000 }, /* R1055 */
+        { 0x02B6, 0x02B6 }, /* R1056  - AIF1 DAC1 Filters (1) */
+        { 0x3F00, 0x3F00 }, /* R1057  - AIF1 DAC1 Filters (2) */
+        { 0x02B6, 0x02B6 }, /* R1058  - AIF1 DAC2 Filters (1) */
+        { 0x3F00, 0x3F00 }, /* R1059  - AIF1 DAC2 Filters (2) */
+        { 0x0000, 0x0000 }, /* R1060 */
+        { 0x0000, 0x0000 }, /* R1061 */
+        { 0x0000, 0x0000 }, /* R1062 */
+        { 0x0000, 0x0000 }, /* R1063 */
+        { 0x0000, 0x0000 }, /* R1064 */
+        { 0x0000, 0x0000 }, /* R1065 */
+        { 0x0000, 0x0000 }, /* R1066 */
+        { 0x0000, 0x0000 }, /* R1067 */
+        { 0x0000, 0x0000 }, /* R1068 */
+        { 0x0000, 0x0000 }, /* R1069 */
+        { 0x0000, 0x0000 }, /* R1070 */
+        { 0x0000, 0x0000 }, /* R1071 */
+        { 0x0000, 0x0000 }, /* R1072 */
+        { 0x0000, 0x0000 }, /* R1073 */
+        { 0x0000, 0x0000 }, /* R1074 */
+        { 0x0000, 0x0000 }, /* R1075 */
+        { 0x0000, 0x0000 }, /* R1076 */
+        { 0x0000, 0x0000 }, /* R1077 */
+        { 0x0000, 0x0000 }, /* R1078 */
+        { 0x0000, 0x0000 }, /* R1079 */
+        { 0x0000, 0x0000 }, /* R1080 */
+        { 0x0000, 0x0000 }, /* R1081 */
+        { 0x0000, 0x0000 }, /* R1082 */
+        { 0x0000, 0x0000 }, /* R1083 */
+        { 0x0000, 0x0000 }, /* R1084 */
+        { 0x0000, 0x0000 }, /* R1085 */
+        { 0x0000, 0x0000 }, /* R1086 */
+        { 0x0000, 0x0000 }, /* R1087 */
+        { 0xFFFF, 0xFFFF }, /* R1088  - AIF1 DRC1 (1) */
+        { 0x1FFF, 0x1FFF }, /* R1089  - AIF1 DRC1 (2) */
+        { 0xFFFF, 0xFFFF }, /* R1090  - AIF1 DRC1 (3) */
+        { 0x07FF, 0x07FF }, /* R1091  - AIF1 DRC1 (4) */
+        { 0x03FF, 0x03FF }, /* R1092  - AIF1 DRC1 (5) */
+        { 0x0000, 0x0000 }, /* R1093 */
+        { 0x0000, 0x0000 }, /* R1094 */
+        { 0x0000, 0x0000 }, /* R1095 */
+        { 0x0000, 0x0000 }, /* R1096 */
+        { 0x0000, 0x0000 }, /* R1097 */
+        { 0x0000, 0x0000 }, /* R1098 */
+        { 0x0000, 0x0000 }, /* R1099 */
+        { 0x0000, 0x0000 }, /* R1100 */
+        { 0x0000, 0x0000 }, /* R1101 */
+        { 0x0000, 0x0000 }, /* R1102 */
+        { 0x0000, 0x0000 }, /* R1103 */
+        { 0xFFFF, 0xFFFF }, /* R1104  - AIF1 DRC2 (1) */
+        { 0x1FFF, 0x1FFF }, /* R1105  - AIF1 DRC2 (2) */
+        { 0xFFFF, 0xFFFF }, /* R1106  - AIF1 DRC2 (3) */
+        { 0x07FF, 0x07FF }, /* R1107  - AIF1 DRC2 (4) */
+        { 0x03FF, 0x03FF }, /* R1108  - AIF1 DRC2 (5) */
+        { 0x0000, 0x0000 }, /* R1109 */
+        { 0x0000, 0x0000 }, /* R1110 */
+        { 0x0000, 0x0000 }, /* R1111 */
+        { 0x0000, 0x0000 }, /* R1112 */
+        { 0x0000, 0x0000 }, /* R1113 */
+        { 0x0000, 0x0000 }, /* R1114 */
+        { 0x0000, 0x0000 }, /* R1115 */
+        { 0x0000, 0x0000 }, /* R1116 */
+        { 0x0000, 0x0000 }, /* R1117 */
+        { 0x0000, 0x0000 }, /* R1118 */
+        { 0x0000, 0x0000 }, /* R1119 */
+        { 0x0000, 0x0000 }, /* R1120 */
+        { 0x0000, 0x0000 }, /* R1121 */
+        { 0x0000, 0x0000 }, /* R1122 */
+        { 0x0000, 0x0000 }, /* R1123 */
+        { 0x0000, 0x0000 }, /* R1124 */
+        { 0x0000, 0x0000 }, /* R1125 */
+        { 0x0000, 0x0000 }, /* R1126 */
+        { 0x0000, 0x0000 }, /* R1127 */
+        { 0x0000, 0x0000 }, /* R1128 */
+        { 0x0000, 0x0000 }, /* R1129 */
+        { 0x0000, 0x0000 }, /* R1130 */
+        { 0x0000, 0x0000 }, /* R1131 */
+        { 0x0000, 0x0000 }, /* R1132 */
+        { 0x0000, 0x0000 }, /* R1133 */
+        { 0x0000, 0x0000 }, /* R1134 */
+        { 0x0000, 0x0000 }, /* R1135 */
+        { 0x0000, 0x0000 }, /* R1136 */
+        { 0x0000, 0x0000 }, /* R1137 */
+        { 0x0000, 0x0000 }, /* R1138 */
+        { 0x0000, 0x0000 }, /* R1139 */
+        { 0x0000, 0x0000 }, /* R1140 */
+        { 0x0000, 0x0000 }, /* R1141 */
+        { 0x0000, 0x0000 }, /* R1142 */
+        { 0x0000, 0x0000 }, /* R1143 */
+        { 0x0000, 0x0000 }, /* R1144 */
+        { 0x0000, 0x0000 }, /* R1145 */
+        { 0x0000, 0x0000 }, /* R1146 */
+        { 0x0000, 0x0000 }, /* R1147 */
+        { 0x0000, 0x0000 }, /* R1148 */
+        { 0x0000, 0x0000 }, /* R1149 */
+        { 0x0000, 0x0000 }, /* R1150 */
+        { 0x0000, 0x0000 }, /* R1151 */
+        { 0xFFFF, 0xFFFF }, /* R1152  - AIF1 DAC1 EQ Gains (1) */
+        { 0xFFC0, 0xFFC0 }, /* R1153  - AIF1 DAC1 EQ Gains (2) */
+        { 0xFFFF, 0xFFFF }, /* R1154  - AIF1 DAC1 EQ Band 1 A */
+        { 0xFFFF, 0xFFFF }, /* R1155  - AIF1 DAC1 EQ Band 1 B */
+        { 0xFFFF, 0xFFFF }, /* R1156  - AIF1 DAC1 EQ Band 1 PG */
+        { 0xFFFF, 0xFFFF }, /* R1157  - AIF1 DAC1 EQ Band 2 A */
+        { 0xFFFF, 0xFFFF }, /* R1158  - AIF1 DAC1 EQ Band 2 B */
+        { 0xFFFF, 0xFFFF }, /* R1159  - AIF1 DAC1 EQ Band 2 C */
+        { 0xFFFF, 0xFFFF }, /* R1160  - AIF1 DAC1 EQ Band 2 PG */
+        { 0xFFFF, 0xFFFF }, /* R1161  - AIF1 DAC1 EQ Band 3 A */
+        { 0xFFFF, 0xFFFF }, /* R1162  - AIF1 DAC1 EQ Band 3 B */
+        { 0xFFFF, 0xFFFF }, /* R1163  - AIF1 DAC1 EQ Band 3 C */
+        { 0xFFFF, 0xFFFF }, /* R1164  - AIF1 DAC1 EQ Band 3 PG */
+        { 0xFFFF, 0xFFFF }, /* R1165  - AIF1 DAC1 EQ Band 4 A */
+        { 0xFFFF, 0xFFFF }, /* R1166  - AIF1 DAC1 EQ Band 4 B */
+        { 0xFFFF, 0xFFFF }, /* R1167  - AIF1 DAC1 EQ Band 4 C */
+        { 0xFFFF, 0xFFFF }, /* R1168  - AIF1 DAC1 EQ Band 4 PG */
+        { 0xFFFF, 0xFFFF }, /* R1169  - AIF1 DAC1 EQ Band 5 A */
+        { 0xFFFF, 0xFFFF }, /* R1170  - AIF1 DAC1 EQ Band 5 B */
+        { 0xFFFF, 0xFFFF }, /* R1171  - AIF1 DAC1 EQ Band 5 PG */
+        { 0x0000, 0x0000 }, /* R1172 */
+        { 0x0000, 0x0000 }, /* R1173 */
+        { 0x0000, 0x0000 }, /* R1174 */
+        { 0x0000, 0x0000 }, /* R1175 */
+        { 0x0000, 0x0000 }, /* R1176 */
+        { 0x0000, 0x0000 }, /* R1177 */
+        { 0x0000, 0x0000 }, /* R1178 */
+        { 0x0000, 0x0000 }, /* R1179 */
+        { 0x0000, 0x0000 }, /* R1180 */
+        { 0x0000, 0x0000 }, /* R1181 */
+        { 0x0000, 0x0000 }, /* R1182 */
+        { 0x0000, 0x0000 }, /* R1183 */
+        { 0xFFFF, 0xFFFF }, /* R1184  - AIF1 DAC2 EQ Gains (1) */
+        { 0xFFC0, 0xFFC0 }, /* R1185  - AIF1 DAC2 EQ Gains (2) */
+        { 0xFFFF, 0xFFFF }, /* R1186  - AIF1 DAC2 EQ Band 1 A */
+        { 0xFFFF, 0xFFFF }, /* R1187  - AIF1 DAC2 EQ Band 1 B */
+        { 0xFFFF, 0xFFFF }, /* R1188  - AIF1 DAC2 EQ Band 1 PG */
+        { 0xFFFF, 0xFFFF }, /* R1189  - AIF1 DAC2 EQ Band 2 A */
+        { 0xFFFF, 0xFFFF }, /* R1190  - AIF1 DAC2 EQ Band 2 B */
+        { 0xFFFF, 0xFFFF }, /* R1191  - AIF1 DAC2 EQ Band 2 C */
+        { 0xFFFF, 0xFFFF }, /* R1192  - AIF1 DAC2 EQ Band 2 PG */
+        { 0xFFFF, 0xFFFF }, /* R1193  - AIF1 DAC2 EQ Band 3 A */
+        { 0xFFFF, 0xFFFF }, /* R1194  - AIF1 DAC2 EQ Band 3 B */
+        { 0xFFFF, 0xFFFF }, /* R1195  - AIF1 DAC2 EQ Band 3 C */
+        { 0xFFFF, 0xFFFF }, /* R1196  - AIF1 DAC2 EQ Band 3 PG */
+        { 0xFFFF, 0xFFFF }, /* R1197  - AIF1 DAC2 EQ Band 4 A */
+        { 0xFFFF, 0xFFFF }, /* R1198  - AIF1 DAC2 EQ Band 4 B */
+        { 0xFFFF, 0xFFFF }, /* R1199  - AIF1 DAC2 EQ Band 4 C */
+        { 0xFFFF, 0xFFFF }, /* R1200  - AIF1 DAC2 EQ Band 4 PG */
+        { 0xFFFF, 0xFFFF }, /* R1201  - AIF1 DAC2 EQ Band 5 A */
+        { 0xFFFF, 0xFFFF }, /* R1202  - AIF1 DAC2 EQ Band 5 B */
+        { 0xFFFF, 0xFFFF }, /* R1203  - AIF1 DAC2 EQ Band 5 PG */
+        { 0x0000, 0x0000 }, /* R1204 */
+        { 0x0000, 0x0000 }, /* R1205 */
+        { 0x0000, 0x0000 }, /* R1206 */
+        { 0x0000, 0x0000 }, /* R1207 */
+        { 0x0000, 0x0000 }, /* R1208 */
+        { 0x0000, 0x0000 }, /* R1209 */
+        { 0x0000, 0x0000 }, /* R1210 */
+        { 0x0000, 0x0000 }, /* R1211 */
+        { 0x0000, 0x0000 }, /* R1212 */
+        { 0x0000, 0x0000 }, /* R1213 */
+        { 0x0000, 0x0000 }, /* R1214 */
+        { 0x0000, 0x0000 }, /* R1215 */
+        { 0x0000, 0x0000 }, /* R1216 */
+        { 0x0000, 0x0000 }, /* R1217 */
+        { 0x0000, 0x0000 }, /* R1218 */
+        { 0x0000, 0x0000 }, /* R1219 */
+        { 0x0000, 0x0000 }, /* R1220 */
+        { 0x0000, 0x0000 }, /* R1221 */
+        { 0x0000, 0x0000 }, /* R1222 */
+        { 0x0000, 0x0000 }, /* R1223 */
+        { 0x0000, 0x0000 }, /* R1224 */
+        { 0x0000, 0x0000 }, /* R1225 */
+        { 0x0000, 0x0000 }, /* R1226 */
+        { 0x0000, 0x0000 }, /* R1227 */
+        { 0x0000, 0x0000 }, /* R1228 */
+        { 0x0000, 0x0000 }, /* R1229 */
+        { 0x0000, 0x0000 }, /* R1230 */
+        { 0x0000, 0x0000 }, /* R1231 */
+        { 0x0000, 0x0000 }, /* R1232 */
+        { 0x0000, 0x0000 }, /* R1233 */
+        { 0x0000, 0x0000 }, /* R1234 */
+        { 0x0000, 0x0000 }, /* R1235 */
+        { 0x0000, 0x0000 }, /* R1236 */
+        { 0x0000, 0x0000 }, /* R1237 */
+        { 0x0000, 0x0000 }, /* R1238 */
+        { 0x0000, 0x0000 }, /* R1239 */
+        { 0x0000, 0x0000 }, /* R1240 */
+        { 0x0000, 0x0000 }, /* R1241 */
+        { 0x0000, 0x0000 }, /* R1242 */
+        { 0x0000, 0x0000 }, /* R1243 */
+        { 0x0000, 0x0000 }, /* R1244 */
+        { 0x0000, 0x0000 }, /* R1245 */
+        { 0x0000, 0x0000 }, /* R1246 */
+        { 0x0000, 0x0000 }, /* R1247 */
+        { 0x0000, 0x0000 }, /* R1248 */
+        { 0x0000, 0x0000 }, /* R1249 */
+        { 0x0000, 0x0000 }, /* R1250 */
+        { 0x0000, 0x0000 }, /* R1251 */
+        { 0x0000, 0x0000 }, /* R1252 */
+        { 0x0000, 0x0000 }, /* R1253 */
+        { 0x0000, 0x0000 }, /* R1254 */
+        { 0x0000, 0x0000 }, /* R1255 */
+        { 0x0000, 0x0000 }, /* R1256 */
+        { 0x0000, 0x0000 }, /* R1257 */
+        { 0x0000, 0x0000 }, /* R1258 */
+        { 0x0000, 0x0000 }, /* R1259 */
+        { 0x0000, 0x0000 }, /* R1260 */
+        { 0x0000, 0x0000 }, /* R1261 */
+        { 0x0000, 0x0000 }, /* R1262 */
+        { 0x0000, 0x0000 }, /* R1263 */
+        { 0x0000, 0x0000 }, /* R1264 */
+        { 0x0000, 0x0000 }, /* R1265 */
+        { 0x0000, 0x0000 }, /* R1266 */
+        { 0x0000, 0x0000 }, /* R1267 */
+        { 0x0000, 0x0000 }, /* R1268 */
+        { 0x0000, 0x0000 }, /* R1269 */
+        { 0x0000, 0x0000 }, /* R1270 */
+        { 0x0000, 0x0000 }, /* R1271 */
+        { 0x0000, 0x0000 }, /* R1272 */
+        { 0x0000, 0x0000 }, /* R1273 */
+        { 0x0000, 0x0000 }, /* R1274 */
+        { 0x0000, 0x0000 }, /* R1275 */
+        { 0x0000, 0x0000 }, /* R1276 */
+        { 0x0000, 0x0000 }, /* R1277 */
+        { 0x0000, 0x0000 }, /* R1278 */
+        { 0x0000, 0x0000 }, /* R1279 */
+        { 0x00FF, 0x01FF }, /* R1280  - AIF2 ADC Left Volume */
+        { 0x00FF, 0x01FF }, /* R1281  - AIF2 ADC Right Volume */
+        { 0x00FF, 0x01FF }, /* R1282  - AIF2 DAC Left Volume */
+        { 0x00FF, 0x01FF }, /* R1283  - AIF2 DAC Right Volume */
+        { 0x0000, 0x0000 }, /* R1284 */
+        { 0x0000, 0x0000 }, /* R1285 */
+        { 0x0000, 0x0000 }, /* R1286 */
+        { 0x0000, 0x0000 }, /* R1287 */
+        { 0x0000, 0x0000 }, /* R1288 */
+        { 0x0000, 0x0000 }, /* R1289 */
+        { 0x0000, 0x0000 }, /* R1290 */
+        { 0x0000, 0x0000 }, /* R1291 */
+        { 0x0000, 0x0000 }, /* R1292 */
+        { 0x0000, 0x0000 }, /* R1293 */
+        { 0x0000, 0x0000 }, /* R1294 */
+        { 0x0000, 0x0000 }, /* R1295 */
+        { 0xF800, 0xF800 }, /* R1296  - AIF2 ADC Filters */
+        { 0x0000, 0x0000 }, /* R1297 */
+        { 0x0000, 0x0000 }, /* R1298 */
+        { 0x0000, 0x0000 }, /* R1299 */
+        { 0x0000, 0x0000 }, /* R1300 */
+        { 0x0000, 0x0000 }, /* R1301 */
+        { 0x0000, 0x0000 }, /* R1302 */
+        { 0x0000, 0x0000 }, /* R1303 */
+        { 0x0000, 0x0000 }, /* R1304 */
+        { 0x0000, 0x0000 }, /* R1305 */
+        { 0x0000, 0x0000 }, /* R1306 */
+        { 0x0000, 0x0000 }, /* R1307 */
+        { 0x0000, 0x0000 }, /* R1308 */
+        { 0x0000, 0x0000 }, /* R1309 */
+        { 0x0000, 0x0000 }, /* R1310 */
+        { 0x0000, 0x0000 }, /* R1311 */
+        { 0x02B6, 0x02B6 }, /* R1312  - AIF2 DAC Filters (1) */
+        { 0x3F00, 0x3F00 }, /* R1313  - AIF2 DAC Filters (2) */
+        { 0x0000, 0x0000 }, /* R1314 */
+        { 0x0000, 0x0000 }, /* R1315 */
+        { 0x0000, 0x0000 }, /* R1316 */
+        { 0x0000, 0x0000 }, /* R1317 */
+        { 0x0000, 0x0000 }, /* R1318 */
+        { 0x0000, 0x0000 }, /* R1319 */
+        { 0x0000, 0x0000 }, /* R1320 */
+        { 0x0000, 0x0000 }, /* R1321 */
+        { 0x0000, 0x0000 }, /* R1322 */
+        { 0x0000, 0x0000 }, /* R1323 */
+        { 0x0000, 0x0000 }, /* R1324 */
+        { 0x0000, 0x0000 }, /* R1325 */
+        { 0x0000, 0x0000 }, /* R1326 */
+        { 0x0000, 0x0000 }, /* R1327 */
+        { 0x0000, 0x0000 }, /* R1328 */
+        { 0x0000, 0x0000 }, /* R1329 */
+        { 0x0000, 0x0000 }, /* R1330 */
+        { 0x0000, 0x0000 }, /* R1331 */
+        { 0x0000, 0x0000 }, /* R1332 */
+        { 0x0000, 0x0000 }, /* R1333 */
+        { 0x0000, 0x0000 }, /* R1334 */
+        { 0x0000, 0x0000 }, /* R1335 */
+        { 0x0000, 0x0000 }, /* R1336 */
+        { 0x0000, 0x0000 }, /* R1337 */
+        { 0x0000, 0x0000 }, /* R1338 */
+        { 0x0000, 0x0000 }, /* R1339 */
+        { 0x0000, 0x0000 }, /* R1340 */
+        { 0x0000, 0x0000 }, /* R1341 */
+        { 0x0000, 0x0000 }, /* R1342 */
+        { 0x0000, 0x0000 }, /* R1343 */
+        { 0xFFFF, 0xFFFF }, /* R1344  - AIF2 DRC (1) */
+        { 0x1FFF, 0x1FFF }, /* R1345  - AIF2 DRC (2) */
+        { 0xFFFF, 0xFFFF }, /* R1346  - AIF2 DRC (3) */
+        { 0x07FF, 0x07FF }, /* R1347  - AIF2 DRC (4) */
+        { 0x03FF, 0x03FF }, /* R1348  - AIF2 DRC (5) */
+        { 0x0000, 0x0000 }, /* R1349 */
+        { 0x0000, 0x0000 }, /* R1350 */
+        { 0x0000, 0x0000 }, /* R1351 */
+        { 0x0000, 0x0000 }, /* R1352 */
+        { 0x0000, 0x0000 }, /* R1353 */
+        { 0x0000, 0x0000 }, /* R1354 */
+        { 0x0000, 0x0000 }, /* R1355 */
+        { 0x0000, 0x0000 }, /* R1356 */
+        { 0x0000, 0x0000 }, /* R1357 */
+        { 0x0000, 0x0000 }, /* R1358 */
+        { 0x0000, 0x0000 }, /* R1359 */
+        { 0x0000, 0x0000 }, /* R1360 */
+        { 0x0000, 0x0000 }, /* R1361 */
+        { 0x0000, 0x0000 }, /* R1362 */
+        { 0x0000, 0x0000 }, /* R1363 */
+        { 0x0000, 0x0000 }, /* R1364 */
+        { 0x0000, 0x0000 }, /* R1365 */
+        { 0x0000, 0x0000 }, /* R1366 */
+        { 0x0000, 0x0000 }, /* R1367 */
+        { 0x0000, 0x0000 }, /* R1368 */
+        { 0x0000, 0x0000 }, /* R1369 */
+        { 0x0000, 0x0000 }, /* R1370 */
+        { 0x0000, 0x0000 }, /* R1371 */
+        { 0x0000, 0x0000 }, /* R1372 */
+        { 0x0000, 0x0000 }, /* R1373 */
+        { 0x0000, 0x0000 }, /* R1374 */
+        { 0x0000, 0x0000 }, /* R1375 */
+        { 0x0000, 0x0000 }, /* R1376 */
+        { 0x0000, 0x0000 }, /* R1377 */
+        { 0x0000, 0x0000 }, /* R1378 */
+        { 0x0000, 0x0000 }, /* R1379 */
+        { 0x0000, 0x0000 }, /* R1380 */
+        { 0x0000, 0x0000 }, /* R1381 */
+        { 0x0000, 0x0000 }, /* R1382 */
+        { 0x0000, 0x0000 }, /* R1383 */
+        { 0x0000, 0x0000 }, /* R1384 */
+        { 0x0000, 0x0000 }, /* R1385 */
+        { 0x0000, 0x0000 }, /* R1386 */
+        { 0x0000, 0x0000 }, /* R1387 */
+        { 0x0000, 0x0000 }, /* R1388 */
+        { 0x0000, 0x0000 }, /* R1389 */
+        { 0x0000, 0x0000 }, /* R1390 */
+        { 0x0000, 0x0000 }, /* R1391 */
+        { 0x0000, 0x0000 }, /* R1392 */
+        { 0x0000, 0x0000 }, /* R1393 */
+        { 0x0000, 0x0000 }, /* R1394 */
+        { 0x0000, 0x0000 }, /* R1395 */
+        { 0x0000, 0x0000 }, /* R1396 */
+        { 0x0000, 0x0000 }, /* R1397 */
+        { 0x0000, 0x0000 }, /* R1398 */
+        { 0x0000, 0x0000 }, /* R1399 */
+        { 0x0000, 0x0000 }, /* R1400 */
+        { 0x0000, 0x0000 }, /* R1401 */
+        { 0x0000, 0x0000 }, /* R1402 */
+        { 0x0000, 0x0000 }, /* R1403 */
+        { 0x0000, 0x0000 }, /* R1404 */
+        { 0x0000, 0x0000 }, /* R1405 */
+        { 0x0000, 0x0000 }, /* R1406 */
+        { 0x0000, 0x0000 }, /* R1407 */
+        { 0xFFFF, 0xFFFF }, /* R1408  - AIF2 EQ Gains (1) */
+        { 0xFFC0, 0xFFC0 }, /* R1409  - AIF2 EQ Gains (2) */
+        { 0xFFFF, 0xFFFF }, /* R1410  - AIF2 EQ Band 1 A */
+        { 0xFFFF, 0xFFFF }, /* R1411  - AIF2 EQ Band 1 B */
+        { 0xFFFF, 0xFFFF }, /* R1412  - AIF2 EQ Band 1 PG */
+        { 0xFFFF, 0xFFFF }, /* R1413  - AIF2 EQ Band 2 A */
+        { 0xFFFF, 0xFFFF }, /* R1414  - AIF2 EQ Band 2 B */
+        { 0xFFFF, 0xFFFF }, /* R1415  - AIF2 EQ Band 2 C */
+        { 0xFFFF, 0xFFFF }, /* R1416  - AIF2 EQ Band 2 PG */
+        { 0xFFFF, 0xFFFF }, /* R1417  - AIF2 EQ Band 3 A */
+        { 0xFFFF, 0xFFFF }, /* R1418  - AIF2 EQ Band 3 B */
+        { 0xFFFF, 0xFFFF }, /* R1419  - AIF2 EQ Band 3 C */
+        { 0xFFFF, 0xFFFF }, /* R1420  - AIF2 EQ Band 3 PG */
+        { 0xFFFF, 0xFFFF }, /* R1421  - AIF2 EQ Band 4 A */
+        { 0xFFFF, 0xFFFF }, /* R1422  - AIF2 EQ Band 4 B */
+        { 0xFFFF, 0xFFFF }, /* R1423  - AIF2 EQ Band 4 C */
+        { 0xFFFF, 0xFFFF }, /* R1424  - AIF2 EQ Band 4 PG */
+        { 0xFFFF, 0xFFFF }, /* R1425  - AIF2 EQ Band 5 A */
+        { 0xFFFF, 0xFFFF }, /* R1426  - AIF2 EQ Band 5 B */
+        { 0xFFFF, 0xFFFF }, /* R1427  - AIF2 EQ Band 5 PG */
+        { 0x0000, 0x0000 }, /* R1428 */
+        { 0x0000, 0x0000 }, /* R1429 */
+        { 0x0000, 0x0000 }, /* R1430 */
+        { 0x0000, 0x0000 }, /* R1431 */
+        { 0x0000, 0x0000 }, /* R1432 */
+        { 0x0000, 0x0000 }, /* R1433 */
+        { 0x0000, 0x0000 }, /* R1434 */
+        { 0x0000, 0x0000 }, /* R1435 */
+        { 0x0000, 0x0000 }, /* R1436 */
+        { 0x0000, 0x0000 }, /* R1437 */
+        { 0x0000, 0x0000 }, /* R1438 */
+        { 0x0000, 0x0000 }, /* R1439 */
+        { 0x0000, 0x0000 }, /* R1440 */
+        { 0x0000, 0x0000 }, /* R1441 */
+        { 0x0000, 0x0000 }, /* R1442 */
+        { 0x0000, 0x0000 }, /* R1443 */
+        { 0x0000, 0x0000 }, /* R1444 */
+        { 0x0000, 0x0000 }, /* R1445 */
+        { 0x0000, 0x0000 }, /* R1446 */
+        { 0x0000, 0x0000 }, /* R1447 */
+        { 0x0000, 0x0000 }, /* R1448 */
+        { 0x0000, 0x0000 }, /* R1449 */
+        { 0x0000, 0x0000 }, /* R1450 */
+        { 0x0000, 0x0000 }, /* R1451 */
+        { 0x0000, 0x0000 }, /* R1452 */
+        { 0x0000, 0x0000 }, /* R1453 */
+        { 0x0000, 0x0000 }, /* R1454 */
+        { 0x0000, 0x0000 }, /* R1455 */
+        { 0x0000, 0x0000 }, /* R1456 */
+        { 0x0000, 0x0000 }, /* R1457 */
+        { 0x0000, 0x0000 }, /* R1458 */
+        { 0x0000, 0x0000 }, /* R1459 */
+        { 0x0000, 0x0000 }, /* R1460 */
+        { 0x0000, 0x0000 }, /* R1461 */
+        { 0x0000, 0x0000 }, /* R1462 */
+        { 0x0000, 0x0000 }, /* R1463 */
+        { 0x0000, 0x0000 }, /* R1464 */
+        { 0x0000, 0x0000 }, /* R1465 */
+        { 0x0000, 0x0000 }, /* R1466 */
+        { 0x0000, 0x0000 }, /* R1467 */
+        { 0x0000, 0x0000 }, /* R1468 */
+        { 0x0000, 0x0000 }, /* R1469 */
+        { 0x0000, 0x0000 }, /* R1470 */
+        { 0x0000, 0x0000 }, /* R1471 */
+        { 0x0000, 0x0000 }, /* R1472 */
+        { 0x0000, 0x0000 }, /* R1473 */
+        { 0x0000, 0x0000 }, /* R1474 */
+        { 0x0000, 0x0000 }, /* R1475 */
+        { 0x0000, 0x0000 }, /* R1476 */
+        { 0x0000, 0x0000 }, /* R1477 */
+        { 0x0000, 0x0000 }, /* R1478 */
+        { 0x0000, 0x0000 }, /* R1479 */
+        { 0x0000, 0x0000 }, /* R1480 */
+        { 0x0000, 0x0000 }, /* R1481 */
+        { 0x0000, 0x0000 }, /* R1482 */
+        { 0x0000, 0x0000 }, /* R1483 */
+        { 0x0000, 0x0000 }, /* R1484 */
+        { 0x0000, 0x0000 }, /* R1485 */
+        { 0x0000, 0x0000 }, /* R1486 */
+        { 0x0000, 0x0000 }, /* R1487 */
+        { 0x0000, 0x0000 }, /* R1488 */
+        { 0x0000, 0x0000 }, /* R1489 */
+        { 0x0000, 0x0000 }, /* R1490 */
+        { 0x0000, 0x0000 }, /* R1491 */
+        { 0x0000, 0x0000 }, /* R1492 */
+        { 0x0000, 0x0000 }, /* R1493 */
+        { 0x0000, 0x0000 }, /* R1494 */
+        { 0x0000, 0x0000 }, /* R1495 */
+        { 0x0000, 0x0000 }, /* R1496 */
+        { 0x0000, 0x0000 }, /* R1497 */
+        { 0x0000, 0x0000 }, /* R1498 */
+        { 0x0000, 0x0000 }, /* R1499 */
+        { 0x0000, 0x0000 }, /* R1500 */
+        { 0x0000, 0x0000 }, /* R1501 */
+        { 0x0000, 0x0000 }, /* R1502 */
+        { 0x0000, 0x0000 }, /* R1503 */
+        { 0x0000, 0x0000 }, /* R1504 */
+        { 0x0000, 0x0000 }, /* R1505 */
+        { 0x0000, 0x0000 }, /* R1506 */
+        { 0x0000, 0x0000 }, /* R1507 */
+        { 0x0000, 0x0000 }, /* R1508 */
+        { 0x0000, 0x0000 }, /* R1509 */
+        { 0x0000, 0x0000 }, /* R1510 */
+        { 0x0000, 0x0000 }, /* R1511 */
+        { 0x0000, 0x0000 }, /* R1512 */
+        { 0x0000, 0x0000 }, /* R1513 */
+        { 0x0000, 0x0000 }, /* R1514 */
+        { 0x0000, 0x0000 }, /* R1515 */
+        { 0x0000, 0x0000 }, /* R1516 */
+        { 0x0000, 0x0000 }, /* R1517 */
+        { 0x0000, 0x0000 }, /* R1518 */
+        { 0x0000, 0x0000 }, /* R1519 */
+        { 0x0000, 0x0000 }, /* R1520 */
+        { 0x0000, 0x0000 }, /* R1521 */
+        { 0x0000, 0x0000 }, /* R1522 */
+        { 0x0000, 0x0000 }, /* R1523 */
+        { 0x0000, 0x0000 }, /* R1524 */
+        { 0x0000, 0x0000 }, /* R1525 */
+        { 0x0000, 0x0000 }, /* R1526 */
+        { 0x0000, 0x0000 }, /* R1527 */
+        { 0x0000, 0x0000 }, /* R1528 */
+        { 0x0000, 0x0000 }, /* R1529 */
+        { 0x0000, 0x0000 }, /* R1530 */
+        { 0x0000, 0x0000 }, /* R1531 */
+        { 0x0000, 0x0000 }, /* R1532 */
+        { 0x0000, 0x0000 }, /* R1533 */
+        { 0x0000, 0x0000 }, /* R1534 */
+        { 0x0000, 0x0000 }, /* R1535 */
+        { 0x01EF, 0x01EF }, /* R1536  - DAC1 Mixer Volumes */
+        { 0x0037, 0x0037 }, /* R1537  - DAC1 Left Mixer Routing */
+        { 0x0037, 0x0037 }, /* R1538  - DAC1 Right Mixer Routing */
+        { 0x01EF, 0x01EF }, /* R1539  - DAC2 Mixer Volumes */
+        { 0x0037, 0x0037 }, /* R1540  - DAC2 Left Mixer Routing */
+        { 0x0037, 0x0037 }, /* R1541  - DAC2 Right Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1542  - AIF1 ADC1 Left Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1543  - AIF1 ADC1 Right Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1544  - AIF1 ADC2 Left Mixer Routing */
+        { 0x0003, 0x0003 }, /* R1545  - AIF1 ADC2 Right mixer Routing */
+        { 0x0000, 0x0000 }, /* R1546 */
+        { 0x0000, 0x0000 }, /* R1547 */
+        { 0x0000, 0x0000 }, /* R1548 */
+        { 0x0000, 0x0000 }, /* R1549 */
+        { 0x0000, 0x0000 }, /* R1550 */
+        { 0x0000, 0x0000 }, /* R1551 */
+        { 0x02FF, 0x03FF }, /* R1552  - DAC1 Left Volume */
+        { 0x02FF, 0x03FF }, /* R1553  - DAC1 Right Volume */
+        { 0x02FF, 0x03FF }, /* R1554  - DAC2 Left Volume */
+        { 0x02FF, 0x03FF }, /* R1555  - DAC2 Right Volume */
+        { 0x0003, 0x0003 }, /* R1556  - DAC Softmute */
+        { 0x0000, 0x0000 }, /* R1557 */
+        { 0x0000, 0x0000 }, /* R1558 */
+        { 0x0000, 0x0000 }, /* R1559 */
+        { 0x0000, 0x0000 }, /* R1560 */
+        { 0x0000, 0x0000 }, /* R1561 */
+        { 0x0000, 0x0000 }, /* R1562 */
+        { 0x0000, 0x0000 }, /* R1563 */
+        { 0x0000, 0x0000 }, /* R1564 */
+        { 0x0000, 0x0000 }, /* R1565 */
+        { 0x0000, 0x0000 }, /* R1566 */
+        { 0x0000, 0x0000 }, /* R1567 */
+        { 0x0003, 0x0003 }, /* R1568  - Oversampling */
+        { 0x03C3, 0x03C3 }, /* R1569  - Sidetone */
+};
+
+const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = {
+        0x8994,     /* R0     - Software Reset */
+        0x0000,     /* R1     - Power Management (1) */
+        0x6000,     /* R2     - Power Management (2) */
+        0x0000,     /* R3     - Power Management (3) */
+        0x0000,     /* R4     - Power Management (4) */
+        0x0000,     /* R5     - Power Management (5) */
+        0x0000,     /* R6     - Power Management (6) */
+        0x0000,     /* R7 */
+        0x0000,     /* R8 */
+        0x0000,     /* R9 */
+        0x0000,     /* R10 */
+        0x0000,     /* R11 */
+        0x0000,     /* R12 */
+        0x0000,     /* R13 */
+        0x0000,     /* R14 */
+        0x0000,     /* R15 */
+        0x0000,     /* R16 */
+        0x0000,     /* R17 */
+        0x0000,     /* R18 */
+        0x0000,     /* R19 */
+        0x0000,     /* R20 */
+        0x0000,     /* R21    - Input Mixer (1) */
+        0x0000,     /* R22 */
+        0x0000,     /* R23 */
+        0x008B,     /* R24    - Left Line Input 1&2 Volume */
+        0x008B,     /* R25    - Left Line Input 3&4 Volume */
+        0x008B,     /* R26    - Right Line Input 1&2 Volume */
+        0x008B,     /* R27    - Right Line Input 3&4 Volume */
+        0x006D,     /* R28    - Left Output Volume */
+        0x006D,     /* R29    - Right Output Volume */
+        0x0066,     /* R30    - Line Outputs Volume */
+        0x0020,     /* R31    - HPOUT2 Volume */
+        0x0079,     /* R32    - Left OPGA Volume */
+        0x0079,     /* R33    - Right OPGA Volume */
+        0x0003,     /* R34    - SPKMIXL Attenuation */
+        0x0003,     /* R35    - SPKMIXR Attenuation */
+        0x0011,     /* R36    - SPKOUT Mixers */
+        0x0140,     /* R37    - ClassD */
+        0x0079,     /* R38    - Speaker Volume Left */
+        0x0079,     /* R39    - Speaker Volume Right */
+        0x0000,     /* R40    - Input Mixer (2) */
+        0x0000,     /* R41    - Input Mixer (3) */
+        0x0000,     /* R42    - Input Mixer (4) */
+        0x0000,     /* R43    - Input Mixer (5) */
+        0x0000,     /* R44    - Input Mixer (6) */
+        0x0000,     /* R45    - Output Mixer (1) */
+        0x0000,     /* R46    - Output Mixer (2) */
+        0x0000,     /* R47    - Output Mixer (3) */
+        0x0000,     /* R48    - Output Mixer (4) */
+        0x0000,     /* R49    - Output Mixer (5) */
+        0x0000,     /* R50    - Output Mixer (6) */
+        0x0000,     /* R51    - HPOUT2 Mixer */
+        0x0000,     /* R52    - Line Mixer (1) */
+        0x0000,     /* R53    - Line Mixer (2) */
+        0x0000,     /* R54    - Speaker Mixer */
+        0x0000,     /* R55    - Additional Control */
+        0x0000,     /* R56    - AntiPOP (1) */
+        0x0000,     /* R57    - AntiPOP (2) */
+        0x0000,     /* R58    - MICBIAS */
+        0x000D,     /* R59    - LDO 1 */
+        0x0003,     /* R60    - LDO 2 */
+        0x0000,     /* R61 */
+        0x0000,     /* R62 */
+        0x0000,     /* R63 */
+        0x0000,     /* R64 */
+        0x0000,     /* R65 */
+        0x0000,     /* R66 */
+        0x0000,     /* R67 */
+        0x0000,     /* R68 */
+        0x0000,     /* R69 */
+        0x0000,     /* R70 */
+        0x0000,     /* R71 */
+        0x0000,     /* R72 */
+        0x0000,     /* R73 */
+        0x0000,     /* R74 */
+        0x0000,     /* R75 */
+        0x1F25,     /* R76    - Charge Pump (1) */
+        0x0000,     /* R77 */
+        0x0000,     /* R78 */
+        0x0000,     /* R79 */
+        0x0000,     /* R80 */
+        0x0004,     /* R81    - Class W (1) */
+        0x0000,     /* R82 */
+        0x0000,     /* R83 */
+        0x0000,     /* R84    - DC Servo (1) */
+        0x054A,     /* R85    - DC Servo (2) */
+        0x0000,     /* R86 */
+        0x0000,     /* R87    - DC Servo (4) */
+        0x0000,     /* R88    - DC Servo Readback */
+        0x0000,     /* R89 */
+        0x0000,     /* R90 */
+        0x0000,     /* R91 */
+        0x0000,     /* R92 */
+        0x0000,     /* R93 */
+        0x0000,     /* R94 */
+        0x0000,     /* R95 */
+        0x0000,     /* R96    - Analogue HP (1) */
+        0x0000,     /* R97 */
+        0x0000,     /* R98 */
+        0x0000,     /* R99 */
+        0x0000,     /* R100 */
+        0x0000,     /* R101 */
+        0x0000,     /* R102 */
+        0x0000,     /* R103 */
+        0x0000,     /* R104 */
+        0x0000,     /* R105 */
+        0x0000,     /* R106 */
+        0x0000,     /* R107 */
+        0x0000,     /* R108 */
+        0x0000,     /* R109 */
+        0x0000,     /* R110 */
+        0x0000,     /* R111 */
+        0x0000,     /* R112 */
+        0x0000,     /* R113 */
+        0x0000,     /* R114 */
+        0x0000,     /* R115 */
+        0x0000,     /* R116 */
+        0x0000,     /* R117 */
+        0x0000,     /* R118 */
+        0x0000,     /* R119 */
+        0x0000,     /* R120 */
+        0x0000,     /* R121 */
+        0x0000,     /* R122 */
+        0x0000,     /* R123 */
+        0x0000,     /* R124 */
+        0x0000,     /* R125 */
+        0x0000,     /* R126 */
+        0x0000,     /* R127 */
+        0x0000,     /* R128 */
+        0x0000,     /* R129 */
+        0x0000,     /* R130 */
+        0x0000,     /* R131 */
+        0x0000,     /* R132 */
+        0x0000,     /* R133 */
+        0x0000,     /* R134 */
+        0x0000,     /* R135 */
+        0x0000,     /* R136 */
+        0x0000,     /* R137 */
+        0x0000,     /* R138 */
+        0x0000,     /* R139 */
+        0x0000,     /* R140 */
+        0x0000,     /* R141 */
+        0x0000,     /* R142 */
+        0x0000,     /* R143 */
+        0x0000,     /* R144 */
+        0x0000,     /* R145 */
+        0x0000,     /* R146 */
+        0x0000,     /* R147 */
+        0x0000,     /* R148 */
+        0x0000,     /* R149 */
+        0x0000,     /* R150 */
+        0x0000,     /* R151 */
+        0x0000,     /* R152 */
+        0x0000,     /* R153 */
+        0x0000,     /* R154 */
+        0x0000,     /* R155 */
+        0x0000,     /* R156 */
+        0x0000,     /* R157 */
+        0x0000,     /* R158 */
+        0x0000,     /* R159 */
+        0x0000,     /* R160 */
+        0x0000,     /* R161 */
+        0x0000,     /* R162 */
+        0x0000,     /* R163 */
+        0x0000,     /* R164 */
+        0x0000,     /* R165 */
+        0x0000,     /* R166 */
+        0x0000,     /* R167 */
+        0x0000,     /* R168 */
+        0x0000,     /* R169 */
+        0x0000,     /* R170 */
+        0x0000,     /* R171 */
+        0x0000,     /* R172 */
+        0x0000,     /* R173 */
+        0x0000,     /* R174 */
+        0x0000,     /* R175 */
+        0x0000,     /* R176 */
+        0x0000,     /* R177 */
+        0x0000,     /* R178 */
+        0x0000,     /* R179 */
+        0x0000,     /* R180 */
+        0x0000,     /* R181 */
+        0x0000,     /* R182 */
+        0x0000,     /* R183 */
+        0x0000,     /* R184 */
+        0x0000,     /* R185 */
+        0x0000,     /* R186 */
+        0x0000,     /* R187 */
+        0x0000,     /* R188 */
+        0x0000,     /* R189 */
+        0x0000,     /* R190 */
+        0x0000,     /* R191 */
+        0x0000,     /* R192 */
+        0x0000,     /* R193 */
+        0x0000,     /* R194 */
+        0x0000,     /* R195 */
+        0x0000,     /* R196 */
+        0x0000,     /* R197 */
+        0x0000,     /* R198 */
+        0x0000,     /* R199 */
+        0x0000,     /* R200 */
+        0x0000,     /* R201 */
+        0x0000,     /* R202 */
+        0x0000,     /* R203 */
+        0x0000,     /* R204 */
+        0x0000,     /* R205 */
+        0x0000,     /* R206 */
+        0x0000,     /* R207 */
+        0x0000,     /* R208 */
+        0x0000,     /* R209 */
+        0x0000,     /* R210 */
+        0x0000,     /* R211 */
+        0x0000,     /* R212 */
+        0x0000,     /* R213 */
+        0x0000,     /* R214 */
+        0x0000,     /* R215 */
+        0x0000,     /* R216 */
+        0x0000,     /* R217 */
+        0x0000,     /* R218 */
+        0x0000,     /* R219 */
+        0x0000,     /* R220 */
+        0x0000,     /* R221 */
+        0x0000,     /* R222 */
+        0x0000,     /* R223 */
+        0x0000,     /* R224 */
+        0x0000,     /* R225 */
+        0x0000,     /* R226 */
+        0x0000,     /* R227 */
+        0x0000,     /* R228 */
+        0x0000,     /* R229 */
+        0x0000,     /* R230 */
+        0x0000,     /* R231 */
+        0x0000,     /* R232 */
+        0x0000,     /* R233 */
+        0x0000,     /* R234 */
+        0x0000,     /* R235 */
+        0x0000,     /* R236 */
+        0x0000,     /* R237 */
+        0x0000,     /* R238 */
+        0x0000,     /* R239 */
+        0x0000,     /* R240 */
+        0x0000,     /* R241 */
+        0x0000,     /* R242 */
+        0x0000,     /* R243 */
+        0x0000,     /* R244 */
+        0x0000,     /* R245 */
+        0x0000,     /* R246 */
+        0x0000,     /* R247 */
+        0x0000,     /* R248 */
+        0x0000,     /* R249 */
+        0x0000,     /* R250 */
+        0x0000,     /* R251 */
+        0x0000,     /* R252 */
+        0x0000,     /* R253 */
+        0x0000,     /* R254 */
+        0x0000,     /* R255 */
+        0x0003,     /* R256   - Chip Revision */
+        0x8004,     /* R257   - Control Interface */
+        0x0000,     /* R258 */
+        0x0000,     /* R259 */
+        0x0000,     /* R260 */
+        0x0000,     /* R261 */
+        0x0000,     /* R262 */
+        0x0000,     /* R263 */
+        0x0000,     /* R264 */
+        0x0000,     /* R265 */
+        0x0000,     /* R266 */
+        0x0000,     /* R267 */
+        0x0000,     /* R268 */
+        0x0000,     /* R269 */
+        0x0000,     /* R270 */
+        0x0000,     /* R271 */
+        0x0000,     /* R272   - Write Sequencer Ctrl (1) */
+        0x0000,     /* R273   - Write Sequencer Ctrl (2) */
+        0x0000,     /* R274 */
+        0x0000,     /* R275 */
+        0x0000,     /* R276 */
+        0x0000,     /* R277 */
+        0x0000,     /* R278 */
+        0x0000,     /* R279 */
+        0x0000,     /* R280 */
+        0x0000,     /* R281 */
+        0x0000,     /* R282 */
+        0x0000,     /* R283 */
+        0x0000,     /* R284 */
+        0x0000,     /* R285 */
+        0x0000,     /* R286 */
+        0x0000,     /* R287 */
+        0x0000,     /* R288 */
+        0x0000,     /* R289 */
+        0x0000,     /* R290 */
+        0x0000,     /* R291 */
+        0x0000,     /* R292 */
+        0x0000,     /* R293 */
+        0x0000,     /* R294 */
+        0x0000,     /* R295 */
+        0x0000,     /* R296 */
+        0x0000,     /* R297 */
+        0x0000,     /* R298 */
+        0x0000,     /* R299 */
+        0x0000,     /* R300 */
+        0x0000,     /* R301 */
+        0x0000,     /* R302 */
+        0x0000,     /* R303 */
+        0x0000,     /* R304 */
+        0x0000,     /* R305 */
+        0x0000,     /* R306 */
+        0x0000,     /* R307 */
+        0x0000,     /* R308 */
+        0x0000,     /* R309 */
+        0x0000,     /* R310 */
+        0x0000,     /* R311 */
+        0x0000,     /* R312 */
+        0x0000,     /* R313 */
+        0x0000,     /* R314 */
+        0x0000,     /* R315 */
+        0x0000,     /* R316 */
+        0x0000,     /* R317 */
+        0x0000,     /* R318 */
+        0x0000,     /* R319 */
+        0x0000,     /* R320 */
+        0x0000,     /* R321 */
+        0x0000,     /* R322 */
+        0x0000,     /* R323 */
+        0x0000,     /* R324 */
+        0x0000,     /* R325 */
+        0x0000,     /* R326 */
+        0x0000,     /* R327 */
+        0x0000,     /* R328 */
+        0x0000,     /* R329 */
+        0x0000,     /* R330 */
+        0x0000,     /* R331 */
+        0x0000,     /* R332 */
+        0x0000,     /* R333 */
+        0x0000,     /* R334 */
+        0x0000,     /* R335 */
+        0x0000,     /* R336 */
+        0x0000,     /* R337 */
+        0x0000,     /* R338 */
+        0x0000,     /* R339 */
+        0x0000,     /* R340 */
+        0x0000,     /* R341 */
+        0x0000,     /* R342 */
+        0x0000,     /* R343 */
+        0x0000,     /* R344 */
+        0x0000,     /* R345 */
+        0x0000,     /* R346 */
+        0x0000,     /* R347 */
+        0x0000,     /* R348 */
+        0x0000,     /* R349 */
+        0x0000,     /* R350 */
+        0x0000,     /* R351 */
+        0x0000,     /* R352 */
+        0x0000,     /* R353 */
+        0x0000,     /* R354 */
+        0x0000,     /* R355 */
+        0x0000,     /* R356 */
+        0x0000,     /* R357 */
+        0x0000,     /* R358 */
+        0x0000,     /* R359 */
+        0x0000,     /* R360 */
+        0x0000,     /* R361 */
+        0x0000,     /* R362 */
+        0x0000,     /* R363 */
+        0x0000,     /* R364 */
+        0x0000,     /* R365 */
+        0x0000,     /* R366 */
+        0x0000,     /* R367 */
+        0x0000,     /* R368 */
+        0x0000,     /* R369 */
+        0x0000,     /* R370 */
+        0x0000,     /* R371 */
+        0x0000,     /* R372 */
+        0x0000,     /* R373 */
+        0x0000,     /* R374 */
+        0x0000,     /* R375 */
+        0x0000,     /* R376 */
+        0x0000,     /* R377 */
+        0x0000,     /* R378 */
+        0x0000,     /* R379 */
+        0x0000,     /* R380 */
+        0x0000,     /* R381 */
+        0x0000,     /* R382 */
+        0x0000,     /* R383 */
+        0x0000,     /* R384 */
+        0x0000,     /* R385 */
+        0x0000,     /* R386 */
+        0x0000,     /* R387 */
+        0x0000,     /* R388 */
+        0x0000,     /* R389 */
+        0x0000,     /* R390 */
+        0x0000,     /* R391 */
+        0x0000,     /* R392 */
+        0x0000,     /* R393 */
+        0x0000,     /* R394 */
+        0x0000,     /* R395 */
+        0x0000,     /* R396 */
+        0x0000,     /* R397 */
+        0x0000,     /* R398 */
+        0x0000,     /* R399 */
+        0x0000,     /* R400 */
+        0x0000,     /* R401 */
+        0x0000,     /* R402 */
+        0x0000,     /* R403 */
+        0x0000,     /* R404 */
+        0x0000,     /* R405 */
+        0x0000,     /* R406 */
+        0x0000,     /* R407 */
+        0x0000,     /* R408 */
+        0x0000,     /* R409 */
+        0x0000,     /* R410 */
+        0x0000,     /* R411 */
+        0x0000,     /* R412 */
+        0x0000,     /* R413 */
+        0x0000,     /* R414 */
+        0x0000,     /* R415 */
+        0x0000,     /* R416 */
+        0x0000,     /* R417 */
+        0x0000,     /* R418 */
+        0x0000,     /* R419 */
+        0x0000,     /* R420 */
+        0x0000,     /* R421 */
+        0x0000,     /* R422 */
+        0x0000,     /* R423 */
+        0x0000,     /* R424 */
+        0x0000,     /* R425 */
+        0x0000,     /* R426 */
+        0x0000,     /* R427 */
+        0x0000,     /* R428 */
+        0x0000,     /* R429 */
+        0x0000,     /* R430 */
+        0x0000,     /* R431 */
+        0x0000,     /* R432 */
+        0x0000,     /* R433 */
+        0x0000,     /* R434 */
+        0x0000,     /* R435 */
+        0x0000,     /* R436 */
+        0x0000,     /* R437 */
+        0x0000,     /* R438 */
+        0x0000,     /* R439 */
+        0x0000,     /* R440 */
+        0x0000,     /* R441 */
+        0x0000,     /* R442 */
+        0x0000,     /* R443 */
+        0x0000,     /* R444 */
+        0x0000,     /* R445 */
+        0x0000,     /* R446 */
+        0x0000,     /* R447 */
+        0x0000,     /* R448 */
+        0x0000,     /* R449 */
+        0x0000,     /* R450 */
+        0x0000,     /* R451 */
+        0x0000,     /* R452 */
+        0x0000,     /* R453 */
+        0x0000,     /* R454 */
+        0x0000,     /* R455 */
+        0x0000,     /* R456 */
+        0x0000,     /* R457 */
+        0x0000,     /* R458 */
+        0x0000,     /* R459 */
+        0x0000,     /* R460 */
+        0x0000,     /* R461 */
+        0x0000,     /* R462 */
+        0x0000,     /* R463 */
+        0x0000,     /* R464 */
+        0x0000,     /* R465 */
+        0x0000,     /* R466 */
+        0x0000,     /* R467 */
+        0x0000,     /* R468 */
+        0x0000,     /* R469 */
+        0x0000,     /* R470 */
+        0x0000,     /* R471 */
+        0x0000,     /* R472 */
+        0x0000,     /* R473 */
+        0x0000,     /* R474 */
+        0x0000,     /* R475 */
+        0x0000,     /* R476 */
+        0x0000,     /* R477 */
+        0x0000,     /* R478 */
+        0x0000,     /* R479 */
+        0x0000,     /* R480 */
+        0x0000,     /* R481 */
+        0x0000,     /* R482 */
+        0x0000,     /* R483 */
+        0x0000,     /* R484 */
+        0x0000,     /* R485 */
+        0x0000,     /* R486 */
+        0x0000,     /* R487 */
+        0x0000,     /* R488 */
+        0x0000,     /* R489 */
+        0x0000,     /* R490 */
+        0x0000,     /* R491 */
+        0x0000,     /* R492 */
+        0x0000,     /* R493 */
+        0x0000,     /* R494 */
+        0x0000,     /* R495 */
+        0x0000,     /* R496 */
+        0x0000,     /* R497 */
+        0x0000,     /* R498 */
+        0x0000,     /* R499 */
+        0x0000,     /* R500 */
+        0x0000,     /* R501 */
+        0x0000,     /* R502 */
+        0x0000,     /* R503 */
+        0x0000,     /* R504 */
+        0x0000,     /* R505 */
+        0x0000,     /* R506 */
+        0x0000,     /* R507 */
+        0x0000,     /* R508 */
+        0x0000,     /* R509 */
+        0x0000,     /* R510 */
+        0x0000,     /* R511 */
+        0x0000,     /* R512   - AIF1 Clocking (1) */
+        0x0000,     /* R513   - AIF1 Clocking (2) */
+        0x0000,     /* R514 */
+        0x0000,     /* R515 */
+        0x0000,     /* R516   - AIF2 Clocking (1) */
+        0x0000,     /* R517   - AIF2 Clocking (2) */
+        0x0000,     /* R518 */
+        0x0000,     /* R519 */
+        0x0000,     /* R520   - Clocking (1) */
+        0x0000,     /* R521   - Clocking (2) */
+        0x0000,     /* R522 */
+        0x0000,     /* R523 */
+        0x0000,     /* R524 */
+        0x0000,     /* R525 */
+        0x0000,     /* R526 */
+        0x0000,     /* R527 */
+        0x0083,     /* R528   - AIF1 Rate */
+        0x0083,     /* R529   - AIF2 Rate */
+        0x0000,     /* R530   - Rate Status */
+        0x0000,     /* R531 */
+        0x0000,     /* R532 */
+        0x0000,     /* R533 */
+        0x0000,     /* R534 */
+        0x0000,     /* R535 */
+        0x0000,     /* R536 */
+        0x0000,     /* R537 */
+        0x0000,     /* R538 */
+        0x0000,     /* R539 */
+        0x0000,     /* R540 */
+        0x0000,     /* R541 */
+        0x0000,     /* R542 */
+        0x0000,     /* R543 */
+        0x0000,     /* R544   - FLL1 Control (1) */
+        0x0000,     /* R545   - FLL1 Control (2) */
+        0x0000,     /* R546   - FLL1 Control (3) */
+        0x0000,     /* R547   - FLL1 Control (4) */
+        0x0C80,     /* R548   - FLL1 Control (5) */
+        0x0000,     /* R549 */
+        0x0000,     /* R550 */
+        0x0000,     /* R551 */
+        0x0000,     /* R552 */
+        0x0000,     /* R553 */
+        0x0000,     /* R554 */
+        0x0000,     /* R555 */
+        0x0000,     /* R556 */
+        0x0000,     /* R557 */
+        0x0000,     /* R558 */
+        0x0000,     /* R559 */
+        0x0000,     /* R560 */
+        0x0000,     /* R561 */
+        0x0000,     /* R562 */
+        0x0000,     /* R563 */
+        0x0000,     /* R564 */
+        0x0000,     /* R565 */
+        0x0000,     /* R566 */
+        0x0000,     /* R567 */
+        0x0000,     /* R568 */
+        0x0000,     /* R569 */
+        0x0000,     /* R570 */
+        0x0000,     /* R571 */
+        0x0000,     /* R572 */
+        0x0000,     /* R573 */
+        0x0000,     /* R574 */
+        0x0000,     /* R575 */
+        0x0000,     /* R576   - FLL2 Control (1) */
+        0x0000,     /* R577   - FLL2 Control (2) */
+        0x0000,     /* R578   - FLL2 Control (3) */
+        0x0000,     /* R579   - FLL2 Control (4) */
+        0x0C80,     /* R580   - FLL2 Control (5) */
+        0x0000,     /* R581 */
+        0x0000,     /* R582 */
+        0x0000,     /* R583 */
+        0x0000,     /* R584 */
+        0x0000,     /* R585 */
+        0x0000,     /* R586 */
+        0x0000,     /* R587 */
+        0x0000,     /* R588 */
+        0x0000,     /* R589 */
+        0x0000,     /* R590 */
+        0x0000,     /* R591 */
+        0x0000,     /* R592 */
+        0x0000,     /* R593 */
+        0x0000,     /* R594 */
+        0x0000,     /* R595 */
+        0x0000,     /* R596 */
+        0x0000,     /* R597 */
+        0x0000,     /* R598 */
+        0x0000,     /* R599 */
+        0x0000,     /* R600 */
+        0x0000,     /* R601 */
+        0x0000,     /* R602 */
+        0x0000,     /* R603 */
+        0x0000,     /* R604 */
+        0x0000,     /* R605 */
+        0x0000,     /* R606 */
+        0x0000,     /* R607 */
+        0x0000,     /* R608 */
+        0x0000,     /* R609 */
+        0x0000,     /* R610 */
+        0x0000,     /* R611 */
+        0x0000,     /* R612 */
+        0x0000,     /* R613 */
+        0x0000,     /* R614 */
+        0x0000,     /* R615 */
+        0x0000,     /* R616 */
+        0x0000,     /* R617 */
+        0x0000,     /* R618 */
+        0x0000,     /* R619 */
+        0x0000,     /* R620 */
+        0x0000,     /* R621 */
+        0x0000,     /* R622 */
+        0x0000,     /* R623 */
+        0x0000,     /* R624 */
+        0x0000,     /* R625 */
+        0x0000,     /* R626 */
+        0x0000,     /* R627 */
+        0x0000,     /* R628 */
+        0x0000,     /* R629 */
+        0x0000,     /* R630 */
+        0x0000,     /* R631 */
+        0x0000,     /* R632 */
+        0x0000,     /* R633 */
+        0x0000,     /* R634 */
+        0x0000,     /* R635 */
+        0x0000,     /* R636 */
+        0x0000,     /* R637 */
+        0x0000,     /* R638 */
+        0x0000,     /* R639 */
+        0x0000,     /* R640 */
+        0x0000,     /* R641 */
+        0x0000,     /* R642 */
+        0x0000,     /* R643 */
+        0x0000,     /* R644 */
+        0x0000,     /* R645 */
+        0x0000,     /* R646 */
+        0x0000,     /* R647 */
+        0x0000,     /* R648 */
+        0x0000,     /* R649 */
+        0x0000,     /* R650 */
+        0x0000,     /* R651 */
+        0x0000,     /* R652 */
+        0x0000,     /* R653 */
+        0x0000,     /* R654 */
+        0x0000,     /* R655 */
+        0x0000,     /* R656 */
+        0x0000,     /* R657 */
+        0x0000,     /* R658 */
+        0x0000,     /* R659 */
+        0x0000,     /* R660 */
+        0x0000,     /* R661 */
+        0x0000,     /* R662 */
+        0x0000,     /* R663 */
+        0x0000,     /* R664 */
+        0x0000,     /* R665 */
+        0x0000,     /* R666 */
+        0x0000,     /* R667 */
+        0x0000,     /* R668 */
+        0x0000,     /* R669 */
+        0x0000,     /* R670 */
+        0x0000,     /* R671 */
+        0x0000,     /* R672 */
+        0x0000,     /* R673 */
+        0x0000,     /* R674 */
+        0x0000,     /* R675 */
+        0x0000,     /* R676 */
+        0x0000,     /* R677 */
+        0x0000,     /* R678 */
+        0x0000,     /* R679 */
+        0x0000,     /* R680 */
+        0x0000,     /* R681 */
+        0x0000,     /* R682 */
+        0x0000,     /* R683 */
+        0x0000,     /* R684 */
+        0x0000,     /* R685 */
+        0x0000,     /* R686 */
+        0x0000,     /* R687 */
+        0x0000,     /* R688 */
+        0x0000,     /* R689 */
+        0x0000,     /* R690 */
+        0x0000,     /* R691 */
+        0x0000,     /* R692 */
+        0x0000,     /* R693 */
+        0x0000,     /* R694 */
+        0x0000,     /* R695 */
+        0x0000,     /* R696 */
+        0x0000,     /* R697 */
+        0x0000,     /* R698 */
+        0x0000,     /* R699 */
+        0x0000,     /* R700 */
+        0x0000,     /* R701 */
+        0x0000,     /* R702 */
+        0x0000,     /* R703 */
+        0x0000,     /* R704 */
+        0x0000,     /* R705 */
+        0x0000,     /* R706 */
+        0x0000,     /* R707 */
+        0x0000,     /* R708 */
+        0x0000,     /* R709 */
+        0x0000,     /* R710 */
+        0x0000,     /* R711 */
+        0x0000,     /* R712 */
+        0x0000,     /* R713 */
+        0x0000,     /* R714 */
+        0x0000,     /* R715 */
+        0x0000,     /* R716 */
+        0x0000,     /* R717 */
+        0x0000,     /* R718 */
+        0x0000,     /* R719 */
+        0x0000,     /* R720 */
+        0x0000,     /* R721 */
+        0x0000,     /* R722 */
+        0x0000,     /* R723 */
+        0x0000,     /* R724 */
+        0x0000,     /* R725 */
+        0x0000,     /* R726 */
+        0x0000,     /* R727 */
+        0x0000,     /* R728 */
+        0x0000,     /* R729 */
+        0x0000,     /* R730 */
+        0x0000,     /* R731 */
+        0x0000,     /* R732 */
+        0x0000,     /* R733 */
+        0x0000,     /* R734 */
+        0x0000,     /* R735 */
+        0x0000,     /* R736 */
+        0x0000,     /* R737 */
+        0x0000,     /* R738 */
+        0x0000,     /* R739 */
+        0x0000,     /* R740 */
+        0x0000,     /* R741 */
+        0x0000,     /* R742 */
+        0x0000,     /* R743 */
+        0x0000,     /* R744 */
+        0x0000,     /* R745 */
+        0x0000,     /* R746 */
+        0x0000,     /* R747 */
+        0x0000,     /* R748 */
+        0x0000,     /* R749 */
+        0x0000,     /* R750 */
+        0x0000,     /* R751 */
+        0x0000,     /* R752 */
+        0x0000,     /* R753 */
+        0x0000,     /* R754 */
+        0x0000,     /* R755 */
+        0x0000,     /* R756 */
+        0x0000,     /* R757 */
+        0x0000,     /* R758 */
+        0x0000,     /* R759 */
+        0x0000,     /* R760 */
+        0x0000,     /* R761 */
+        0x0000,     /* R762 */
+        0x0000,     /* R763 */
+        0x0000,     /* R764 */
+        0x0000,     /* R765 */
+        0x0000,     /* R766 */
+        0x0000,     /* R767 */
+        0x4050,     /* R768   - AIF1 Control (1) */
+        0x4000,     /* R769   - AIF1 Control (2) */
+        0x0000,     /* R770   - AIF1 Master/Slave */
+        0x0040,     /* R771   - AIF1 BCLK */
+        0x0040,     /* R772   - AIF1ADC LRCLK */
+        0x0040,     /* R773   - AIF1DAC LRCLK */
+        0x0004,     /* R774   - AIF1DAC Data */
+        0x0100,     /* R775   - AIF1ADC Data */
+        0x0000,     /* R776 */
+        0x0000,     /* R777 */
+        0x0000,     /* R778 */
+        0x0000,     /* R779 */
+        0x0000,     /* R780 */
+        0x0000,     /* R781 */
+        0x0000,     /* R782 */
+        0x0000,     /* R783 */
+        0x4050,     /* R784   - AIF2 Control (1) */
+        0x4000,     /* R785   - AIF2 Control (2) */
+        0x0000,     /* R786   - AIF2 Master/Slave */
+        0x0040,     /* R787   - AIF2 BCLK */
+        0x0040,     /* R788   - AIF2ADC LRCLK */
+        0x0040,     /* R789   - AIF2DAC LRCLK */
+        0x0000,     /* R790   - AIF2DAC Data */
+        0x0000,     /* R791   - AIF2ADC Data */
+        0x0000,     /* R792 */
+        0x0000,     /* R793 */
+        0x0000,     /* R794 */
+        0x0000,     /* R795 */
+        0x0000,     /* R796 */
+        0x0000,     /* R797 */
+        0x0000,     /* R798 */
+        0x0000,     /* R799 */
+        0x0000,     /* R800 */
+        0x0000,     /* R801 */
+        0x0000,     /* R802 */
+        0x0000,     /* R803 */
+        0x0000,     /* R804 */
+        0x0000,     /* R805 */
+        0x0000,     /* R806 */
+        0x0000,     /* R807 */
+        0x0000,     /* R808 */
+        0x0000,     /* R809 */
+        0x0000,     /* R810 */
+        0x0000,     /* R811 */
+        0x0000,     /* R812 */
+        0x0000,     /* R813 */
+        0x0000,     /* R814 */
+        0x0000,     /* R815 */
+        0x0000,     /* R816 */
+        0x0000,     /* R817 */
+        0x0000,     /* R818 */
+        0x0000,     /* R819 */
+        0x0000,     /* R820 */
+        0x0000,     /* R821 */
+        0x0000,     /* R822 */
+        0x0000,     /* R823 */
+        0x0000,     /* R824 */
+        0x0000,     /* R825 */
+        0x0000,     /* R826 */
+        0x0000,     /* R827 */
+        0x0000,     /* R828 */
+        0x0000,     /* R829 */
+        0x0000,     /* R830 */
+        0x0000,     /* R831 */
+        0x0000,     /* R832 */
+        0x0000,     /* R833 */
+        0x0000,     /* R834 */
+        0x0000,     /* R835 */
+        0x0000,     /* R836 */
+        0x0000,     /* R837 */
+        0x0000,     /* R838 */
+        0x0000,     /* R839 */
+        0x0000,     /* R840 */
+        0x0000,     /* R841 */
+        0x0000,     /* R842 */
+        0x0000,     /* R843 */
+        0x0000,     /* R844 */
+        0x0000,     /* R845 */
+        0x0000,     /* R846 */
+        0x0000,     /* R847 */
+        0x0000,     /* R848 */
+        0x0000,     /* R849 */
+        0x0000,     /* R850 */
+        0x0000,     /* R851 */
+        0x0000,     /* R852 */
+        0x0000,     /* R853 */
+        0x0000,     /* R854 */
+        0x0000,     /* R855 */
+        0x0000,     /* R856 */
+        0x0000,     /* R857 */
+        0x0000,     /* R858 */
+        0x0000,     /* R859 */
+        0x0000,     /* R860 */
+        0x0000,     /* R861 */
+        0x0000,     /* R862 */
+        0x0000,     /* R863 */
+        0x0000,     /* R864 */
+        0x0000,     /* R865 */
+        0x0000,     /* R866 */
+        0x0000,     /* R867 */
+        0x0000,     /* R868 */
+        0x0000,     /* R869 */
+        0x0000,     /* R870 */
+        0x0000,     /* R871 */
+        0x0000,     /* R872 */
+        0x0000,     /* R873 */
+        0x0000,     /* R874 */
+        0x0000,     /* R875 */
+        0x0000,     /* R876 */
+        0x0000,     /* R877 */
+        0x0000,     /* R878 */
+        0x0000,     /* R879 */
+        0x0000,     /* R880 */
+        0x0000,     /* R881 */
+        0x0000,     /* R882 */
+        0x0000,     /* R883 */
+        0x0000,     /* R884 */
+        0x0000,     /* R885 */
+        0x0000,     /* R886 */
+        0x0000,     /* R887 */
+        0x0000,     /* R888 */
+        0x0000,     /* R889 */
+        0x0000,     /* R890 */
+        0x0000,     /* R891 */
+        0x0000,     /* R892 */
+        0x0000,     /* R893 */
+        0x0000,     /* R894 */
+        0x0000,     /* R895 */
+        0x0000,     /* R896 */
+        0x0000,     /* R897 */
+        0x0000,     /* R898 */
+        0x0000,     /* R899 */
+        0x0000,     /* R900 */
+        0x0000,     /* R901 */
+        0x0000,     /* R902 */
+        0x0000,     /* R903 */
+        0x0000,     /* R904 */
+        0x0000,     /* R905 */
+        0x0000,     /* R906 */
+        0x0000,     /* R907 */
+        0x0000,     /* R908 */
+        0x0000,     /* R909 */
+        0x0000,     /* R910 */
+        0x0000,     /* R911 */
+        0x0000,     /* R912 */
+        0x0000,     /* R913 */
+        0x0000,     /* R914 */
+        0x0000,     /* R915 */
+        0x0000,     /* R916 */
+        0x0000,     /* R917 */
+        0x0000,     /* R918 */
+        0x0000,     /* R919 */
+        0x0000,     /* R920 */
+        0x0000,     /* R921 */
+        0x0000,     /* R922 */
+        0x0000,     /* R923 */
+        0x0000,     /* R924 */
+        0x0000,     /* R925 */
+        0x0000,     /* R926 */
+        0x0000,     /* R927 */
+        0x0000,     /* R928 */
+        0x0000,     /* R929 */
+        0x0000,     /* R930 */
+        0x0000,     /* R931 */
+        0x0000,     /* R932 */
+        0x0000,     /* R933 */
+        0x0000,     /* R934 */
+        0x0000,     /* R935 */
+        0x0000,     /* R936 */
+        0x0000,     /* R937 */
+        0x0000,     /* R938 */
+        0x0000,     /* R939 */
+        0x0000,     /* R940 */
+        0x0000,     /* R941 */
+        0x0000,     /* R942 */
+        0x0000,     /* R943 */
+        0x0000,     /* R944 */
+        0x0000,     /* R945 */
+        0x0000,     /* R946 */
+        0x0000,     /* R947 */
+        0x0000,     /* R948 */
+        0x0000,     /* R949 */
+        0x0000,     /* R950 */
+        0x0000,     /* R951 */
+        0x0000,     /* R952 */
+        0x0000,     /* R953 */
+        0x0000,     /* R954 */
+        0x0000,     /* R955 */
+        0x0000,     /* R956 */
+        0x0000,     /* R957 */
+        0x0000,     /* R958 */
+        0x0000,     /* R959 */
+        0x0000,     /* R960 */
+        0x0000,     /* R961 */
+        0x0000,     /* R962 */
+        0x0000,     /* R963 */
+        0x0000,     /* R964 */
+        0x0000,     /* R965 */
+        0x0000,     /* R966 */
+        0x0000,     /* R967 */
+        0x0000,     /* R968 */
+        0x0000,     /* R969 */
+        0x0000,     /* R970 */
+        0x0000,     /* R971 */
+        0x0000,     /* R972 */
+        0x0000,     /* R973 */
+        0x0000,     /* R974 */
+        0x0000,     /* R975 */
+        0x0000,     /* R976 */
+        0x0000,     /* R977 */
+        0x0000,     /* R978 */
+        0x0000,     /* R979 */
+        0x0000,     /* R980 */
+        0x0000,     /* R981 */
+        0x0000,     /* R982 */
+        0x0000,     /* R983 */
+        0x0000,     /* R984 */
+        0x0000,     /* R985 */
+        0x0000,     /* R986 */
+        0x0000,     /* R987 */
+        0x0000,     /* R988 */
+        0x0000,     /* R989 */
+        0x0000,     /* R990 */
+        0x0000,     /* R991 */
+        0x0000,     /* R992 */
+        0x0000,     /* R993 */
+        0x0000,     /* R994 */
+        0x0000,     /* R995 */
+        0x0000,     /* R996 */
+        0x0000,     /* R997 */
+        0x0000,     /* R998 */
+        0x0000,     /* R999 */
+        0x0000,     /* R1000 */
+        0x0000,     /* R1001 */
+        0x0000,     /* R1002 */
+        0x0000,     /* R1003 */
+        0x0000,     /* R1004 */
+        0x0000,     /* R1005 */
+        0x0000,     /* R1006 */
+        0x0000,     /* R1007 */
+        0x0000,     /* R1008 */
+        0x0000,     /* R1009 */
+        0x0000,     /* R1010 */
+        0x0000,     /* R1011 */
+        0x0000,     /* R1012 */
+        0x0000,     /* R1013 */
+        0x0000,     /* R1014 */
+        0x0000,     /* R1015 */
+        0x0000,     /* R1016 */
+        0x0000,     /* R1017 */
+        0x0000,     /* R1018 */
+        0x0000,     /* R1019 */
+        0x0000,     /* R1020 */
+        0x0000,     /* R1021 */
+        0x0000,     /* R1022 */
+        0x0000,     /* R1023 */
+        0x00C0,     /* R1024  - AIF1 ADC1 Left Volume */
+        0x00C0,     /* R1025  - AIF1 ADC1 Right Volume */
+        0x00C0,     /* R1026  - AIF1 DAC1 Left Volume */
+        0x00C0,     /* R1027  - AIF1 DAC1 Right Volume */
+        0x00C0,     /* R1028  - AIF1 ADC2 Left Volume */
+        0x00C0,     /* R1029  - AIF1 ADC2 Right Volume */
+        0x00C0,     /* R1030  - AIF1 DAC2 Left Volume */
+        0x00C0,     /* R1031  - AIF1 DAC2 Right Volume */
+        0x0000,     /* R1032 */
+        0x0000,     /* R1033 */
+        0x0000,     /* R1034 */
+        0x0000,     /* R1035 */
+        0x0000,     /* R1036 */
+        0x0000,     /* R1037 */
+        0x0000,     /* R1038 */
+        0x0000,     /* R1039 */
+        0x0000,     /* R1040  - AIF1 ADC1 Filters */
+        0x0000,     /* R1041  - AIF1 ADC2 Filters */
+        0x0000,     /* R1042 */
+        0x0000,     /* R1043 */
+        0x0000,     /* R1044 */
+        0x0000,     /* R1045 */
+        0x0000,     /* R1046 */
+        0x0000,     /* R1047 */
+        0x0000,     /* R1048 */
+        0x0000,     /* R1049 */
+        0x0000,     /* R1050 */
+        0x0000,     /* R1051 */
+        0x0000,     /* R1052 */
+        0x0000,     /* R1053 */
+        0x0000,     /* R1054 */
+        0x0000,     /* R1055 */
+        0x0200,     /* R1056  - AIF1 DAC1 Filters (1) */
+        0x0010,     /* R1057  - AIF1 DAC1 Filters (2) */
+        0x0200,     /* R1058  - AIF1 DAC2 Filters (1) */
+        0x0010,     /* R1059  - AIF1 DAC2 Filters (2) */
+        0x0000,     /* R1060 */
+        0x0000,     /* R1061 */
+        0x0000,     /* R1062 */
+        0x0000,     /* R1063 */
+        0x0000,     /* R1064 */
+        0x0000,     /* R1065 */
+        0x0000,     /* R1066 */
+        0x0000,     /* R1067 */
+        0x0000,     /* R1068 */
+        0x0000,     /* R1069 */
+        0x0000,     /* R1070 */
+        0x0000,     /* R1071 */
+        0x0000,     /* R1072 */
+        0x0000,     /* R1073 */
+        0x0000,     /* R1074 */
+        0x0000,     /* R1075 */
+        0x0000,     /* R1076 */
+        0x0000,     /* R1077 */
+        0x0000,     /* R1078 */
+        0x0000,     /* R1079 */
+        0x0000,     /* R1080 */
+        0x0000,     /* R1081 */
+        0x0000,     /* R1082 */
+        0x0000,     /* R1083 */
+        0x0000,     /* R1084 */
+        0x0000,     /* R1085 */
+        0x0000,     /* R1086 */
+        0x0000,     /* R1087 */
+        0x0098,     /* R1088  - AIF1 DRC1 (1) */
+        0x0845,     /* R1089  - AIF1 DRC1 (2) */
+        0x0000,     /* R1090  - AIF1 DRC1 (3) */
+        0x0000,     /* R1091  - AIF1 DRC1 (4) */
+        0x0000,     /* R1092  - AIF1 DRC1 (5) */
+        0x0000,     /* R1093 */
+        0x0000,     /* R1094 */
+        0x0000,     /* R1095 */
+        0x0000,     /* R1096 */
+        0x0000,     /* R1097 */
+        0x0000,     /* R1098 */
+        0x0000,     /* R1099 */
+        0x0000,     /* R1100 */
+        0x0000,     /* R1101 */
+        0x0000,     /* R1102 */
+        0x0000,     /* R1103 */
+        0x0098,     /* R1104  - AIF1 DRC2 (1) */
+        0x0845,     /* R1105  - AIF1 DRC2 (2) */
+        0x0000,     /* R1106  - AIF1 DRC2 (3) */
+        0x0000,     /* R1107  - AIF1 DRC2 (4) */
+        0x0000,     /* R1108  - AIF1 DRC2 (5) */
+        0x0000,     /* R1109 */
+        0x0000,     /* R1110 */
+        0x0000,     /* R1111 */
+        0x0000,     /* R1112 */
+        0x0000,     /* R1113 */
+        0x0000,     /* R1114 */
+        0x0000,     /* R1115 */
+        0x0000,     /* R1116 */
+        0x0000,     /* R1117 */
+        0x0000,     /* R1118 */
+        0x0000,     /* R1119 */
+        0x0000,     /* R1120 */
+        0x0000,     /* R1121 */
+        0x0000,     /* R1122 */
+        0x0000,     /* R1123 */
+        0x0000,     /* R1124 */
+        0x0000,     /* R1125 */
+        0x0000,     /* R1126 */
+        0x0000,     /* R1127 */
+        0x0000,     /* R1128 */
+        0x0000,     /* R1129 */
+        0x0000,     /* R1130 */
+        0x0000,     /* R1131 */
+        0x0000,     /* R1132 */
+        0x0000,     /* R1133 */
+        0x0000,     /* R1134 */
+        0x0000,     /* R1135 */
+        0x0000,     /* R1136 */
+        0x0000,     /* R1137 */
+        0x0000,     /* R1138 */
+        0x0000,     /* R1139 */
+        0x0000,     /* R1140 */
+        0x0000,     /* R1141 */
+        0x0000,     /* R1142 */
+        0x0000,     /* R1143 */
+        0x0000,     /* R1144 */
+        0x0000,     /* R1145 */
+        0x0000,     /* R1146 */
+        0x0000,     /* R1147 */
+        0x0000,     /* R1148 */
+        0x0000,     /* R1149 */
+        0x0000,     /* R1150 */
+        0x0000,     /* R1151 */
+        0x6318,     /* R1152  - AIF1 DAC1 EQ Gains (1) */
+        0x6300,     /* R1153  - AIF1 DAC1 EQ Gains (2) */
+        0x0FCA,     /* R1154  - AIF1 DAC1 EQ Band 1 A */
+        0x0400,     /* R1155  - AIF1 DAC1 EQ Band 1 B */
+        0x00D8,     /* R1156  - AIF1 DAC1 EQ Band 1 PG */
+        0x1EB5,     /* R1157  - AIF1 DAC1 EQ Band 2 A */
+        0xF145,     /* R1158  - AIF1 DAC1 EQ Band 2 B */
+        0x0B75,     /* R1159  - AIF1 DAC1 EQ Band 2 C */
+        0x01C5,     /* R1160  - AIF1 DAC1 EQ Band 2 PG */
+        0x1C58,     /* R1161  - AIF1 DAC1 EQ Band 3 A */
+        0xF373,     /* R1162  - AIF1 DAC1 EQ Band 3 B */
+        0x0A54,     /* R1163  - AIF1 DAC1 EQ Band 3 C */
+        0x0558,     /* R1164  - AIF1 DAC1 EQ Band 3 PG */
+        0x168E,     /* R1165  - AIF1 DAC1 EQ Band 4 A */
+        0xF829,     /* R1166  - AIF1 DAC1 EQ Band 4 B */
+        0x07AD,     /* R1167  - AIF1 DAC1 EQ Band 4 C */
+        0x1103,     /* R1168  - AIF1 DAC1 EQ Band 4 PG */
+        0x0564,     /* R1169  - AIF1 DAC1 EQ Band 5 A */
+        0x0559,     /* R1170  - AIF1 DAC1 EQ Band 5 B */
+        0x4000,     /* R1171  - AIF1 DAC1 EQ Band 5 PG */
+        0x0000,     /* R1172 */
+        0x0000,     /* R1173 */
+        0x0000,     /* R1174 */
+        0x0000,     /* R1175 */
+        0x0000,     /* R1176 */
+        0x0000,     /* R1177 */
+        0x0000,     /* R1178 */
+        0x0000,     /* R1179 */
+        0x0000,     /* R1180 */
+        0x0000,     /* R1181 */
+        0x0000,     /* R1182 */
+        0x0000,     /* R1183 */
+        0x6318,     /* R1184  - AIF1 DAC2 EQ Gains (1) */
+        0x6300,     /* R1185  - AIF1 DAC2 EQ Gains (2) */
+        0x0FCA,     /* R1186  - AIF1 DAC2 EQ Band 1 A */
+        0x0400,     /* R1187  - AIF1 DAC2 EQ Band 1 B */
+        0x00D8,     /* R1188  - AIF1 DAC2 EQ Band 1 PG */
+        0x1EB5,     /* R1189  - AIF1 DAC2 EQ Band 2 A */
+        0xF145,     /* R1190  - AIF1 DAC2 EQ Band 2 B */
+        0x0B75,     /* R1191  - AIF1 DAC2 EQ Band 2 C */
+        0x01C5,     /* R1192  - AIF1 DAC2 EQ Band 2 PG */
+        0x1C58,     /* R1193  - AIF1 DAC2 EQ Band 3 A */
+        0xF373,     /* R1194  - AIF1 DAC2 EQ Band 3 B */
+        0x0A54,     /* R1195  - AIF1 DAC2 EQ Band 3 C */
+        0x0558,     /* R1196  - AIF1 DAC2 EQ Band 3 PG */
+        0x168E,     /* R1197  - AIF1 DAC2 EQ Band 4 A */
+        0xF829,     /* R1198  - AIF1 DAC2 EQ Band 4 B */
+        0x07AD,     /* R1199  - AIF1 DAC2 EQ Band 4 C */
+        0x1103,     /* R1200  - AIF1 DAC2 EQ Band 4 PG */
+        0x0564,     /* R1201  - AIF1 DAC2 EQ Band 5 A */
+        0x0559,     /* R1202  - AIF1 DAC2 EQ Band 5 B */
+        0x4000,     /* R1203  - AIF1 DAC2 EQ Band 5 PG */
+        0x0000,     /* R1204 */
+        0x0000,     /* R1205 */
+        0x0000,     /* R1206 */
+        0x0000,     /* R1207 */
+        0x0000,     /* R1208 */
+        0x0000,     /* R1209 */
+        0x0000,     /* R1210 */
+        0x0000,     /* R1211 */
+        0x0000,     /* R1212 */
+        0x0000,     /* R1213 */
+        0x0000,     /* R1214 */
+        0x0000,     /* R1215 */
+        0x0000,     /* R1216 */
+        0x0000,     /* R1217 */
+        0x0000,     /* R1218 */
+        0x0000,     /* R1219 */
+        0x0000,     /* R1220 */
+        0x0000,     /* R1221 */
+        0x0000,     /* R1222 */
+        0x0000,     /* R1223 */
+        0x0000,     /* R1224 */
+        0x0000,     /* R1225 */
+        0x0000,     /* R1226 */
+        0x0000,     /* R1227 */
+        0x0000,     /* R1228 */
+        0x0000,     /* R1229 */
+        0x0000,     /* R1230 */
+        0x0000,     /* R1231 */
+        0x0000,     /* R1232 */
+        0x0000,     /* R1233 */
+        0x0000,     /* R1234 */
+        0x0000,     /* R1235 */
+        0x0000,     /* R1236 */
+        0x0000,     /* R1237 */
+        0x0000,     /* R1238 */
+        0x0000,     /* R1239 */
+        0x0000,     /* R1240 */
+        0x0000,     /* R1241 */
+        0x0000,     /* R1242 */
+        0x0000,     /* R1243 */
+        0x0000,     /* R1244 */
+        0x0000,     /* R1245 */
+        0x0000,     /* R1246 */
+        0x0000,     /* R1247 */
+        0x0000,     /* R1248 */
+        0x0000,     /* R1249 */
+        0x0000,     /* R1250 */
+        0x0000,     /* R1251 */
+        0x0000,     /* R1252 */
+        0x0000,     /* R1253 */
+        0x0000,     /* R1254 */
+        0x0000,     /* R1255 */
+        0x0000,     /* R1256 */
+        0x0000,     /* R1257 */
+        0x0000,     /* R1258 */
+        0x0000,     /* R1259 */
+        0x0000,     /* R1260 */
+        0x0000,     /* R1261 */
+        0x0000,     /* R1262 */
+        0x0000,     /* R1263 */
+        0x0000,     /* R1264 */
+        0x0000,     /* R1265 */
+        0x0000,     /* R1266 */
+        0x0000,     /* R1267 */
+        0x0000,     /* R1268 */
+        0x0000,     /* R1269 */
+        0x0000,     /* R1270 */
+        0x0000,     /* R1271 */
+        0x0000,     /* R1272 */
+        0x0000,     /* R1273 */
+        0x0000,     /* R1274 */
+        0x0000,     /* R1275 */
+        0x0000,     /* R1276 */
+        0x0000,     /* R1277 */
+        0x0000,     /* R1278 */
+        0x0000,     /* R1279 */
+        0x00C0,     /* R1280  - AIF2 ADC Left Volume */
+        0x00C0,     /* R1281  - AIF2 ADC Right Volume */
+        0x00C0,     /* R1282  - AIF2 DAC Left Volume */
+        0x00C0,     /* R1283  - AIF2 DAC Right Volume */
+        0x0000,     /* R1284 */
+        0x0000,     /* R1285 */
+        0x0000,     /* R1286 */
+        0x0000,     /* R1287 */
+        0x0000,     /* R1288 */
+        0x0000,     /* R1289 */
+        0x0000,     /* R1290 */
+        0x0000,     /* R1291 */
+        0x0000,     /* R1292 */
+        0x0000,     /* R1293 */
+        0x0000,     /* R1294 */
+        0x0000,     /* R1295 */
+        0x0000,     /* R1296  - AIF2 ADC Filters */
+        0x0000,     /* R1297 */
+        0x0000,     /* R1298 */
+        0x0000,     /* R1299 */
+        0x0000,     /* R1300 */
+        0x0000,     /* R1301 */
+        0x0000,     /* R1302 */
+        0x0000,     /* R1303 */
+        0x0000,     /* R1304 */
+        0x0000,     /* R1305 */
+        0x0000,     /* R1306 */
+        0x0000,     /* R1307 */
+        0x0000,     /* R1308 */
+        0x0000,     /* R1309 */
+        0x0000,     /* R1310 */
+        0x0000,     /* R1311 */
+        0x0200,     /* R1312  - AIF2 DAC Filters (1) */
+        0x0010,     /* R1313  - AIF2 DAC Filters (2) */
+        0x0000,     /* R1314 */
+        0x0000,     /* R1315 */
+        0x0000,     /* R1316 */
+        0x0000,     /* R1317 */
+        0x0000,     /* R1318 */
+        0x0000,     /* R1319 */
+        0x0000,     /* R1320 */
+        0x0000,     /* R1321 */
+        0x0000,     /* R1322 */
+        0x0000,     /* R1323 */
+        0x0000,     /* R1324 */
+        0x0000,     /* R1325 */
+        0x0000,     /* R1326 */
+        0x0000,     /* R1327 */
+        0x0000,     /* R1328 */
+        0x0000,     /* R1329 */
+        0x0000,     /* R1330 */
+        0x0000,     /* R1331 */
+        0x0000,     /* R1332 */
+        0x0000,     /* R1333 */
+        0x0000,     /* R1334 */
+        0x0000,     /* R1335 */
+        0x0000,     /* R1336 */
+        0x0000,     /* R1337 */
+        0x0000,     /* R1338 */
+        0x0000,     /* R1339 */
+        0x0000,     /* R1340 */
+        0x0000,     /* R1341 */
+        0x0000,     /* R1342 */
+        0x0000,     /* R1343 */
+        0x0098,     /* R1344  - AIF2 DRC (1) */
+        0x0845,     /* R1345  - AIF2 DRC (2) */
+        0x0000,     /* R1346  - AIF2 DRC (3) */
+        0x0000,     /* R1347  - AIF2 DRC (4) */
+        0x0000,     /* R1348  - AIF2 DRC (5) */
+        0x0000,     /* R1349 */
+        0x0000,     /* R1350 */
+        0x0000,     /* R1351 */
+        0x0000,     /* R1352 */
+        0x0000,     /* R1353 */
+        0x0000,     /* R1354 */
+        0x0000,     /* R1355 */
+        0x0000,     /* R1356 */
+        0x0000,     /* R1357 */
+        0x0000,     /* R1358 */
+        0x0000,     /* R1359 */
+        0x0000,     /* R1360 */
+        0x0000,     /* R1361 */
+        0x0000,     /* R1362 */
+        0x0000,     /* R1363 */
+        0x0000,     /* R1364 */
+        0x0000,     /* R1365 */
+        0x0000,     /* R1366 */
+        0x0000,     /* R1367 */
+        0x0000,     /* R1368 */
+        0x0000,     /* R1369 */
+        0x0000,     /* R1370 */
+        0x0000,     /* R1371 */
+        0x0000,     /* R1372 */
+        0x0000,     /* R1373 */
+        0x0000,     /* R1374 */
+        0x0000,     /* R1375 */
+        0x0000,     /* R1376 */
+        0x0000,     /* R1377 */
+        0x0000,     /* R1378 */
+        0x0000,     /* R1379 */
+        0x0000,     /* R1380 */
+        0x0000,     /* R1381 */
+        0x0000,     /* R1382 */
+        0x0000,     /* R1383 */
+        0x0000,     /* R1384 */
+        0x0000,     /* R1385 */
+        0x0000,     /* R1386 */
+        0x0000,     /* R1387 */
+        0x0000,     /* R1388 */
+        0x0000,     /* R1389 */
+        0x0000,     /* R1390 */
+        0x0000,     /* R1391 */
+        0x0000,     /* R1392 */
+        0x0000,     /* R1393 */
+        0x0000,     /* R1394 */
+        0x0000,     /* R1395 */
+        0x0000,     /* R1396 */
+        0x0000,     /* R1397 */
+        0x0000,     /* R1398 */
+        0x0000,     /* R1399 */
+        0x0000,     /* R1400 */
+        0x0000,     /* R1401 */
+        0x0000,     /* R1402 */
+        0x0000,     /* R1403 */
+        0x0000,     /* R1404 */
+        0x0000,     /* R1405 */
+        0x0000,     /* R1406 */
+        0x0000,     /* R1407 */
+        0x6318,     /* R1408  - AIF2 EQ Gains (1) */
+        0x6300,     /* R1409  - AIF2 EQ Gains (2) */
+        0x0FCA,     /* R1410  - AIF2 EQ Band 1 A */
+        0x0400,     /* R1411  - AIF2 EQ Band 1 B */
+        0x00D8,     /* R1412  - AIF2 EQ Band 1 PG */
+        0x1EB5,     /* R1413  - AIF2 EQ Band 2 A */
+        0xF145,     /* R1414  - AIF2 EQ Band 2 B */
+        0x0B75,     /* R1415  - AIF2 EQ Band 2 C */
+        0x01C5,     /* R1416  - AIF2 EQ Band 2 PG */
+        0x1C58,     /* R1417  - AIF2 EQ Band 3 A */
+        0xF373,     /* R1418  - AIF2 EQ Band 3 B */
+        0x0A54,     /* R1419  - AIF2 EQ Band 3 C */
+        0x0558,     /* R1420  - AIF2 EQ Band 3 PG */
+        0x168E,     /* R1421  - AIF2 EQ Band 4 A */
+        0xF829,     /* R1422  - AIF2 EQ Band 4 B */
+        0x07AD,     /* R1423  - AIF2 EQ Band 4 C */
+        0x1103,     /* R1424  - AIF2 EQ Band 4 PG */
+        0x0564,     /* R1425  - AIF2 EQ Band 5 A */
+        0x0559,     /* R1426  - AIF2 EQ Band 5 B */
+        0x4000,     /* R1427  - AIF2 EQ Band 5 PG */
+        0x0000,     /* R1428 */
+        0x0000,     /* R1429 */
+        0x0000,     /* R1430 */
+        0x0000,     /* R1431 */
+        0x0000,     /* R1432 */
+        0x0000,     /* R1433 */
+        0x0000,     /* R1434 */
+        0x0000,     /* R1435 */
+        0x0000,     /* R1436 */
+        0x0000,     /* R1437 */
+        0x0000,     /* R1438 */
+        0x0000,     /* R1439 */
+        0x0000,     /* R1440 */
+        0x0000,     /* R1441 */
+        0x0000,     /* R1442 */
+        0x0000,     /* R1443 */
+        0x0000,     /* R1444 */
+        0x0000,     /* R1445 */
+        0x0000,     /* R1446 */
+        0x0000,     /* R1447 */
+        0x0000,     /* R1448 */
+        0x0000,     /* R1449 */
+        0x0000,     /* R1450 */
+        0x0000,     /* R1451 */
+        0x0000,     /* R1452 */
+        0x0000,     /* R1453 */
+        0x0000,     /* R1454 */
+        0x0000,     /* R1455 */
+        0x0000,     /* R1456 */
+        0x0000,     /* R1457 */
+        0x0000,     /* R1458 */
+        0x0000,     /* R1459 */
+        0x0000,     /* R1460 */
+        0x0000,     /* R1461 */
+        0x0000,     /* R1462 */
+        0x0000,     /* R1463 */
+        0x0000,     /* R1464 */
+        0x0000,     /* R1465 */
+        0x0000,     /* R1466 */
+        0x0000,     /* R1467 */
+        0x0000,     /* R1468 */
+        0x0000,     /* R1469 */
+        0x0000,     /* R1470 */
+        0x0000,     /* R1471 */
+        0x0000,     /* R1472 */
+        0x0000,     /* R1473 */
+        0x0000,     /* R1474 */
+        0x0000,     /* R1475 */
+        0x0000,     /* R1476 */
+        0x0000,     /* R1477 */
+        0x0000,     /* R1478 */
+        0x0000,     /* R1479 */
+        0x0000,     /* R1480 */
+        0x0000,     /* R1481 */
+        0x0000,     /* R1482 */
+        0x0000,     /* R1483 */
+        0x0000,     /* R1484 */
+        0x0000,     /* R1485 */
+        0x0000,     /* R1486 */
+        0x0000,     /* R1487 */
+        0x0000,     /* R1488 */
+        0x0000,     /* R1489 */
+        0x0000,     /* R1490 */
+        0x0000,     /* R1491 */
+        0x0000,     /* R1492 */
+        0x0000,     /* R1493 */
+        0x0000,     /* R1494 */
+        0x0000,     /* R1495 */
+        0x0000,     /* R1496 */
+        0x0000,     /* R1497 */
+        0x0000,     /* R1498 */
+        0x0000,     /* R1499 */
+        0x0000,     /* R1500 */
+        0x0000,     /* R1501 */
+        0x0000,     /* R1502 */
+        0x0000,     /* R1503 */
+        0x0000,     /* R1504 */
+        0x0000,     /* R1505 */
+        0x0000,     /* R1506 */
+        0x0000,     /* R1507 */
+        0x0000,     /* R1508 */
+        0x0000,     /* R1509 */
+        0x0000,     /* R1510 */
+        0x0000,     /* R1511 */
+        0x0000,     /* R1512 */
+        0x0000,     /* R1513 */
+        0x0000,     /* R1514 */
+        0x0000,     /* R1515 */
+        0x0000,     /* R1516 */
+        0x0000,     /* R1517 */
+        0x0000,     /* R1518 */
+        0x0000,     /* R1519 */
+        0x0000,     /* R1520 */
+        0x0000,     /* R1521 */
+        0x0000,     /* R1522 */
+        0x0000,     /* R1523 */
+        0x0000,     /* R1524 */
+        0x0000,     /* R1525 */
+        0x0000,     /* R1526 */
+        0x0000,     /* R1527 */
+        0x0000,     /* R1528 */
+        0x0000,     /* R1529 */
+        0x0000,     /* R1530 */
+        0x0000,     /* R1531 */
+        0x0000,     /* R1532 */
+        0x0000,     /* R1533 */
+        0x0000,     /* R1534 */
+        0x0000,     /* R1535 */
+        0x0000,     /* R1536  - DAC1 Mixer Volumes */
+        0x0000,     /* R1537  - DAC1 Left Mixer Routing */
+        0x0000,     /* R1538  - DAC1 Right Mixer Routing */
+        0x0000,     /* R1539  - DAC2 Mixer Volumes */
+        0x0000,     /* R1540  - DAC2 Left Mixer Routing */
+        0x0000,     /* R1541  - DAC2 Right Mixer Routing */
+        0x0000,     /* R1542  - AIF1 ADC1 Left Mixer Routing */
+        0x0000,     /* R1543  - AIF1 ADC1 Right Mixer Routing */
+        0x0000,     /* R1544  - AIF1 ADC2 Left Mixer Routing */
+        0x0000,     /* R1545  - AIF1 ADC2 Right mixer Routing */
+        0x0000,     /* R1546 */
+        0x0000,     /* R1547 */
+        0x0000,     /* R1548 */
+        0x0000,     /* R1549 */
+        0x0000,     /* R1550 */
+        0x0000,     /* R1551 */
+        0x02C0,     /* R1552  - DAC1 Left Volume */
+        0x02C0,     /* R1553  - DAC1 Right Volume */
+        0x02C0,     /* R1554  - DAC2 Left Volume */
+        0x02C0,     /* R1555  - DAC2 Right Volume */
+        0x0000,     /* R1556  - DAC Softmute */
+        0x0000,     /* R1557 */
+        0x0000,     /* R1558 */
+        0x0000,     /* R1559 */
+        0x0000,     /* R1560 */
+        0x0000,     /* R1561 */
+        0x0000,     /* R1562 */
+        0x0000,     /* R1563 */
+        0x0000,     /* R1564 */
+        0x0000,     /* R1565 */
+        0x0000,     /* R1566 */
+        0x0000,     /* R1567 */
+        0x0002,     /* R1568  - Oversampling */
+        0x0000,     /* R1569  - Sidetone */
+};
diff --git a/sound/soc/ep93xx/Kconfig b/sound/soc/ep93xx/Kconfig
new file mode 100644
index 00000000000..91a28de9410
--- /dev/null
+++ b/sound/soc/ep93xx/Kconfig
@@ -0,0 +1,41 @@
+config SND_EP93XX_SOC
+        tristate "SoC Audio support for the Cirrus Logic EP93xx series"
+        depends on ARCH_EP93XX && SND_SOC
+        help
+          Say Y or M if you want to add support for codecs attached to
+          the EP93xx I2S or AC97 interfaces.
+
+config SND_EP93XX_SOC_I2S
+        tristate
+
+config SND_EP93XX_SOC_AC97
+        tristate
+        select AC97_BUS
+        select SND_SOC_AC97_BUS
+
+config SND_EP93XX_SOC_SNAPPERCL15
+        tristate "SoC Audio support for Bluewater Systems Snapper CL15 module"
+        depends on SND_EP93XX_SOC && MACH_SNAPPER_CL15
+        select SND_EP93XX_SOC_I2S
+        select SND_SOC_TLV320AIC23
+        help
+          Say Y or M here if you want to add support for I2S audio on the
+          Bluewater Systems Snapper CL15 module.
+
+config SND_EP93XX_SOC_SIMONE
+        tristate "SoC Audio support for Simplemachines Sim.One board"
+        depends on SND_EP93XX_SOC && MACH_SIM_ONE
+        select SND_EP93XX_SOC_AC97
+        select SND_SOC_AC97_CODEC
+        help
+          Say Y or M here if you want to add support for AC97 audio on the
+          Simplemachines Sim.One board.
+
+config SND_EP93XX_SOC_EDB93XX
+        tristate "SoC Audio support for Cirrus Logic EDB93xx boards"
+        depends on SND_EP93XX_SOC && (MACH_EDB9301 || MACH_EDB9302 || MACH_EDB9302A || MACH_EDB9307A || MACH_EDB9315A)
+        select SND_EP93XX_SOC_I2S
+        select SND_SOC_CS4271
+        help
+          Say Y or M here if you want to add support for I2S audio on the
+          Cirrus Logic EDB93xx boards.
diff --git a/sound/soc/ep93xx/Makefile b/sound/soc/ep93xx/Makefile
new file mode 100644
index 00000000000..5514146cbdf
--- /dev/null
+++ b/sound/soc/ep93xx/Makefile
@@ -0,0 +1,17 @@
+# EP93xx Platform Support
+snd-soc-ep93xx-objs                             := ep93xx-pcm.o
+snd-soc-ep93xx-i2s-objs                         := ep93xx-i2s.o
+snd-soc-ep93xx-ac97-objs                        := ep93xx-ac97.o
+
+obj-$(CONFIG_SND_EP93XX_SOC)                    += snd-soc-ep93xx.o
+obj-$(CONFIG_SND_EP93XX_SOC_I2S)                += snd-soc-ep93xx-i2s.o
+obj-$(CONFIG_SND_EP93XX_SOC_AC97)               += snd-soc-ep93xx-ac97.o
+
+# EP93XX Machine Support
+snd-soc-snappercl15-objs                        := snappercl15.o
+snd-soc-simone-objs                             := simone.o
+snd-soc-edb93xx-objs                            := edb93xx.o
+
+obj-$(CONFIG_SND_EP93XX_SOC_SNAPPERCL15)        += snd-soc-snappercl15.o
+obj-$(CONFIG_SND_EP93XX_SOC_SIMONE)             += snd-soc-simone.o
+obj-$(CONFIG_SND_EP93XX_SOC_EDB93XX)            += snd-soc-edb93xx.o
diff --git a/sound/soc/ep93xx/edb93xx.c b/sound/soc/ep93xx/edb93xx.c
new file mode 100644
index 00000000000..d3aa15119d2
--- /dev/null
+++ b/sound/soc/ep93xx/edb93xx.c
@@ -0,0 +1,142 @@
+/*
+ * SoC audio for EDB93xx
+ *
+ * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * This driver support CS4271 codec being master or slave, working
+ * in control port mode, connected either via SPI or I2C.
+ * The data format accepted is I2S or left-justified.
+ * DAPM support not implemented.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include "ep93xx-pcm.h"
+
+#define edb93xx_has_audio() (machine_is_edb9301() ||    \
+                             machine_is_edb9302() ||    \
+                             machine_is_edb9302a() ||   \
+                             machine_is_edb9307a() ||   \
+                             machine_is_edb9315a())
+
+static int edb93xx_hw_params(struct snd_pcm_substream *substream,
+                             struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int err;
+        unsigned int mclk_rate;
+        unsigned int rate = params_rate(params);
+
+        /*
+         * According to CS4271 datasheet we use MCLK/LRCK=256 for
+         * rates below 50kHz and 128 for higher sample rates
+         */
+        if (rate < 50000)
+                mclk_rate = rate * 64 * 4;
+        else
+                mclk_rate = rate * 64 * 2;
+
+        err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_IF |
+                                  SND_SOC_DAIFMT_CBS_CFS);
+        if (err)
+                return err;
+
+        err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_IF |
+                                  SND_SOC_DAIFMT_CBS_CFS);
+        if (err)
+                return err;
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate,
+                                     SND_SOC_CLOCK_IN);
+        if (err)
+                return err;
+
+        return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate,
+                                      SND_SOC_CLOCK_OUT);
+}
+
+static struct snd_soc_ops edb93xx_ops = {
+        .hw_params      = edb93xx_hw_params,
+};
+
+static struct snd_soc_dai_link edb93xx_dai = {
+        .name           = "CS4271",
+        .stream_name    = "CS4271 HiFi",
+        .platform_name  = "ep93xx-pcm-audio",
+        .cpu_dai_name   = "ep93xx-i2s",
+        .codec_name     = "spi0.0",
+        .codec_dai_name = "cs4271-hifi",
+        .ops            = &edb93xx_ops,
+};
+
+static struct snd_soc_card snd_soc_edb93xx = {
+        .name           = "EDB93XX",
+        .dai_link       = &edb93xx_dai,
+        .num_links      = 1,
+};
+
+static struct platform_device *edb93xx_snd_device;
+
+static int __init edb93xx_init(void)
+{
+        int ret;
+
+        if (!edb93xx_has_audio())
+                return -ENODEV;
+
+        ret = ep93xx_i2s_acquire(EP93XX_SYSCON_DEVCFG_I2SONAC97,
+                                 EP93XX_SYSCON_I2SCLKDIV_ORIDE |
+                                 EP93XX_SYSCON_I2SCLKDIV_SPOL);
+        if (ret)
+                return ret;
+
+        edb93xx_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!edb93xx_snd_device) {
+                ret = -ENOMEM;
+                goto free_i2s;
+        }
+
+        platform_set_drvdata(edb93xx_snd_device, &snd_soc_edb93xx);
+        ret = platform_device_add(edb93xx_snd_device);
+        if (ret)
+                goto device_put;
+
+        return 0;
+
+device_put:
+        platform_device_put(edb93xx_snd_device);
+free_i2s:
+        ep93xx_i2s_release();
+        return ret;
+}
+module_init(edb93xx_init);
+
+static void __exit edb93xx_exit(void)
+{
+        platform_device_unregister(edb93xx_snd_device);
+        ep93xx_i2s_release();
+}
+module_exit(edb93xx_exit);
+
+MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
+MODULE_DESCRIPTION("ALSA SoC EDB93xx");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/ep93xx-ac97.c b/sound/soc/ep93xx/ep93xx-ac97.c
new file mode 100644
index 00000000000..c7417c76552
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-ac97.c
@@ -0,0 +1,467 @@
+/*
+ * ASoC driver for Cirrus Logic EP93xx AC97 controller.
+ *
+ * Copyright (c) 2010 Mika Westerberg
+ *
+ * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <sound/core.h>
+#include <sound/ac97_codec.h>
+#include <sound/soc.h>
+
+#include <mach/dma.h>
+#include "ep93xx-pcm.h"
+
+/*
+ * Per channel (1-4) registers.
+ */
+#define AC97CH(n)               (((n) - 1) * 0x20)
+
+#define AC97DR(n)               (AC97CH(n) + 0x0000)
+
+#define AC97RXCR(n)             (AC97CH(n) + 0x0004)
+#define AC97RXCR_REN            BIT(0)
+#define AC97RXCR_RX3            BIT(3)
+#define AC97RXCR_RX4            BIT(4)
+#define AC97RXCR_CM             BIT(15)
+
+#define AC97TXCR(n)             (AC97CH(n) + 0x0008)
+#define AC97TXCR_TEN            BIT(0)
+#define AC97TXCR_TX3            BIT(3)
+#define AC97TXCR_TX4            BIT(4)
+#define AC97TXCR_CM             BIT(15)
+
+#define AC97SR(n)               (AC97CH(n) + 0x000c)
+#define AC97SR_TXFE             BIT(1)
+#define AC97SR_TXUE             BIT(6)
+
+#define AC97RISR(n)             (AC97CH(n) + 0x0010)
+#define AC97ISR(n)              (AC97CH(n) + 0x0014)
+#define AC97IE(n)               (AC97CH(n) + 0x0018)
+
+/*
+ * Global AC97 controller registers.
+ */
+#define AC97S1DATA              0x0080
+#define AC97S2DATA              0x0084
+#define AC97S12DATA             0x0088
+
+#define AC97RGIS                0x008c
+#define AC97GIS                 0x0090
+#define AC97IM                  0x0094
+/*
+ * Common bits for RGIS, GIS and IM registers.
+ */
+#define AC97_SLOT2RXVALID       BIT(1)
+#define AC97_CODECREADY         BIT(5)
+#define AC97_SLOT2TXCOMPLETE    BIT(6)
+
+#define AC97EOI                 0x0098
+#define AC97EOI_WINT            BIT(0)
+#define AC97EOI_CODECREADY      BIT(1)
+
+#define AC97GCR                 0x009c
+#define AC97GCR_AC97IFE         BIT(0)
+
+#define AC97RESET               0x00a0
+#define AC97RESET_TIMEDRESET    BIT(0)
+
+#define AC97SYNC                0x00a4
+#define AC97SYNC_TIMEDSYNC      BIT(0)
+
+#define AC97_TIMEOUT            msecs_to_jiffies(5)
+
+/**
+ * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
+ * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
+ * @dev: pointer to the platform device dev structure
+ * @mem: physical memory resource for the registers
+ * @regs: mapped AC97 controller registers
+ * @irq: AC97 interrupt number
+ * @done: bus ops wait here for an interrupt
+ */
+struct ep93xx_ac97_info {
+        struct mutex            lock;
+        struct device           *dev;
+        struct resource         *mem;
+        void __iomem            *regs;
+        int                     irq;
+        struct completion       done;
+};
+
+/* currently ALSA only supports a single AC97 device */
+static struct ep93xx_ac97_info *ep93xx_ac97_info;
+
+static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_out = {
+        .name           = "ac97-pcm-out",
+        .dma_port       = EP93XX_DMA_AAC1,
+};
+
+static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_in = {
+        .name           = "ac97-pcm-in",
+        .dma_port       = EP93XX_DMA_AAC1,
+};
+
+static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
+                                            unsigned reg)
+{
+        return __raw_readl(info->regs + reg);
+}
+
+static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
+                                         unsigned reg, unsigned val)
+{
+        __raw_writel(val, info->regs + reg);
+}
+
+static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
+                                       unsigned short reg)
+{
+        struct ep93xx_ac97_info *info = ep93xx_ac97_info;
+        unsigned short val;
+
+        mutex_lock(&info->lock);
+
+        ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
+        ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
+        if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
+                dev_warn(info->dev, "timeout reading register %x\n", reg);
+                mutex_unlock(&info->lock);
+                return -ETIMEDOUT;
+        }
+        val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
+
+        mutex_unlock(&info->lock);
+        return val;
+}
+
+static void ep93xx_ac97_write(struct snd_ac97 *ac97,
+                              unsigned short reg,
+                              unsigned short val)
+{
+        struct ep93xx_ac97_info *info = ep93xx_ac97_info;
+
+        mutex_lock(&info->lock);
+
+        /*
+         * Writes to the codec need to be done so that slot 2 is filled in
+         * before slot 1.
+         */
+        ep93xx_ac97_write_reg(info, AC97S2DATA, val);
+        ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
+
+        ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
+        if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
+                dev_warn(info->dev, "timeout writing register %x\n", reg);
+
+        mutex_unlock(&info->lock);
+}
+
+static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+        struct ep93xx_ac97_info *info = ep93xx_ac97_info;
+
+        mutex_lock(&info->lock);
+
+        /*
+         * We are assuming that before this functions gets called, the codec
+         * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
+         * control the SYNC signal directly via AC97SYNC register. Using
+         * TIMEDSYNC the controller will keep the SYNC high > 1us.
+         */
+        ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
+        ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
+        if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
+                dev_warn(info->dev, "codec warm reset timeout\n");
+
+        mutex_unlock(&info->lock);
+}
+
+static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
+{
+        struct ep93xx_ac97_info *info = ep93xx_ac97_info;
+
+        mutex_lock(&info->lock);
+
+        /*
+         * For doing cold reset, we disable the AC97 controller interface, clear
+         * WINT and CODECREADY bits, and finally enable the interface again.
+         */
+        ep93xx_ac97_write_reg(info, AC97GCR, 0);
+        ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
+        ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
+
+        /*
+         * Now, assert the reset and wait for the codec to become ready.
+         */
+        ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
+        ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
+        if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
+                dev_warn(info->dev, "codec cold reset timeout\n");
+
+        /*
+         * Give the codec some time to come fully out from the reset. This way
+         * we ensure that the subsequent reads/writes will work.
+         */
+        usleep_range(15000, 20000);
+
+        mutex_unlock(&info->lock);
+}
+
+static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
+{
+        struct ep93xx_ac97_info *info = dev_id;
+        unsigned status, mask;
+
+        /*
+         * Just mask out the interrupt and wake up the waiting thread.
+         * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
+         * the waiting thread.
+         */
+        status = ep93xx_ac97_read_reg(info, AC97GIS);
+        mask = ep93xx_ac97_read_reg(info, AC97IM);
+        mask &= ~status;
+        ep93xx_ac97_write_reg(info, AC97IM, mask);
+
+        complete(&info->done);
+        return IRQ_HANDLED;
+}
+
+struct snd_ac97_bus_ops soc_ac97_ops = {
+        .read           = ep93xx_ac97_read,
+        .write          = ep93xx_ac97_write,
+        .reset          = ep93xx_ac97_cold_reset,
+        .warm_reset     = ep93xx_ac97_warm_reset,
+};
+EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
+static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
+                               int cmd, struct snd_soc_dai *dai)
+{
+        struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
+        unsigned v = 0;
+
+        switch (cmd) {
+        case SNDRV_PCM_TRIGGER_START:
+        case SNDRV_PCM_TRIGGER_RESUME:
+        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                        /*
+                         * Enable compact mode, TX slots 3 & 4, and the TX FIFO
+                         * itself.
+                         */
+                        v |= AC97TXCR_CM;
+                        v |= AC97TXCR_TX3 | AC97TXCR_TX4;
+                        v |= AC97TXCR_TEN;
+                        ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
+                } else {
+                        /*
+                         * Enable compact mode, RX slots 3 & 4, and the RX FIFO
+                         * itself.
+                         */
+                        v |= AC97RXCR_CM;
+                        v |= AC97RXCR_RX3 | AC97RXCR_RX4;
+                        v |= AC97RXCR_REN;
+                        ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
+                }
+                break;
+
+        case SNDRV_PCM_TRIGGER_STOP:
+        case SNDRV_PCM_TRIGGER_SUSPEND:
+        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                        /*
+                         * As per Cirrus EP93xx errata described below:
+                         *
+                         * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
+                         *
+                         * we will wait for the TX FIFO to be empty before
+                         * clearing the TEN bit.
+                         */
+                        unsigned long timeout = jiffies + AC97_TIMEOUT;
+
+                        do {
+                                v = ep93xx_ac97_read_reg(info, AC97SR(1));
+                                if (time_after(jiffies, timeout)) {
+                                        dev_warn(info->dev, "TX timeout\n");
+                                        break;
+                                }
+                        } while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
+
+                        /* disable the TX FIFO */
+                        ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
+                } else {
+                        /* disable the RX FIFO */
+                        ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
+                }
+                break;
+
+        default:
+                dev_warn(info->dev, "unknown command %d\n", cmd);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int ep93xx_ac97_startup(struct snd_pcm_substream *substream,
+                               struct snd_soc_dai *dai)
+{
+        struct ep93xx_pcm_dma_params *dma_data;
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                dma_data = &ep93xx_ac97_pcm_out;
+        else
+                dma_data = &ep93xx_ac97_pcm_in;
+
+        snd_soc_dai_set_dma_data(dai, substream, dma_data);
+        return 0;
+}
+
+static struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
+        .startup        = ep93xx_ac97_startup,
+        .trigger        = ep93xx_ac97_trigger,
+};
+
+struct snd_soc_dai_driver ep93xx_ac97_dai = {
+        .name           = "ep93xx-ac97",
+        .id             = 0,
+        .ac97_control   = 1,
+        .playback       = {
+                .stream_name    = "AC97 Playback",
+                .channels_min   = 2,
+                .channels_max   = 2,
+                .rates          = SNDRV_PCM_RATE_8000_48000,
+                .formats        = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .capture        = {
+                .stream_name    = "AC97 Capture",
+                .channels_min   = 2,
+                .channels_max   = 2,
+                .rates          = SNDRV_PCM_RATE_8000_48000,
+                .formats        = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .ops                    = &ep93xx_ac97_dai_ops,
+};
+
+static int __devinit ep93xx_ac97_probe(struct platform_device *pdev)
+{
+        struct ep93xx_ac97_info *info;
+        int ret;
+
+        info = kzalloc(sizeof(struct ep93xx_ac97_info), GFP_KERNEL);
+        if (!info)
+                return -ENOMEM;
+
+        dev_set_drvdata(&pdev->dev, info);
+
+        mutex_init(&info->lock);
+        init_completion(&info->done);
+        info->dev = &pdev->dev;
+
+        info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!info->mem) {
+                ret = -ENXIO;
+                goto fail_free_info;
+        }
+
+        info->irq = platform_get_irq(pdev, 0);
+        if (!info->irq) {
+                ret = -ENXIO;
+                goto fail_free_info;
+        }
+
+        if (!request_mem_region(info->mem->start, resource_size(info->mem),
+                                pdev->name)) {
+                ret = -EBUSY;
+                goto fail_free_info;
+        }
+
+        info->regs = ioremap(info->mem->start, resource_size(info->mem));
+        if (!info->regs) {
+                ret = -ENOMEM;
+                goto fail_release_mem;
+        }
+
+        ret = request_irq(info->irq, ep93xx_ac97_interrupt, IRQF_TRIGGER_HIGH,
+                          pdev->name, info);
+        if (ret)
+                goto fail_unmap_mem;
+
+        ep93xx_ac97_info = info;
+        platform_set_drvdata(pdev, info);
+
+        ret = snd_soc_register_dai(&pdev->dev, &ep93xx_ac97_dai);
+        if (ret)
+                goto fail_free_irq;
+
+        return 0;
+
+fail_free_irq:
+        platform_set_drvdata(pdev, NULL);
+        free_irq(info->irq, info);
+fail_unmap_mem:
+        iounmap(info->regs);
+fail_release_mem:
+        release_mem_region(info->mem->start, resource_size(info->mem));
+fail_free_info:
+        kfree(info);
+
+        return ret;
+}
+
+static int __devexit ep93xx_ac97_remove(struct platform_device *pdev)
+{
+        struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
+
+        snd_soc_unregister_dai(&pdev->dev);
+
+        /* disable the AC97 controller */
+        ep93xx_ac97_write_reg(info, AC97GCR, 0);
+
+        free_irq(info->irq, info);
+        iounmap(info->regs);
+        release_mem_region(info->mem->start, resource_size(info->mem));
+        platform_set_drvdata(pdev, NULL);
+        kfree(info);
+
+        return 0;
+}
+
+static struct platform_driver ep93xx_ac97_driver = {
+        .probe  = ep93xx_ac97_probe,
+        .remove = __devexit_p(ep93xx_ac97_remove),
+        .driver = {
+                .name = "ep93xx-ac97",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init ep93xx_ac97_init(void)
+{
+        return platform_driver_register(&ep93xx_ac97_driver);
+}
+module_init(ep93xx_ac97_init);
+
+static void __exit ep93xx_ac97_exit(void)
+{
+        platform_driver_unregister(&ep93xx_ac97_driver);
+}
+module_exit(ep93xx_ac97_exit);
+
+MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ep93xx-ac97");
diff --git a/sound/soc/ep93xx/ep93xx-i2s.c b/sound/soc/ep93xx/ep93xx-i2s.c
new file mode 100644
index 00000000000..099614e1665
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-i2s.c
@@ -0,0 +1,483 @@
+/*
+ * linux/sound/soc/ep93xx-i2s.c
+ * EP93xx I2S driver
+ *
+ * Copyright (C) 2010 Ryan Mallon
+ *
+ * Based on the original driver by:
+ *   Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
+ *   Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <mach/hardware.h>
+#include <mach/ep93xx-regs.h>
+#include <mach/dma.h>
+
+#include "ep93xx-pcm.h"
+
+#define EP93XX_I2S_TXCLKCFG             0x00
+#define EP93XX_I2S_RXCLKCFG             0x04
+#define EP93XX_I2S_GLCTRL               0x0C
+
+#define EP93XX_I2S_TXLINCTRLDATA        0x28
+#define EP93XX_I2S_TXCTRL               0x2C
+#define EP93XX_I2S_TXWRDLEN             0x30
+#define EP93XX_I2S_TX0EN                0x34
+
+#define EP93XX_I2S_RXLINCTRLDATA        0x58
+#define EP93XX_I2S_RXCTRL               0x5C
+#define EP93XX_I2S_RXWRDLEN             0x60
+#define EP93XX_I2S_RX0EN                0x64
+
+#define EP93XX_I2S_WRDLEN_16            (0 << 0)
+#define EP93XX_I2S_WRDLEN_24            (1 << 0)
+#define EP93XX_I2S_WRDLEN_32            (2 << 0)
+
+#define EP93XX_I2S_LINCTRLDATA_R_JUST   (1 << 2) /* Right justify */
+
+#define EP93XX_I2S_CLKCFG_LRS           (1 << 0) /* lrclk polarity */
+#define EP93XX_I2S_CLKCFG_CKP           (1 << 1) /* Bit clock polarity */
+#define EP93XX_I2S_CLKCFG_REL           (1 << 2) /* First bit transition */
+#define EP93XX_I2S_CLKCFG_MASTER        (1 << 3) /* Master mode */
+#define EP93XX_I2S_CLKCFG_NBCG          (1 << 4) /* Not bit clock gating */
+
+struct ep93xx_i2s_info {
+        struct clk                      *mclk;
+        struct clk                      *sclk;
+        struct clk                      *lrclk;
+        struct ep93xx_pcm_dma_params    *dma_params;
+        struct resource                 *mem;
+        void __iomem                    *regs;
+};
+
+struct ep93xx_pcm_dma_params ep93xx_i2s_dma_params[] = {
+        [SNDRV_PCM_STREAM_PLAYBACK] = {
+                .name           = "i2s-pcm-out",
+                .dma_port       = EP93XX_DMA_I2S1,
+        },
+        [SNDRV_PCM_STREAM_CAPTURE] = {
+                .name           = "i2s-pcm-in",
+                .dma_port       = EP93XX_DMA_I2S1,
+        },
+};
+
+static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
+                                        unsigned reg, unsigned val)
+{
+        __raw_writel(val, info->regs + reg);
+}
+
+static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
+                                           unsigned reg)
+{
+        return __raw_readl(info->regs + reg);
+}
+
+static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
+{
+        unsigned base_reg;
+        int i;
+
+        if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
+            (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
+                /* Enable clocks */
+                clk_enable(info->mclk);
+                clk_enable(info->sclk);
+                clk_enable(info->lrclk);
+
+                /* Enable i2s */
+                ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
+        }
+
+        /* Enable fifos */
+        if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+                base_reg = EP93XX_I2S_TX0EN;
+        else
+                base_reg = EP93XX_I2S_RX0EN;
+        for (i = 0; i < 3; i++)
+                ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
+}
+
+static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
+{
+        unsigned base_reg;
+        int i;
+
+        /* Disable fifos */
+        if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+                base_reg = EP93XX_I2S_TX0EN;
+        else
+                base_reg = EP93XX_I2S_RX0EN;
+        for (i = 0; i < 3; i++)
+                ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
+
+        if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
+            (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
+                /* Disable i2s */
+                ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
+
+                /* Disable clocks */
+                clk_disable(info->lrclk);
+                clk_disable(info->sclk);
+                clk_disable(info->mclk);
+        }
+}
+
+static int ep93xx_i2s_startup(struct snd_pcm_substream *substream,
+                              struct snd_soc_dai *dai)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+
+        snd_soc_dai_set_dma_data(cpu_dai, substream,
+                                 &info->dma_params[substream->stream]);
+        return 0;
+}
+
+static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
+                                struct snd_soc_dai *dai)
+{
+        struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
+
+        ep93xx_i2s_disable(info, substream->stream);
+}
+
+static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
+                                  unsigned int fmt)
+{
+        struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
+        unsigned int clk_cfg, lin_ctrl;
+
+        clk_cfg  = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
+        lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
+
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                clk_cfg |= EP93XX_I2S_CLKCFG_REL;
+                lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
+                break;
+
+        case SND_SOC_DAIFMT_LEFT_J:
+                clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+                lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
+                break;
+
+        case SND_SOC_DAIFMT_RIGHT_J:
+                clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+                lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBS_CFS:
+                /* CPU is master */
+                clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
+                break;
+
+        case SND_SOC_DAIFMT_CBM_CFM:
+                /* Codec is master */
+                clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_NB_NF:
+                /* Negative bit clock, lrclk low on left word */
+                clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
+                break;
+
+        case SND_SOC_DAIFMT_NB_IF:
+                /* Negative bit clock, lrclk low on right word */
+                clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
+                clk_cfg |= EP93XX_I2S_CLKCFG_REL;
+                break;
+
+        case SND_SOC_DAIFMT_IB_NF:
+                /* Positive bit clock, lrclk low on left word */
+                clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
+                clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+                break;
+
+        case SND_SOC_DAIFMT_IB_IF:
+                /* Positive bit clock, lrclk low on right word */
+                clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
+                break;
+        }
+
+        /* Write new register values */
+        ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
+        ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
+        ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
+        ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
+        return 0;
+}
+
+static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params,
+                                struct snd_soc_dai *dai)
+{
+        struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
+        unsigned word_len, div, sdiv, lrdiv;
+        int err;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                word_len = EP93XX_I2S_WRDLEN_16;
+                break;
+
+        case SNDRV_PCM_FORMAT_S24_LE:
+                word_len = EP93XX_I2S_WRDLEN_24;
+                break;
+
+        case SNDRV_PCM_FORMAT_S32_LE:
+                word_len = EP93XX_I2S_WRDLEN_32;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
+        else
+                ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
+
+        /*
+         * EP93xx I2S module can be setup so SCLK / LRCLK value can be
+         * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
+         * We set LRCLK equal to `rate' and minimum SCLK / LRCLK 
+         * value is 64, because our sample size is 32 bit * 2 channels.
+         * I2S standard permits us to transmit more bits than
+         * the codec uses.
+         */
+        div = clk_get_rate(info->mclk) / params_rate(params);
+        sdiv = 4;
+        if (div > (256 + 512) / 2) {
+                lrdiv = 128;
+        } else {
+                lrdiv = 64;
+                if (div < (128 + 256) / 2)
+                        sdiv = 2;
+        }
+
+        err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
+        if (err)
+                return err;
+
+        err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
+        if (err)
+                return err;
+
+        ep93xx_i2s_enable(info, substream->stream);
+        return 0;
+}
+
+static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
+                                 unsigned int freq, int dir)
+{
+        struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
+
+        if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
+                return -EINVAL;
+
+        return clk_set_rate(info->mclk, freq);
+}
+
+#ifdef CONFIG_PM
+static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
+{
+        struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
+
+        if (!dai->active)
+                return 0;
+
+        ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
+        ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
+
+        return 0;
+}
+
+static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
+{
+        struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
+
+        if (!dai->active)
+                return 0;
+
+        ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
+        ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
+
+        return 0;
+}
+#else
+#define ep93xx_i2s_suspend      NULL
+#define ep93xx_i2s_resume       NULL
+#endif
+
+static struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
+        .startup        = ep93xx_i2s_startup,
+        .shutdown       = ep93xx_i2s_shutdown,
+        .hw_params      = ep93xx_i2s_hw_params,
+        .set_sysclk     = ep93xx_i2s_set_sysclk,
+        .set_fmt        = ep93xx_i2s_set_dai_fmt,
+};
+
+#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver ep93xx_i2s_dai = {
+        .symmetric_rates= 1,
+        .suspend        = ep93xx_i2s_suspend,
+        .resume         = ep93xx_i2s_resume,
+        .playback       = {
+                .channels_min   = 2,
+                .channels_max   = 2,
+                .rates          = SNDRV_PCM_RATE_8000_192000,
+                .formats        = EP93XX_I2S_FORMATS,
+        },
+        .capture        = {
+                 .channels_min  = 2,
+                 .channels_max  = 2,
+                 .rates         = SNDRV_PCM_RATE_8000_192000,
+                 .formats       = EP93XX_I2S_FORMATS,
+        },
+        .ops            = &ep93xx_i2s_dai_ops,
+};
+
+static int ep93xx_i2s_probe(struct platform_device *pdev)
+{
+        struct ep93xx_i2s_info *info;
+        struct resource *res;
+        int err;
+
+        info = kzalloc(sizeof(struct ep93xx_i2s_info), GFP_KERNEL);
+        if (!info) {
+                err = -ENOMEM;
+                goto fail;
+        }
+
+        dev_set_drvdata(&pdev->dev, info);
+        info->dma_params = ep93xx_i2s_dma_params;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                err = -ENODEV;
+                goto fail_free_info;
+        }
+
+        info->mem = request_mem_region(res->start, resource_size(res),
+                                       pdev->name);
+        if (!info->mem) {
+                err = -EBUSY;
+                goto fail_free_info;
+        }
+
+        info->regs = ioremap(info->mem->start, resource_size(info->mem));
+        if (!info->regs) {
+                err = -ENXIO;
+                goto fail_release_mem;
+        }
+
+        info->mclk = clk_get(&pdev->dev, "mclk");
+        if (IS_ERR(info->mclk)) {
+                err = PTR_ERR(info->mclk);
+                goto fail_unmap_mem;
+        }
+
+        info->sclk = clk_get(&pdev->dev, "sclk");
+        if (IS_ERR(info->sclk)) {
+                err = PTR_ERR(info->sclk);
+                goto fail_put_mclk;
+        }
+
+        info->lrclk = clk_get(&pdev->dev, "lrclk");
+        if (IS_ERR(info->lrclk)) {
+                err = PTR_ERR(info->lrclk);
+                goto fail_put_sclk;
+        }
+
+        err = snd_soc_register_dai(&pdev->dev, &ep93xx_i2s_dai);
+        if (err)
+                goto fail_put_lrclk;
+
+        return 0;
+
+fail_put_lrclk:
+        clk_put(info->lrclk);
+fail_put_sclk:
+        clk_put(info->sclk);
+fail_put_mclk:
+        clk_put(info->mclk);
+fail_unmap_mem:
+        iounmap(info->regs);
+fail_release_mem:
+        release_mem_region(info->mem->start, resource_size(info->mem));
+fail_free_info:
+        kfree(info);
+fail:
+        return err;
+}
+
+static int __devexit ep93xx_i2s_remove(struct platform_device *pdev)
+{
+        struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
+
+        snd_soc_unregister_dai(&pdev->dev);
+        clk_put(info->lrclk);
+        clk_put(info->sclk);
+        clk_put(info->mclk);
+        iounmap(info->regs);
+        release_mem_region(info->mem->start, resource_size(info->mem));
+        kfree(info);
+        return 0;
+}
+
+static struct platform_driver ep93xx_i2s_driver = {
+        .probe  = ep93xx_i2s_probe,
+        .remove = __devexit_p(ep93xx_i2s_remove),
+        .driver = {
+                .name   = "ep93xx-i2s",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init ep93xx_i2s_init(void)
+{
+        return platform_driver_register(&ep93xx_i2s_driver);
+}
+
+static void __exit ep93xx_i2s_exit(void)
+{
+        platform_driver_unregister(&ep93xx_i2s_driver);
+}
+
+module_init(ep93xx_i2s_init);
+module_exit(ep93xx_i2s_exit);
+
+MODULE_ALIAS("platform:ep93xx-i2s");
+MODULE_AUTHOR("Ryan Mallon");
+MODULE_DESCRIPTION("EP93XX I2S driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/ep93xx-pcm.c b/sound/soc/ep93xx/ep93xx-pcm.c
new file mode 100644
index 00000000000..8dfd3ad84b1
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-pcm.c
@@ -0,0 +1,357 @@
+/*
+ * linux/sound/arm/ep93xx-pcm.c - EP93xx ALSA PCM interface
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * Rewritten for the SoC audio subsystem (Based on PXA2xx code):
+ *   Copyright (c) 2008 Ryan Mallon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/dma.h>
+#include <mach/hardware.h>
+#include <mach/ep93xx-regs.h>
+
+#include "ep93xx-pcm.h"
+
+static const struct snd_pcm_hardware ep93xx_pcm_hardware = {
+        .info                   = (SNDRV_PCM_INFO_MMAP          |
+                                   SNDRV_PCM_INFO_MMAP_VALID    |
+                                   SNDRV_PCM_INFO_INTERLEAVED   |
+                                   SNDRV_PCM_INFO_BLOCK_TRANSFER),
+                                   
+        .rates                  = SNDRV_PCM_RATE_8000_192000,
+        .rate_min               = SNDRV_PCM_RATE_8000,
+        .rate_max               = SNDRV_PCM_RATE_192000,
+        
+        .formats                = (SNDRV_PCM_FMTBIT_S16_LE |
+                                   SNDRV_PCM_FMTBIT_S24_LE |
+                                   SNDRV_PCM_FMTBIT_S32_LE),
+        
+        .buffer_bytes_max       = 131072,
+        .period_bytes_min       = 32,
+        .period_bytes_max       = 32768,
+        .periods_min            = 1,
+        .periods_max            = 32,
+        .fifo_size              = 32,
+};
+
+struct ep93xx_runtime_data
+{
+        int                             pointer_bytes;
+        int                             periods;
+        int                             period_bytes;
+        struct dma_chan                 *dma_chan;
+        struct ep93xx_dma_data          dma_data;
+};
+
+static void ep93xx_pcm_dma_callback(void *data)
+{
+        struct snd_pcm_substream *substream = data;
+        struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+        rtd->pointer_bytes += rtd->period_bytes;
+        rtd->pointer_bytes %= rtd->period_bytes * rtd->periods;
+
+        snd_pcm_period_elapsed(substream);
+}
+
+static bool ep93xx_pcm_dma_filter(struct dma_chan *chan, void *filter_param)
+{
+        struct ep93xx_dma_data *data = filter_param;
+
+        if (data->direction == ep93xx_dma_chan_direction(chan)) {
+                chan->private = data;
+                return true;
+        }
+
+        return false;
+}
+
+static int ep93xx_pcm_open(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *soc_rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = soc_rtd->cpu_dai;
+        struct ep93xx_pcm_dma_params *dma_params;
+        struct ep93xx_runtime_data *rtd;    
+        dma_cap_mask_t mask;
+        int ret;
+
+        ret = snd_pcm_hw_constraint_integer(substream->runtime,
+                                            SNDRV_PCM_HW_PARAM_PERIODS);
+        if (ret < 0)
+                return ret;
+
+        snd_soc_set_runtime_hwparams(substream, &ep93xx_pcm_hardware);
+
+        rtd = kmalloc(sizeof(*rtd), GFP_KERNEL);
+        if (!rtd) 
+                return -ENOMEM;
+
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
+        dma_cap_set(DMA_CYCLIC, mask);
+
+        dma_params = snd_soc_dai_get_dma_data(cpu_dai, substream);
+        rtd->dma_data.port = dma_params->dma_port;
+        rtd->dma_data.name = dma_params->name;
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                rtd->dma_data.direction = DMA_TO_DEVICE;
+        else
+                rtd->dma_data.direction = DMA_FROM_DEVICE;
+
+        rtd->dma_chan = dma_request_channel(mask, ep93xx_pcm_dma_filter,
+                                            &rtd->dma_data);
+        if (!rtd->dma_chan) {
+                kfree(rtd);
+                return -EINVAL;
+        }
+        
+        substream->runtime->private_data = rtd;
+        return 0;
+}
+
+static int ep93xx_pcm_close(struct snd_pcm_substream *substream)
+{
+        struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+        dma_release_channel(rtd->dma_chan);
+        kfree(rtd);
+        return 0;
+}
+
+static int ep93xx_pcm_dma_submit(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct ep93xx_runtime_data *rtd = runtime->private_data;
+        struct dma_chan *chan = rtd->dma_chan;
+        struct dma_device *dma_dev = chan->device;
+        struct dma_async_tx_descriptor *desc;
+
+        rtd->pointer_bytes = 0;
+        desc = dma_dev->device_prep_dma_cyclic(chan, runtime->dma_addr,
+                                               rtd->period_bytes * rtd->periods,
+                                               rtd->period_bytes,
+                                               rtd->dma_data.direction);
+        if (!desc)
+                return -EINVAL;
+
+        desc->callback = ep93xx_pcm_dma_callback;
+        desc->callback_param = substream;
+
+        dmaengine_submit(desc);
+        return 0;
+}
+
+static void ep93xx_pcm_dma_flush(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct ep93xx_runtime_data *rtd = runtime->private_data;
+
+        dmaengine_terminate_all(rtd->dma_chan);
+}
+
+static int ep93xx_pcm_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct ep93xx_runtime_data *rtd = runtime->private_data;
+
+        snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+
+        rtd->periods = params_periods(params);
+        rtd->period_bytes = params_period_bytes(params);
+        return 0;
+}
+
+static int ep93xx_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+        snd_pcm_set_runtime_buffer(substream, NULL);
+        return 0;
+}
+
+static int ep93xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+        int ret;
+
+        ret = 0;
+        switch (cmd) {
+        case SNDRV_PCM_TRIGGER_START:
+        case SNDRV_PCM_TRIGGER_RESUME:
+        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+                ret = ep93xx_pcm_dma_submit(substream);
+                break;
+
+        case SNDRV_PCM_TRIGGER_STOP:
+        case SNDRV_PCM_TRIGGER_SUSPEND:
+        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+                ep93xx_pcm_dma_flush(substream);
+                break;
+
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
+static snd_pcm_uframes_t ep93xx_pcm_pointer(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+        /* FIXME: implement this with sub-period granularity */
+        return bytes_to_frames(runtime, rtd->pointer_bytes);
+}
+
+static int ep93xx_pcm_mmap(struct snd_pcm_substream *substream,
+                           struct vm_area_struct *vma)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+
+        return dma_mmap_writecombine(substream->pcm->card->dev, vma,
+                                     runtime->dma_area,
+                                     runtime->dma_addr,
+                                     runtime->dma_bytes);
+}
+
+static struct snd_pcm_ops ep93xx_pcm_ops = {
+        .open           = ep93xx_pcm_open,
+        .close          = ep93xx_pcm_close,
+        .ioctl          = snd_pcm_lib_ioctl,
+        .hw_params      = ep93xx_pcm_hw_params,
+        .hw_free        = ep93xx_pcm_hw_free,
+        .trigger        = ep93xx_pcm_trigger,
+        .pointer        = ep93xx_pcm_pointer,
+        .mmap           = ep93xx_pcm_mmap,
+};
+
+static int ep93xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+        struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+        struct snd_dma_buffer *buf = &substream->dma_buffer;
+        size_t size = ep93xx_pcm_hardware.buffer_bytes_max;
+
+        buf->dev.type = SNDRV_DMA_TYPE_DEV;
+        buf->dev.dev = pcm->card->dev;
+        buf->private_data = NULL;
+        buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+                                           &buf->addr, GFP_KERNEL);
+        buf->bytes = size;
+
+        return (buf->area == NULL) ? -ENOMEM : 0;
+}
+
+static void ep93xx_pcm_free_dma_buffers(struct snd_pcm *pcm)
+{
+        struct snd_pcm_substream *substream;
+        struct snd_dma_buffer *buf;
+        int stream;
+
+        for (stream = 0; stream < 2; stream++) {                
+                substream = pcm->streams[stream].substream;
+                if (!substream)
+                        continue;
+                
+                buf = &substream->dma_buffer;
+                if (!buf->area)
+                        continue;
+
+                dma_free_writecombine(pcm->card->dev, buf->bytes, buf->area,
+                                      buf->addr);
+                buf->area = NULL;
+        }
+}
+
+static u64 ep93xx_pcm_dmamask = 0xffffffff;
+
+static int ep93xx_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_card *card = rtd->card->snd_card;
+        struct snd_soc_dai *dai = rtd->cpu_dai;
+        struct snd_pcm *pcm = rtd->pcm;
+        int ret = 0;
+
+        if (!card->dev->dma_mask)
+                card->dev->dma_mask = &ep93xx_pcm_dmamask;
+        if (!card->dev->coherent_dma_mask)
+                card->dev->coherent_dma_mask = 0xffffffff;
+
+        if (dai->driver->playback.channels_min) {
+                ret = ep93xx_pcm_preallocate_dma_buffer(pcm,
+                                        SNDRV_PCM_STREAM_PLAYBACK);
+                if (ret)
+                        return ret;
+        }
+
+        if (dai->driver->capture.channels_min) {
+                ret = ep93xx_pcm_preallocate_dma_buffer(pcm,
+                                        SNDRV_PCM_STREAM_CAPTURE);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_platform_driver ep93xx_soc_platform = {
+        .ops            = &ep93xx_pcm_ops,
+        .pcm_new        = &ep93xx_pcm_new,
+        .pcm_free       = &ep93xx_pcm_free_dma_buffers,
+};
+
+static int __devinit ep93xx_soc_platform_probe(struct platform_device *pdev)
+{
+        return snd_soc_register_platform(&pdev->dev, &ep93xx_soc_platform);
+}
+
+static int __devexit ep93xx_soc_platform_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_platform(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver ep93xx_pcm_driver = {
+        .driver = {
+                        .name = "ep93xx-pcm-audio",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = ep93xx_soc_platform_probe,
+        .remove = __devexit_p(ep93xx_soc_platform_remove),
+};
+
+static int __init ep93xx_soc_platform_init(void)
+{
+        return platform_driver_register(&ep93xx_pcm_driver);
+}
+
+static void __exit ep93xx_soc_platform_exit(void)
+{
+        platform_driver_unregister(&ep93xx_pcm_driver);
+}
+
+module_init(ep93xx_soc_platform_init);
+module_exit(ep93xx_soc_platform_exit);
+
+MODULE_AUTHOR("Ryan Mallon");
+MODULE_DESCRIPTION("EP93xx ALSA PCM interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/ep93xx-pcm.h b/sound/soc/ep93xx/ep93xx-pcm.h
new file mode 100644
index 00000000000..111e1121ecb
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-pcm.h
@@ -0,0 +1,20 @@
+/*
+ * sound/soc/ep93xx/ep93xx-pcm.h - EP93xx ALSA PCM interface
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EP93XX_SND_SOC_PCM_H
+#define _EP93XX_SND_SOC_PCM_H
+
+struct ep93xx_pcm_dma_params {
+        char    *name;
+        int     dma_port;
+};
+
+#endif /* _EP93XX_SND_SOC_PCM_H */
diff --git a/sound/soc/ep93xx/simone.c b/sound/soc/ep93xx/simone.c
new file mode 100644
index 00000000000..286817946c5
--- /dev/null
+++ b/sound/soc/ep93xx/simone.c
@@ -0,0 +1,91 @@
+/*
+ * simone.c -- ASoC audio for Simplemachines Sim.One board
+ *
+ * Copyright (c) 2010 Mika Westerberg
+ *
+ * Based on snappercl15 machine driver by Ryan Mallon.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include "ep93xx-pcm.h"
+
+static struct snd_soc_dai_link simone_dai = {
+        .name           = "AC97",
+        .stream_name    = "AC97 HiFi",
+        .cpu_dai_name   = "ep93xx-ac97",
+        .codec_dai_name = "ac97-hifi",
+        .codec_name     = "ac97-codec",
+        .platform_name  = "ep93xx-pcm-audio",
+};
+
+static struct snd_soc_card snd_soc_simone = {
+        .name           = "Sim.One",
+        .dai_link       = &simone_dai,
+        .num_links      = 1,
+};
+
+static struct platform_device *simone_snd_ac97_device;
+static struct platform_device *simone_snd_device;
+
+static int __init simone_init(void)
+{
+        int ret;
+
+        if (!machine_is_sim_one())
+                return -ENODEV;
+
+        simone_snd_ac97_device = platform_device_alloc("ac97-codec", -1);
+        if (!simone_snd_ac97_device)
+                return -ENOMEM;
+
+        ret = platform_device_add(simone_snd_ac97_device);
+        if (ret)
+                goto fail1;
+
+        simone_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!simone_snd_device) {
+                ret = -ENOMEM;
+                goto fail2;
+        }
+
+        platform_set_drvdata(simone_snd_device, &snd_soc_simone);
+        ret = platform_device_add(simone_snd_device);
+        if (ret)
+                goto fail3;
+
+        return 0;
+
+fail3:
+        platform_device_put(simone_snd_device);
+fail2:
+        platform_device_del(simone_snd_ac97_device);
+fail1:
+        platform_device_put(simone_snd_ac97_device);
+        return ret;
+}
+module_init(simone_init);
+
+static void __exit simone_exit(void)
+{
+        platform_device_unregister(simone_snd_device);
+        platform_device_unregister(simone_snd_ac97_device);
+}
+module_exit(simone_exit);
+
+MODULE_DESCRIPTION("ALSA SoC Simplemachines Sim.One");
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/snappercl15.c b/sound/soc/ep93xx/snappercl15.c
new file mode 100644
index 00000000000..c8aa8a5003c
--- /dev/null
+++ b/sound/soc/ep93xx/snappercl15.c
@@ -0,0 +1,146 @@
+/*
+ * snappercl15.c -- SoC audio for Bluewater Systems Snapper CL15 module
+ *
+ * Copyright (C) 2008 Bluewater Systems Ltd
+ * Author: Ryan Mallon
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include "../codecs/tlv320aic23.h"
+#include "ep93xx-pcm.h"
+
+#define CODEC_CLOCK 5644800
+
+static int snappercl15_hw_params(struct snd_pcm_substream *substream,
+                                 struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int err;
+
+        err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_IF |
+                                  SND_SOC_DAIFMT_CBS_CFS);
+
+        err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | 
+                                  SND_SOC_DAIFMT_NB_IF |                  
+                                  SND_SOC_DAIFMT_CBS_CFS);
+        if (err)
+                return err;
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_CLOCK, 
+                                     SND_SOC_CLOCK_IN);
+        if (err)
+                return err;
+
+        err = snd_soc_dai_set_sysclk(cpu_dai, 0, CODEC_CLOCK, 
+                                     SND_SOC_CLOCK_OUT);
+        if (err)
+                return err;
+
+        return 0;
+}
+
+static struct snd_soc_ops snappercl15_ops = {
+        .hw_params      = snappercl15_hw_params,
+};
+
+static const struct snd_soc_dapm_widget tlv320aic23_dapm_widgets[] = {
+        SND_SOC_DAPM_HP("Headphone Jack", NULL),
+        SND_SOC_DAPM_LINE("Line In", NULL),
+        SND_SOC_DAPM_MIC("Mic Jack", NULL),
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+        {"Headphone Jack", NULL, "LHPOUT"},
+        {"Headphone Jack", NULL, "RHPOUT"},
+
+        {"LLINEIN", NULL, "Line In"},
+        {"RLINEIN", NULL, "Line In"},
+
+        {"MICIN", NULL, "Mic Jack"},
+};
+
+static int snappercl15_tlv320aic23_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_dapm_new_controls(dapm, tlv320aic23_dapm_widgets,
+                                  ARRAY_SIZE(tlv320aic23_dapm_widgets));
+
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+        return 0;
+}
+
+static struct snd_soc_dai_link snappercl15_dai = {
+        .name           = "tlv320aic23",
+        .stream_name    = "AIC23",
+        .cpu_dai_name   = "ep93xx-i2s",
+        .codec_dai_name = "tlv320aic23-hifi",
+        .codec_name     = "tlv320aic23-codec.0-001a",
+        .platform_name  =  "ep93xx-pcm-audio",
+        .init           = snappercl15_tlv320aic23_init,
+        .ops            = &snappercl15_ops,
+};
+
+static struct snd_soc_card snd_soc_snappercl15 = {
+        .name           = "Snapper CL15",
+        .dai_link       = &snappercl15_dai,
+        .num_links      = 1,
+};
+
+static struct platform_device *snappercl15_snd_device;
+
+static int __init snappercl15_init(void)
+{
+        int ret;
+
+        if (!machine_is_snapper_cl15())
+                return -ENODEV;
+
+        ret = ep93xx_i2s_acquire(EP93XX_SYSCON_DEVCFG_I2SONAC97,
+                                 EP93XX_SYSCON_I2SCLKDIV_ORIDE |
+                                 EP93XX_SYSCON_I2SCLKDIV_SPOL);
+        if (ret)
+                return ret;
+
+        snappercl15_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!snappercl15_snd_device)
+                return -ENOMEM;
+        
+        platform_set_drvdata(snappercl15_snd_device, &snd_soc_snappercl15);
+        ret = platform_device_add(snappercl15_snd_device);
+        if (ret)
+                platform_device_put(snappercl15_snd_device);
+
+        return ret;
+}
+
+static void __exit snappercl15_exit(void)
+{
+        platform_device_unregister(snappercl15_snd_device);
+        ep93xx_i2s_release();
+}
+
+module_init(snappercl15_init);
+module_exit(snappercl15_exit);
+
+MODULE_AUTHOR("Ryan Mallon");
+MODULE_DESCRIPTION("ALSA SoC Snapper CL15");
+MODULE_LICENSE("GPL");
+
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
new file mode 100644
index 00000000000..bb699bb55a5
--- /dev/null
+++ b/sound/soc/imx/Kconfig
@@ -0,0 +1,59 @@
+menuconfig SND_IMX_SOC
+        tristate "SoC Audio for Freescale i.MX CPUs"
+        depends on ARCH_MXC
+        select SND_PCM
+        select FIQ
+        select SND_SOC_AC97_BUS
+        help
+          Say Y or M if you want to add support for codecs attached to
+          the i.MX SSI interface.
+
+
+if SND_IMX_SOC
+
+config SND_MXC_SOC_FIQ
+        tristate
+
+config SND_MXC_SOC_MX2
+        tristate
+
+config SND_MXC_SOC_WM1133_EV1
+        tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
+        depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
+        select SND_SOC_WM8350
+        select SND_MXC_SOC_FIQ
+        help
+          Enable support for audio on the i.MX31ADS with the WM1133-EV1
+          PMIC board with WM8835x fitted.
+
+config SND_SOC_MX27VIS_AIC32X4
+        tristate "SoC audio support for Visstrim M10 boards"
+        depends on MACH_IMX27_VISSTRIM_M10
+        select SND_SOC_TVL320AIC32X4
+        select SND_MXC_SOC_MX2
+        help
+          Say Y if you want to add support for SoC audio on Visstrim SM10
+          board with TLV320AIC32X4 codec.
+
+config SND_SOC_PHYCORE_AC97
+        tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
+        depends on MACH_PCM043 || MACH_PCA100
+        select SND_SOC_WM9712
+        select SND_MXC_SOC_FIQ
+        help
+          Say Y if you want to add support for SoC audio on Phytec phyCORE
+          and phyCARD boards in AC97 mode
+
+config SND_SOC_EUKREA_TLV320
+        tristate "Eukrea TLV320"
+        depends on MACH_EUKREA_MBIMX27_BASEBOARD \
+                || MACH_EUKREA_MBIMXSD25_BASEBOARD \
+                || MACH_EUKREA_MBIMXSD35_BASEBOARD \
+                || MACH_EUKREA_MBIMXSD51_BASEBOARD
+        select SND_SOC_TLV320AIC23
+        select SND_MXC_SOC_FIQ
+        help
+          Enable I2S based access to the TLV320AIC23B codec attached
+          to the SSI interface
+
+endif   # SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
new file mode 100644
index 00000000000..d6d609ba7e2
--- /dev/null
+++ b/sound/soc/imx/Makefile
@@ -0,0 +1,19 @@
+# i.MX Platform Support
+snd-soc-imx-objs := imx-ssi.o
+snd-soc-imx-fiq-objs := imx-pcm-fiq.o
+snd-soc-imx-mx2-objs := imx-pcm-dma-mx2.o
+
+obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
+obj-$(CONFIG_SND_MXC_SOC_FIQ) += snd-soc-imx-fiq.o
+obj-$(CONFIG_SND_MXC_SOC_MX2) += snd-soc-imx-mx2.o
+
+# i.MX Machine Support
+snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+snd-soc-phycore-ac97-objs := phycore-ac97.o
+snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+
+obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
new file mode 100644
index 00000000000..75fb4b83548
--- /dev/null
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -0,0 +1,131 @@
+/*
+ * eukrea-tlv320.c  --  SoC audio for eukrea_cpuimxXX in I2S mode
+ *
+ * Copyright 2010 Eric Bénard, Eukréa Electromatique <eric@eukrea.com>
+ *
+ * based on sound/soc/s3c24xx/s3c24xx_simtec_tlv320aic23.c
+ * which is Copyright 2009 Simtec Electronics
+ * and on sound/soc/imx/phycore-ac97.c which is
+ * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * 
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <asm/mach-types.h>
+
+#include "../codecs/tlv320aic23.h"
+#include "imx-ssi.h"
+
+#define CODEC_CLOCK 12000000
+
+static int eukrea_tlv320_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int ret;
+
+        ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret) {
+                pr_err("%s: failed set cpu dai format\n", __func__);
+                return ret;
+        }
+
+        ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret) {
+                pr_err("%s: failed set codec dai format\n", __func__);
+                return ret;
+        }
+
+        ret = snd_soc_dai_set_sysclk(codec_dai, 0,
+                                     CODEC_CLOCK, SND_SOC_CLOCK_OUT);
+        if (ret) {
+                pr_err("%s: failed setting codec sysclk\n", __func__);
+                return ret;
+        }
+        snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0);
+
+        ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
+                                SND_SOC_CLOCK_IN);
+        if (ret) {
+                pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_ops eukrea_tlv320_snd_ops = {
+        .hw_params      = eukrea_tlv320_hw_params,
+};
+
+static struct snd_soc_dai_link eukrea_tlv320_dai = {
+        .name           = "tlv320aic23",
+        .stream_name    = "TLV320AIC23",
+        .codec_dai_name = "tlv320aic23-hifi",
+        .platform_name  = "imx-fiq-pcm-audio.0",
+        .codec_name     = "tlv320aic23-codec.0-001a",
+        .cpu_dai_name   = "imx-ssi.0",
+        .ops            = &eukrea_tlv320_snd_ops,
+};
+
+static struct snd_soc_card eukrea_tlv320 = {
+        .name           = "cpuimx-audio",
+        .dai_link       = &eukrea_tlv320_dai,
+        .num_links      = 1,
+};
+
+static struct platform_device *eukrea_tlv320_snd_device;
+
+static int __init eukrea_tlv320_init(void)
+{
+        int ret;
+
+        if (!machine_is_eukrea_cpuimx27() && !machine_is_eukrea_cpuimx25sd()
+                && !machine_is_eukrea_cpuimx35sd()
+                && !machine_is_eukrea_cpuimx51sd())
+                /* return happy. We might run on a totally different machine */
+                return 0;
+
+        eukrea_tlv320_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!eukrea_tlv320_snd_device)
+                return -ENOMEM;
+
+        platform_set_drvdata(eukrea_tlv320_snd_device, &eukrea_tlv320);
+        ret = platform_device_add(eukrea_tlv320_snd_device);
+
+        if (ret) {
+                printk(KERN_ERR "ASoC: Platform device allocation failed\n");
+                platform_device_put(eukrea_tlv320_snd_device);
+        }
+
+        return ret;
+}
+
+static void __exit eukrea_tlv320_exit(void)
+{
+        platform_device_unregister(eukrea_tlv320_snd_device);
+}
+
+module_init(eukrea_tlv320_init);
+module_exit(eukrea_tlv320_exit);
+
+MODULE_AUTHOR("Eric Bénard <eric@eukrea.com>");
+MODULE_DESCRIPTION("CPUIMX ALSA SoC driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/imx/imx-pcm-dma-mx2.c
new file mode 100644
index 00000000000..43fdc24f7e8
--- /dev/null
+++ b/sound/soc/imx/imx-pcm-dma-mx2.c
@@ -0,0 +1,341 @@
+/*
+ * imx-pcm-dma-mx2.c  --  ALSA Soc Audio Layer
+ *
+ * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This code is based on code copyrighted by Freescale,
+ * Liam Girdwood, Javier Martin and probably others.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dmaengine.h>
+
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/dma.h>
+
+#include "imx-ssi.h"
+
+struct imx_pcm_runtime_data {
+        int period_bytes;
+        int periods;
+        int dma;
+        unsigned long offset;
+        unsigned long size;
+        void *buf;
+        int period_time;
+        struct dma_async_tx_descriptor *desc;
+        struct dma_chan *dma_chan;
+        struct imx_dma_data dma_data;
+};
+
+static void audio_dma_irq(void *data)
+{
+        struct snd_pcm_substream *substream = (struct snd_pcm_substream *)data;
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        iprtd->offset += iprtd->period_bytes;
+        iprtd->offset %= iprtd->period_bytes * iprtd->periods;
+
+        snd_pcm_period_elapsed(substream);
+}
+
+static bool filter(struct dma_chan *chan, void *param)
+{
+        struct imx_pcm_runtime_data *iprtd = param;
+
+        if (!imx_dma_is_general_purpose(chan))
+                return false;
+
+        chan->private = &iprtd->dma_data;
+
+        return true;
+}
+
+static int imx_ssi_dma_alloc(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct imx_pcm_dma_params *dma_params;
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+        struct dma_slave_config slave_config;
+        dma_cap_mask_t mask;
+        enum dma_slave_buswidth buswidth;
+        int ret;
+
+        dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+
+        iprtd->dma_data.peripheral_type = IMX_DMATYPE_SSI;
+        iprtd->dma_data.priority = DMA_PRIO_HIGH;
+        iprtd->dma_data.dma_request = dma_params->dma;
+
+        /* Try to grab a DMA channel */
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
+        iprtd->dma_chan = dma_request_channel(mask, filter, iprtd);
+        if (!iprtd->dma_chan)
+                return -EINVAL;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+        case SNDRV_PCM_FORMAT_S24_LE:
+                buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
+                break;
+        default:
+                return 0;
+        }
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                slave_config.direction = DMA_TO_DEVICE;
+                slave_config.dst_addr = dma_params->dma_addr;
+                slave_config.dst_addr_width = buswidth;
+                slave_config.dst_maxburst = dma_params->burstsize;
+        } else {
+                slave_config.direction = DMA_FROM_DEVICE;
+                slave_config.src_addr = dma_params->dma_addr;
+                slave_config.src_addr_width = buswidth;
+                slave_config.src_maxburst = dma_params->burstsize;
+        }
+
+        ret = dmaengine_slave_config(iprtd->dma_chan, &slave_config);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int snd_imx_pcm_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+        unsigned long dma_addr;
+        struct dma_chan *chan;
+        struct imx_pcm_dma_params *dma_params;
+        int ret;
+
+        dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+        ret = imx_ssi_dma_alloc(substream, params);
+        if (ret)
+                return ret;
+        chan = iprtd->dma_chan;
+
+        iprtd->size = params_buffer_bytes(params);
+        iprtd->periods = params_periods(params);
+        iprtd->period_bytes = params_period_bytes(params);
+        iprtd->offset = 0;
+        iprtd->period_time = HZ / (params_rate(params) /
+                        params_period_size(params));
+
+        snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+
+        dma_addr = runtime->dma_addr;
+
+        iprtd->buf = (unsigned int *)substream->dma_buffer.area;
+
+        iprtd->desc = chan->device->device_prep_dma_cyclic(chan, dma_addr,
+                        iprtd->period_bytes * iprtd->periods,
+                        iprtd->period_bytes,
+                        substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
+                        DMA_TO_DEVICE : DMA_FROM_DEVICE);
+        if (!iprtd->desc) {
+                dev_err(&chan->dev->device, "cannot prepare slave dma\n");
+                return -EINVAL;
+        }
+
+        iprtd->desc->callback = audio_dma_irq;
+        iprtd->desc->callback_param = substream;
+
+        return 0;
+}
+
+static int snd_imx_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        if (iprtd->dma_chan) {
+                dma_release_channel(iprtd->dma_chan);
+                iprtd->dma_chan = NULL;
+        }
+
+        return 0;
+}
+
+static int snd_imx_pcm_prepare(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct imx_pcm_dma_params *dma_params;
+
+        dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+
+        return 0;
+}
+
+static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        switch (cmd) {
+        case SNDRV_PCM_TRIGGER_START:
+        case SNDRV_PCM_TRIGGER_RESUME:
+        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+                dmaengine_submit(iprtd->desc);
+
+                break;
+
+        case SNDRV_PCM_TRIGGER_STOP:
+        case SNDRV_PCM_TRIGGER_SUSPEND:
+        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+                dmaengine_terminate_all(iprtd->dma_chan);
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static snd_pcm_uframes_t snd_imx_pcm_pointer(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        pr_debug("%s: %ld %ld\n", __func__, iprtd->offset,
+                        bytes_to_frames(substream->runtime, iprtd->offset));
+
+        return bytes_to_frames(substream->runtime, iprtd->offset);
+}
+
+static struct snd_pcm_hardware snd_imx_hardware = {
+        .info = SNDRV_PCM_INFO_INTERLEAVED |
+                SNDRV_PCM_INFO_BLOCK_TRANSFER |
+                SNDRV_PCM_INFO_MMAP |
+                SNDRV_PCM_INFO_MMAP_VALID |
+                SNDRV_PCM_INFO_PAUSE |
+                SNDRV_PCM_INFO_RESUME,
+        .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        .rate_min = 8000,
+        .channels_min = 2,
+        .channels_max = 2,
+        .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
+        .period_bytes_min = 128,
+        .period_bytes_max = 65535, /* Limited by SDMA engine */
+        .periods_min = 2,
+        .periods_max = 255,
+        .fifo_size = 0,
+};
+
+static int snd_imx_open(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd;
+        int ret;
+
+        iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
+        if (iprtd == NULL)
+                return -ENOMEM;
+        runtime->private_data = iprtd;
+
+        ret = snd_pcm_hw_constraint_integer(substream->runtime,
+                        SNDRV_PCM_HW_PARAM_PERIODS);
+        if (ret < 0) {
+                kfree(iprtd);
+                return ret;
+        }
+
+        snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
+
+        return 0;
+}
+
+static int snd_imx_close(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        kfree(iprtd);
+
+        return 0;
+}
+
+static struct snd_pcm_ops imx_pcm_ops = {
+        .open           = snd_imx_open,
+        .close          = snd_imx_close,
+        .ioctl          = snd_pcm_lib_ioctl,
+        .hw_params      = snd_imx_pcm_hw_params,
+        .hw_free        = snd_imx_pcm_hw_free,
+        .prepare        = snd_imx_pcm_prepare,
+        .trigger        = snd_imx_pcm_trigger,
+        .pointer        = snd_imx_pcm_pointer,
+        .mmap           = snd_imx_pcm_mmap,
+};
+
+static struct snd_soc_platform_driver imx_soc_platform_mx2 = {
+        .ops            = &imx_pcm_ops,
+        .pcm_new        = imx_pcm_new,
+        .pcm_free       = imx_pcm_free,
+};
+
+static int __devinit imx_soc_platform_probe(struct platform_device *pdev)
+{
+        struct imx_ssi *ssi = platform_get_drvdata(pdev);
+
+        ssi->dma_params_tx.burstsize = 6;
+        ssi->dma_params_rx.burstsize = 4;
+
+        return snd_soc_register_platform(&pdev->dev, &imx_soc_platform_mx2);
+}
+
+static int __devexit imx_soc_platform_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_platform(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver imx_pcm_driver = {
+        .driver = {
+                        .name = "imx-pcm-audio",
+                        .owner = THIS_MODULE,
+        },
+        .probe = imx_soc_platform_probe,
+        .remove = __devexit_p(imx_soc_platform_remove),
+};
+
+static int __init snd_imx_pcm_init(void)
+{
+        return platform_driver_register(&imx_pcm_driver);
+}
+module_init(snd_imx_pcm_init);
+
+static void __exit snd_imx_pcm_exit(void)
+{
+        platform_driver_unregister(&imx_pcm_driver);
+}
+module_exit(snd_imx_pcm_exit);
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:imx-pcm-audio");
diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/imx/imx-pcm-fiq.c
new file mode 100644
index 00000000000..7945625e0e0
--- /dev/null
+++ b/sound/soc/imx/imx-pcm-fiq.c
@@ -0,0 +1,346 @@
+/*
+ * imx-pcm-fiq.c  --  ALSA Soc Audio Layer
+ *
+ * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This code is based on code copyrighted by Freescale,
+ * Liam Girdwood, Javier Martin and probably others.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <asm/fiq.h>
+
+#include <mach/ssi.h>
+
+#include "imx-ssi.h"
+
+struct imx_pcm_runtime_data {
+        int period;
+        int periods;
+        unsigned long offset;
+        unsigned long last_offset;
+        unsigned long size;
+        struct hrtimer hrt;
+        int poll_time_ns;
+        struct snd_pcm_substream *substream;
+        atomic_t running;
+};
+
+static enum hrtimer_restart snd_hrtimer_callback(struct hrtimer *hrt)
+{
+        struct imx_pcm_runtime_data *iprtd =
+                container_of(hrt, struct imx_pcm_runtime_data, hrt);
+        struct snd_pcm_substream *substream = iprtd->substream;
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct pt_regs regs;
+        unsigned long delta;
+
+        if (!atomic_read(&iprtd->running))
+                return HRTIMER_NORESTART;
+
+        get_fiq_regs(&regs);
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                iprtd->offset = regs.ARM_r8 & 0xffff;
+        else
+                iprtd->offset = regs.ARM_r9 & 0xffff;
+
+        /* How much data have we transferred since the last period report? */
+        if (iprtd->offset >= iprtd->last_offset)
+                delta = iprtd->offset - iprtd->last_offset;
+        else
+                delta = runtime->buffer_size + iprtd->offset
+                        - iprtd->last_offset;
+
+        /* If we've transferred at least a period then report it and
+         * reset our poll time */
+        if (delta >= iprtd->period) {
+                snd_pcm_period_elapsed(substream);
+                iprtd->last_offset = iprtd->offset;
+        }
+
+        hrtimer_forward_now(hrt, ns_to_ktime(iprtd->poll_time_ns));
+
+        return HRTIMER_RESTART;
+}
+
+static struct fiq_handler fh = {
+        .name           = DRV_NAME,
+};
+
+static int snd_imx_pcm_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        iprtd->size = params_buffer_bytes(params);
+        iprtd->periods = params_periods(params);
+        iprtd->period = params_period_bytes(params) ;
+        iprtd->offset = 0;
+        iprtd->last_offset = 0;
+        iprtd->poll_time_ns = 1000000000 / params_rate(params) *
+                                params_period_size(params);
+        snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+
+        return 0;
+}
+
+static int snd_imx_pcm_prepare(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+        struct pt_regs regs;
+
+        get_fiq_regs(&regs);
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                regs.ARM_r8 = (iprtd->period * iprtd->periods - 1) << 16;
+        else
+                regs.ARM_r9 = (iprtd->period * iprtd->periods - 1) << 16;
+
+        set_fiq_regs(&regs);
+
+        return 0;
+}
+
+static int fiq_enable;
+static int imx_pcm_fiq;
+
+static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        switch (cmd) {
+        case SNDRV_PCM_TRIGGER_START:
+        case SNDRV_PCM_TRIGGER_RESUME:
+        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+                atomic_set(&iprtd->running, 1);
+                hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns),
+                      HRTIMER_MODE_REL);
+                if (++fiq_enable == 1)
+                        enable_fiq(imx_pcm_fiq);
+
+                break;
+
+        case SNDRV_PCM_TRIGGER_STOP:
+        case SNDRV_PCM_TRIGGER_SUSPEND:
+        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+                atomic_set(&iprtd->running, 0);
+
+                if (--fiq_enable == 0)
+                        disable_fiq(imx_pcm_fiq);
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static snd_pcm_uframes_t snd_imx_pcm_pointer(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        return bytes_to_frames(substream->runtime, iprtd->offset);
+}
+
+static struct snd_pcm_hardware snd_imx_hardware = {
+        .info = SNDRV_PCM_INFO_INTERLEAVED |
+                SNDRV_PCM_INFO_BLOCK_TRANSFER |
+                SNDRV_PCM_INFO_MMAP |
+                SNDRV_PCM_INFO_MMAP_VALID |
+                SNDRV_PCM_INFO_PAUSE |
+                SNDRV_PCM_INFO_RESUME,
+        .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        .rate_min = 8000,
+        .channels_min = 2,
+        .channels_max = 2,
+        .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
+        .period_bytes_min = 128,
+        .period_bytes_max = 16 * 1024,
+        .periods_min = 4,
+        .periods_max = 255,
+        .fifo_size = 0,
+};
+
+static int snd_imx_open(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd;
+        int ret;
+
+        iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
+        if (iprtd == NULL)
+                return -ENOMEM;
+        runtime->private_data = iprtd;
+
+        iprtd->substream = substream;
+
+        atomic_set(&iprtd->running, 0);
+        hrtimer_init(&iprtd->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+        iprtd->hrt.function = snd_hrtimer_callback;
+
+        ret = snd_pcm_hw_constraint_integer(substream->runtime,
+                        SNDRV_PCM_HW_PARAM_PERIODS);
+        if (ret < 0) {
+                kfree(iprtd);
+                return ret;
+        }
+
+        snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
+        return 0;
+}
+
+static int snd_imx_close(struct snd_pcm_substream *substream)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        struct imx_pcm_runtime_data *iprtd = runtime->private_data;
+
+        hrtimer_cancel(&iprtd->hrt);
+
+        kfree(iprtd);
+
+        return 0;
+}
+
+static struct snd_pcm_ops imx_pcm_ops = {
+        .open           = snd_imx_open,
+        .close          = snd_imx_close,
+        .ioctl          = snd_pcm_lib_ioctl,
+        .hw_params      = snd_imx_pcm_hw_params,
+        .prepare        = snd_imx_pcm_prepare,
+        .trigger        = snd_imx_pcm_trigger,
+        .pointer        = snd_imx_pcm_pointer,
+        .mmap           = snd_imx_pcm_mmap,
+};
+
+static int ssi_irq = 0;
+
+static int imx_pcm_fiq_new(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_dai *dai = rtd->cpu_dai;
+        struct snd_pcm *pcm = rtd->pcm;
+        int ret;
+
+        ret = imx_pcm_new(rtd);
+        if (ret)
+                return ret;
+
+        if (dai->driver->playback.channels_min) {
+                struct snd_pcm_substream *substream =
+                        pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
+                struct snd_dma_buffer *buf = &substream->dma_buffer;
+
+                imx_ssi_fiq_tx_buffer = (unsigned long)buf->area;
+        }
+
+        if (dai->driver->capture.channels_min) {
+                struct snd_pcm_substream *substream =
+                        pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
+                struct snd_dma_buffer *buf = &substream->dma_buffer;
+
+                imx_ssi_fiq_rx_buffer = (unsigned long)buf->area;
+        }
+
+        set_fiq_handler(&imx_ssi_fiq_start,
+                &imx_ssi_fiq_end - &imx_ssi_fiq_start);
+
+        return 0;
+}
+
+static void imx_pcm_fiq_free(struct snd_pcm *pcm)
+{
+        mxc_set_irq_fiq(ssi_irq, 0);
+        release_fiq(&fh);
+        imx_pcm_free(pcm);
+}
+
+static struct snd_soc_platform_driver imx_soc_platform_fiq = {
+        .ops            = &imx_pcm_ops,
+        .pcm_new        = imx_pcm_fiq_new,
+        .pcm_free       = imx_pcm_fiq_free,
+};
+
+static int __devinit imx_soc_platform_probe(struct platform_device *pdev)
+{
+        struct imx_ssi *ssi = platform_get_drvdata(pdev);
+        int ret;
+
+        ret = claim_fiq(&fh);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to claim fiq: %d", ret);
+                return ret;
+        }
+
+        mxc_set_irq_fiq(ssi->irq, 1);
+        ssi_irq = ssi->irq;
+
+        imx_pcm_fiq = ssi->irq;
+
+        imx_ssi_fiq_base = (unsigned long)ssi->base;
+
+        ssi->dma_params_tx.burstsize = 4;
+        ssi->dma_params_rx.burstsize = 6;
+
+        ret = snd_soc_register_platform(&pdev->dev, &imx_soc_platform_fiq);
+        if (ret)
+                goto failed_register;
+
+        return 0;
+
+failed_register:
+        mxc_set_irq_fiq(ssi_irq, 0);
+        release_fiq(&fh);
+
+        return ret;
+}
+
+static int __devexit imx_soc_platform_remove(struct platform_device *pdev)
+{
+        snd_soc_unregister_platform(&pdev->dev);
+        return 0;
+}
+
+static struct platform_driver imx_pcm_driver = {
+        .driver = {
+                        .name = "imx-fiq-pcm-audio",
+                        .owner = THIS_MODULE,
+        },
+
+        .probe = imx_soc_platform_probe,
+        .remove = __devexit_p(imx_soc_platform_remove),
+};
+
+static int __init snd_imx_pcm_init(void)
+{
+        return platform_driver_register(&imx_pcm_driver);
+}
+module_init(snd_imx_pcm_init);
+
+static void __exit snd_imx_pcm_exit(void)
+{
+        platform_driver_unregister(&imx_pcm_driver);
+}
+module_exit(snd_imx_pcm_exit);
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c
new file mode 100644
index 00000000000..10a8e278375
--- /dev/null
+++ b/sound/soc/imx/imx-ssi.c
@@ -0,0 +1,778 @@
+/*
+ * imx-ssi.c  --  ALSA Soc Audio Layer
+ *
+ * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This code is based on code copyrighted by Freescale,
+ * Liam Girdwood, Javier Martin and probably others.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *
+ * The i.MX SSI core has some nasty limitations in AC97 mode. While most
+ * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
+ * one FIFO which combines all valid receive slots. We cannot even select
+ * which slots we want to receive. The WM9712 with which this driver
+ * was developed with always sends GPIO status data in slot 12 which
+ * we receive in our (PCM-) data stream. The only chance we have is to
+ * manually skip this data in the FIQ handler. With sampling rates different
+ * from 48000Hz not every frame has valid receive data, so the ratio
+ * between pcm data and GPIO status data changes. Our FIQ handler is not
+ * able to handle this, hence this driver only works with 48000Hz sampling
+ * rate.
+ * Reading and writing AC97 registers is another challenge. The core
+ * provides us status bits when the read register is updated with *another*
+ * value. When we read the same register two times (and the register still
+ * contains the same value) these status bits are not set. We work
+ * around this by not polling these bits but only wait a fixed delay.
+ * 
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/ssi.h>
+#include <mach/hardware.h>
+
+#include "imx-ssi.h"
+
+#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
+
+/*
+ * SSI Network Mode or TDM slots configuration.
+ * Should only be called when port is inactive (i.e. SSIEN = 0).
+ */
+static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
+        unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
+{
+        struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
+        u32 sccr;
+
+        sccr = readl(ssi->base + SSI_STCCR);
+        sccr &= ~SSI_STCCR_DC_MASK;
+        sccr |= SSI_STCCR_DC(slots - 1);
+        writel(sccr, ssi->base + SSI_STCCR);
+
+        sccr = readl(ssi->base + SSI_SRCCR);
+        sccr &= ~SSI_STCCR_DC_MASK;
+        sccr |= SSI_STCCR_DC(slots - 1);
+        writel(sccr, ssi->base + SSI_SRCCR);
+
+        writel(tx_mask, ssi->base + SSI_STMSK);
+        writel(rx_mask, ssi->base + SSI_SRMSK);
+
+        return 0;
+}
+
+/*
+ * SSI DAI format configuration.
+ * Should only be called when port is inactive (i.e. SSIEN = 0).
+ */
+static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+{
+        struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
+        u32 strcr = 0, scr;
+
+        scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
+
+        /* DAI mode */
+        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+        case SND_SOC_DAIFMT_I2S:
+                /* data on rising edge of bclk, frame low 1clk before data */
+                strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
+                scr |= SSI_SCR_NET;
+                if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
+                        scr &= ~SSI_I2S_MODE_MASK;
+                        scr |= SSI_SCR_I2S_MODE_SLAVE;
+                }
+                break;
+        case SND_SOC_DAIFMT_LEFT_J:
+                /* data on rising edge of bclk, frame high with data */
+                strcr |= SSI_STCR_TXBIT0;
+                break;
+        case SND_SOC_DAIFMT_DSP_B:
+                /* data on rising edge of bclk, frame high with data */
+                strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0;
+                break;
+        case SND_SOC_DAIFMT_DSP_A:
+                /* data on rising edge of bclk, frame high 1clk before data */
+                strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
+                break;
+        }
+
+        /* DAI clock inversion */
+        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+        case SND_SOC_DAIFMT_IB_IF:
+                strcr |= SSI_STCR_TFSI;
+                strcr &= ~SSI_STCR_TSCKP;
+                break;
+        case SND_SOC_DAIFMT_IB_NF:
+                strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
+                break;
+        case SND_SOC_DAIFMT_NB_IF:
+                strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
+                break;
+        case SND_SOC_DAIFMT_NB_NF:
+                strcr &= ~SSI_STCR_TFSI;
+                strcr |= SSI_STCR_TSCKP;
+                break;
+        }
+
+        /* DAI clock master masks */
+        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                break;
+        default:
+                /* Master mode not implemented, needs handling of clocks. */
+                return -EINVAL;
+        }
+
+        strcr |= SSI_STCR_TFEN0;
+
+        if (ssi->flags & IMX_SSI_NET)
+                scr |= SSI_SCR_NET;
+        if (ssi->flags & IMX_SSI_SYN)
+                scr |= SSI_SCR_SYN;
+
+        writel(strcr, ssi->base + SSI_STCR);
+        writel(strcr, ssi->base + SSI_SRCR);
+        writel(scr, ssi->base + SSI_SCR);
+
+        return 0;
+}
+
+/*
+ * SSI system clock configuration.
+ * Should only be called when port is inactive (i.e. SSIEN = 0).
+ */
+static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
+                                  int clk_id, unsigned int freq, int dir)
+{
+        struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
+        u32 scr;
+
+        scr = readl(ssi->base + SSI_SCR);
+
+        switch (clk_id) {
+        case IMX_SSP_SYS_CLK:
+                if (dir == SND_SOC_CLOCK_OUT)
+                        scr |= SSI_SCR_SYS_CLK_EN;
+                else
+                        scr &= ~SSI_SCR_SYS_CLK_EN;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel(scr, ssi->base + SSI_SCR);
+
+        return 0;
+}
+
+/*
+ * SSI Clock dividers
+ * Should only be called when port is inactive (i.e. SSIEN = 0).
+ */
+static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
+                                  int div_id, int div)
+{
+        struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
+        u32 stccr, srccr;
+
+        stccr = readl(ssi->base + SSI_STCCR);
+        srccr = readl(ssi->base + SSI_SRCCR);
+
+        switch (div_id) {
+        case IMX_SSI_TX_DIV_2:
+                stccr &= ~SSI_STCCR_DIV2;
+                stccr |= div;
+                break;
+        case IMX_SSI_TX_DIV_PSR:
+                stccr &= ~SSI_STCCR_PSR;
+                stccr |= div;
+                break;
+        case IMX_SSI_TX_DIV_PM:
+                stccr &= ~0xff;
+                stccr |= SSI_STCCR_PM(div);
+                break;
+        case IMX_SSI_RX_DIV_2:
+                stccr &= ~SSI_STCCR_DIV2;
+                stccr |= div;
+                break;
+        case IMX_SSI_RX_DIV_PSR:
+                stccr &= ~SSI_STCCR_PSR;
+                stccr |= div;
+                break;
+        case IMX_SSI_RX_DIV_PM:
+                stccr &= ~0xff;
+                stccr |= SSI_STCCR_PM(div);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel(stccr, ssi->base + SSI_STCCR);
+        writel(srccr, ssi->base + SSI_SRCCR);
+
+        return 0;
+}
+
+/*
+ * Should only be called when port is inactive (i.e. SSIEN = 0),
+ * although can be called multiple times by upper layers.
+ */
+static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
+                             struct snd_pcm_hw_params *params,
+                             struct snd_soc_dai *cpu_dai)
+{
+        struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
+        struct imx_pcm_dma_params *dma_data;
+        u32 reg, sccr;
+
+        /* Tx/Rx config */
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                reg = SSI_STCCR;
+                dma_data = &ssi->dma_params_tx;
+        } else {
+                reg = SSI_SRCCR;
+                dma_data = &ssi->dma_params_rx;
+        }
+
+        if (ssi->flags & IMX_SSI_SYN)
+                reg = SSI_STCCR;
+
+        snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
+
+        sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
+
+        /* DAI data (word) size */
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                sccr |= SSI_SRCCR_WL(16);
+                break;
+        case SNDRV_PCM_FORMAT_S20_3LE:
+                sccr |= SSI_SRCCR_WL(20);
+                break;
+        case SNDRV_PCM_FORMAT_S24_LE:
+                sccr |= SSI_SRCCR_WL(24);
+                break;
+        }
+
+        writel(sccr, ssi->base + reg);
+
+        return 0;
+}
+
+static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
+                struct snd_soc_dai *dai)
+{
+        struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
+        unsigned int sier_bits, sier;
+        unsigned int scr;
+
+        scr = readl(ssi->base + SSI_SCR);
+        sier = readl(ssi->base + SSI_SIER);
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                if (ssi->flags & IMX_SSI_DMA)
+                        sier_bits = SSI_SIER_TDMAE;
+                else
+                        sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
+        } else {
+                if (ssi->flags & IMX_SSI_DMA)
+                        sier_bits = SSI_SIER_RDMAE;
+                else
+                        sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
+        }
+
+        switch (cmd) {
+        case SNDRV_PCM_TRIGGER_START:
+        case SNDRV_PCM_TRIGGER_RESUME:
+        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                        scr |= SSI_SCR_TE;
+                else
+                        scr |= SSI_SCR_RE;
+                sier |= sier_bits;
+
+                if (++ssi->enabled == 1)
+                        scr |= SSI_SCR_SSIEN;
+
+                break;
+
+        case SNDRV_PCM_TRIGGER_STOP:
+        case SNDRV_PCM_TRIGGER_SUSPEND:
+        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                        scr &= ~SSI_SCR_TE;
+                else
+                        scr &= ~SSI_SCR_RE;
+                sier &= ~sier_bits;
+
+                if (--ssi->enabled == 0)
+                        scr &= ~SSI_SCR_SSIEN;
+
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (!(ssi->flags & IMX_SSI_USE_AC97))
+                /* rx/tx are always enabled to access ac97 registers */
+                writel(scr, ssi->base + SSI_SCR);
+
+        writel(sier, ssi->base + SSI_SIER);
+
+        return 0;
+}
+
+static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
+        .hw_params      = imx_ssi_hw_params,
+        .set_fmt        = imx_ssi_set_dai_fmt,
+        .set_clkdiv     = imx_ssi_set_dai_clkdiv,
+        .set_sysclk     = imx_ssi_set_dai_sysclk,
+        .set_tdm_slot   = imx_ssi_set_dai_tdm_slot,
+        .trigger        = imx_ssi_trigger,
+};
+
+int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
+                struct vm_area_struct *vma)
+{
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        int ret;
+
+        ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
+                        runtime->dma_addr, runtime->dma_bytes);
+
+        pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
+                        runtime->dma_area,
+                        runtime->dma_addr,
+                        runtime->dma_bytes);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(snd_imx_pcm_mmap);
+
+static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+        struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+        struct snd_dma_buffer *buf = &substream->dma_buffer;
+        size_t size = IMX_SSI_DMABUF_SIZE;
+
+        buf->dev.type = SNDRV_DMA_TYPE_DEV;
+        buf->dev.dev = pcm->card->dev;
+        buf->private_data = NULL;
+        buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+                                           &buf->addr, GFP_KERNEL);
+        if (!buf->area)
+                return -ENOMEM;
+        buf->bytes = size;
+
+        return 0;
+}
+
+static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
+
+int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_card *card = rtd->card->snd_card;
+        struct snd_soc_dai *dai = rtd->cpu_dai;
+        struct snd_pcm *pcm = rtd->pcm;
+        int ret = 0;
+
+        if (!card->dev->dma_mask)
+                card->dev->dma_mask = &imx_pcm_dmamask;
+        if (!card->dev->coherent_dma_mask)
+                card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+        if (dai->driver->playback.channels_min) {
+                ret = imx_pcm_preallocate_dma_buffer(pcm,
+                        SNDRV_PCM_STREAM_PLAYBACK);
+                if (ret)
+                        goto out;
+        }
+
+        if (dai->driver->capture.channels_min) {
+                ret = imx_pcm_preallocate_dma_buffer(pcm,
+                        SNDRV_PCM_STREAM_CAPTURE);
+                if (ret)
+                        goto out;
+        }
+
+out:
+        return ret;
+}
+EXPORT_SYMBOL_GPL(imx_pcm_new);
+
+void imx_pcm_free(struct snd_pcm *pcm)
+{
+        struct snd_pcm_substream *substream;
+        struct snd_dma_buffer *buf;
+        int stream;
+
+        for (stream = 0; stream < 2; stream++) {
+                substream = pcm->streams[stream].substream;
+                if (!substream)
+                        continue;
+
+                buf = &substream->dma_buffer;
+                if (!buf->area)
+                        continue;
+
+                dma_free_writecombine(pcm->card->dev, buf->bytes,
+                                      buf->area, buf->addr);
+                buf->area = NULL;
+        }
+}
+EXPORT_SYMBOL_GPL(imx_pcm_free);
+
+static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
+{
+        struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
+        uint32_t val;
+
+        snd_soc_dai_set_drvdata(dai, ssi);
+
+        val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
+                SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
+        writel(val, ssi->base + SSI_SFCSR);
+
+        return 0;
+}
+
+static struct snd_soc_dai_driver imx_ssi_dai = {
+        .probe = imx_ssi_dai_probe,
+        .playback = {
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_96000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .capture = {
+                .channels_min = 1,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_8000_96000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .ops = &imx_ssi_pcm_dai_ops,
+};
+
+static struct snd_soc_dai_driver imx_ac97_dai = {
+        .probe = imx_ssi_dai_probe,
+        .ac97_control = 1,
+        .playback = {
+                .stream_name = "AC97 Playback",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_48000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .capture = {
+                .stream_name = "AC97 Capture",
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_48000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .ops = &imx_ssi_pcm_dai_ops,
+};
+
+static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
+{
+        void __iomem *base = imx_ssi->base;
+
+        writel(0x0, base + SSI_SCR);
+        writel(0x0, base + SSI_STCR);
+        writel(0x0, base + SSI_SRCR);
+
+        writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
+
+        writel(SSI_SFCSR_RFWM0(8) |
+                SSI_SFCSR_TFWM0(8) |
+                SSI_SFCSR_RFWM1(8) |
+                SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
+
+        writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
+        writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
+
+        writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
+        writel(SSI_SOR_WAIT(3), base + SSI_SOR);
+
+        writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
+                        SSI_SCR_TE | SSI_SCR_RE,
+                        base + SSI_SCR);
+
+        writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
+        writel(0xff, base + SSI_SACCDIS);
+        writel(0x300, base + SSI_SACCEN);
+}
+
+static struct imx_ssi *ac97_ssi;
+
+static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+                unsigned short val)
+{
+        struct imx_ssi *imx_ssi = ac97_ssi;
+        void __iomem *base = imx_ssi->base;
+        unsigned int lreg;
+        unsigned int lval;
+
+        if (reg > 0x7f)
+                return;
+
+        pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
+
+        lreg = reg <<  12;
+        writel(lreg, base + SSI_SACADD);
+
+        lval = val << 4;
+        writel(lval , base + SSI_SACDAT);
+
+        writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
+        udelay(100);
+}
+
+static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
+                unsigned short reg)
+{
+        struct imx_ssi *imx_ssi = ac97_ssi;
+        void __iomem *base = imx_ssi->base;
+
+        unsigned short val = -1;
+        unsigned int lreg;
+
+        lreg = (reg & 0x7f) <<  12 ;
+        writel(lreg, base + SSI_SACADD);
+        writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
+
+        udelay(100);
+
+        val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
+
+        pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
+
+        return val;
+}
+
+static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
+{
+        struct imx_ssi *imx_ssi = ac97_ssi;
+
+        if (imx_ssi->ac97_reset)
+                imx_ssi->ac97_reset(ac97);
+}
+
+static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+        struct imx_ssi *imx_ssi = ac97_ssi;
+
+        if (imx_ssi->ac97_warm_reset)
+                imx_ssi->ac97_warm_reset(ac97);
+}
+
+struct snd_ac97_bus_ops soc_ac97_ops = {
+        .read           = imx_ssi_ac97_read,
+        .write          = imx_ssi_ac97_write,
+        .reset          = imx_ssi_ac97_reset,
+        .warm_reset     = imx_ssi_ac97_warm_reset
+};
+EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
+static int imx_ssi_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        struct imx_ssi *ssi;
+        struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
+        int ret = 0;
+        struct snd_soc_dai_driver *dai;
+
+        ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
+        if (!ssi)
+                return -ENOMEM;
+        dev_set_drvdata(&pdev->dev, ssi);
+
+        if (pdata) {
+                ssi->ac97_reset = pdata->ac97_reset;
+                ssi->ac97_warm_reset = pdata->ac97_warm_reset;
+                ssi->flags = pdata->flags;
+        }
+
+        ssi->irq = platform_get_irq(pdev, 0);
+
+        ssi->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(ssi->clk)) {
+                ret = PTR_ERR(ssi->clk);
+                dev_err(&pdev->dev, "Cannot get the clock: %d\n",
+                        ret);
+                goto failed_clk;
+        }
+        clk_enable(ssi->clk);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                ret = -ENODEV;
+                goto failed_get_resource;
+        }
+
+        if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
+                dev_err(&pdev->dev, "request_mem_region failed\n");
+                ret = -EBUSY;
+                goto failed_get_resource;
+        }
+
+        ssi->base = ioremap(res->start, resource_size(res));
+        if (!ssi->base) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENODEV;
+                goto failed_ioremap;
+        }
+
+        if (ssi->flags & IMX_SSI_USE_AC97) {
+                if (ac97_ssi) {
+                        ret = -EBUSY;
+                        goto failed_ac97;
+                }
+                ac97_ssi = ssi;
+                setup_channel_to_ac97(ssi);
+                dai = &imx_ac97_dai;
+        } else
+                dai = &imx_ssi_dai;
+
+        writel(0x0, ssi->base + SSI_SIER);
+
+        ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
+        ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
+
+        ssi->dma_params_tx.burstsize = 4;
+        ssi->dma_params_rx.burstsize = 4;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
+        if (res)
+                ssi->dma_params_tx.dma = res->start;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
+        if (res)
+                ssi->dma_params_rx.dma = res->start;
+
+        platform_set_drvdata(pdev, ssi);
+
+        ret = snd_soc_register_dai(&pdev->dev, dai);
+        if (ret) {
+                dev_err(&pdev->dev, "register DAI failed\n");
+                goto failed_register;
+        }
+
+        ssi->soc_platform_pdev_fiq = platform_device_alloc("imx-fiq-pcm-audio", pdev->id);
+        if (!ssi->soc_platform_pdev_fiq) {
+                ret = -ENOMEM;
+                goto failed_pdev_fiq_alloc;
+        }
+
+        platform_set_drvdata(ssi->soc_platform_pdev_fiq, ssi);
+        ret = platform_device_add(ssi->soc_platform_pdev_fiq);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to add platform device\n");
+                goto failed_pdev_fiq_add;
+        }
+
+        ssi->soc_platform_pdev = platform_device_alloc("imx-pcm-audio", pdev->id);
+        if (!ssi->soc_platform_pdev) {
+                ret = -ENOMEM;
+                goto failed_pdev_alloc;
+        }
+
+        platform_set_drvdata(ssi->soc_platform_pdev, ssi);
+        ret = platform_device_add(ssi->soc_platform_pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to add platform device\n");
+                goto failed_pdev_add;
+        }
+
+        return 0;
+
+failed_pdev_add:
+        platform_device_put(ssi->soc_platform_pdev);
+failed_pdev_alloc:
+        platform_device_del(ssi->soc_platform_pdev_fiq);
+failed_pdev_fiq_add:
+        platform_device_put(ssi->soc_platform_pdev_fiq);
+failed_pdev_fiq_alloc:
+        snd_soc_unregister_dai(&pdev->dev);
+failed_register:
+failed_ac97:
+        iounmap(ssi->base);
+failed_ioremap:
+        release_mem_region(res->start, resource_size(res));
+failed_get_resource:
+        clk_disable(ssi->clk);
+        clk_put(ssi->clk);
+failed_clk:
+        kfree(ssi);
+
+        return ret;
+}
+
+static int __devexit imx_ssi_remove(struct platform_device *pdev)
+{
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        struct imx_ssi *ssi = platform_get_drvdata(pdev);
+
+        platform_device_unregister(ssi->soc_platform_pdev);
+        platform_device_unregister(ssi->soc_platform_pdev_fiq);
+
+        snd_soc_unregister_dai(&pdev->dev);
+
+        if (ssi->flags & IMX_SSI_USE_AC97)
+                ac97_ssi = NULL;
+
+        iounmap(ssi->base);
+        release_mem_region(res->start, resource_size(res));
+        clk_disable(ssi->clk);
+        clk_put(ssi->clk);
+        kfree(ssi);
+
+        return 0;
+}
+
+static struct platform_driver imx_ssi_driver = {
+        .probe = imx_ssi_probe,
+        .remove = __devexit_p(imx_ssi_remove),
+
+        .driver = {
+                .name = "imx-ssi",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init imx_ssi_init(void)
+{
+        return platform_driver_register(&imx_ssi_driver);
+}
+
+static void __exit imx_ssi_exit(void)
+{
+        platform_driver_unregister(&imx_ssi_driver);
+}
+
+module_init(imx_ssi_init);
+module_exit(imx_ssi_exit);
+
+/* Module information */
+MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
+MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:imx-ssi");
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h
new file mode 100644
index 00000000000..0a84cec3599
--- /dev/null
+++ b/sound/soc/imx/imx-ssi.h
@@ -0,0 +1,236 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IMX_SSI_H
+#define _IMX_SSI_H
+
+#define SSI_STX0        0x00
+#define SSI_STX1        0x04
+#define SSI_SRX0        0x08
+#define SSI_SRX1        0x0c
+
+#define SSI_SCR         0x10
+#define SSI_SCR_CLK_IST         (1 << 9)
+#define SSI_SCR_CLK_IST_SHIFT   9
+#define SSI_SCR_TCH_EN          (1 << 8)
+#define SSI_SCR_SYS_CLK_EN      (1 << 7)
+#define SSI_SCR_I2S_MODE_NORM   (0 << 5)
+#define SSI_SCR_I2S_MODE_MSTR   (1 << 5)
+#define SSI_SCR_I2S_MODE_SLAVE  (2 << 5)
+#define SSI_I2S_MODE_MASK       (3 << 5)
+#define SSI_SCR_SYN             (1 << 4)
+#define SSI_SCR_NET             (1 << 3)
+#define SSI_SCR_RE              (1 << 2)
+#define SSI_SCR_TE              (1 << 1)
+#define SSI_SCR_SSIEN           (1 << 0)
+
+#define SSI_SISR        0x14
+#define SSI_SISR_MASK           ((1 << 19) - 1)
+#define SSI_SISR_CMDAU          (1 << 18)
+#define SSI_SISR_CMDDU          (1 << 17)
+#define SSI_SISR_RXT            (1 << 16)
+#define SSI_SISR_RDR1           (1 << 15)
+#define SSI_SISR_RDR0           (1 << 14)
+#define SSI_SISR_TDE1           (1 << 13)
+#define SSI_SISR_TDE0           (1 << 12)
+#define SSI_SISR_ROE1           (1 << 11)
+#define SSI_SISR_ROE0           (1 << 10)
+#define SSI_SISR_TUE1           (1 << 9)
+#define SSI_SISR_TUE0           (1 << 8)
+#define SSI_SISR_TFS            (1 << 7)
+#define SSI_SISR_RFS            (1 << 6)
+#define SSI_SISR_TLS            (1 << 5)
+#define SSI_SISR_RLS            (1 << 4)
+#define SSI_SISR_RFF1           (1 << 3)
+#define SSI_SISR_RFF0           (1 << 2)
+#define SSI_SISR_TFE1           (1 << 1)
+#define SSI_SISR_TFE0           (1 << 0)
+
+#define SSI_SIER        0x18
+#define SSI_SIER_RDMAE          (1 << 22)
+#define SSI_SIER_RIE            (1 << 21)
+#define SSI_SIER_TDMAE          (1 << 20)
+#define SSI_SIER_TIE            (1 << 19)
+#define SSI_SIER_CMDAU_EN       (1 << 18)
+#define SSI_SIER_CMDDU_EN       (1 << 17)
+#define SSI_SIER_RXT_EN         (1 << 16)
+#define SSI_SIER_RDR1_EN        (1 << 15)
+#define SSI_SIER_RDR0_EN        (1 << 14)
+#define SSI_SIER_TDE1_EN        (1 << 13)
+#define SSI_SIER_TDE0_EN        (1 << 12)
+#define SSI_SIER_ROE1_EN        (1 << 11)
+#define SSI_SIER_ROE0_EN        (1 << 10)
+#define SSI_SIER_TUE1_EN        (1 << 9)
+#define SSI_SIER_TUE0_EN        (1 << 8)
+#define SSI_SIER_TFS_EN         (1 << 7)
+#define SSI_SIER_RFS_EN         (1 << 6)
+#define SSI_SIER_TLS_EN         (1 << 5)
+#define SSI_SIER_RLS_EN         (1 << 4)
+#define SSI_SIER_RFF1_EN        (1 << 3)
+#define SSI_SIER_RFF0_EN        (1 << 2)
+#define SSI_SIER_TFE1_EN        (1 << 1)
+#define SSI_SIER_TFE0_EN        (1 << 0)
+
+#define SSI_STCR        0x1c
+#define SSI_STCR_TXBIT0         (1 << 9)
+#define SSI_STCR_TFEN1          (1 << 8)
+#define SSI_STCR_TFEN0          (1 << 7)
+#define SSI_FIFO_ENABLE_0_SHIFT 7
+#define SSI_STCR_TFDIR          (1 << 6)
+#define SSI_STCR_TXDIR          (1 << 5)
+#define SSI_STCR_TSHFD          (1 << 4)
+#define SSI_STCR_TSCKP          (1 << 3)
+#define SSI_STCR_TFSI           (1 << 2)
+#define SSI_STCR_TFSL           (1 << 1)
+#define SSI_STCR_TEFS           (1 << 0)
+
+#define SSI_SRCR        0x20
+#define SSI_SRCR_RXBIT0         (1 << 9)
+#define SSI_SRCR_RFEN1          (1 << 8)
+#define SSI_SRCR_RFEN0          (1 << 7)
+#define SSI_FIFO_ENABLE_0_SHIFT 7
+#define SSI_SRCR_RFDIR          (1 << 6)
+#define SSI_SRCR_RXDIR          (1 << 5)
+#define SSI_SRCR_RSHFD          (1 << 4)
+#define SSI_SRCR_RSCKP          (1 << 3)
+#define SSI_SRCR_RFSI           (1 << 2)
+#define SSI_SRCR_RFSL           (1 << 1)
+#define SSI_SRCR_REFS           (1 << 0)
+
+#define SSI_SRCCR               0x28
+#define SSI_SRCCR_DIV2          (1 << 18)
+#define SSI_SRCCR_PSR           (1 << 17)
+#define SSI_SRCCR_WL(x)         ((((x) - 2) >> 1) << 13)
+#define SSI_SRCCR_DC(x)         (((x) & 0x1f) << 8)
+#define SSI_SRCCR_PM(x)         (((x) & 0xff) << 0)
+#define SSI_SRCCR_WL_MASK       (0xf << 13)
+#define SSI_SRCCR_DC_MASK       (0x1f << 8)
+#define SSI_SRCCR_PM_MASK       (0xff << 0)
+
+#define SSI_STCCR               0x24
+#define SSI_STCCR_DIV2          (1 << 18)
+#define SSI_STCCR_PSR           (1 << 17)
+#define SSI_STCCR_WL(x)         ((((x) - 2) >> 1) << 13)
+#define SSI_STCCR_DC(x)         (((x) & 0x1f) << 8)
+#define SSI_STCCR_PM(x)         (((x) & 0xff) << 0)
+#define SSI_STCCR_WL_MASK       (0xf << 13)
+#define SSI_STCCR_DC_MASK       (0x1f << 8)
+#define SSI_STCCR_PM_MASK       (0xff << 0)
+
+#define SSI_SFCSR       0x2c
+#define SSI_SFCSR_RFCNT1(x)     (((x) & 0xf) << 28)
+#define SSI_RX_FIFO_1_COUNT_SHIFT 28
+#define SSI_SFCSR_TFCNT1(x)     (((x) & 0xf) << 24)
+#define SSI_TX_FIFO_1_COUNT_SHIFT 24
+#define SSI_SFCSR_RFWM1(x)      (((x) & 0xf) << 20)
+#define SSI_SFCSR_TFWM1(x)      (((x) & 0xf) << 16)
+#define SSI_SFCSR_RFCNT0(x)     (((x) & 0xf) << 12)
+#define SSI_RX_FIFO_0_COUNT_SHIFT 12
+#define SSI_SFCSR_TFCNT0(x)     (((x) & 0xf) <<  8)
+#define SSI_TX_FIFO_0_COUNT_SHIFT 8
+#define SSI_SFCSR_RFWM0(x)      (((x) & 0xf) <<  4)
+#define SSI_SFCSR_TFWM0(x)      (((x) & 0xf) <<  0)
+#define SSI_SFCSR_RFWM0_MASK    (0xf <<  4)
+#define SSI_SFCSR_TFWM0_MASK    (0xf <<  0)
+
+#define SSI_STR         0x30
+#define SSI_STR_TEST            (1 << 15)
+#define SSI_STR_RCK2TCK         (1 << 14)
+#define SSI_STR_RFS2TFS         (1 << 13)
+#define SSI_STR_RXSTATE(x)      (((x) & 0xf) << 8)
+#define SSI_STR_TXD2RXD         (1 <<  7)
+#define SSI_STR_TCK2RCK         (1 <<  6)
+#define SSI_STR_TFS2RFS         (1 <<  5)
+#define SSI_STR_TXSTATE(x)      (((x) & 0xf) << 0)
+
+#define SSI_SOR         0x34
+#define SSI_SOR_CLKOFF          (1 << 6)
+#define SSI_SOR_RX_CLR          (1 << 5)
+#define SSI_SOR_TX_CLR          (1 << 4)
+#define SSI_SOR_INIT            (1 << 3)
+#define SSI_SOR_WAIT(x)         (((x) & 0x3) << 1)
+#define SSI_SOR_WAIT_MASK       (0x3 << 1)
+#define SSI_SOR_SYNRST          (1 << 0)
+
+#define SSI_SACNT       0x38
+#define SSI_SACNT_FRDIV(x)      (((x) & 0x3f) << 5)
+#define SSI_SACNT_WR            (1 << 4)
+#define SSI_SACNT_RD            (1 << 3)
+#define SSI_SACNT_TIF           (1 << 2)
+#define SSI_SACNT_FV            (1 << 1)
+#define SSI_SACNT_AC97EN        (1 << 0)
+
+#define SSI_SACADD      0x3c
+#define SSI_SACDAT      0x40
+#define SSI_SATAG       0x44
+#define SSI_STMSK       0x48
+#define SSI_SRMSK       0x4c
+#define SSI_SACCST      0x50
+#define SSI_SACCEN      0x54
+#define SSI_SACCDIS     0x58
+
+/* SSI clock sources */
+#define IMX_SSP_SYS_CLK         0
+
+/* SSI audio dividers */
+#define IMX_SSI_TX_DIV_2        0
+#define IMX_SSI_TX_DIV_PSR      1
+#define IMX_SSI_TX_DIV_PM       2
+#define IMX_SSI_RX_DIV_2        3
+#define IMX_SSI_RX_DIV_PSR      4
+#define IMX_SSI_RX_DIV_PM       5
+
+#define DRV_NAME "imx-ssi"
+
+#include <linux/dmaengine.h>
+#include <mach/dma.h>
+
+struct imx_pcm_dma_params {
+        int dma;
+        unsigned long dma_addr;
+        int burstsize;
+};
+
+struct imx_ssi {
+        struct platform_device *ac97_dev;
+
+        struct snd_soc_dai *imx_ac97;
+        struct clk *clk;
+        void __iomem *base;
+        int irq;
+        int fiq_enable;
+        unsigned int offset;
+
+        unsigned int flags;
+
+        void (*ac97_reset) (struct snd_ac97 *ac97);
+        void (*ac97_warm_reset)(struct snd_ac97 *ac97);
+
+        struct imx_pcm_dma_params       dma_params_rx;
+        struct imx_pcm_dma_params       dma_params_tx;
+
+        int enabled;
+
+        struct platform_device *soc_platform_pdev;
+        struct platform_device *soc_platform_pdev_fiq;
+};
+
+struct snd_soc_platform *imx_ssi_fiq_init(struct platform_device *pdev,
+                struct imx_ssi *ssi);
+void imx_ssi_fiq_exit(struct platform_device *pdev, struct imx_ssi *ssi);
+struct snd_soc_platform *imx_ssi_dma_mx2_init(struct platform_device *pdev,
+                struct imx_ssi *ssi);
+
+int snd_imx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma);
+int imx_pcm_new(struct snd_soc_pcm_runtime *rtd);
+void imx_pcm_free(struct snd_pcm *pcm);
+
+/*
+ * Do not change this as the FIQ handler depends on this size
+ */
+#define IMX_SSI_DMABUF_SIZE     (64 * 1024)
+
+#endif /* _IMX_SSI_H */
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/imx/mx27vis-aic32x4.c
new file mode 100644
index 00000000000..054110b91d4
--- /dev/null
+++ b/sound/soc/imx/mx27vis-aic32x4.c
@@ -0,0 +1,137 @@
+/*
+ * mx27vis-aic32x4.c
+ *
+ * Copyright 2011 Vista Silicon S.L.
+ *
+ * Author: Javier Martin <javier.martin@vista-silicon.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asm/mach-types.h>
+#include <mach/audmux.h>
+
+#include "../codecs/tlv320aic32x4.h"
+#include "imx-ssi.h"
+
+static int mx27vis_aic32x4_hw_params(struct snd_pcm_substream *substream,
+                            struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int ret;
+        u32 dai_format;
+
+        dai_format = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_NB_NF |
+                SND_SOC_DAIFMT_CBM_CFM;
+
+        /* set codec DAI configuration */
+        snd_soc_dai_set_fmt(codec_dai, dai_format);
+
+        /* set cpu DAI configuration */
+        snd_soc_dai_set_fmt(cpu_dai, dai_format);
+
+        ret = snd_soc_dai_set_sysclk(codec_dai, 0,
+                                     25000000, SND_SOC_CLOCK_OUT);
+        if (ret) {
+                pr_err("%s: failed setting codec sysclk\n", __func__);
+                return ret;
+        }
+
+        ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
+                                SND_SOC_CLOCK_IN);
+        if (ret) {
+                pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_ops mx27vis_aic32x4_snd_ops = {
+        .hw_params      = mx27vis_aic32x4_hw_params,
+};
+
+static struct snd_soc_dai_link mx27vis_aic32x4_dai = {
+        .name           = "tlv320aic32x4",
+        .stream_name    = "TLV320AIC32X4",
+        .codec_dai_name = "tlv320aic32x4-hifi",
+        .platform_name  = "imx-pcm-audio.0",
+        .codec_name     = "tlv320aic32x4.0-0018",
+        .cpu_dai_name   = "imx-ssi.0",
+        .ops            = &mx27vis_aic32x4_snd_ops,
+};
+
+static struct snd_soc_card mx27vis_aic32x4 = {
+        .name           = "visstrim_m10-audio",
+        .dai_link       = &mx27vis_aic32x4_dai,
+        .num_links      = 1,
+};
+
+static struct platform_device *mx27vis_aic32x4_snd_device;
+
+static int __init mx27vis_aic32x4_init(void)
+{
+        int ret;
+
+        mx27vis_aic32x4_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!mx27vis_aic32x4_snd_device)
+                return -ENOMEM;
+
+        platform_set_drvdata(mx27vis_aic32x4_snd_device, &mx27vis_aic32x4);
+        ret = platform_device_add(mx27vis_aic32x4_snd_device);
+
+        if (ret) {
+                printk(KERN_ERR "ASoC: Platform device allocation failed\n");
+                platform_device_put(mx27vis_aic32x4_snd_device);
+        }
+
+        /* Connect SSI0 as clock slave to SSI1 external pins */
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_TFSDIR |
+                        MXC_AUDMUX_V1_PCR_TCLKDIR |
+                        MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1) |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1)
+        );
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_PPCR1_SSI_PINS_1,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+        );
+
+        return ret;
+}
+
+static void __exit mx27vis_aic32x4_exit(void)
+{
+        platform_device_unregister(mx27vis_aic32x4_snd_device);
+}
+
+module_init(mx27vis_aic32x4_init);
+module_exit(mx27vis_aic32x4_exit);
+
+MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
+MODULE_DESCRIPTION("ALSA SoC AIC32X4 mx27 visstrim");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/imx/phycore-ac97.c
new file mode 100644
index 00000000000..a7deb5cb243
--- /dev/null
+++ b/sound/soc/imx/phycore-ac97.c
@@ -0,0 +1,99 @@
+/*
+ * phycore-ac97.c  --  SoC audio for imx_phycore in AC97 mode
+ *
+ * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <asm/mach-types.h>
+
+static struct snd_soc_card imx_phycore;
+
+static struct snd_soc_ops imx_phycore_hifi_ops = {
+};
+
+static struct snd_soc_dai_link imx_phycore_dai_ac97[] = {
+        {
+                .name           = "HiFi",
+                .stream_name    = "HiFi",
+                .codec_dai_name         = "wm9712-hifi",
+                .codec_name     = "wm9712-codec",
+                .cpu_dai_name   = "imx-ssi.0",
+                .platform_name  = "imx-fiq-pcm-audio.0",
+                .ops            = &imx_phycore_hifi_ops,
+        },
+};
+
+static struct snd_soc_card imx_phycore = {
+        .name           = "PhyCORE-ac97-audio",
+        .dai_link       = imx_phycore_dai_ac97,
+        .num_links      = ARRAY_SIZE(imx_phycore_dai_ac97),
+};
+
+static struct platform_device *imx_phycore_snd_ac97_device;
+static struct platform_device *imx_phycore_snd_device;
+
+static int __init imx_phycore_init(void)
+{
+        int ret;
+
+        if (!machine_is_pcm043() && !machine_is_pca100())
+                /* return happy. We might run on a totally different machine */
+                return 0;
+
+        imx_phycore_snd_ac97_device = platform_device_alloc("soc-audio", -1);
+        if (!imx_phycore_snd_ac97_device)
+                return -ENOMEM;
+
+        platform_set_drvdata(imx_phycore_snd_ac97_device, &imx_phycore);
+        ret = platform_device_add(imx_phycore_snd_ac97_device);
+        if (ret)
+                goto fail1;
+
+        imx_phycore_snd_device = platform_device_alloc("wm9712-codec", -1);
+        if (!imx_phycore_snd_device) {
+                ret = -ENOMEM;
+                goto fail2;
+        }
+        ret = platform_device_add(imx_phycore_snd_device);
+
+        if (ret) {
+                printk(KERN_ERR "ASoC: Platform device allocation failed\n");
+                goto fail3;
+        }
+
+        return 0;
+
+fail3:
+        platform_device_put(imx_phycore_snd_device);
+fail2:
+        platform_device_del(imx_phycore_snd_ac97_device);
+fail1:
+        platform_device_put(imx_phycore_snd_ac97_device);
+        return ret;
+}
+
+static void __exit imx_phycore_exit(void)
+{
+        platform_device_unregister(imx_phycore_snd_device);
+        platform_device_unregister(imx_phycore_snd_ac97_device);
+}
+
+late_initcall(imx_phycore_init);
+module_exit(imx_phycore_exit);
+
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+MODULE_DESCRIPTION("PhyCORE ALSA SoC driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/imx/wm1133-ev1.c
new file mode 100644
index 00000000000..75b4c72787e
--- /dev/null
+++ b/sound/soc/imx/wm1133-ev1.c
@@ -0,0 +1,303 @@
+/*
+ *  wm1133-ev1.c - Audio for WM1133-EV1 on i.MX31ADS
+ *
+ *  Copyright (c) 2010 Wolfson Microelectronics plc
+ *  Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ *  Based on an earlier driver for the same hardware by Liam Girdwood.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/audmux.h>
+
+#include "imx-ssi.h"
+#include "../codecs/wm8350.h"
+
+/* There is a silicon mic on the board optionally connected via a solder pad
+ * SP1.  Define this to enable it.
+ */
+#undef USE_SIMIC
+
+struct _wm8350_audio {
+        unsigned int channels;
+        snd_pcm_format_t format;
+        unsigned int rate;
+        unsigned int sysclk;
+        unsigned int bclkdiv;
+        unsigned int clkdiv;
+        unsigned int lr_rate;
+};
+
+/* in order of power consumption per rate (lowest first) */
+static const struct _wm8350_audio wm8350_audio[] = {
+        /* 16bit mono modes */
+        {1, SNDRV_PCM_FORMAT_S16_LE, 8000, 12288000 >> 1,
+         WM8350_BCLK_DIV_48, WM8350_DACDIV_3, 16,},
+
+        /* 16 bit stereo modes */
+        {2, SNDRV_PCM_FORMAT_S16_LE, 8000, 12288000,
+         WM8350_BCLK_DIV_48, WM8350_DACDIV_6, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 16000, 12288000,
+         WM8350_BCLK_DIV_24, WM8350_DACDIV_3, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 32000, 12288000,
+         WM8350_BCLK_DIV_12, WM8350_DACDIV_1_5, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 48000, 12288000,
+         WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 96000, 24576000,
+         WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 11025, 11289600,
+         WM8350_BCLK_DIV_32, WM8350_DACDIV_4, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 22050, 11289600,
+         WM8350_BCLK_DIV_16, WM8350_DACDIV_2, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 44100, 11289600,
+         WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,},
+        {2, SNDRV_PCM_FORMAT_S16_LE, 88200, 22579200,
+         WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,},
+
+        /* 24bit stereo modes */
+        {2, SNDRV_PCM_FORMAT_S24_LE, 48000, 12288000,
+         WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,},
+        {2, SNDRV_PCM_FORMAT_S24_LE, 96000, 24576000,
+         WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,},
+        {2, SNDRV_PCM_FORMAT_S24_LE, 44100, 11289600,
+         WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,},
+        {2, SNDRV_PCM_FORMAT_S24_LE, 88200, 22579200,
+         WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,},
+};
+
+static int wm1133_ev1_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int i, found = 0;
+        snd_pcm_format_t format = params_format(params);
+        unsigned int rate = params_rate(params);
+        unsigned int channels = params_channels(params);
+        u32 dai_format;
+
+        /* find the correct audio parameters */
+        for (i = 0; i < ARRAY_SIZE(wm8350_audio); i++) {
+                if (rate == wm8350_audio[i].rate &&
+                    format == wm8350_audio[i].format &&
+                    channels == wm8350_audio[i].channels) {
+                        found = 1;
+                        break;
+                }
+        }
+        if (!found)
+                return -EINVAL;
+
+        /* codec FLL input is 14.75 MHz from MCLK */
+        snd_soc_dai_set_pll(codec_dai, 0, 0, 14750000, wm8350_audio[i].sysclk);
+
+        dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+                SND_SOC_DAIFMT_CBM_CFM;
+
+        /* set codec DAI configuration */
+        snd_soc_dai_set_fmt(codec_dai, dai_format);
+
+        /* set cpu DAI configuration */
+        snd_soc_dai_set_fmt(cpu_dai, dai_format);
+
+        /* TODO: The SSI driver should figure this out for us */
+        switch (channels) {
+        case 2:
+                snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0);
+                break;
+        case 1:
+                snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffe, 0xffffffe, 1, 0);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* set MCLK as the codec system clock for DAC and ADC */
+        snd_soc_dai_set_sysclk(codec_dai, WM8350_MCLK_SEL_PLL_MCLK,
+                               wm8350_audio[i].sysclk, SND_SOC_CLOCK_IN);
+
+        /* set codec BCLK division for sample rate */
+        snd_soc_dai_set_clkdiv(codec_dai, WM8350_BCLK_CLKDIV,
+                               wm8350_audio[i].bclkdiv);
+
+        /* DAI is synchronous and clocked with DAC LRCLK & ADC LRC */
+        snd_soc_dai_set_clkdiv(codec_dai,
+                               WM8350_DACLR_CLKDIV, wm8350_audio[i].lr_rate);
+        snd_soc_dai_set_clkdiv(codec_dai,
+                               WM8350_ADCLR_CLKDIV, wm8350_audio[i].lr_rate);
+
+        /* now configure DAC and ADC clocks */
+        snd_soc_dai_set_clkdiv(codec_dai,
+                               WM8350_DAC_CLKDIV, wm8350_audio[i].clkdiv);
+
+        snd_soc_dai_set_clkdiv(codec_dai,
+                               WM8350_ADC_CLKDIV, wm8350_audio[i].clkdiv);
+
+        return 0;
+}
+
+static struct snd_soc_ops wm1133_ev1_ops = {
+        .hw_params = wm1133_ev1_hw_params,
+};
+
+static const struct snd_soc_dapm_widget wm1133_ev1_widgets[] = {
+#ifdef USE_SIMIC
+        SND_SOC_DAPM_MIC("SiMIC", NULL),
+#endif
+        SND_SOC_DAPM_MIC("Mic1 Jack", NULL),
+        SND_SOC_DAPM_MIC("Mic2 Jack", NULL),
+        SND_SOC_DAPM_LINE("Line In Jack", NULL),
+        SND_SOC_DAPM_LINE("Line Out Jack", NULL),
+        SND_SOC_DAPM_HP("Headphone Jack", NULL),
+};
+
+/* imx32ads soc_card audio map */
+static const struct snd_soc_dapm_route wm1133_ev1_map[] = {
+
+#ifdef USE_SIMIC
+        /* SiMIC --> IN1LN (with automatic bias) via SP1 */
+        { "IN1LN", NULL, "Mic Bias" },
+        { "Mic Bias", NULL, "SiMIC" },
+#endif
+
+        /* Mic 1 Jack --> IN1LN and IN1LP (with automatic bias) */
+        { "IN1LN", NULL, "Mic Bias" },
+        { "IN1LP", NULL, "Mic1 Jack" },
+        { "Mic Bias", NULL, "Mic1 Jack" },
+
+        /* Mic 2 Jack --> IN1RN and IN1RP (with automatic bias) */
+        { "IN1RN", NULL, "Mic Bias" },
+        { "IN1RP", NULL, "Mic2 Jack" },
+        { "Mic Bias", NULL, "Mic2 Jack" },
+
+        /* Line in Jack --> AUX (L+R) */
+        { "IN3R", NULL, "Line In Jack" },
+        { "IN3L", NULL, "Line In Jack" },
+
+        /* Out1 --> Headphone Jack */
+        { "Headphone Jack", NULL, "OUT1R" },
+        { "Headphone Jack", NULL, "OUT1L" },
+
+        /* Out1 --> Line Out Jack */
+        { "Line Out Jack", NULL, "OUT2R" },
+        { "Line Out Jack", NULL, "OUT2L" },
+};
+
+static struct snd_soc_jack hp_jack;
+
+static struct snd_soc_jack_pin hp_jack_pins[] = {
+        { .pin = "Headphone Jack", .mask = SND_JACK_HEADPHONE },
+};
+
+static struct snd_soc_jack mic_jack;
+
+static struct snd_soc_jack_pin mic_jack_pins[] = {
+        { .pin = "Mic1 Jack", .mask = SND_JACK_MICROPHONE },
+        { .pin = "Mic2 Jack", .mask = SND_JACK_MICROPHONE },
+};
+
+static int wm1133_ev1_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+        snd_soc_dapm_new_controls(dapm, wm1133_ev1_widgets,
+                                  ARRAY_SIZE(wm1133_ev1_widgets));
+
+        snd_soc_dapm_add_routes(dapm, wm1133_ev1_map,
+                                ARRAY_SIZE(wm1133_ev1_map));
+
+        /* Headphone jack detection */
+        snd_soc_jack_new(codec, "Headphone", SND_JACK_HEADPHONE, &hp_jack);
+        snd_soc_jack_add_pins(&hp_jack, ARRAY_SIZE(hp_jack_pins),
+                              hp_jack_pins);
+        wm8350_hp_jack_detect(codec, WM8350_JDR, &hp_jack, SND_JACK_HEADPHONE);
+
+        /* Microphone jack detection */
+        snd_soc_jack_new(codec, "Microphone",
+                         SND_JACK_MICROPHONE | SND_JACK_BTN_0, &mic_jack);
+        snd_soc_jack_add_pins(&mic_jack, ARRAY_SIZE(mic_jack_pins),
+                              mic_jack_pins);
+        wm8350_mic_jack_detect(codec, &mic_jack, SND_JACK_MICROPHONE,
+                               SND_JACK_BTN_0);
+
+        snd_soc_dapm_force_enable_pin(dapm, "Mic Bias");
+
+        return 0;
+}
+
+
+static struct snd_soc_dai_link wm1133_ev1_dai = {
+        .name = "WM1133-EV1",
+        .stream_name = "Audio",
+        .cpu_dai_name = "imx-ssi.0",
+        .codec_dai_name = "wm8350-hifi",
+        .platform_name = "imx-fiq-pcm-audio.0",
+        .codec_name = "wm8350-codec.0-0x1a",
+        .init = wm1133_ev1_init,
+        .ops = &wm1133_ev1_ops,
+        .symmetric_rates = 1,
+};
+
+static struct snd_soc_card wm1133_ev1 = {
+        .name = "WM1133-EV1",
+        .dai_link = &wm1133_ev1_dai,
+        .num_links = 1,
+};
+
+static struct platform_device *wm1133_ev1_snd_device;
+
+static int __init wm1133_ev1_audio_init(void)
+{
+        int ret;
+        unsigned int ptcr, pdcr;
+
+        /* SSI0 mastered by port 5 */
+        ptcr = MXC_AUDMUX_V2_PTCR_SYN |
+                MXC_AUDMUX_V2_PTCR_TFSDIR |
+                MXC_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT5_SSI_PINS_5) |
+                MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                MXC_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
+        pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
+        mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0, ptcr, pdcr);
+
+        ptcr = MXC_AUDMUX_V2_PTCR_SYN;
+        pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0);
+        mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT5_SSI_PINS_5, ptcr, pdcr);
+
+        wm1133_ev1_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!wm1133_ev1_snd_device)
+                return -ENOMEM;
+
+        platform_set_drvdata(wm1133_ev1_snd_device, &wm1133_ev1);
+        ret = platform_device_add(wm1133_ev1_snd_device);
+
+        if (ret)
+                platform_device_put(wm1133_ev1_snd_device);
+
+        return ret;
+}
+module_init(wm1133_ev1_audio_init);
+
+static void __exit wm1133_ev1_audio_exit(void)
+{
+        platform_device_unregister(wm1133_ev1_snd_device);
+}
+module_exit(wm1133_ev1_audio_exit);
+
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_DESCRIPTION("Audio for WM1133-EV1 on i.MX31ADS");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/igep0020.c b/sound/soc/omap/igep0020.c
new file mode 100644
index 00000000000..0ae34702995
--- /dev/null
+++ b/sound/soc/omap/igep0020.c
@@ -0,0 +1,137 @@
+/*
+ * igep0020.c  --  SoC audio for IGEP v2
+ *
+ * Based on sound/soc/omap/overo.c by Steve Sakoman
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <plat/mcbsp.h>
+
+#include "omap-mcbsp.h"
+#include "omap-pcm.h"
+
+static int igep2_hw_params(struct snd_pcm_substream *substream,
+        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int ret;
+
+        /* Set codec DAI configuration */
+        ret = snd_soc_dai_set_fmt(codec_dai,
+                                  SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set codec DAI configuration\n");
+                return ret;
+        }
+
+        /* Set cpu DAI configuration */
+        ret = snd_soc_dai_set_fmt(cpu_dai,
+                                  SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set cpu DAI configuration\n");
+                return ret;
+        }
+
+        /* Set the codec system clock for DAC and ADC */
+        ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
+                                            SND_SOC_CLOCK_IN);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set codec system clock\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_ops igep2_ops = {
+        .hw_params = igep2_hw_params,
+};
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link igep2_dai = {
+        .name = "TWL4030",
+        .stream_name = "TWL4030",
+        .cpu_dai_name = "omap-mcbsp-dai.1",
+        .codec_dai_name = "twl4030-hifi",
+        .platform_name = "omap-pcm-audio",
+        .codec_name = "twl4030-codec",
+        .ops = &igep2_ops,
+};
+
+/* Audio machine driver */
+static struct snd_soc_card snd_soc_card_igep2 = {
+        .name = "igep2",
+        .dai_link = &igep2_dai,
+        .num_links = 1,
+};
+
+static struct platform_device *igep2_snd_device;
+
+static int __init igep2_soc_init(void)
+{
+        int ret;
+
+        if (!machine_is_igep0020())
+                return -ENODEV;
+        printk(KERN_INFO "IGEP v2 SoC init\n");
+
+        igep2_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!igep2_snd_device) {
+                printk(KERN_ERR "Platform device allocation failed\n");
+                return -ENOMEM;
+        }
+
+        platform_set_drvdata(igep2_snd_device, &snd_soc_card_igep2);
+
+        ret = platform_device_add(igep2_snd_device);
+        if (ret)
+                goto err1;
+
+        return 0;
+
+err1:
+        printk(KERN_ERR "Unable to add platform device\n");
+        platform_device_put(igep2_snd_device);
+
+        return ret;
+}
+module_init(igep2_soc_init);
+
+static void __exit igep2_soc_exit(void)
+{
+        platform_device_unregister(igep2_snd_device);
+}
+module_exit(igep2_soc_exit);
+
+MODULE_AUTHOR("Enric Balletbo i Serra <eballetbo@iseebcn.com>");
+MODULE_DESCRIPTION("ALSA SoC IGEP v2");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/mcpdm.c b/sound/soc/omap/mcpdm.c
new file mode 100644
index 00000000000..50e59194ad8
--- /dev/null
+++ b/sound/soc/omap/mcpdm.c
@@ -0,0 +1,470 @@
+/*
+ * mcpdm.c  --  McPDM interface driver
+ *
+ * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
+ * Copyright (C) 2009 - Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include "mcpdm.h"
+
+static struct omap_mcpdm *mcpdm;
+
+static inline void omap_mcpdm_write(u16 reg, u32 val)
+{
+        __raw_writel(val, mcpdm->io_base + reg);
+}
+
+static inline int omap_mcpdm_read(u16 reg)
+{
+        return __raw_readl(mcpdm->io_base + reg);
+}
+
+static void omap_mcpdm_reg_dump(void)
+{
+        dev_dbg(mcpdm->dev, "***********************\n");
+        dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
+                        omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
+        dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
+                        omap_mcpdm_read(MCPDM_IRQSTATUS));
+        dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
+                        omap_mcpdm_read(MCPDM_IRQENABLE_SET));
+        dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
+                        omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
+        dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
+                        omap_mcpdm_read(MCPDM_IRQWAKE_EN));
+        dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
+                        omap_mcpdm_read(MCPDM_DMAENABLE_SET));
+        dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
+                        omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
+        dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
+                        omap_mcpdm_read(MCPDM_DMAWAKEEN));
+        dev_dbg(mcpdm->dev, "CTRL:      0x%04x\n",
+                        omap_mcpdm_read(MCPDM_CTRL));
+        dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
+                        omap_mcpdm_read(MCPDM_DN_DATA));
+        dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
+                        omap_mcpdm_read(MCPDM_UP_DATA));
+        dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
+                        omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
+        dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
+                        omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
+        dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n",
+                        omap_mcpdm_read(MCPDM_DN_OFFSET));
+        dev_dbg(mcpdm->dev, "***********************\n");
+}
+
+/*
+ * Takes the McPDM module in and out of reset state.
+ * Uplink and downlink can be reset individually.
+ */
+static void omap_mcpdm_reset_capture(int reset)
+{
+        int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+
+        if (reset)
+                ctrl |= SW_UP_RST;
+        else
+                ctrl &= ~SW_UP_RST;
+
+        omap_mcpdm_write(MCPDM_CTRL, ctrl);
+}
+
+static void omap_mcpdm_reset_playback(int reset)
+{
+        int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+
+        if (reset)
+                ctrl |= SW_DN_RST;
+        else
+                ctrl &= ~SW_DN_RST;
+
+        omap_mcpdm_write(MCPDM_CTRL, ctrl);
+}
+
+/*
+ * Enables the transfer through the PDM interface to/from the Phoenix
+ * codec by enabling the corresponding UP or DN channels.
+ */
+void omap_mcpdm_start(int stream)
+{
+        int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+
+        if (stream)
+                ctrl |= mcpdm->up_channels;
+        else
+                ctrl |= mcpdm->dn_channels;
+
+        omap_mcpdm_write(MCPDM_CTRL, ctrl);
+}
+
+/*
+ * Disables the transfer through the PDM interface to/from the Phoenix
+ * codec by disabling the corresponding UP or DN channels.
+ */
+void omap_mcpdm_stop(int stream)
+{
+        int ctrl = omap_mcpdm_read(MCPDM_CTRL);
+
+        if (stream)
+                ctrl &= ~mcpdm->up_channels;
+        else
+                ctrl &= ~mcpdm->dn_channels;
+
+        omap_mcpdm_write(MCPDM_CTRL, ctrl);
+}
+
+/*
+ * Configures McPDM uplink for audio recording.
+ * This function should be called before omap_mcpdm_start.
+ */
+int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
+{
+        int irq_mask = 0;
+        int ctrl;
+
+        if (!uplink)
+                return -EINVAL;
+
+        mcpdm->uplink = uplink;
+
+        /* Enable irq request generation */
+        irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
+        omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
+
+        /* Configure uplink threshold */
+        if (uplink->threshold > UP_THRES_MAX)
+                uplink->threshold = UP_THRES_MAX;
+
+        omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
+
+        /* Configure DMA controller */
+        omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
+
+        /* Set pdm out format */
+        ctrl = omap_mcpdm_read(MCPDM_CTRL);
+        ctrl &= ~PDMOUTFORMAT;
+        ctrl |= uplink->format & PDMOUTFORMAT;
+
+        /* Uplink channels */
+        mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
+
+        omap_mcpdm_write(MCPDM_CTRL, ctrl);
+
+        return 0;
+}
+
+/*
+ * Configures McPDM downlink for audio playback.
+ * This function should be called before omap_mcpdm_start.
+ */
+int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
+{
+        int irq_mask = 0;
+        int ctrl;
+
+        if (!downlink)
+                return -EINVAL;
+
+        mcpdm->downlink = downlink;
+
+        /* Enable irq request generation */
+        irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
+        omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
+
+        /* Configure uplink threshold */
+        if (downlink->threshold > DN_THRES_MAX)
+                downlink->threshold = DN_THRES_MAX;
+
+        omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
+
+        /* Enable DMA request generation */
+        omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
+
+        /* Set pdm out format */
+        ctrl = omap_mcpdm_read(MCPDM_CTRL);
+        ctrl &= ~PDMOUTFORMAT;
+        ctrl |= downlink->format & PDMOUTFORMAT;
+
+        /* Downlink channels */
+        mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
+
+        omap_mcpdm_write(MCPDM_CTRL, ctrl);
+
+        return 0;
+}
+
+/*
+ * Cleans McPDM uplink configuration.
+ * This function should be called when the stream is closed.
+ */
+int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
+{
+        int irq_mask = 0;
+
+        if (!uplink)
+                return -EINVAL;
+
+        /* Disable irq request generation */
+        irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
+        omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
+
+        /* Disable DMA request generation */
+        omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
+
+        /* Clear Downlink channels */
+        mcpdm->up_channels = 0;
+
+        mcpdm->uplink = NULL;
+
+        return 0;
+}
+
+/*
+ * Cleans McPDM downlink configuration.
+ * This function should be called when the stream is closed.
+ */
+int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink)
+{
+        int irq_mask = 0;
+
+        if (!downlink)
+                return -EINVAL;
+
+        /* Disable irq request generation */
+        irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
+        omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
+
+        /* Disable DMA request generation */
+        omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
+
+        /* clear Downlink channels */
+        mcpdm->dn_channels = 0;
+
+        mcpdm->downlink = NULL;
+
+        return 0;
+}
+
+static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
+{
+        struct omap_mcpdm *mcpdm_irq = dev_id;
+        int irq_status;
+
+        irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
+
+        /* Acknowledge irq event */
+        omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
+
+        if (irq & MCPDM_DN_IRQ_FULL) {
+                dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
+                omap_mcpdm_reset_playback(1);
+                omap_mcpdm_playback_open(mcpdm_irq->downlink);
+                omap_mcpdm_reset_playback(0);
+        }
+
+        if (irq & MCPDM_DN_IRQ_EMPTY) {
+                dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
+                omap_mcpdm_reset_playback(1);
+                omap_mcpdm_playback_open(mcpdm_irq->downlink);
+                omap_mcpdm_reset_playback(0);
+        }
+
+        if (irq & MCPDM_DN_IRQ) {
+                dev_dbg(mcpdm_irq->dev, "DN write request\n");
+        }
+
+        if (irq & MCPDM_UP_IRQ_FULL) {
+                dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
+                omap_mcpdm_reset_capture(1);
+                omap_mcpdm_capture_open(mcpdm_irq->uplink);
+                omap_mcpdm_reset_capture(0);
+        }
+
+        if (irq & MCPDM_UP_IRQ_EMPTY) {
+                dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
+                omap_mcpdm_reset_capture(1);
+                omap_mcpdm_capture_open(mcpdm_irq->uplink);
+                omap_mcpdm_reset_capture(0);
+        }
+
+        if (irq & MCPDM_UP_IRQ) {
+                dev_dbg(mcpdm_irq->dev, "UP write request\n");
+        }
+
+        return IRQ_HANDLED;
+}
+
+int omap_mcpdm_request(void)
+{
+        int ret;
+
+        clk_enable(mcpdm->clk);
+
+        spin_lock(&mcpdm->lock);
+
+        if (!mcpdm->free) {
+                dev_err(mcpdm->dev, "McPDM interface is in use\n");
+                spin_unlock(&mcpdm->lock);
+                ret = -EBUSY;
+                goto err;
+        }
+        mcpdm->free = 0;
+
+        spin_unlock(&mcpdm->lock);
+
+        /* Disable lines while request is ongoing */
+        omap_mcpdm_write(MCPDM_CTRL, 0x00);
+
+        ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
+                                0, "McPDM", (void *)mcpdm);
+        if (ret) {
+                dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
+                goto err;
+        }
+
+        return 0;
+
+err:
+        clk_disable(mcpdm->clk);
+        return ret;
+}
+
+void omap_mcpdm_free(void)
+{
+        spin_lock(&mcpdm->lock);
+        if (mcpdm->free) {
+                dev_err(mcpdm->dev, "McPDM interface is already free\n");
+                spin_unlock(&mcpdm->lock);
+                return;
+        }
+        mcpdm->free = 1;
+        spin_unlock(&mcpdm->lock);
+
+        clk_disable(mcpdm->clk);
+
+        free_irq(mcpdm->irq, (void *)mcpdm);
+}
+
+/* Enable/disable DC offset cancelation for the analog
+ * headset path (PDM channels 1 and 2).
+ */
+int omap_mcpdm_set_offset(int offset1, int offset2)
+{
+        int offset;
+
+        if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
+                return -EINVAL;
+
+        offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
+
+        /* offset cancellation for channel 1 */
+        if (offset1)
+                offset |= DN_OFST_RX1_EN;
+        else
+                offset &= ~DN_OFST_RX1_EN;
+
+        /* offset cancellation for channel 2 */
+        if (offset2)
+                offset |= DN_OFST_RX2_EN;
+        else
+                offset &= ~DN_OFST_RX2_EN;
+
+        omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
+
+        return 0;
+}
+
+int __devinit omap_mcpdm_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        int ret = 0;
+
+        mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
+        if (!mcpdm) {
+                ret = -ENOMEM;
+                goto exit;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no resource\n");
+                goto err_resource;
+        }
+
+        spin_lock_init(&mcpdm->lock);
+        mcpdm->free = 1;
+        mcpdm->io_base = ioremap(res->start, resource_size(res));
+        if (!mcpdm->io_base) {
+                ret = -ENOMEM;
+                goto err_resource;
+        }
+
+        mcpdm->irq = platform_get_irq(pdev, 0);
+
+        mcpdm->clk = clk_get(&pdev->dev, "pdm_ck");
+        if (IS_ERR(mcpdm->clk)) {
+                ret = PTR_ERR(mcpdm->clk);
+                dev_err(&pdev->dev, "unable to get pdm_ck: %d\n", ret);
+                goto err_clk;
+        }
+
+        mcpdm->dev = &pdev->dev;
+        platform_set_drvdata(pdev, mcpdm);
+
+        return 0;
+
+err_clk:
+        iounmap(mcpdm->io_base);
+err_resource:
+        kfree(mcpdm);
+exit:
+        return ret;
+}
+
+int omap_mcpdm_remove(struct platform_device *pdev)
+{
+        struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
+
+        platform_set_drvdata(pdev, NULL);
+
+        clk_put(mcpdm_ptr->clk);
+
+        iounmap(mcpdm_ptr->io_base);
+
+        mcpdm_ptr->clk = NULL;
+        mcpdm_ptr->free = 0;
+        mcpdm_ptr->dev = NULL;
+
+        kfree(mcpdm_ptr);
+
+        return 0;
+}
+
diff --git a/sound/soc/omap/mcpdm.h b/sound/soc/omap/mcpdm.h
new file mode 100644
index 00000000000..20c20a8649f
--- /dev/null
+++ b/sound/soc/omap/mcpdm.h
@@ -0,0 +1,153 @@
+/*
+ * mcpdm.h -- Defines for McPDM driver
+ *
+ * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+/* McPDM registers */
+
+#define MCPDM_REVISION         0x00
+#define MCPDM_SYSCONFIG                0x10
+#define MCPDM_IRQSTATUS_RAW    0x24
+#define MCPDM_IRQSTATUS                0x28
+#define MCPDM_IRQENABLE_SET    0x2C
+#define MCPDM_IRQENABLE_CLR    0x30
+#define MCPDM_IRQWAKE_EN       0x34
+#define MCPDM_DMAENABLE_SET    0x38
+#define MCPDM_DMAENABLE_CLR    0x3C
+#define MCPDM_DMAWAKEEN                0x40
+#define MCPDM_CTRL             0x44
+#define MCPDM_DN_DATA          0x48
+#define MCPDM_UP_DATA          0x4C
+#define MCPDM_FIFO_CTRL_DN     0x50
+#define MCPDM_FIFO_CTRL_UP     0x54
+#define MCPDM_DN_OFFSET                0x58
+
+/*
+ * MCPDM_IRQ bit fields
+ * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
+ */
+
+#define MCPDM_DN_IRQ                   (1 << 0)
+#define MCPDM_DN_IRQ_EMPTY             (1 << 1)
+#define MCPDM_DN_IRQ_ALMST_EMPTY       (1 << 2)
+#define MCPDM_DN_IRQ_FULL              (1 << 3)
+
+#define MCPDM_UP_IRQ                   (1 << 8)
+#define MCPDM_UP_IRQ_EMPTY             (1 << 9)
+#define MCPDM_UP_IRQ_ALMST_FULL                (1 << 10)
+#define MCPDM_UP_IRQ_FULL              (1 << 11)
+
+#define MCPDM_DOWNLINK_IRQ_MASK                0x00F
+#define MCPDM_UPLINK_IRQ_MASK          0xF00
+
+/*
+ * MCPDM_DMAENABLE bit fields
+ */
+
+#define DMA_DN_ENABLE          0x1
+#define DMA_UP_ENABLE          0x2
+
+/*
+ * MCPDM_CTRL bit fields
+ */
+
+#define PDM_UP1_EN             0x0001
+#define PDM_UP2_EN             0x0002
+#define PDM_UP3_EN             0x0004
+#define PDM_DN1_EN             0x0008
+#define PDM_DN2_EN             0x0010
+#define PDM_DN3_EN             0x0020
+#define PDM_DN4_EN             0x0040
+#define PDM_DN5_EN             0x0080
+#define PDMOUTFORMAT           0x0100
+#define CMD_INT                        0x0200
+#define STATUS_INT             0x0400
+#define SW_UP_RST              0x0800
+#define SW_DN_RST              0x1000
+#define PDM_UP_MASK            0x007
+#define PDM_DN_MASK            0x0F8
+#define PDM_CMD_MASK           0x200
+#define PDM_STATUS_MASK                0x400
+
+
+#define PDMOUTFORMAT_LJUST     (0 << 8)
+#define PDMOUTFORMAT_RJUST     (1 << 8)
+
+/*
+ * MCPDM_FIFO_CTRL bit fields
+ */
+
+#define UP_THRES_MAX           0xF
+#define DN_THRES_MAX           0xF
+
+/*
+ * MCPDM_DN_OFFSET bit fields
+ */
+
+#define DN_OFST_RX1_EN         0x0001
+#define DN_OFST_RX2_EN         0x0100
+
+#define DN_OFST_RX1            1
+#define DN_OFST_RX2            9
+#define DN_OFST_MAX            0x1F
+
+#define MCPDM_UPLINK           1
+#define MCPDM_DOWNLINK         2
+
+struct omap_mcpdm_link {
+       int irq_mask;
+       int threshold;
+       int format;
+       int channels;
+};
+
+struct omap_mcpdm_platform_data {
+       unsigned long phys_base;
+       u16 irq;
+};
+
+struct omap_mcpdm {
+       struct device *dev;
+       unsigned long phys_base;
+       void __iomem *io_base;
+       u8 free;
+       int irq;
+
+       spinlock_t lock;
+       struct omap_mcpdm_platform_data *pdata;
+       struct clk *clk;
+       struct omap_mcpdm_link *downlink;
+       struct omap_mcpdm_link *uplink;
+       struct completion irq_completion;
+
+       int dn_channels;
+       int up_channels;
+};
+
+extern void omap_mcpdm_start(int stream);
+extern void omap_mcpdm_stop(int stream);
+extern int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink);
+extern int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink);
+extern int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink);
+extern int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink);
+extern int omap_mcpdm_request(void);
+extern void omap_mcpdm_free(void);
+extern int omap_mcpdm_set_offset(int offset1, int offset2);
+int __devinit omap_mcpdm_probe(struct platform_device *pdev);
+int omap_mcpdm_remove(struct platform_device *pdev);
diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c
new file mode 100644
index 00000000000..40db813c079
--- /dev/null
+++ b/sound/soc/omap/omap3beagle.c
@@ -0,0 +1,149 @@
+/*
+ * omap3beagle.c  --  SoC audio for OMAP3 Beagle
+ *
+ * Author: Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <plat/mcbsp.h>
+
+#include "omap-mcbsp.h"
+#include "omap-pcm.h"
+
+static int omap3beagle_hw_params(struct snd_pcm_substream *substream,
+        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        unsigned int fmt;
+        int ret;
+
+        switch (params_channels(params)) {
+        case 2: /* Stereo I2S mode */
+                fmt =   SND_SOC_DAIFMT_I2S |
+                        SND_SOC_DAIFMT_NB_NF |
+                        SND_SOC_DAIFMT_CBM_CFM;
+                break;
+        case 4: /* Four channel TDM mode */
+                fmt =   SND_SOC_DAIFMT_DSP_A |
+                        SND_SOC_DAIFMT_IB_NF |
+                        SND_SOC_DAIFMT_CBM_CFM;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Set codec DAI configuration */
+        ret = snd_soc_dai_set_fmt(codec_dai, fmt);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set codec DAI configuration\n");
+                return ret;
+        }
+
+        /* Set cpu DAI configuration */
+        ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set cpu DAI configuration\n");
+                return ret;
+        }
+
+        /* Set the codec system clock for DAC and ADC */
+        ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
+                                     SND_SOC_CLOCK_IN);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set codec system clock\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_ops omap3beagle_ops = {
+        .hw_params = omap3beagle_hw_params,
+};
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link omap3beagle_dai = {
+        .name = "TWL4030",
+        .stream_name = "TWL4030",
+        .cpu_dai_name = "omap-mcbsp-dai.1",
+        .platform_name = "omap-pcm-audio",
+        .codec_dai_name = "twl4030-hifi",
+        .codec_name = "twl4030-codec",
+        .ops = &omap3beagle_ops,
+};
+
+/* Audio machine driver */
+static struct snd_soc_card snd_soc_omap3beagle = {
+        .name = "omap3beagle",
+        .owner = THIS_MODULE,
+        .dai_link = &omap3beagle_dai,
+        .num_links = 1,
+};
+
+static struct platform_device *omap3beagle_snd_device;
+
+static int __init omap3beagle_soc_init(void)
+{
+        int ret;
+
+        if (!(machine_is_omap3_beagle() || machine_is_devkit8000()))
+                return -ENODEV;
+        pr_info("OMAP3 Beagle/Devkit8000 SoC init\n");
+
+        omap3beagle_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!omap3beagle_snd_device) {
+                printk(KERN_ERR "Platform device allocation failed\n");
+                return -ENOMEM;
+        }
+
+        platform_set_drvdata(omap3beagle_snd_device, &snd_soc_omap3beagle);
+
+        ret = platform_device_add(omap3beagle_snd_device);
+        if (ret)
+                goto err1;
+
+        return 0;
+
+err1:
+        printk(KERN_ERR "Unable to add platform device\n");
+        platform_device_put(omap3beagle_snd_device);
+
+        return ret;
+}
+
+static void __exit omap3beagle_soc_exit(void)
+{
+        platform_device_unregister(omap3beagle_snd_device);
+}
+
+module_init(omap3beagle_soc_init);
+module_exit(omap3beagle_soc_exit);
+
+MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>");
+MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
new file mode 100644
index 00000000000..0daa0446983
--- /dev/null
+++ b/sound/soc/omap/omap3evm.c
@@ -0,0 +1,135 @@
+/*
+ * omap3evm.c  -- ALSA SoC support for OMAP3 EVM
+ *
+ * Author: Anuj Aggarwal <anuj.aggarwal@ti.com>
+ *
+ * Based on sound/soc/omap/beagle.c by Steve Sakoman
+ *
+ * Copyright (C) 2008 Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <plat/mcbsp.h>
+
+#include "omap-mcbsp.h"
+#include "omap-pcm.h"
+
+static int omap3evm_hw_params(struct snd_pcm_substream *substream,
+        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int ret;
+
+        /* Set codec DAI configuration */
+        ret = snd_soc_dai_set_fmt(codec_dai,
+                                  SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0) {
+                printk(KERN_ERR "Can't set codec DAI configuration\n");
+                return ret;
+        }
+
+        /* Set cpu DAI configuration */
+        ret = snd_soc_dai_set_fmt(cpu_dai,
+                                  SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0) {
+                printk(KERN_ERR "Can't set cpu DAI configuration\n");
+                return ret;
+        }
+
+        /* Set the codec system clock for DAC and ADC */
+        ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
+                                     SND_SOC_CLOCK_IN);
+        if (ret < 0) {
+                printk(KERN_ERR "Can't set codec system clock\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_ops omap3evm_ops = {
+        .hw_params = omap3evm_hw_params,
+};
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link omap3evm_dai = {
+        .name           = "TWL4030",
+        .stream_name    = "TWL4030",
+        .cpu_dai_name = "omap-mcbsp-dai.1",
+        .codec_dai_name = "twl4030-hifi",
+        .platform_name = "omap-pcm-audio",
+        .codec_name = "twl4030-codec",
+        .ops            = &omap3evm_ops,
+};
+
+/* Audio machine driver */
+static struct snd_soc_card snd_soc_omap3evm = {
+        .name = "omap3evm",
+        .dai_link = &omap3evm_dai,
+        .num_links = 1,
+};
+
+static struct platform_device *omap3evm_snd_device;
+
+static int __init omap3evm_soc_init(void)
+{
+        int ret;
+
+        if (!machine_is_omap3evm())
+                return -ENODEV;
+        pr_info("OMAP3 EVM SoC init\n");
+
+        omap3evm_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!omap3evm_snd_device) {
+                printk(KERN_ERR "Platform device allocation failed\n");
+                return -ENOMEM;
+        }
+
+        platform_set_drvdata(omap3evm_snd_device, &snd_soc_omap3evm);
+        ret = platform_device_add(omap3evm_snd_device);
+        if (ret)
+                goto err1;
+
+        return 0;
+
+err1:
+        printk(KERN_ERR "Unable to add platform device\n");
+        platform_device_put(omap3evm_snd_device);
+
+        return ret;
+}
+
+static void __exit omap3evm_soc_exit(void)
+{
+        platform_device_unregister(omap3evm_snd_device);
+}
+
+module_init(omap3evm_soc_init);
+module_exit(omap3evm_soc_exit);
+
+MODULE_AUTHOR("Anuj Aggarwal <anuj.aggarwal@ti.com>");
+MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/omap/omap4-hdmi-card.c b/sound/soc/omap/omap4-hdmi-card.c
new file mode 100644
index 00000000000..9f32615b81f
--- /dev/null
+++ b/sound/soc/omap/omap4-hdmi-card.c
@@ -0,0 +1,129 @@
+/*
+ * omap4-hdmi-card.c
+ *
+ * OMAP ALSA SoC machine driver for TI OMAP4 HDMI
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Ricardo Neri <ricardo.neri@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <asm/mach-types.h>
+#include <video/omapdss.h>
+
+#define DRV_NAME "omap4-hdmi-audio"
+
+static int omap4_hdmi_dai_hw_params(struct snd_pcm_substream *substream,
+                struct snd_pcm_hw_params *params)
+{
+        int i;
+        struct omap_overlay_manager *mgr = NULL;
+        struct device *dev = substream->pcm->card->dev;
+
+        /* Find DSS HDMI device */
+        for (i = 0; i < omap_dss_get_num_overlay_managers(); i++) {
+                mgr = omap_dss_get_overlay_manager(i);
+                if (mgr && mgr->device
+                        && mgr->device->type == OMAP_DISPLAY_TYPE_HDMI)
+                        break;
+        }
+
+        if (i == omap_dss_get_num_overlay_managers()) {
+                dev_err(dev, "HDMI display device not found!\n");
+                return -ENODEV;
+        }
+
+        /* Make sure HDMI is power-on to avoid L3 interconnect errors */
+        if (mgr->device->state != OMAP_DSS_DISPLAY_ACTIVE) {
+                dev_err(dev, "HDMI display is not active!\n");
+                return -EIO;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_ops omap4_hdmi_dai_ops = {
+        .hw_params = omap4_hdmi_dai_hw_params,
+};
+
+static struct snd_soc_dai_link omap4_hdmi_dai = {
+        .name = "HDMI",
+        .stream_name = "HDMI",
+        .cpu_dai_name = "hdmi-audio-dai",
+        .platform_name = "omap-pcm-audio",
+        .codec_name = "omapdss_hdmi",
+        .codec_dai_name = "hdmi-audio-codec",
+        .ops = &omap4_hdmi_dai_ops,
+};
+
+static struct snd_soc_card snd_soc_omap4_hdmi = {
+        .name = "OMAP4HDMI",
+        .dai_link = &omap4_hdmi_dai,
+        .num_links = 1,
+};
+
+static __devinit int omap4_hdmi_probe(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = &snd_soc_omap4_hdmi;
+        int ret;
+
+        card->dev = &pdev->dev;
+
+        ret = snd_soc_register_card(card);
+        if (ret) {
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+                card->dev = NULL;
+                return ret;
+        }
+        return 0;
+}
+
+static int __devexit omap4_hdmi_remove(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+        snd_soc_unregister_card(card);
+        card->dev = NULL;
+        return 0;
+}
+
+static struct platform_driver omap4_hdmi_driver = {
+        .driver = {
+                .name = "omap4-hdmi-audio",
+                .owner = THIS_MODULE,
+        },
+        .probe = omap4_hdmi_probe,
+        .remove = __devexit_p(omap4_hdmi_remove),
+};
+
+static int __init omap4_hdmi_init(void)
+{
+        return platform_driver_register(&omap4_hdmi_driver);
+}
+module_init(omap4_hdmi_init);
+
+static void __exit omap4_hdmi_exit(void)
+{
+        platform_driver_unregister(&omap4_hdmi_driver);
+}
+module_exit(omap4_hdmi_exit);
+
+MODULE_AUTHOR("Ricardo Neri <ricardo.neri@ti.com>");
+MODULE_DESCRIPTION("OMAP4 HDMI machine ASoC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/omap/overo.c b/sound/soc/omap/overo.c
new file mode 100644
index 00000000000..bbcf380bfb5
--- /dev/null
+++ b/sound/soc/omap/overo.c
@@ -0,0 +1,139 @@
+/*
+ * overo.c  --  SoC audio for Gumstix Overo
+ *
+ * Author: Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <plat/mcbsp.h>
+
+#include "omap-mcbsp.h"
+#include "omap-pcm.h"
+
+static int overo_hw_params(struct snd_pcm_substream *substream,
+        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        int ret;
+
+        /* Set codec DAI configuration */
+        ret = snd_soc_dai_set_fmt(codec_dai,
+                                  SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set codec DAI configuration\n");
+                return ret;
+        }
+
+        /* Set cpu DAI configuration */
+        ret = snd_soc_dai_set_fmt(cpu_dai,
+                                  SND_SOC_DAIFMT_I2S |
+                                  SND_SOC_DAIFMT_NB_NF |
+                                  SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set cpu DAI configuration\n");
+                return ret;
+        }
+
+        /* Set the codec system clock for DAC and ADC */
+        ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
+                                            SND_SOC_CLOCK_IN);
+        if (ret < 0) {
+                printk(KERN_ERR "can't set codec system clock\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static struct snd_soc_ops overo_ops = {
+        .hw_params = overo_hw_params,
+};
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link overo_dai = {
+        .name = "TWL4030",
+        .stream_name = "TWL4030",
+        .cpu_dai_name = "omap-mcbsp-dai.1",
+        .codec_dai_name = "twl4030-hifi",
+        .platform_name = "omap-pcm-audio",
+        .codec_name = "twl4030-codec",
+        .ops = &overo_ops,
+};
+
+/* Audio machine driver */
+static struct snd_soc_card snd_soc_card_overo = {
+        .name = "overo",
+        .dai_link = &overo_dai,
+        .num_links = 1,
+};
+
+static struct platform_device *overo_snd_device;
+
+static int __init overo_soc_init(void)
+{
+        int ret;
+
+        if (!(machine_is_overo() || machine_is_cm_t35())) {
+                pr_debug("Incomatible machine!\n");
+                return -ENODEV;
+        }
+        printk(KERN_INFO "overo SoC init\n");
+
+        overo_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!overo_snd_device) {
+                printk(KERN_ERR "Platform device allocation failed\n");
+                return -ENOMEM;
+        }
+
+        platform_set_drvdata(overo_snd_device, &snd_soc_card_overo);
+
+        ret = platform_device_add(overo_snd_device);
+        if (ret)
+                goto err1;
+
+        return 0;
+
+err1:
+        printk(KERN_ERR "Unable to add platform device\n");
+        platform_device_put(overo_snd_device);
+
+        return ret;
+}
+module_init(overo_soc_init);
+
+static void __exit overo_soc_exit(void)
+{
+        platform_device_unregister(overo_snd_device);
+}
+module_exit(overo_soc_exit);
+
+MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>");
+MODULE_DESCRIPTION("ALSA SoC overo");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/sdp4430.c b/sound/soc/omap/sdp4430.c
new file mode 100644
index 00000000000..b80efb02bfc
--- /dev/null
+++ b/sound/soc/omap/sdp4430.c
@@ -0,0 +1,223 @@
+/*
+ * sdp4430.c  --  SoC audio for TI OMAP4430 SDP
+ *
+ * Author: Misael Lopez Cruz <x0052729@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/twl6040.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+
+#include <asm/mach-types.h>
+#include <plat/hardware.h>
+#include <plat/mux.h>
+
+#include "mcpdm.h"
+#include "omap-pcm.h"
+#include "../codecs/twl6040.h"
+
+static int sdp4430_hw_params(struct snd_pcm_substream *substream,
+        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        int clk_id, freq;
+        int ret;
+
+        clk_id = twl6040_get_clk_id(rtd->codec);
+        if (clk_id == TWL6040_SYSCLK_SEL_HPPLL)
+                freq = 38400000;
+        else if (clk_id == TWL6040_SYSCLK_SEL_LPPLL)
+                freq = 32768;
+        else
+                return -EINVAL;
+
+        /* set the codec mclk */
+        ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, freq,
+                                SND_SOC_CLOCK_IN);
+        if (ret) {
+                printk(KERN_ERR "can't set codec system clock\n");
+                return ret;
+        }
+        return ret;
+}
+
+static struct snd_soc_ops sdp4430_ops = {
+        .hw_params = sdp4430_hw_params,
+};
+
+/* Headset jack */
+static struct snd_soc_jack hs_jack;
+
+/*Headset jack detection DAPM pins */
+static struct snd_soc_jack_pin hs_jack_pins[] = {
+        {
+                .pin = "Headset Mic",
+                .mask = SND_JACK_MICROPHONE,
+        },
+        {
+                .pin = "Headset Stereophone",
+                .mask = SND_JACK_HEADPHONE,
+        },
+};
+
+/* SDP4430 machine DAPM */
+static const struct snd_soc_dapm_widget sdp4430_twl6040_dapm_widgets[] = {
+        SND_SOC_DAPM_MIC("Ext Mic", NULL),
+        SND_SOC_DAPM_SPK("Ext Spk", NULL),
+        SND_SOC_DAPM_MIC("Headset Mic", NULL),
+        SND_SOC_DAPM_HP("Headset Stereophone", NULL),
+        SND_SOC_DAPM_SPK("Earphone Spk", NULL),
+        SND_SOC_DAPM_INPUT("Aux/FM Stereo In"),
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+        /* External Mics: MAINMIC, SUBMIC with bias*/
+        {"MAINMIC", NULL, "Main Mic Bias"},
+        {"SUBMIC", NULL, "Main Mic Bias"},
+        {"Main Mic Bias", NULL, "Ext Mic"},
+
+        /* External Speakers: HFL, HFR */
+        {"Ext Spk", NULL, "HFL"},
+        {"Ext Spk", NULL, "HFR"},
+
+        /* Headset Mic: HSMIC with bias */
+        {"HSMIC", NULL, "Headset Mic Bias"},
+        {"Headset Mic Bias", NULL, "Headset Mic"},
+
+        /* Headset Stereophone (Headphone): HSOL, HSOR */
+        {"Headset Stereophone", NULL, "HSOL"},
+        {"Headset Stereophone", NULL, "HSOR"},
+
+        /* Earphone speaker */
+        {"Earphone Spk", NULL, "EP"},
+
+        /* Aux/FM Stereo In: AFML, AFMR */
+        {"AFML", NULL, "Aux/FM Stereo In"},
+        {"AFMR", NULL, "Aux/FM Stereo In"},
+};
+
+static int sdp4430_twl6040_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        int ret;
+
+        /* Add SDP4430 specific widgets */
+        ret = snd_soc_dapm_new_controls(dapm, sdp4430_twl6040_dapm_widgets,
+                                ARRAY_SIZE(sdp4430_twl6040_dapm_widgets));
+        if (ret)
+                return ret;
+
+        /* Set up SDP4430 specific audio path audio_map */
+        snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+
+        /* SDP4430 connected pins */
+        snd_soc_dapm_enable_pin(dapm, "Ext Mic");
+        snd_soc_dapm_enable_pin(dapm, "Ext Spk");
+        snd_soc_dapm_enable_pin(dapm, "AFML");
+        snd_soc_dapm_enable_pin(dapm, "AFMR");
+        snd_soc_dapm_enable_pin(dapm, "Headset Mic");
+        snd_soc_dapm_enable_pin(dapm, "Headset Stereophone");
+
+        ret = snd_soc_dapm_sync(dapm);
+        if (ret)
+                return ret;
+
+        /* Headset jack detection */
+        ret = snd_soc_jack_new(codec, "Headset Jack",
+                                SND_JACK_HEADSET, &hs_jack);
+        if (ret)
+                return ret;
+
+        ret = snd_soc_jack_add_pins(&hs_jack, ARRAY_SIZE(hs_jack_pins),
+                                hs_jack_pins);
+
+        if (machine_is_omap_4430sdp())
+                twl6040_hs_jack_detect(codec, &hs_jack, SND_JACK_HEADSET);
+        else
+                snd_soc_jack_report(&hs_jack, SND_JACK_HEADSET, SND_JACK_HEADSET);
+
+        return ret;
+}
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link sdp4430_dai = {
+        .name = "TWL6040",
+        .stream_name = "TWL6040",
+        .cpu_dai_name ="omap-mcpdm-dai",
+        .codec_dai_name = "twl6040-hifi",
+        .platform_name = "omap-pcm-audio",
+        .codec_name = "twl6040-codec",
+        .init = sdp4430_twl6040_init,
+        .ops = &sdp4430_ops,
+};
+
+/* Audio machine driver */
+static struct snd_soc_card snd_soc_sdp4430 = {
+        .name = "SDP4430",
+        .dai_link = &sdp4430_dai,
+        .num_links = 1,
+};
+
+static struct platform_device *sdp4430_snd_device;
+
+static int __init sdp4430_soc_init(void)
+{
+        int ret;
+
+        if (!machine_is_omap_4430sdp())
+                return -ENODEV;
+        printk(KERN_INFO "SDP4430 SoC init\n");
+
+        sdp4430_snd_device = platform_device_alloc("soc-audio", -1);
+        if (!sdp4430_snd_device) {
+                printk(KERN_ERR "Platform device allocation failed\n");
+                return -ENOMEM;
+        }
+
+        platform_set_drvdata(sdp4430_snd_device, &snd_soc_sdp4430);
+
+        ret = platform_device_add(sdp4430_snd_device);
+        if (ret)
+                goto err;
+
+        return 0;
+
+err:
+        printk(KERN_ERR "Unable to add platform device\n");
+        platform_device_put(sdp4430_snd_device);
+        return ret;
+}
+module_init(sdp4430_soc_init);
+
+static void __exit sdp4430_soc_exit(void)
+{
+        platform_device_unregister(sdp4430_snd_device);
+}
+module_exit(sdp4430_soc_exit);
+
+MODULE_AUTHOR("Misael Lopez Cruz <x0052729@ti.com>");
+MODULE_DESCRIPTION("ALSA SoC SDP4430");
+MODULE_LICENSE("GPL");
+
diff --git a/sound/soc/samsung/speyside_wm8962.c b/sound/soc/samsung/speyside_wm8962.c
new file mode 100644
index 00000000000..72535f2daaf
--- /dev/null
+++ b/sound/soc/samsung/speyside_wm8962.c
@@ -0,0 +1,270 @@
+/*
+ * Speyside with WM8962 audio support
+ *
+ * Copyright 2011 Wolfson Microelectronics
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/jack.h>
+#include <linux/gpio.h>
+
+#include "../codecs/wm8962.h"
+
+static int speyside_wm8962_set_bias_level(struct snd_soc_card *card,
+                                          struct snd_soc_dapm_context *dapm,
+                                          enum snd_soc_bias_level level)
+{
+        struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+        int ret;
+
+        if (dapm->dev != codec_dai->dev)
+                return 0;
+
+        switch (level) {
+        case SND_SOC_BIAS_PREPARE:
+                if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
+                        ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL,
+                                                  WM8962_FLL_MCLK, 32768,
+                                                  44100 * 256);
+                        if (ret < 0)
+                                pr_err("Failed to start FLL: %d\n", ret);
+
+                        ret = snd_soc_dai_set_sysclk(codec_dai,
+                                                     WM8962_SYSCLK_FLL,
+                                                     44100 * 256,
+                                                     SND_SOC_CLOCK_IN);
+                        if (ret < 0) {
+                                pr_err("Failed to set SYSCLK: %d\n", ret);
+                                return ret;
+                        }
+                }
+                break;
+
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int speyside_wm8962_set_bias_level_post(struct snd_soc_card *card,
+                                               struct snd_soc_dapm_context *dapm,
+                                               enum snd_soc_bias_level level)
+{
+        struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+        int ret;
+
+        if (dapm->dev != codec_dai->dev)
+                return 0;
+
+        switch (level) {
+        case SND_SOC_BIAS_STANDBY:
+                ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
+                                             32768, SND_SOC_CLOCK_IN);
+                if (ret < 0) {
+                        pr_err("Failed to switch away from FLL: %d\n", ret);
+                        return ret;
+                }
+
+                ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL,
+                                          0, 0, 0);
+                if (ret < 0) {
+                        pr_err("Failed to stop FLL: %d\n", ret);
+                        return ret;
+                }
+                break;
+
+        default:
+                break;
+        }
+
+        dapm->bias_level = level;
+
+        return 0;
+}
+
+static int speyside_wm8962_hw_params(struct snd_pcm_substream *substream,
+                              struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        int ret;
+
+        ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+                                         | SND_SOC_DAIFMT_NB_NF
+                                         | SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0)
+                return ret;
+
+        ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+                                         | SND_SOC_DAIFMT_NB_NF
+                                         | SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
+static struct snd_soc_ops speyside_wm8962_ops = {
+        .hw_params = speyside_wm8962_hw_params,
+};
+
+static struct snd_soc_dai_link speyside_wm8962_dai[] = {
+        {
+                .name = "CPU",
+                .stream_name = "CPU",
+                .cpu_dai_name = "samsung-i2s.0",
+                .codec_dai_name = "wm8962",
+                .platform_name = "samsung-audio",
+                .codec_name = "wm8962.1-001a",
+                .ops = &speyside_wm8962_ops,
+        },
+};
+
+static const struct snd_kcontrol_new controls[] = {
+        SOC_DAPM_PIN_SWITCH("Main Speaker"),
+};
+
+static struct snd_soc_dapm_widget widgets[] = {
+        SND_SOC_DAPM_HP("Headphone", NULL),
+        SND_SOC_DAPM_MIC("Headset Mic", NULL),
+
+        SND_SOC_DAPM_MIC("DMIC", NULL),
+
+        SND_SOC_DAPM_SPK("Main Speaker", NULL),
+};
+
+static struct snd_soc_dapm_route audio_paths[] = {
+        { "Headphone", NULL, "HPOUTL" },
+        { "Headphone", NULL, "HPOUTR" },
+
+        { "Main Speaker", NULL, "SPKOUTL" },
+        { "Main Speaker", NULL, "SPKOUTR" },
+
+        { "MICBIAS", NULL, "Headset Mic" },
+        { "IN4L", NULL, "MICBIAS" },
+        { "IN4R", NULL, "MICBIAS" },
+
+        { "MICBIAS", NULL, "DMIC" },
+        { "DMICDAT", NULL, "MICBIAS" },
+};
+
+static struct snd_soc_jack speyside_wm8962_headset;
+
+/* Headset jack detection DAPM pins */
+static struct snd_soc_jack_pin speyside_wm8962_headset_pins[] = {
+        {
+                .pin = "Headset Mic",
+                .mask = SND_JACK_MICROPHONE,
+        },
+        {
+                .pin = "Headphone",
+                .mask = SND_JACK_MICROPHONE,
+        },
+};
+
+static int speyside_wm8962_late_probe(struct snd_soc_card *card)
+{
+        struct snd_soc_codec *codec = card->rtd[0].codec;
+        struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+        int ret;
+
+        ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
+                                     32768, SND_SOC_CLOCK_IN);
+        if (ret < 0)
+                return ret;
+
+        ret = snd_soc_jack_new(codec, "Headset",
+                               SND_JACK_HEADSET | SND_JACK_BTN_0,
+                               &speyside_wm8962_headset);
+        if (ret)
+                return ret;
+
+        ret = snd_soc_jack_add_pins(&speyside_wm8962_headset,
+                                    ARRAY_SIZE(speyside_wm8962_headset_pins),
+                                    speyside_wm8962_headset_pins);
+        if (ret)
+                return ret;
+
+        wm8962_mic_detect(codec, &speyside_wm8962_headset);
+
+        return 0;
+}
+
+static struct snd_soc_card speyside_wm8962 = {
+        .name = "Speyside WM8962",
+        .dai_link = speyside_wm8962_dai,
+        .num_links = ARRAY_SIZE(speyside_wm8962_dai),
+
+        .set_bias_level = speyside_wm8962_set_bias_level,
+        .set_bias_level_post = speyside_wm8962_set_bias_level_post,
+
+        .controls = controls,
+        .num_controls = ARRAY_SIZE(controls),
+        .dapm_widgets = widgets,
+        .num_dapm_widgets = ARRAY_SIZE(widgets),
+        .dapm_routes = audio_paths,
+        .num_dapm_routes = ARRAY_SIZE(audio_paths),
+
+        .late_probe = speyside_wm8962_late_probe,
+};
+
+static __devinit int speyside_wm8962_probe(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = &speyside_wm8962;
+        int ret;
+
+        card->dev = &pdev->dev;
+
+        ret = snd_soc_register_card(card);
+        if (ret) {
+                dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
+                        ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int __devexit speyside_wm8962_remove(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+        snd_soc_unregister_card(card);
+
+        return 0;
+}
+
+static struct platform_driver speyside_wm8962_driver = {
+        .driver = {
+                .name = "speyside-wm8962",
+                .owner = THIS_MODULE,
+                .pm = &snd_soc_pm_ops,
+        },
+        .probe = speyside_wm8962_probe,
+        .remove = __devexit_p(speyside_wm8962_remove),
+};
+
+static int __init speyside_wm8962_audio_init(void)
+{
+        return platform_driver_register(&speyside_wm8962_driver);
+}
+module_init(speyside_wm8962_audio_init);
+
+static void __exit speyside_wm8962_audio_exit(void)
+{
+        platform_driver_unregister(&speyside_wm8962_driver);
+}
+module_exit(speyside_wm8962_audio_exit);
+
+MODULE_DESCRIPTION("Speyside WM8962 audio support");
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:speyside-wm8962");
diff --git a/sound/soc/sh/fsi-ak4642.c b/sound/soc/sh/fsi-ak4642.c
new file mode 100644
index 00000000000..770a71a1536
--- /dev/null
+++ b/sound/soc/sh/fsi-ak4642.c
@@ -0,0 +1,209 @@
+/*
+ * FSI-AK464x sound support for ms7724se
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <sound/sh_fsi.h>
+
+struct fsi_ak4642_data {
+        const char *name;
+        const char *card;
+        const char *cpu_dai;
+        const char *codec;
+        const char *platform;
+        int id;
+};
+
+static int fsi_ak4642_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_dai *codec = rtd->codec_dai;
+        struct snd_soc_dai *cpu = rtd->cpu_dai;
+        int ret;
+
+        ret = snd_soc_dai_set_fmt(codec, SND_SOC_DAIFMT_LEFT_J |
+                                         SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0)
+                return ret;
+
+        ret = snd_soc_dai_set_sysclk(codec, 0, 11289600, 0);
+        if (ret < 0)
+                return ret;
+
+        ret = snd_soc_dai_set_fmt(cpu, SND_SOC_DAIFMT_LEFT_J |
+                                       SND_SOC_DAIFMT_CBS_CFS);
+
+        return ret;
+}
+
+static struct snd_soc_dai_link fsi_dai_link = {
+        .codec_dai_name = "ak4642-hifi",
+        .init           = fsi_ak4642_dai_init,
+};
+
+static struct snd_soc_card fsi_soc_card  = {
+        .dai_link       = &fsi_dai_link,
+        .num_links      = 1,
+};
+
+static struct platform_device *fsi_snd_device;
+
+static int fsi_ak4642_probe(struct platform_device *pdev)
+{
+        int ret = -ENOMEM;
+        const struct platform_device_id *id_entry;
+        struct fsi_ak4642_data *pdata;
+
+        id_entry = pdev->id_entry;
+        if (!id_entry) {
+                dev_err(&pdev->dev, "unknown fsi ak4642\n");
+                return -ENODEV;
+        }
+
+        pdata = (struct fsi_ak4642_data *)id_entry->driver_data;
+
+        fsi_snd_device = platform_device_alloc("soc-audio", pdata->id);
+        if (!fsi_snd_device)
+                goto out;
+
+        fsi_dai_link.name               = pdata->name;
+        fsi_dai_link.stream_name        = pdata->name;
+        fsi_dai_link.cpu_dai_name       = pdata->cpu_dai;
+        fsi_dai_link.platform_name      = pdata->platform;
+        fsi_dai_link.codec_name         = pdata->codec;
+        fsi_soc_card.name               = pdata->card;
+
+        platform_set_drvdata(fsi_snd_device, &fsi_soc_card);
+        ret = platform_device_add(fsi_snd_device);
+
+        if (ret)
+                platform_device_put(fsi_snd_device);
+
+out:
+        return ret;
+}
+
+static int fsi_ak4642_remove(struct platform_device *pdev)
+{
+        platform_device_unregister(fsi_snd_device);
+        return 0;
+}
+
+static struct fsi_ak4642_data fsi_a_ak4642 = {
+        .name           = "AK4642",
+        .card           = "FSIA-AK4642",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "ak4642-codec.0-0012",
+        .platform       = "sh_fsi.0",
+        .id             = FSI_PORT_A,
+};
+
+static struct fsi_ak4642_data fsi_b_ak4642 = {
+        .name           = "AK4642",
+        .card           = "FSIB-AK4642",
+        .cpu_dai        = "fsib-dai",
+        .codec          = "ak4642-codec.0-0012",
+        .platform       = "sh_fsi.0",
+        .id             = FSI_PORT_B,
+};
+
+static struct fsi_ak4642_data fsi_a_ak4643 = {
+        .name           = "AK4643",
+        .card           = "FSIA-AK4643",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "ak4642-codec.0-0013",
+        .platform       = "sh_fsi.0",
+        .id             = FSI_PORT_A,
+};
+
+static struct fsi_ak4642_data fsi_b_ak4643 = {
+        .name           = "AK4643",
+        .card           = "FSIB-AK4643",
+        .cpu_dai        = "fsib-dai",
+        .codec          = "ak4642-codec.0-0013",
+        .platform       = "sh_fsi.0",
+        .id             = FSI_PORT_B,
+};
+
+static struct fsi_ak4642_data fsi2_a_ak4642 = {
+        .name           = "AK4642",
+        .card           = "FSI2A-AK4642",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "ak4642-codec.0-0012",
+        .platform       = "sh_fsi2",
+        .id             = FSI_PORT_A,
+};
+
+static struct fsi_ak4642_data fsi2_b_ak4642 = {
+        .name           = "AK4642",
+        .card           = "FSI2B-AK4642",
+        .cpu_dai        = "fsib-dai",
+        .codec          = "ak4642-codec.0-0012",
+        .platform       = "sh_fsi2",
+        .id             = FSI_PORT_B,
+};
+
+static struct fsi_ak4642_data fsi2_a_ak4643 = {
+        .name           = "AK4643",
+        .card           = "FSI2A-AK4643",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "ak4642-codec.0-0013",
+        .platform       = "sh_fsi2",
+        .id             = FSI_PORT_A,
+};
+
+static struct fsi_ak4642_data fsi2_b_ak4643 = {
+        .name           = "AK4643",
+        .card           = "FSI2B-AK4643",
+        .cpu_dai        = "fsib-dai",
+        .codec          = "ak4642-codec.0-0013",
+        .platform       = "sh_fsi2",
+        .id             = FSI_PORT_B,
+};
+
+static struct platform_device_id fsi_id_table[] = {
+        /* FSI */
+        { "sh_fsi_a_ak4642",    (kernel_ulong_t)&fsi_a_ak4642 },
+        { "sh_fsi_b_ak4642",    (kernel_ulong_t)&fsi_b_ak4642 },
+        { "sh_fsi_a_ak4643",    (kernel_ulong_t)&fsi_a_ak4643 },
+        { "sh_fsi_b_ak4643",    (kernel_ulong_t)&fsi_b_ak4643 },
+
+        /* FSI 2 */
+        { "sh_fsi2_a_ak4642",   (kernel_ulong_t)&fsi2_a_ak4642 },
+        { "sh_fsi2_b_ak4642",   (kernel_ulong_t)&fsi2_b_ak4642 },
+        { "sh_fsi2_a_ak4643",   (kernel_ulong_t)&fsi2_a_ak4643 },
+        { "sh_fsi2_b_ak4643",   (kernel_ulong_t)&fsi2_b_ak4643 },
+        {},
+};
+
+static struct platform_driver fsi_ak4642 = {
+        .driver = {
+                .name   = "fsi-ak4642-audio",
+        },
+        .probe          = fsi_ak4642_probe,
+        .remove         = fsi_ak4642_remove,
+        .id_table       = fsi_id_table,
+};
+
+static int __init fsi_ak4642_init(void)
+{
+        return platform_driver_register(&fsi_ak4642);
+}
+
+static void __exit fsi_ak4642_exit(void)
+{
+        platform_driver_unregister(&fsi_ak4642);
+}
+
+module_init(fsi_ak4642_init);
+module_exit(fsi_ak4642_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Generic SH4 FSI-AK4642 sound card");
+MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
diff --git a/sound/soc/sh/fsi-da7210.c b/sound/soc/sh/fsi-da7210.c
new file mode 100644
index 00000000000..59553fd8c2f
--- /dev/null
+++ b/sound/soc/sh/fsi-da7210.c
@@ -0,0 +1,79 @@
+/*
+ * fsi-da7210.c
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <sound/sh_fsi.h>
+
+static int fsi_da7210_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_dai *codec = rtd->codec_dai;
+        struct snd_soc_dai *cpu = rtd->cpu_dai;
+        int ret;
+
+        ret = snd_soc_dai_set_fmt(codec,
+                                   SND_SOC_DAIFMT_I2S |
+                                   SND_SOC_DAIFMT_CBM_CFM);
+        if (ret < 0)
+                return ret;
+
+        ret = snd_soc_dai_set_fmt(cpu, SND_SOC_DAIFMT_I2S |
+                                       SND_SOC_DAIFMT_CBS_CFS);
+
+        return ret;
+}
+
+static struct snd_soc_dai_link fsi_da7210_dai = {
+        .name           = "DA7210",
+        .stream_name    = "DA7210",
+        .cpu_dai_name   = "fsib-dai", /* FSI B */
+        .codec_dai_name = "da7210-hifi",
+        .platform_name  = "sh_fsi.0",
+        .codec_name     = "da7210-codec.0-001a",
+        .init           = fsi_da7210_init,
+};
+
+static struct snd_soc_card fsi_soc_card = {
+        .name           = "FSI-DA7210",
+        .dai_link       = &fsi_da7210_dai,
+        .num_links      = 1,
+};
+
+static struct platform_device *fsi_da7210_snd_device;
+
+static int __init fsi_da7210_sound_init(void)
+{
+        int ret;
+
+        fsi_da7210_snd_device = platform_device_alloc("soc-audio", FSI_PORT_B);
+        if (!fsi_da7210_snd_device)
+                return -ENOMEM;
+
+        platform_set_drvdata(fsi_da7210_snd_device, &fsi_soc_card);
+        ret = platform_device_add(fsi_da7210_snd_device);
+        if (ret)
+                platform_device_put(fsi_da7210_snd_device);
+
+        return ret;
+}
+
+static void __exit fsi_da7210_sound_exit(void)
+{
+        platform_device_unregister(fsi_da7210_snd_device);
+}
+
+module_init(fsi_da7210_sound_init);
+module_exit(fsi_da7210_sound_exit);
+
+/* Module information */
+MODULE_DESCRIPTION("ALSA SoC FSI DA2710");
+MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/sh/fsi-hdmi.c b/sound/soc/sh/fsi-hdmi.c
new file mode 100644
index 00000000000..d3d9fd88068
--- /dev/null
+++ b/sound/soc/sh/fsi-hdmi.c
@@ -0,0 +1,127 @@
+/*
+ * FSI - HDMI sound support
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <sound/sh_fsi.h>
+
+struct fsi_hdmi_data {
+        const char *cpu_dai;
+        const char *card;
+        int id;
+};
+
+static int fsi_hdmi_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_dai *cpu = rtd->cpu_dai;
+        int ret;
+
+        ret = snd_soc_dai_set_fmt(cpu, SND_SOC_DAIFMT_CBM_CFM);
+
+        return ret;
+}
+
+static struct snd_soc_dai_link fsi_dai_link = {
+        .name           = "HDMI",
+        .stream_name    = "HDMI",
+        .codec_dai_name = "sh_mobile_hdmi-hifi",
+        .platform_name  = "sh_fsi2",
+        .codec_name     = "sh-mobile-hdmi",
+        .init           = fsi_hdmi_dai_init,
+};
+
+static struct snd_soc_card fsi_soc_card  = {
+        .dai_link       = &fsi_dai_link,
+        .num_links      = 1,
+};
+
+static struct platform_device *fsi_snd_device;
+
+static int fsi_hdmi_probe(struct platform_device *pdev)
+{
+        int ret = -ENOMEM;
+        const struct platform_device_id *id_entry;
+        struct fsi_hdmi_data *pdata;
+
+        id_entry = pdev->id_entry;
+        if (!id_entry) {
+                dev_err(&pdev->dev, "unknown fsi hdmi\n");
+                return -ENODEV;
+        }
+
+        pdata = (struct fsi_hdmi_data *)id_entry->driver_data;
+
+        fsi_snd_device = platform_device_alloc("soc-audio", pdata->id);
+        if (!fsi_snd_device)
+                goto out;
+
+        fsi_dai_link.cpu_dai_name       = pdata->cpu_dai;
+        fsi_soc_card.name               = pdata->card;
+
+        platform_set_drvdata(fsi_snd_device, &fsi_soc_card);
+        ret = platform_device_add(fsi_snd_device);
+
+        if (ret)
+                platform_device_put(fsi_snd_device);
+
+out:
+        return ret;
+}
+
+static int fsi_hdmi_remove(struct platform_device *pdev)
+{
+        platform_device_unregister(fsi_snd_device);
+        return 0;
+}
+
+static struct fsi_hdmi_data fsi2_a_hdmi = {
+        .cpu_dai        = "fsia-dai",
+        .card           = "FSI2A-HDMI",
+        .id             = FSI_PORT_A,
+};
+
+static struct fsi_hdmi_data fsi2_b_hdmi = {
+        .cpu_dai        = "fsib-dai",
+        .card           = "FSI2B-HDMI",
+        .id             = FSI_PORT_B,
+};
+
+static struct platform_device_id fsi_id_table[] = {
+        /* FSI 2 */
+        { "sh_fsi2_a_hdmi",     (kernel_ulong_t)&fsi2_a_hdmi },
+        { "sh_fsi2_b_hdmi",     (kernel_ulong_t)&fsi2_b_hdmi },
+        {},
+};
+
+static struct platform_driver fsi_hdmi = {
+        .driver = {
+                .name   = "fsi-hdmi-audio",
+        },
+        .probe          = fsi_hdmi_probe,
+        .remove         = fsi_hdmi_remove,
+        .id_table       = fsi_id_table,
+};
+
+static int __init fsi_hdmi_init(void)
+{
+        return platform_driver_register(&fsi_hdmi);
+}
+
+static void __exit fsi_hdmi_exit(void)
+{
+        platform_driver_unregister(&fsi_hdmi);
+}
+
+module_init(fsi_hdmi_init);
+module_exit(fsi_hdmi_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Generic SH4 FSI-HDMI sound card");
+MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
diff --git a/sound/soc/tegra/tegra30_dam.c b/sound/soc/tegra/tegra30_dam.c
new file mode 100644
index 00000000000..d308179110c
--- /dev/null
+++ b/sound/soc/tegra/tegra30_dam.c
@@ -0,0 +1,650 @@
+/*
+ * tegra30_dam.c - Tegra 30 DAM driver
+ *
+ * Author: Nikesh Oswal <noswal@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <sound/soc.h>
+#include "tegra30_dam.h"
+#include "tegra30_ahub.h"
+
+#define DRV_NAME "tegra30-dam"
+
+static struct tegra30_dam_context       *dams_cont_info[TEGRA30_NR_DAM_IFC];
+
+enum {
+        dam_ch_in0 = 0x0,
+        dam_ch_in1,
+        dam_ch_out,
+        dam_ch_maxnum
+} tegra30_dam_chtype;
+
+struct tegra30_dam_src_step_table  step_table[] = {
+        { 8000, 44100, 80 },
+        { 8000, 48000, 1 },
+        { 16000, 44100, 160 },
+        { 16000, 48000, 1 },
+        { 44100, 8000, 441 },
+        { 48000, 8000, 0 },
+        { 44100, 16000, 441 },
+        { 48000, 16000, 0 },
+};
+
+static void tegra30_dam_set_output_samplerate(struct tegra30_dam_context *dam,
+                int fsout);
+static void tegra30_dam_set_input_samplerate(struct tegra30_dam_context *dam,
+                int fsin);
+static int tegra30_dam_set_step_reset(struct tegra30_dam_context *dam,
+                int insample, int outsample);
+static void tegra30_dam_ch0_set_step(struct tegra30_dam_context *dam, int step);
+
+static inline void tegra30_dam_writel(struct tegra30_dam_context *dam,
+                        u32 val, u32 reg)
+{
+#ifdef CONFIG_PM
+        dam->reg_cache[reg >> 2] = val;
+#endif
+        __raw_writel(val, dam->damregs + reg);
+}
+
+static inline u32 tegra30_dam_readl(struct tegra30_dam_context *dam, u32 reg)
+{
+        u32 val = __raw_readl(dam->damregs + reg);
+
+        return val;
+}
+
+#ifdef CONFIG_PM
+int tegra30_dam_resume(int ifc)
+{
+        int i = 0;
+        struct tegra30_dam_context *dam;
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return -EINVAL;
+
+        dam = dams_cont_info[ifc];
+
+        if (dam->in_use) {
+                tegra30_dam_enable_clock(ifc);
+
+                for (i = 0; i <= TEGRA30_DAM_CTRL_REGINDEX; i++) {
+                        if ((i == TEGRA30_DAM_CTRL_RSVD_6) ||
+                                (i == TEGRA30_DAM_CTRL_RSVD_10))
+                                continue;
+
+                        tegra30_dam_writel(dam, dam->reg_cache[i],
+                                                (i << 2));
+                }
+
+                tegra30_dam_disable_clock(ifc);
+        }
+
+        return 0;
+}
+#endif
+
+void tegra30_dam_disable_clock(int ifc)
+{
+        struct tegra30_dam_context *dam;
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return;
+
+        dam =  dams_cont_info[ifc];
+        clk_disable(dam->dam_clk);
+        tegra30_ahub_disable_clocks();
+}
+
+int tegra30_dam_enable_clock(int ifc)
+{
+        struct tegra30_dam_context *dam;
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return -EINVAL;
+
+        dam =  dams_cont_info[ifc];
+        tegra30_ahub_enable_clocks();
+        clk_enable(dam->dam_clk);
+
+        return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int tegra30_dam_show(struct seq_file *s, void *unused)
+{
+#define REG(r) { r, #r }
+        static const struct {
+                int offset;
+                const char *name;
+        } regs[] = {
+                REG(TEGRA30_DAM_CTRL),
+                REG(TEGRA30_DAM_CLIP),
+                REG(TEGRA30_DAM_CLIP_THRESHOLD),
+                REG(TEGRA30_DAM_AUDIOCIF_OUT_CTRL),
+                REG(TEGRA30_DAM_CH0_CTRL),
+                REG(TEGRA30_DAM_CH0_CONV),
+                REG(TEGRA30_DAM_AUDIOCIF_CH0_CTRL),
+                REG(TEGRA30_DAM_CH1_CTRL),
+                REG(TEGRA30_DAM_CH1_CONV),
+                REG(TEGRA30_DAM_AUDIOCIF_CH1_CTRL),
+        };
+#undef REG
+
+        struct tegra30_dam_context *dam = s->private;
+        int i;
+
+        clk_enable(dam->dam_clk);
+
+        for (i = 0; i < ARRAY_SIZE(regs); i++) {
+                u32 val = tegra30_dam_readl(dam, regs[i].offset);
+                seq_printf(s, "%s = %08x\n", regs[i].name, val);
+        }
+
+        clk_disable(dam->dam_clk);
+
+        return 0;
+}
+
+static int tegra30_dam_debug_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, tegra30_dam_show, inode->i_private);
+}
+
+static const struct file_operations tegra30_dam_debug_fops = {
+        .open    = tegra30_dam_debug_open,
+        .read    = seq_read,
+        .llseek  = seq_lseek,
+        .release = single_release,
+};
+
+static void tegra30_dam_debug_add(struct tegra30_dam_context *dam, int id)
+{
+        char name[] = DRV_NAME ".0";
+
+        snprintf(name, sizeof(name), DRV_NAME".%1d", id);
+        dam->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
+                        dam, &tegra30_dam_debug_fops);
+}
+
+static void tegra30_dam_debug_remove(struct tegra30_dam_context *dam)
+{
+        if (dam->debug)
+                debugfs_remove(dam->debug);
+}
+#else
+static inline void tegra30_dam_debug_add(struct tegra30_dam_context *dam,
+                                                int id)
+{
+}
+
+static inline void tegra30_dam_debug_remove(struct tegra30_dam_context *dam)
+{
+}
+#endif
+
+int tegra30_dam_allocate_controller()
+{
+        int i = 0;
+        struct tegra30_dam_context *dam = NULL;
+
+        for (i = 0; i < TEGRA30_NR_DAM_IFC; i++) {
+
+                dam =  dams_cont_info[i];
+
+                if (!dam->in_use) {
+                        dam->in_use = true;
+                        return i;
+                }
+        }
+
+        return -ENOENT;
+}
+
+int tegra30_dam_allocate_channel(int ifc, int chid)
+{
+        struct tegra30_dam_context *dam = NULL;
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return -EINVAL;
+
+        dam =  dams_cont_info[ifc];
+
+        if (!dam->ch_alloc[chid]) {
+                dam->ch_alloc[chid] = true;
+                return 0;
+        }
+
+        return -ENOENT;
+}
+
+int tegra30_dam_free_channel(int ifc, int chid)
+{
+        struct tegra30_dam_context *dam = NULL;
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return -EINVAL;
+
+        dam =  dams_cont_info[ifc];
+
+        if (dam->ch_alloc[chid]) {
+                dam->ch_alloc[chid] = false;
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+int tegra30_dam_free_controller(int ifc)
+{
+        struct tegra30_dam_context *dam = NULL;
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return -EINVAL;
+
+        dam =  dams_cont_info[ifc];
+
+        if (!dam->ch_alloc[dam_ch_in0] &&
+                !dam->ch_alloc[dam_ch_in1]) {
+                dam->in_use = false;
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+void tegra30_dam_set_samplerate(int ifc, int chid, int samplerate)
+{
+        struct tegra30_dam_context *dam = dams_cont_info[ifc];
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return;
+
+        switch (chid) {
+        case dam_ch_in0:
+                tegra30_dam_set_input_samplerate(dam, samplerate);
+                dam->ch_insamplerate[dam_ch_in0] = samplerate;
+                tegra30_dam_set_step_reset(dam, samplerate, dam->outsamplerate);
+                break;
+        case dam_ch_in1:
+                if (samplerate != dam->outsamplerate)
+                        return;
+                dam->ch_insamplerate[dam_ch_in1] = samplerate;
+                break;
+        case dam_ch_out:
+                tegra30_dam_set_output_samplerate(dam, samplerate);
+                dam->outsamplerate = samplerate;
+                break;
+        default:
+                break;
+        }
+}
+
+void tegra30_dam_set_output_samplerate(struct tegra30_dam_context *dam,
+                                        int fsout)
+{
+        u32 val;
+
+        val = tegra30_dam_readl(dam, TEGRA30_DAM_CTRL);
+        val &= ~TEGRA30_DAM_CTRL_FSOUT_MASK;
+
+        switch (fsout) {
+        case TEGRA30_AUDIO_SAMPLERATE_8000:
+                val |= TEGRA30_DAM_CTRL_FSOUT_FS8;
+                break;
+        case TEGRA30_AUDIO_SAMPLERATE_16000:
+                val |= TEGRA30_DAM_CTRL_FSOUT_FS16;
+                break;
+        case TEGRA30_AUDIO_SAMPLERATE_44100:
+                val |= TEGRA30_DAM_CTRL_FSOUT_FS44;
+                break;
+        case TEGRA30_AUDIO_SAMPLERATE_48000:
+                val |= TEGRA30_DAM_CTRL_FSOUT_FS48;
+                break;
+        default:
+                break;
+        }
+
+        tegra30_dam_writel(dam, val, TEGRA30_DAM_CTRL);
+}
+
+void tegra30_dam_set_input_samplerate(struct tegra30_dam_context *dam, int fsin)
+{
+        u32 val;
+
+        val = tegra30_dam_readl(dam, TEGRA30_DAM_CH0_CTRL);
+        val &= ~TEGRA30_DAM_CH0_CTRL_FSIN_MASK;
+
+        switch (fsin) {
+        case TEGRA30_AUDIO_SAMPLERATE_8000:
+                val |= TEGRA30_DAM_CH0_CTRL_FSIN_FS8;
+                break;
+        case TEGRA30_AUDIO_SAMPLERATE_16000:
+                val |= TEGRA30_DAM_CH0_CTRL_FSIN_FS16;
+                break;
+        case TEGRA30_AUDIO_SAMPLERATE_44100:
+                val |= TEGRA30_DAM_CH0_CTRL_FSIN_FS44;
+                break;
+        case TEGRA30_AUDIO_SAMPLERATE_48000:
+                val |= TEGRA30_DAM_CH0_CTRL_FSIN_FS48;
+                break;
+        default:
+                break;
+        }
+
+        tegra30_dam_writel(dam, val, TEGRA30_DAM_CH0_CTRL);
+}
+
+int tegra30_dam_set_step_reset(struct tegra30_dam_context *dam,
+                int insample, int outsample)
+{
+        int step_reset = 0;
+        int i = 0;
+
+        for (i = 0; i < ARRAY_SIZE(step_table); i++) {
+                if ((insample == step_table[i].insample) &&
+                        (outsample == step_table[i].outsample))
+                        step_reset = step_table[i].stepreset;
+        }
+
+        tegra30_dam_ch0_set_step(dam, step_reset);
+
+        return 0;
+}
+
+void tegra30_dam_ch0_set_step(struct tegra30_dam_context *dam, int step)
+{
+        u32 val;
+
+        val = tegra30_dam_readl(dam, TEGRA30_DAM_CH0_CTRL);
+        val &= ~TEGRA30_DAM_CH0_CTRL_STEP_MASK;
+        val |= step << TEGRA30_DAM_CH0_CTRL_STEP_SHIFT;
+        tegra30_dam_writel(dam, val, TEGRA30_DAM_CH0_CTRL);
+}
+
+int tegra30_dam_set_gain(int ifc, int chid, int gain)
+{
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return -EINVAL;
+
+        switch (chid) {
+        case dam_ch_in0:
+                tegra30_dam_writel(dams_cont_info[ifc], gain,
+                        TEGRA30_DAM_CH0_CONV);
+                break;
+        case dam_ch_in1:
+                tegra30_dam_writel(dams_cont_info[ifc], gain,
+                        TEGRA30_DAM_CH1_CONV);
+                break;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+int tegra30_dam_set_acif(int ifc, int chid, unsigned int audio_channels,
+        unsigned int audio_bits, unsigned int client_channels,
+        unsigned int client_bits)
+{
+        unsigned int reg;
+        unsigned int value = 0;
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return -EINVAL;
+
+        /*ch0 takes input as mono/16bit always*/
+        if ((chid == dam_ch_in0) &&
+                ((client_channels != 1) || (client_bits != 16)))
+                return -EINVAL;
+
+        value |= TEGRA30_CIF_MONOCONV_COPY;
+        value |= TEGRA30_CIF_STEREOCONV_CH0;
+        value |= (audio_channels-1)  << TEGRA30_AUDIO_CHANNELS_SHIFT;
+        value |= (((audio_bits>>2)-1)<<TEGRA30_AUDIO_BITS_SHIFT);
+        value |= (client_channels-1)  << TEGRA30_CLIENT_CHANNELS_SHIFT;
+        value |= (((client_bits>>2)-1)<<TEGRA30_CLIENT_BITS_SHIFT);
+
+        switch (chid) {
+        case dam_ch_out:
+                value |= TEGRA30_CIF_DIRECTION_TX;
+                reg = TEGRA30_DAM_AUDIOCIF_OUT_CTRL;
+                break;
+        case dam_ch_in0:
+                value |= TEGRA30_CIF_DIRECTION_RX;
+                reg = TEGRA30_DAM_AUDIOCIF_CH0_CTRL;
+                break;
+        case dam_ch_in1:
+                value |= TEGRA30_CIF_DIRECTION_RX;
+                reg = TEGRA30_DAM_AUDIOCIF_CH1_CTRL;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        tegra30_dam_writel(dams_cont_info[ifc], value, reg);
+
+        return 0;
+}
+
+void tegra30_dam_enable(int ifc, int on, int chid)
+{
+        u32 old_val, val, enreg;
+        struct tegra30_dam_context *dam = dams_cont_info[ifc];
+
+        if (ifc >= TEGRA30_NR_DAM_IFC)
+                return;
+
+        if (chid == dam_ch_in0)
+                enreg = TEGRA30_DAM_CH0_CTRL;
+        else
+                enreg = TEGRA30_DAM_CH1_CTRL;
+
+        old_val = val = tegra30_dam_readl(dam, enreg);
+
+        if (on) {
+                if (!dam->ch_enable_refcnt[chid]++)
+                        val |= TEGRA30_DAM_CH0_CTRL_EN;
+        } else if (dam->ch_enable_refcnt[chid]) {
+                dam->ch_enable_refcnt[chid]--;
+                if (!dam->ch_enable_refcnt[chid])
+                        val &= ~TEGRA30_DAM_CH0_CTRL_EN;
+        }
+
+        if (val != old_val)
+                tegra30_dam_writel(dam, val, enreg);
+
+        old_val = val = tegra30_dam_readl(dam, TEGRA30_DAM_CTRL);
+
+        if (dam->ch_enable_refcnt[dam_ch_in0] ||
+                dam->ch_enable_refcnt[dam_ch_in1])
+                val |= TEGRA30_DAM_CTRL_DAM_EN;
+        else
+                val &= ~TEGRA30_DAM_CTRL_DAM_EN;
+
+        if (old_val != val)
+                tegra30_dam_writel(dam, val, TEGRA30_DAM_CTRL);
+}
+
+void tegra30_dam_ch0_set_datasync(struct tegra30_dam_context *dam, int datasync)
+{
+        u32 val;
+
+        val = tegra30_dam_readl(dam, TEGRA30_DAM_CH0_CTRL);
+        val &= ~TEGRA30_DAM_CH0_CTRL_DATA_SYNC_MASK;
+        val |= datasync << TEGRA30_DAM_DATA_SYNC_SHIFT;
+        tegra30_dam_writel(dam, val, TEGRA30_DAM_CH0_CTRL);
+}
+
+void tegra30_dam_ch1_set_datasync(struct tegra30_dam_context *dam, int datasync)
+{
+        u32 val;
+
+        val = tegra30_dam_readl(dam, TEGRA30_DAM_CH1_CTRL);
+        val &= ~TEGRA30_DAM_CH1_CTRL_DATA_SYNC_MASK;
+        val |= datasync << TEGRA30_DAM_DATA_SYNC_SHIFT;
+        tegra30_dam_writel(dam, val, TEGRA30_DAM_CH1_CTRL);
+}
+
+void tegra30_dam_enable_clip_counter(struct tegra30_dam_context *dam, int on)
+{
+        u32 val;
+
+        val = tegra30_dam_readl(dam, TEGRA30_DAM_CLIP);
+        val &= ~TEGRA30_DAM_CLIP_COUNTER_ENABLE;
+        val |= on ?  TEGRA30_DAM_CLIP_COUNTER_ENABLE : 0;
+        tegra30_dam_writel(dam, val, TEGRA30_DAM_CLIP);
+}
+
+static int __devinit tegra30_dam_probe(struct platform_device *pdev)
+{
+        struct resource *res,  *region;
+        struct tegra30_dam_context *dam;
+        int ret = 0;
+#ifdef CONFIG_PM
+        int i;
+#endif
+        int clkm_rate;
+
+        if ((pdev->id < 0) ||
+                (pdev->id >= TEGRA30_NR_DAM_IFC)) {
+                dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
+                return -EINVAL;
+        }
+
+        dams_cont_info[pdev->id] = devm_kzalloc(&pdev->dev,
+                                        sizeof(struct tegra30_dam_context),
+                                        GFP_KERNEL);
+        if (!dams_cont_info[pdev->id]) {
+                dev_err(&pdev->dev, "Can't allocate dam context\n");
+                ret = -ENOMEM;
+                goto exit;
+        }
+        dam = dams_cont_info[pdev->id];
+
+        dam->dam_clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(dam->dam_clk)) {
+                dev_err(&pdev->dev, "Can't retrieve dam clock\n");
+                ret = PTR_ERR(dam->dam_clk);
+                goto err_free;
+        }
+        clkm_rate = clk_get_rate(clk_get_parent(dam->dam_clk));
+        while (clkm_rate > 12000000)
+                clkm_rate >>= 1;
+
+        clk_set_rate(dam->dam_clk,clkm_rate);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "No memory 0 resource\n");
+                ret = -ENODEV;
+                goto err_clk_put_dam;
+        }
+
+        region = devm_request_mem_region(&pdev->dev, res->start,
+                        resource_size(res), pdev->name);
+        if (!region) {
+                dev_err(&pdev->dev, "Memory region 0 already claimed\n");
+                ret = -EBUSY;
+                goto err_clk_put_dam;
+        }
+
+        dam->damregs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!dam->damregs) {
+                dev_err(&pdev->dev, "ioremap 0 failed\n");
+                ret = -ENOMEM;
+                goto err_clk_put_dam;
+        }
+
+#ifdef CONFIG_PM
+        /* cache the POR values of DAM regs*/
+        tegra30_dam_enable_clock(pdev->id);
+
+        for (i = 0; i <= TEGRA30_DAM_CTRL_REGINDEX; i++) {
+                if ((i == TEGRA30_DAM_CTRL_RSVD_6) ||
+                        (i == TEGRA30_DAM_CTRL_RSVD_10))
+                        continue;
+
+                        dam->reg_cache[i] =
+                                tegra30_dam_readl(dam, i << 2);
+        }
+
+        tegra30_dam_disable_clock(pdev->id);
+#endif
+
+        platform_set_drvdata(pdev, dam);
+
+        tegra30_dam_debug_add(dam, pdev->id);
+
+        return 0;
+
+err_clk_put_dam:
+        clk_put(dam->dam_clk);
+err_free:
+        dams_cont_info[pdev->id] = NULL;
+exit:
+        return ret;
+}
+
+static int __devexit tegra30_dam_remove(struct platform_device *pdev)
+{
+        struct tegra30_dam_context *dam;
+
+        dam = platform_get_drvdata(pdev);
+        clk_put(dam->dam_clk);
+        tegra30_dam_debug_remove(dam);
+        dams_cont_info[pdev->id] = NULL;
+
+        return 0;
+}
+
+static struct platform_driver tegra30_dam_driver = {
+        .probe = tegra30_dam_probe,
+        .remove = __devexit_p(tegra30_dam_remove),
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init tegra30_dam_modinit(void)
+{
+        return platform_driver_register(&tegra30_dam_driver);
+}
+module_init(tegra30_dam_modinit);
+
+static void __exit tegra30_dam_modexit(void)
+{
+        platform_driver_unregister(&tegra30_dam_driver);
+}
+module_exit(tegra30_dam_modexit);
+
+MODULE_AUTHOR("Nikesh Oswal <noswal@nvidia.com>");
+MODULE_DESCRIPTION("Tegra 30 DAM driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/tegra/tegra30_dam.h b/sound/soc/tegra/tegra30_dam.h
new file mode 100644
index 00000000000..371e8139eec
--- /dev/null
+++ b/sound/soc/tegra/tegra30_dam.h
@@ -0,0 +1,163 @@
+/*
+ * tegra30_dam.h - Tegra 30 DAM driver.
+ *
+ * Author: Nikesh Oswal <noswal@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __TEGRA30_DAM_H
+#define __TEGRA30_DAM_H
+
+/* Register offsets from TEGRA30_DAM*_BASE */
+#define TEGRA30_DAM_CTRL                                0
+#define TEGRA30_DAM_CLIP                                4
+#define TEGRA30_DAM_CLIP_THRESHOLD                      8
+#define TEGRA30_DAM_AUDIOCIF_OUT_CTRL                   0x0C
+#define TEGRA30_DAM_CH0_CTRL                            0x10
+#define TEGRA30_DAM_CH0_CONV                            0x14
+#define TEGRA30_DAM_AUDIOCIF_CH0_CTRL                   0x1C
+#define TEGRA30_DAM_CH1_CTRL                            0x20
+#define TEGRA30_DAM_CH1_CONV                            0x24
+#define TEGRA30_DAM_AUDIOCIF_CH1_CTRL                   0x2C
+#define TEGRA30_DAM_CTRL_REGINDEX                       (TEGRA30_DAM_AUDIOCIF_CH1_CTRL >> 2)
+#define TEGRA30_DAM_CTRL_RSVD_6                         6
+#define TEGRA30_DAM_CTRL_RSVD_10                        10
+
+#define TEGRA30_NR_DAM_IFC                              3
+
+#define TEGRA30_DAM_NUM_INPUT_CHANNELS                  2
+
+/* Fields in TEGRA30_DAM_CTRL */
+#define TEGRA30_DAM_CTRL_SOFT_RESET_ENABLE              (1 << 31)
+#define TEGRA30_DAM_CTRL_FSOUT_SHIFT                    4
+#define TEGRA30_DAM_CTRL_FSOUT_MASK                     (0xf << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
+#define TEGRA30_DAM_FS_8KHZ                             0
+#define TEGRA30_DAM_FS_16KHZ                            1
+#define TEGRA30_DAM_FS_44KHZ                            2
+#define TEGRA30_DAM_FS_48KHZ                            3
+#define TEGRA30_DAM_CTRL_FSOUT_FS8                      (TEGRA30_DAM_FS_8KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
+#define TEGRA30_DAM_CTRL_FSOUT_FS16                     (TEGRA30_DAM_FS_16KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
+#define TEGRA30_DAM_CTRL_FSOUT_FS44                     (TEGRA30_DAM_FS_44KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
+#define TEGRA30_DAM_CTRL_FSOUT_FS48                     (TEGRA30_DAM_FS_48KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
+#define TEGRA30_DAM_CTRL_CG_EN                          (1 << 1)
+#define TEGRA30_DAM_CTRL_DAM_EN                         (1 << 0)
+
+
+/* Fields in TEGRA30_DAM_CLIP */
+#define TEGRA30_DAM_CLIP_COUNTER_ENABLE                 (1 << 31)
+#define TEGRA30_DAM_CLIP_COUNT_MASK                     0x7fffffff
+
+
+/* Fields in TEGRA30_DAM_CH0_CTRL */
+#define TEGRA30_STEP_RESET                              1
+#define TEGRA30_DAM_DATA_SYNC                           1
+#define TEGRA30_DAM_DATA_SYNC_SHIFT                     4
+#define TEGRA30_DAM_CH0_CTRL_FSIN_SHIFT                 8
+#define TEGRA30_DAM_CH0_CTRL_STEP_SHIFT                 16
+#define TEGRA30_DAM_CH0_CTRL_STEP_MASK                  (0xffff << 16)
+#define TEGRA30_DAM_CH0_CTRL_STEP_RESET                 (TEGRA30_STEP_RESET << 16)
+#define TEGRA30_DAM_CH0_CTRL_FSIN_MASK                  (0xf << 8)
+#define TEGRA30_DAM_CH0_CTRL_FSIN_FS8                   (TEGRA30_DAM_FS_8KHZ << 8)
+#define TEGRA30_DAM_CH0_CTRL_FSIN_FS16                  (TEGRA30_DAM_FS_16KHZ << 8)
+#define TEGRA30_DAM_CH0_CTRL_FSIN_FS44                  (TEGRA30_DAM_FS_44KHZ << 8)
+#define TEGRA30_DAM_CH0_CTRL_FSIN_FS48                  (TEGRA30_DAM_FS_48KHZ << 8)
+#define TEGRA30_DAM_CH0_CTRL_DATA_SYNC_MASK             (0xf << TEGRA30_DAM_DATA_SYNC_SHIFT)
+#define TEGRA30_DAM_CH0_CTRL_DATA_SYNC                  (TEGRA30_DAM_DATA_SYNC << TEGRA30_DAM_DATA_SYNC_SHIFT)
+#define TEGRA30_DAM_CH0_CTRL_EN                         (1 << 0)
+
+
+/* Fields in TEGRA30_DAM_CH0_CONV */
+#define TEGRA30_DAM_GAIN                                1
+#define TEGRA30_DAM_GAIN_SHIFT                          0
+#define TEGRA30_DAM_CH0_CONV_GAIN                       (TEGRA30_DAM_GAIN << TEGRA30_DAM_GAIN_SHIFT)
+
+/* Fields in TEGRA30_DAM_CH1_CTRL */
+#define TEGRA30_DAM_CH1_CTRL_DATA_SYNC_MASK             (0xf << TEGRA30_DAM_DATA_SYNC_SHIFT)
+#define TEGRA30_DAM_CH1_CTRL_DATA_SYNC                  (TEGRA30_DAM_DATA_SYNC << TEGRA30_DAM_DATA_SYNC_SHIFT)
+#define TEGRA30_DAM_CH1_CTRL_EN                         (1 << 0)
+
+/* Fields in TEGRA30_DAM_CH1_CONV */
+#define TEGRA30_DAM_CH1_CONV_GAIN                       (TEGRA30_DAM_GAIN << TEGRA30_DAM_GAIN_SHIFT)
+
+#define TEGRA30_AUDIO_CHANNELS_SHIFT                    24
+#define TEGRA30_AUDIO_CHANNELS_MASK                     (7 << TEGRA30_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_CLIENT_CHANNELS_SHIFT                   16
+#define TEGRA30_CLIENT_CHANNELS_MASK                    (7 << TEGRA30_CLIENT_CHANNELS_SHIFT)
+#define TEGRA30_AUDIO_BITS_SHIFT                        12
+#define TEGRA30_AUDIO_BITS_MASK                         (7 << TEGRA30_AUDIO_BITS_SHIFT)
+#define TEGRA30_CLIENT_BITS_SHIFT                       8
+#define TEGRA30_CLIENT_BITS_MASK                        (7 << TEGRA30_CLIENT_BITS_SHIFT)
+#define TEGRA30_CIF_DIRECTION_TX                        (0 << 2)
+#define TEGRA30_CIF_DIRECTION_RX                        (1 << 2)
+#define TEGRA30_CIF_BIT24                               5
+#define TEGRA30_CIF_BIT16                               3
+#define TEGRA30_CIF_CH1                                 0
+#define TEGRA30_CIF_MONOCONV_COPY                       (1<<0)
+#define TEGRA30_CIF_STEREOCONV_CH0                      (0<<4)
+
+/*
+* Audio Samplerates
+*/
+#define TEGRA30_AUDIO_SAMPLERATE_8000                   8000
+#define TEGRA30_AUDIO_SAMPLERATE_16000                  16000
+#define TEGRA30_AUDIO_SAMPLERATE_44100                  44100
+#define TEGRA30_AUDIO_SAMPLERATE_48000                  48000
+
+#define TEGRA30_DAM_CHIN0_SRC                           0
+#define TEGRA30_DAM_CHIN1                               1
+#define TEGRA30_DAM_CHOUT                               2
+#define TEGRA30_DAM_ENABLE                              1
+#define TEGRA30_DAM_DISABLE                             0
+
+struct tegra30_dam_context {
+        int                     outsamplerate;
+        bool                    ch_alloc[TEGRA30_DAM_NUM_INPUT_CHANNELS];
+        int                     ch_enable_refcnt[TEGRA30_DAM_NUM_INPUT_CHANNELS];
+        int                     ch_insamplerate[TEGRA30_DAM_NUM_INPUT_CHANNELS];
+#ifdef CONFIG_PM
+        int                     reg_cache[TEGRA30_DAM_CTRL_REGINDEX + 1];
+#endif
+        struct clk              *dam_clk;
+        bool                    in_use;
+        void __iomem            *damregs;
+        struct dentry           *debug;
+};
+
+struct tegra30_dam_src_step_table {
+        int insample;
+        int outsample;
+        int stepreset;
+};
+
+#ifdef CONFIG_PM
+int tegra30_dam_resume(int ifc);
+#endif
+void tegra30_dam_disable_clock(int ifc);
+int tegra30_dam_enable_clock(int ifc);
+int tegra30_dam_allocate_controller(void);
+int tegra30_dam_allocate_channel(int ifc, int chid);
+int tegra30_dam_free_channel(int ifc, int chid);
+int tegra30_dam_free_controller(int ifc);
+void tegra30_dam_set_samplerate(int ifc, int chtype, int samplerate);
+int tegra30_dam_set_gain(int ifc, int chtype, int gain);
+int tegra30_dam_set_acif(int ifc, int chtype, unsigned int audio_channels,
+        unsigned int audio_bits, unsigned int client_channels,
+        unsigned int client_bits);
+void tegra30_dam_enable(int ifc, int on, int chtype);
+
+#endif
diff --git a/sound/soc/tegra/tegra30_spdif.c b/sound/soc/tegra/tegra30_spdif.c
new file mode 100644
index 00000000000..038127c0afb
--- /dev/null
+++ b/sound/soc/tegra/tegra30_spdif.c
@@ -0,0 +1,505 @@
+/*
+ * tegra30_spdif.c - Tegra30 SPDIF driver
+ *
+ * Author: Sumit Bhattacharya <sumitb@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ *
+ * Copyright (c) 2009-2011, NVIDIA Corporation.
+ * Scott Peterson <speterson@nvidia.com>
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Iliyan Malchev <malchev@google.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <mach/iomap.h>
+#include <mach/hdmi-audio.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "tegra30_spdif.h"
+
+#define DRV_NAME "tegra30-spdif"
+
+static inline void tegra30_spdif_write(struct tegra30_spdif *spdif,
+                                                u32 reg, u32 val)
+{
+        __raw_writel(val, spdif->regs + reg);
+}
+
+static inline u32 tegra30_spdif_read(struct tegra30_spdif *spdif, u32 reg)
+{
+        return __raw_readl(spdif->regs + reg);
+}
+
+static void tegra30_spdif_enable_clocks(struct tegra30_spdif *spdif)
+{
+        clk_enable(spdif->clk_spdif_out);
+        tegra30_ahub_enable_clocks();
+}
+
+static void tegra30_spdif_disable_clocks(struct tegra30_spdif *spdif)
+{
+        tegra30_ahub_disable_clocks();
+        clk_disable(spdif->clk_spdif_out);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int tegra30_spdif_show(struct seq_file *s, void *unused)
+{
+#define REG(r) { r, #r }
+        static const struct {
+                int offset;
+                const char *name;
+        } regs[] = {
+                REG(TEGRA30_SPDIF_CTRL),
+                REG(TEGRA30_SPDIF_STROBE_CTRL),
+                REG(TEGRA30_SPDIF_CIF_TXD_CTRL),
+                REG(TEGRA30_SPDIF_CIF_RXD_CTRL),
+                REG(TEGRA30_SPDIF_CIF_TXU_CTRL),
+                REG(TEGRA30_SPDIF_CIF_RXU_CTRL),
+                REG(TEGRA30_SPDIF_CH_STA_RX_A),
+                REG(TEGRA30_SPDIF_CH_STA_RX_B),
+                REG(TEGRA30_SPDIF_CH_STA_RX_C),
+                REG(TEGRA30_SPDIF_CH_STA_RX_D),
+                REG(TEGRA30_SPDIF_CH_STA_RX_E),
+                REG(TEGRA30_SPDIF_CH_STA_RX_F),
+                REG(TEGRA30_SPDIF_CH_STA_TX_A),
+                REG(TEGRA30_SPDIF_CH_STA_TX_B),
+                REG(TEGRA30_SPDIF_CH_STA_TX_C),
+                REG(TEGRA30_SPDIF_CH_STA_TX_D),
+                REG(TEGRA30_SPDIF_CH_STA_TX_E),
+                REG(TEGRA30_SPDIF_CH_STA_TX_F),
+                REG(TEGRA30_SPDIF_FLOWCTL_CTRL),
+                REG(TEGRA30_SPDIF_TX_STEP),
+                REG(TEGRA30_SPDIF_FLOW_STATUS),
+                REG(TEGRA30_SPDIF_FLOW_TOTAL),
+                REG(TEGRA30_SPDIF_FLOW_OVER),
+                REG(TEGRA30_SPDIF_FLOW_UNDER),
+                REG(TEGRA30_SPDIF_LCOEF_1_4_0),
+                REG(TEGRA30_SPDIF_LCOEF_1_4_1),
+                REG(TEGRA30_SPDIF_LCOEF_1_4_2),
+                REG(TEGRA30_SPDIF_LCOEF_1_4_3),
+                REG(TEGRA30_SPDIF_LCOEF_1_4_4),
+                REG(TEGRA30_SPDIF_LCOEF_1_4_5),
+                REG(TEGRA30_SPDIF_LCOEF_2_4_0),
+                REG(TEGRA30_SPDIF_LCOEF_2_4_1),
+                REG(TEGRA30_SPDIF_LCOEF_2_4_2),
+        };
+#undef REG
+
+        struct tegra30_spdif *spdif = s->private;
+        int i;
+
+        tegra30_spdif_enable_clocks(spdif);
+
+        for (i = 0; i < ARRAY_SIZE(regs); i++) {
+                u32 val = tegra30_spdif_read(spdif, regs[i].offset);
+                seq_printf(s, "%s = %08x\n", regs[i].name, val);
+        }
+
+        tegra30_spdif_disable_clocks(spdif);
+
+        return 0;
+}
+
+static int tegra30_spdif_debug_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, tegra30_spdif_show, inode->i_private);
+}
+
+static const struct file_operations tegra30_spdif_debug_fops = {
+        .open    = tegra30_spdif_debug_open,
+        .read    = seq_read,
+        .llseek  = seq_lseek,
+        .release = single_release,
+};
+
+static void tegra30_spdif_debug_add(struct tegra30_spdif *spdif)
+{
+        char name[] = DRV_NAME;
+
+        spdif->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
+                                        spdif, &tegra30_spdif_debug_fops);
+}
+
+static void tegra30_spdif_debug_remove(struct tegra30_spdif *spdif)
+{
+        if (spdif->debug)
+                debugfs_remove(spdif->debug);
+}
+#else
+static inline void tegra30_spdif_debug_add(struct tegra30_spdif *spdif)
+{
+}
+
+static inline void tegra30_spdif_debug_remove(struct tegra30_spdif *spdif)
+{
+}
+#endif
+
+int tegra30_spdif_startup(struct snd_pcm_substream *substream,
+                        struct snd_soc_dai *dai)
+{
+        struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+        int ret = 0;
+
+        tegra30_spdif_enable_clocks(spdif);
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                ret = tegra30_ahub_allocate_tx_fifo(&spdif->txcif,
+                                        &spdif->playback_dma_data.addr,
+                                        &spdif->playback_dma_data.req_sel);
+                spdif->playback_dma_data.wrap = 4;
+                spdif->playback_dma_data.width = 32;
+                tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_SPDIF_RX0,
+                                               spdif->txcif);
+        }
+
+        tegra30_spdif_disable_clocks(spdif);
+
+        return ret;
+}
+
+void tegra30_spdif_shutdown(struct snd_pcm_substream *substream,
+                        struct snd_soc_dai *dai)
+{
+        struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+
+        tegra30_spdif_enable_clocks(spdif);
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_SPDIF_RX0);
+                tegra30_ahub_free_tx_fifo(spdif->txcif);
+        }
+
+        tegra30_spdif_disable_clocks(spdif);
+}
+
+static int tegra30_spdif_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params,
+                                struct snd_soc_dai *dai)
+{
+        struct device *dev = substream->pcm->card->dev;
+        struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+        int ret, srate, spdifclock;
+
+        if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
+                dev_err(dev, "spdif capture is not supported\n");
+                return -EINVAL;
+        }
+
+        spdif->reg_ctrl &= ~TEGRA30_SPDIF_CTRL_BIT_MODE_MASK;
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_PACK_ENABLE;
+                spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        srate = params_rate(params);
+        spdif->reg_ch_sta_a &= ~TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK;
+        spdif->reg_ch_sta_b &= ~TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK;
+        switch (srate) {
+        case 32000:
+                spdifclock = 4096000;
+                spdif->reg_ch_sta_a |=
+                        TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000;
+                spdif->reg_ch_sta_b |=
+                        TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000;
+                break;
+        case 44100:
+                spdifclock = 5644800;
+                spdif->reg_ch_sta_a |=
+                        TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100;
+                spdif->reg_ch_sta_b |=
+                        TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100;
+                break;
+        case 48000:
+                spdifclock = 6144000;
+                spdif->reg_ch_sta_a |=
+                        TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000;
+                spdif->reg_ch_sta_b |=
+                        TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000;
+                break;
+        case 88200:
+                spdifclock = 11289600;
+                spdif->reg_ch_sta_a |=
+                        TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200;
+                spdif->reg_ch_sta_b |=
+                        TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200;
+                break;
+        case 96000:
+                spdifclock = 12288000;
+                spdif->reg_ch_sta_a |=
+                        TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000;
+                spdif->reg_ch_sta_b |=
+                        TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000;
+                break;
+        case 176400:
+                spdifclock = 22579200;
+                spdif->reg_ch_sta_a |=
+                        TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400;
+                spdif->reg_ch_sta_b |=
+                        TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400;
+                break;
+        case 192000:
+                spdifclock = 24576000;
+                spdif->reg_ch_sta_a |=
+                        TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000;
+                spdif->reg_ch_sta_b |=
+                        TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
+        if (ret) {
+                dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
+                return ret;
+        }
+
+        tegra30_spdif_enable_clocks(spdif);
+
+        tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_A,
+                                                spdif->reg_ch_sta_a);
+        tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_B,
+                                                spdif->reg_ch_sta_b);
+
+        tegra30_spdif_disable_clocks(spdif);
+
+        ret = tegra_hdmi_setup_audio_freq_source(srate, SPDIF);
+        if (ret) {
+                dev_err(dev, "Can't set HDMI audio freq source: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+static void tegra30_spdif_start_playback(struct tegra30_spdif *spdif)
+{
+        tegra30_ahub_enable_tx_fifo(spdif->txcif);
+        spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_TX_EN_ENABLE |
+                                TEGRA30_SPDIF_CTRL_TC_EN_ENABLE;
+        tegra30_spdif_write(spdif, TEGRA30_SPDIF_CTRL, spdif->reg_ctrl);
+}
+
+static void tegra30_spdif_stop_playback(struct tegra30_spdif *spdif)
+{
+        tegra30_ahub_disable_tx_fifo(spdif->txcif);
+        spdif->reg_ctrl &= ~(TEGRA30_SPDIF_CTRL_TX_EN_ENABLE |
+                                TEGRA30_SPDIF_CTRL_TC_EN_ENABLE);
+        tegra30_spdif_write(spdif, TEGRA30_SPDIF_CTRL, spdif->reg_ctrl);
+}
+
+static int tegra30_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
+                                struct snd_soc_dai *dai)
+{
+        struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+
+        switch (cmd) {
+        case SNDRV_PCM_TRIGGER_START:
+        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+        case SNDRV_PCM_TRIGGER_RESUME:
+                tegra30_spdif_enable_clocks(spdif);
+                tegra30_spdif_start_playback(spdif);
+                break;
+        case SNDRV_PCM_TRIGGER_STOP:
+        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+        case SNDRV_PCM_TRIGGER_SUSPEND:
+                tegra30_spdif_stop_playback(spdif);
+                tegra30_spdif_disable_clocks(spdif);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int tegra30_spdif_probe(struct snd_soc_dai *dai)
+{
+        struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+
+        dai->playback_dma_data = &spdif->playback_dma_data;
+        dai->capture_dma_data = NULL;
+
+        return 0;
+}
+
+static struct snd_soc_dai_ops tegra30_spdif_dai_ops = {
+        .startup        = tegra30_spdif_startup,
+        .shutdown       = tegra30_spdif_shutdown,
+        .hw_params      = tegra30_spdif_hw_params,
+        .trigger        = tegra30_spdif_trigger,
+};
+
+struct snd_soc_dai_driver tegra30_spdif_dai = {
+        .name = DRV_NAME,
+        .probe = tegra30_spdif_probe,
+        .playback = {
+                .channels_min = 2,
+                .channels_max = 2,
+                .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
+                                SNDRV_PCM_RATE_48000,
+                .formats = SNDRV_PCM_FMTBIT_S16_LE,
+        },
+        .ops = &tegra30_spdif_dai_ops,
+};
+
+static __devinit int tegra30_spdif_platform_probe(struct platform_device *pdev)
+{
+        struct tegra30_spdif *spdif;
+        struct resource *mem, *memregion;
+        int ret;
+        u32 reg_val;
+
+        spdif = kzalloc(sizeof(struct tegra30_spdif), GFP_KERNEL);
+        if (!spdif) {
+                dev_err(&pdev->dev, "Can't allocate tegra30_spdif\n");
+                ret = -ENOMEM;
+                goto exit;
+        }
+        dev_set_drvdata(&pdev->dev, spdif);
+
+        spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out");
+        if (IS_ERR(spdif->clk_spdif_out)) {
+                dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
+                ret = PTR_ERR(spdif->clk_spdif_out);
+                goto err_free;
+        }
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "No memory resource\n");
+                ret = -ENODEV;
+                goto err_clk_put_spdif;
+        }
+
+        memregion = request_mem_region(mem->start, resource_size(mem),
+                                        DRV_NAME);
+        if (!memregion) {
+                dev_err(&pdev->dev, "Memory region already claimed\n");
+                ret = -EBUSY;
+                goto err_clk_put_spdif;
+        }
+
+        spdif->regs = ioremap(mem->start, resource_size(mem));
+        if (!spdif->regs) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err_release;
+        }
+
+        tegra30_spdif_enable_clocks(spdif);
+
+        reg_val = TEGRA30_SPDIF_CIF_TXD_CTRL_DIRECTION_RXCIF |
+                TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT16 |
+                TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT16 |
+                TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH2 |
+                TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH2 |
+                (3 << TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT);
+
+        tegra30_spdif_write(spdif, TEGRA30_SPDIF_CIF_TXD_CTRL, reg_val);
+
+        tegra30_spdif_disable_clocks(spdif);
+
+        ret = snd_soc_register_dai(&pdev->dev, &tegra30_spdif_dai);
+        if (ret) {
+                dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
+                ret = -ENOMEM;
+                goto err_unmap;
+        }
+
+        tegra30_spdif_debug_add(spdif);
+
+        return 0;
+
+err_unmap:
+        iounmap(spdif->regs);
+err_release:
+        release_mem_region(mem->start, resource_size(mem));
+err_clk_put_spdif:
+        clk_put(spdif->clk_spdif_out);
+err_free:
+        kfree(spdif);
+exit:
+        return ret;
+}
+
+static int __devexit tegra30_spdif_platform_remove(struct platform_device *pdev)
+{
+        struct tegra30_spdif *spdif = dev_get_drvdata(&pdev->dev);
+        struct resource *res;
+
+        snd_soc_unregister_dai(&pdev->dev);
+
+        tegra30_spdif_debug_remove(spdif);
+
+        iounmap(spdif->regs);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(res->start, resource_size(res));
+
+        clk_put(spdif->clk_spdif_out);
+
+        kfree(spdif);
+
+        return 0;
+}
+
+static struct platform_driver tegra30_spdif_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+        },
+        .probe = tegra30_spdif_platform_probe,
+        .remove = __devexit_p(tegra30_spdif_platform_remove),
+};
+
+static int __init snd_tegra30_spdif_init(void)
+{
+        return platform_driver_register(&tegra30_spdif_driver);
+}
+module_init(snd_tegra30_spdif_init);
+
+static void __exit snd_tegra30_spdif_exit(void)
+{
+        platform_driver_unregister(&tegra30_spdif_driver);
+}
+module_exit(snd_tegra30_spdif_exit);
+
+MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
+MODULE_DESCRIPTION("Tegra30 SPDIF ASoC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/tegra/tegra30_spdif.h b/sound/soc/tegra/tegra30_spdif.h
new file mode 100644
index 00000000000..c4763c31b25
--- /dev/null
+++ b/sound/soc/tegra/tegra30_spdif.h
@@ -0,0 +1,777 @@
+/*
+ * tegra30_spdif.h - Definitions for Tegra30 SPDIF driver
+ *
+ * Author: Sumit Bhattacharya <sumitb@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ *
+ * Copyright (c) 2009-2011, NVIDIA Corporation.
+ * Scott Peterson <speterson@nvidia.com>
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Iliyan Malchev <malchev@google.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __TEGRA30_SPDIF_H__
+#define __TEGRA30_SPDIF_H__
+
+#include "tegra_pcm.h"
+#include "tegra30_ahub.h"
+
+/* Register offsets from TEGRA_SPDIF_BASE */
+
+#define TEGRA30_SPDIF_CTRL                      0x0
+#define TEGRA30_SPDIF_STROBE_CTRL               0x4
+#define TEGRA30_SPDIF_CIF_TXD_CTRL              0x08
+#define TEGRA30_SPDIF_CIF_RXD_CTRL              0x0C
+#define TEGRA30_SPDIF_CIF_TXU_CTRL              0x10
+#define TEGRA30_SPDIF_CIF_RXU_CTRL              0x14
+#define TEGRA30_SPDIF_CH_STA_RX_A               0x18
+#define TEGRA30_SPDIF_CH_STA_RX_B               0x1C
+#define TEGRA30_SPDIF_CH_STA_RX_C               0x20
+#define TEGRA30_SPDIF_CH_STA_RX_D               0x24
+#define TEGRA30_SPDIF_CH_STA_RX_E               0x28
+#define TEGRA30_SPDIF_CH_STA_RX_F               0x2C
+#define TEGRA30_SPDIF_CH_STA_TX_A               0x30
+#define TEGRA30_SPDIF_CH_STA_TX_B               0x34
+#define TEGRA30_SPDIF_CH_STA_TX_C               0x38
+#define TEGRA30_SPDIF_CH_STA_TX_D               0x3C
+#define TEGRA30_SPDIF_CH_STA_TX_E               0x40
+#define TEGRA30_SPDIF_CH_STA_TX_F               0x44
+#define TEGRA30_SPDIF_FLOWCTL_CTRL              0x70
+#define TEGRA30_SPDIF_TX_STEP                   0x74
+#define TEGRA30_SPDIF_FLOW_STATUS               0x78
+#define TEGRA30_SPDIF_FLOW_TOTAL                0x7c
+#define TEGRA30_SPDIF_FLOW_OVER                 0x80
+#define TEGRA30_SPDIF_FLOW_UNDER                0x84
+#define TEGRA30_SPDIF_LCOEF_1_4_0               0x88
+#define TEGRA30_SPDIF_LCOEF_1_4_1               0x8c
+#define TEGRA30_SPDIF_LCOEF_1_4_2               0x90
+#define TEGRA30_SPDIF_LCOEF_1_4_3               0x94
+#define TEGRA30_SPDIF_LCOEF_1_4_4               0x98
+#define TEGRA30_SPDIF_LCOEF_1_4_5               0x9c
+#define TEGRA30_SPDIF_LCOEF_2_4_0               0xa0
+#define TEGRA30_SPDIF_LCOEF_2_4_1               0xa4
+#define TEGRA30_SPDIF_LCOEF_2_4_2               0xa8
+
+/* Fields in TEGRA30_SPDIF_CTRL */
+#define TEGRA30_SPDIF_CTRL_FLOWCTL_EN_ENABLE    (1<<31)
+#define TEGRA30_SPDIF_CTRL_CAP_LC_LEFT_CH       (1<<30)
+#define TEGRA30_SPDIF_CTRL_RX_EN_ENABLE         (1<<29)
+#define TEGRA30_SPDIF_CTRL_TX_EN_ENABLE         (1<<28)
+#define TEGRA30_SPDIF_CTRL_TC_EN_ENABLE         (1<<27)
+#define TEGRA30_SPDIF_CTRL_TU_EN_ENABLE         (1<<26)
+#define TEGRA30_SPDIF_CTRL_IE_P_RSVD_ENABLE     (1<<23)
+#define TEGRA30_SPDIF_CTRL_IE_B_RSVD_ENABLE     (1<<22)
+#define TEGRA30_SPDIF_CTRL_IE_C_RSVD_ENABLE     (1<<21)
+#define TEGRA30_SPDIF_CTRL_IE_U_RSVD_ENABLE     (1<<20)
+#define TEGRA30_SPDIF_CTRL_LBK_EN_ENABLE        (1<<15)
+#define TEGRA30_SPDIF_CTRL_PACK_ENABLE          (1<<14)
+
+#define TEGRA30_SPDIF_BIT_MODE16                0
+#define TEGRA30_SPDIF_BIT_MODE20                1
+#define TEGRA30_SPDIF_BIT_MODE24                2
+#define TEGRA30_SPDIF_BIT_MODERAW               3
+
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT       12
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_MASK        (3                         << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT       (TEGRA30_SPDIF_BIT_MODE16  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_20BIT       (TEGRA30_SPDIF_BIT_MODE20  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_24BIT       (TEGRA30_SPDIF_BIT_MODE24  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_RAW         (TEGRA30_SPDIF_BIT_MODERAW << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+
+#define TEGRA30_SPDIF_CTRL_CG_EN_ENABLE         (1<<11)
+
+#define TEGRA30_SPDIF_CTRL_OBS_SEL_SHIFT        8
+#define TEGRA30_SPDIF_CTRL_OBS_SEL_NASK         (0x7 << TEGRA30_SPDIF_CTRL_OBS_SEL_SHIFT)
+
+#define TEGRA30_SPDIF_CTRL_SOFT_RESET_ENABLE    (1<<7)
+
+/* Fields in TEGRA30_SPDIF_STROBE_CTRL */
+#define TEGRA30_SPDIF_STROBE_CTRL_PERIOD_SHIFT          16
+#define TEGRA30_SPDIF_STROBE_CTRL_PERIOD_MASK           (0xff << TEGRA30_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_STROBE                (1<<15)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT    8
+#define TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_MASK     (0x1f << TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT    0
+#define TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK     (0x3f << TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CIF_TXD_CTRL */
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_MONO_CONV_COPY       (1<<0)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_TRUNCATE_CHOP        (1<<1)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_DIRECTION_RXCIF      (1<<2)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_REPLICATE_ENABLE     (1<<3)
+
+#define TEGRA30_SPDIF_CIF_STEREO_CH0                    0
+#define TEGRA30_SPDIF_CIF_STEREO_CH1                    1
+#define TEGRA30_SPDIF_CIF_STEREO_AVG                    2
+#define TEGRA30_SPDIF_CIF_STEREO_RSVD                   3
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT    4
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_MASK     \
+                (0x3                           << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_CH0      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_CH1      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_AVG      \
+                (TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_RSVD     \
+                (TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_EXPAND_ZERO                   0
+#define TEGRA30_SPDIF_CIF_EXPAND_ONE                    1
+#define TEGRA30_SPDIF_CIF_EXPAND_LFSR                   2
+#define TEGRA30_SPDIF_CIF_EXPAND_RSVD                   3
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT         6
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_MASK          \
+                (0x3                           << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_ZERO          \
+                (TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_ONE           \
+                (TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_LFSR          \
+                (TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_RSVD          \
+                (TEGRA30_SPDIF_CIF_EXPAND_RSVD << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_BIT4                          0
+#define TEGRA30_SPDIF_CIF_BIT8                          1
+#define TEGRA30_SPDIF_CIF_BIT12                         2
+#define TEGRA30_SPDIF_CIF_BIT16                         3
+#define TEGRA30_SPDIF_CIF_BIT20                         4
+#define TEGRA30_SPDIF_CIF_BIT24                         5
+#define TEGRA30_SPDIF_CIF_BIT28                         6
+#define TEGRA30_SPDIF_CIF_BIT32                         7
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT    8
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_MASK     \
+                (0x7                     << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT4          \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT8          \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT12         \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT16         \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT20         \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT24         \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT28         \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT32         \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT     12
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_MASK      \
+                (0x7                     << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT4           \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT8           \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT12          \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT16          \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT20          \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT24          \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT28          \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT32          \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_CH1                           0
+#define TEGRA30_SPDIF_CIF_CH2                           1
+#define TEGRA30_SPDIF_CIF_CH3                           2
+#define TEGRA30_SPDIF_CIF_CH4                           3
+#define TEGRA30_SPDIF_CIF_CH5                           4
+#define TEGRA30_SPDIF_CIF_CH6                           5
+#define TEGRA30_SPDIF_CIF_CH7                           6
+#define TEGRA30_SPDIF_CIF_CH8                           7
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT      16
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_MASK       \
+                (0x7                   << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH1           \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH2           \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH3           \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH4           \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH5           \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH6           \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH7           \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH8           \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT       24
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_MASK        \
+                (0x7                   << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH1            \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH2            \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH3            \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH4            \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH5            \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH6            \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH7            \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH8            \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT        28
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_MASK         (0x7 << TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_TEGRA30_SPDIF_CIF_RXD_CTRL */
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_MONO_CONV_COPY       (1<<0)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_TRUNCATE_CHOP        (1<<1)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_DIRECTION_RXCIF      (1<<2)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_REPLICATE_ENABLE     (1<<3)
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT    4
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_MASK     \
+                (0x3                           << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_CH0      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_CH1      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_AVG      \
+                (TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_RSVD     \
+                (TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT         6
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_MASK          \
+                (0x3                           << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_ZERO          \
+                (TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_ONE           \
+                (TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_LFSR          \
+                (TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_RSVD          \
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT    8
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_MASK     \
+                (0x7                     << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT4          \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT8          \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT12         \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT16         \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT20         \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT24         \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT28         \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT32         \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT     12
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_MASK      \
+                (0x7                     << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT4           \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT8           \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT12          \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT16          \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT20          \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT24          \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT28          \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT32          \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT 16
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_MASK       \
+                (0x7                   << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH1           \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH2           \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH3           \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH4           \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH5           \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH6           \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH7           \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH8           \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT 24
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_MASK  \
+                (0x7                   << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH1            \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH2            \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH3            \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH4            \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH5            \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH6            \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH7            \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH8            \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT        28
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_MASK         (0x7  << TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_TEGRA30_SPDIF_CIF_TXU_CTRL */
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_MONO_CONV_COPY       (1<<0)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_TRUNCATE_CHOP        (1<<1)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_DIRECTION_RXCIF      (1<<2)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_REPLICATE_ENABLE     (1<<3)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_SHIFT    4
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_MASK     \
+                (0x3                                    << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_CH0      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_CH1      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_AVG      \
+                (TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_RSVD     \
+                (TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT         6
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_MASK          \
+                (0x3                           << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_ZERO          \
+                (TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_ONE           \
+                (TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_LFSR          \
+                (TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_RSVD          \
+                (TEGRA30_SPDIF_CIF_EXPAND_RSVD << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT    8
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_MASK     \
+                (0x7                     << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT4          \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT8          \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT12         \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT16         \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT20         \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT24         \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT28         \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT32         \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT     12
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_MASK      \
+                (0x7                     << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT4           \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT8           \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT12          \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT16          \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT20          \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT24          \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT28          \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT32          \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT 16
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_MASK       \
+                (0x7                   << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH1           \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH2           \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH3           \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH4           \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH5           \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH6           \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH7           \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH8           \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT       24
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_MASK        \
+                (0x7                   << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH1            \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH2            \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH3            \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH4            \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH5            \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH6            \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH7            \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH8            \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT        28
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_MASK         (0x7 << TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_TEGRA30_SPDIF_CIF_RXU_CTRL */
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_MONO_CONV_COPY       (1<<0)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_TRUNCATE_CHOP        (1<<1)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_DIRECTION_RXCIF      (1<<2)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_REPLICATE_ENABLE     (1<<3)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_SHIFT    4
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_MASK     \
+                (0x3                           << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_CH0      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_CH1      \
+                (TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_AVG      \
+                (TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_RSVD     \
+                (TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT         6
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_MASK          \
+                (0x3                           << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_ZERO          \
+                (TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_ONE           \
+                (TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_LFSR          \
+                (TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_RSVD          \
+                (TEGRA30_SPDIF_CIF_EXPAND_RSVD << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT    8
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_MASK     \
+                (0x7                     << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT4          \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT8          \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT12         \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT16         \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT20         \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT24         \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT28         \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT32         \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT     12
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_MASK      \
+                (0x7                     << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT4           \
+                (TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT8           \
+                (TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT12          \
+                (TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT16          \
+                (TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT20          \
+                (TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT24          \
+                (TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT28          \
+                (TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT32          \
+                (TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT 16
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_MASK       \
+                (0x7                   << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH1           \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH2           \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH3           \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH4           \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH5           \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH6           \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH7           \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH8           \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT       24
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_MASK        \
+                (0x7                   << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH1            \
+                (TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH2            \
+                (TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH3            \
+                (TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH4            \
+                (TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH5            \
+                (TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH6            \
+                (TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH7            \
+                (TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH8            \
+                (TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT        28
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_MASK         (0x7 << TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_A */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_B */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_C */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_D */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_E */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_F */
+
+/*
+ * The 6-word receive channel data page buffer holds a block (192 frames) of
+ * channel status information. The order of receive is from LSB to MSB
+ * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
+ */
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_A */
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_22050                      0x4
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_24000                      0x6
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_32000                      0x3
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_44100                      0x0
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_48000                      0x2
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_88200                      0x8
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_96000                      0xA
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_176400                     0xC
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_192000                     0xE
+
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT               24
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK                \
+                (0xF                                 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_22050       \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_22050  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_24000               \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_24000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000               \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_32000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100               \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_44100  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000               \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_48000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200               \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_88200  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000               \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_96000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400              \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_176400 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000              \
+                (TEGRA30_SPDIF_CH_STA_TX_A_SF_192000 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_B */
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_8000                       0x6
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_11025                      0xA
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_12000                      0x2
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_16000                      0x8
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_22050                      0xB
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_24000                      0x9
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_32000                      0xC
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_44100                      0xF
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_48000                      0xD
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_88200                      0x7
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_96000                      0x5
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_176400                     0x3
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_192000                     0x1
+
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT          4
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK           \
+                (0xF                                 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_8000           \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_8000   << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_11025          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_11025  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_12000          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_12000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_16000          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_16000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_22050          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_22025  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_24000          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_24000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_32000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_44100  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_48000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_88200  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000          \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_96000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400         \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_176400 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000         \
+                (TEGRA30_SPDIF_CH_STA_TX_B_SF_192000 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_C */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_D */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_E */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_F */
+
+/* Fields in TEGRA30_SPDIF_FLOWCTL_CTRL */
+#define TEGRA30_SPDIF_FLOWCTL_CTRL_FILTER_QUAD          (1<<31)
+
+/* Fields in TEGRA30_SPDIF_TX_STEP */
+#define TEGRA30_SPDIF_TX_STEP_STEP_SIZE_SHIFT           0
+#define TEGRA30_SPDIF_TX_STEP_STEP_SIZE_MASK            (0xffff << TEGRA30_SPDIF_TX_STEP_STEP_SIZE_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_FLOW_STATUS */
+#define TEGRA30_SPDIF_FLOW_STATUS_COUNTER_EN_ENABLE     (1<<1)
+#define TEGRA30_SPDIF_FLOW_STATUS_MONITOR_CLR_CLEAR     (1<<2)
+#define TEGRA30_SPDIF_FLOW_STATUS_COUNTER_CLR_CLEAR     (1<<3)
+#define TEGRA30_SPDIF_FLOW_STATUS_MONITOR_INT_EN_ENABLE (1<<4)
+#define TEGRA30_SPDIF_FLOW_STATUS_FLOW_OVERFLOW_OVER    (1<<30)
+#define TEGRA30_SPDIF_FLOW_STATUS_FLOW_UNDERFLOW_UNDER  (1<<31)
+
+/* Fields in TEGRA30_SPDIF_FLOW_TOTAL */
+/* Fields in TEGRA30_SPDIF_FLOW_OVER */
+/* Fields in TEGRA30_SPDIF_FLOW_UNDER */
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_0 */
+#define TEGRA30_SPDIF_LCOEF_1_4_0_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_1_4_0_COEF_MASK             (0xffff << TEGRA30_TEGRA30_SPDIF_LCOEF_1_4_0_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_1 */
+#define TEGRA30_SPDIF_LCOEF_1_4_1_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_1_4_1_COEF_MASK             (0xffff << TEGRA30_SPDIF_LCOEF_1_4_1_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_2 */
+#define TEGRA30_SPDIF_LCOEF_1_4_2_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_1_4_2_COEF_MASK             (0xffff << TEGRA30_SPDIF_LCOEF_1_4_2_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_3 */
+#define TEGRA30_SPDIF_LCOEF_1_4_3_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_1_4_3_COEF_MASK             (0xffff << TEGRA30_SPDIF_LCOEF_1_4_3_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_4 */
+#define TEGRA30_SPDIF_LCOEF_1_4_4_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_1_4_4_COEF_MASK             (0xffff << TEGRA30_SPDIF_LCOEF_1_4_4_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_5 */
+#define TEGRA30_SPDIF_LCOEF_1_4_5_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_1_4_5_COEF_MASK             (0xffff << TEGRA30_SPDIF_LCOEF_1_4_5_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_0 */
+#define TEGRA30_SPDIF_LCOEF_2_4_0_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_2_4_0_COEF_MASK             (0xffff << TEGRA30_SPDIF_LCOEF_2_4_0_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_1 */
+#define TEGRA30_SPDIF_LCOEF_2_4_1_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_2_4_1_COEF_MASK             (0xffff << TEGRA30_SPDIF_LCOEF_2_4_1_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_2 */
+#define TEGRA30_SPDIF_LCOEF_2_4_2_COEF_SHIFT            0
+#define TEGRA30_SPDIF_LCOEF_2_4_2_COEF_MASK             (0xffff << SPDIF_LCOEF_2_4_2_COEF_SHIFT)
+
+struct tegra30_spdif {
+        struct clk *clk_spdif_out;
+        enum tegra30_ahub_txcif txcif;
+        struct tegra_pcm_dma_params playback_dma_data;
+        void __iomem *regs;
+        struct dentry *debug;
+        u32 reg_ctrl;
+        u32 reg_ch_sta_a;
+        u32 reg_ch_sta_b;
+};
+
+#endif
diff --git a/sound/soc/tegra/tegra_aic326x.c b/sound/soc/tegra/tegra_aic326x.c
new file mode 100644
index 00000000000..6d38934138b
--- /dev/null
+++ b/sound/soc/tegra/tegra_aic326x.c
@@ -0,0 +1,1281 @@
+/*
+ * tegra_aic326x.c - Tegra machine ASoC driver for boards using TI 3262 codec.
+ *
+ * Author: Vinod G. <vinodg@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ *
+ * (c) 2010, 2011 Nvidia Graphics Pvt. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <asm/mach-types.h>
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#ifdef CONFIG_SWITCH
+#include <linux/switch.h>
+#endif
+
+#include <mach/tegra_aic326x_pdata.h>
+
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "../codecs/tlv320aic326x.h"
+
+#include "tegra_pcm.h"
+#include "tegra_asoc_utils.h"
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#include "tegra20_das.h"
+#else
+#include "tegra30_ahub.h"
+#include "tegra30_i2s.h"
+#include "tegra30_dam.h"
+#endif
+
+
+#define DRV_NAME "tegra-snd-aic326x"
+
+#define GPIO_SPKR_EN    BIT(0)
+#define GPIO_HP_MUTE    BIT(1)
+#define GPIO_INT_MIC_EN BIT(2)
+#define GPIO_EXT_MIC_EN BIT(3)
+
+#define DAI_LINK_HIFI           0
+#define DAI_LINK_SPDIF          1
+#define DAI_LINK_BTSCO          2
+#define DAI_LINK_VOICE_CALL     3
+#define DAI_LINK_BT_VOICE_CALL  4
+#define NUM_DAI_LINKS   5
+
+extern int g_is_call_mode;
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+const char *tegra_i2s_dai_name[TEGRA30_NR_I2S_IFC] = {
+        "tegra30-i2s.0",
+        "tegra30-i2s.1",
+        "tegra30-i2s.2",
+        "tegra30-i2s.3",
+        "tegra30-i2s.4",
+};
+#endif
+
+struct tegra_aic326x {
+        struct tegra_asoc_utils_data util_data;
+        struct tegra_aic326x_platform_data *pdata;
+        struct regulator *audio_reg;
+        int gpio_requested;
+        bool init_done;
+        int is_call_mode;
+        int is_device_bt;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct codec_config codec_info[NUM_I2S_DEVICES];
+        struct snd_soc_card *pcard;
+#endif
+};
+
+static int tegra_aic326x_call_mode_info(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+        uinfo->count = 1;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 1;
+        return 0;
+}
+
+static int tegra_aic326x_call_mode_get(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct tegra_aic326x *machine = snd_kcontrol_chip(kcontrol);
+
+        ucontrol->value.integer.value[0] = machine->is_call_mode;
+
+        return 0;
+}
+
+static int tegra_aic326x_call_mode_put(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct tegra_aic326x *machine = snd_kcontrol_chip(kcontrol);
+        int is_call_mode_new = ucontrol->value.integer.value[0];
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        int codec_dap_id, codec_dap_sel, bb_dap_id, bb_dap_sel;
+#else /*assumes tegra3*/
+        int codec_index;
+        unsigned int i;
+#endif
+
+        if (machine->is_call_mode == is_call_mode_new)
+                return 0;
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        bb_dap_id = TEGRA20_DAS_DAP_ID_3;
+        bb_dap_sel = TEGRA20_DAS_DAP_SEL_DAP3;
+
+        if (machine->is_device_bt) {
+                codec_dap_id = TEGRA20_DAS_DAP_ID_4;
+                codec_dap_sel = TEGRA20_DAS_DAP_SEL_DAP4;
+        }
+        else {
+                codec_dap_id = TEGRA20_DAS_DAP_ID_2;
+                codec_dap_sel = TEGRA20_DAS_DAP_SEL_DAP2;
+        }
+#else /*assumes tegra3*/
+        if (machine->is_device_bt)
+                codec_index = BT_SCO;
+        else
+                codec_index = HIFI_CODEC;
+#endif
+
+        if (is_call_mode_new) {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+                tegra20_das_set_tristate(codec_dap_id, 1);
+                tegra20_das_set_tristate(bb_dap_id, 1);
+                tegra20_das_connect_dap_to_dap(codec_dap_id,
+                        bb_dap_sel, 0, 0, 0);
+                tegra20_das_connect_dap_to_dap(bb_dap_id,
+                        codec_dap_sel, 1, 0, 0);
+                tegra20_das_set_tristate(codec_dap_id, 0);
+                tegra20_das_set_tristate(bb_dap_id, 0);
+#else /*assumes tegra3*/
+                if (machine->codec_info[codec_index].rate == 0 ||
+                        machine->codec_info[codec_index].channels == 0)
+                                return -EINVAL;
+
+                for (i = 0; i < machine->pcard->num_links; i++)
+                        machine->pcard->dai_link[i].ignore_suspend = 1;
+
+                tegra30_make_voice_call_connections(
+                        &machine->codec_info[codec_index],
+                        &machine->codec_info[BASEBAND]);
+#endif
+        } else {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+                tegra20_das_set_tristate(codec_dap_id, 1);
+                tegra20_das_set_tristate(bb_dap_id, 1);
+                tegra20_das_connect_dap_to_dap(bb_dap_id,
+                        bb_dap_sel, 0, 0, 0);
+                tegra20_das_connect_dap_to_dap(codec_dap_id,
+                        codec_dap_sel, 0, 0, 0);
+                tegra20_das_set_tristate(codec_dap_id, 0);
+                tegra20_das_set_tristate(bb_dap_id, 0);
+#else /*assumes tegra3*/
+                tegra30_break_voice_call_connections(
+                        &machine->codec_info[codec_index],
+                        &machine->codec_info[BASEBAND]);
+
+                for (i = 0; i < machine->pcard->num_links; i++)
+                        machine->pcard->dai_link[i].ignore_suspend = 0;
+#endif
+        }
+
+        machine->is_call_mode = is_call_mode_new;
+        g_is_call_mode = machine->is_call_mode;
+
+        return 1;
+}
+
+struct snd_kcontrol_new tegra_aic326x_call_mode_control = {
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+        .name = "Call Mode Switch",
+        .private_value = 0xffff,
+        .info = tegra_aic326x_call_mode_info,
+        .get = tegra_aic326x_call_mode_get,
+        .put = tegra_aic326x_call_mode_put
+};
+
+static int tegra_aic326x_get_mclk(int srate)
+{
+        int mclk = 0;
+        switch (srate) {
+        case 8000:
+        case 16000:
+        case 24000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        default:
+                mclk = -EINVAL;
+                break;
+        }
+
+        return mclk;
+}
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static int tegra_aic326x_set_dam_cif(int dam_ifc, int srate,
+                        int channels, int bit_size, int src_on, int src_srate,
+                        int src_channels, int src_bit_size)
+{
+        tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN1, 0x1000);
+        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHOUT,
+                                srate);
+        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1,
+                                srate);
+        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
+                channels, bit_size, channels,
+                                bit_size);
+        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
+                channels, bit_size, channels,
+                                bit_size);
+
+        if (src_on) {
+                tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
+                tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+                        src_srate);
+                tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+                        src_channels, src_bit_size, 1, 16);
+        }
+
+        return 0;
+}
+#endif
+
+static int tegra_aic326x_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk, sample_size, daifmt;
+        int err;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+#endif
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                sample_size = 16;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        srate = params_rate(params);
+
+        mclk = tegra_aic326x_get_mclk(srate);
+        if (mclk < 0)
+                return mclk;
+
+        daifmt = SND_SOC_DAIFMT_I2S |
+                        SND_SOC_DAIFMT_NB_NF |
+                        SND_SOC_DAIFMT_CBS_CFS;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        err = snd_soc_dai_set_fmt(codec_dai, daifmt);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_fmt(cpu_dai, daifmt);
+        if (err < 0) {
+                dev_err(card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+                                        SND_SOC_CLOCK_IN);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai clock not set\n");
+                return err;
+        }
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        err = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAP_SEL_DAC1,
+                                        TEGRA20_DAS_DAP_ID_1);
+        if (err < 0) {
+                dev_err(card->dev, "failed to set dap-dac path\n");
+                return err;
+        }
+
+        err = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1,
+                                        TEGRA20_DAS_DAP_SEL_DAC1);
+        if (err < 0) {
+                dev_err(card->dev, "failed to set dac-dap path\n");
+                return err;
+        }
+#else /*assumes tegra3*/
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK  && i2s->is_dam_used)
+                tegra_aic326x_set_dam_cif(i2s->dam_ifc, srate,
+                        params_channels(params), sample_size, 0, 0, 0, 0);
+#endif
+
+        return 0;
+}
+
+static int tegra_aic326x_spdif_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk, min_mclk;
+        int err;
+
+        srate = params_rate(params);
+
+        mclk = tegra_aic326x_get_mclk(srate);
+        if (mclk < 0)
+                return mclk;
+
+        min_mclk = 128 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        return 0;
+}
+
+static int tegra_aic326x_bt_hw_params(struct snd_pcm_substream *substream,
+                struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        int err, srate, mclk, min_mclk, sample_size;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+#endif
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                sample_size = 16;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        srate = params_rate(params);
+
+        mclk = tegra_aic326x_get_mclk(srate);
+        if (mclk < 0)
+                return mclk;
+
+        min_mclk = 64 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        err = snd_soc_dai_set_fmt(rtd->cpu_dai,
+                        SND_SOC_DAIFMT_DSP_A |
+                        SND_SOC_DAIFMT_NB_NF |
+                        SND_SOC_DAIFMT_CBS_CFS);
+
+        if (err < 0) {
+                dev_err(rtd->codec->card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        err = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAP_SEL_DAC2,
+                                        TEGRA20_DAS_DAP_ID_4);
+        if (err < 0) {
+                dev_err(card->dev, "failed to set dac-dap path\n");
+                return err;
+        }
+
+        err = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_4,
+                                        TEGRA20_DAS_DAP_SEL_DAC2);
+        if (err < 0) {
+                dev_err(card->dev, "failed to set dac-dap path\n");
+                return err;
+        }
+#else
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && i2s->is_dam_used)
+                tegra_aic326x_set_dam_cif(i2s->dam_ifc, params_rate(params),
+                        params_channels(params), sample_size, 0, 0, 0, 0);
+#endif
+
+        return 0;
+}
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static int tegra_aic326x_startup(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(rtd->card);
+        struct codec_config *codec_info;
+        struct codec_config *bb_info;
+        int codec_index;
+
+        if (!i2s->is_dam_used)
+                return 0;
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                /*dam configuration*/
+                if (!i2s->dam_ch_refcount)
+                        i2s->dam_ifc = tegra30_dam_allocate_controller();
+
+                tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
+                i2s->dam_ch_refcount++;
+                tegra30_dam_enable_clock(i2s->dam_ifc);
+
+                tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                                (i2s->dam_ifc*2), i2s->txcif);
+
+                /*
+                *make the dam tx to i2s rx connection if this is the only client
+                *using i2s for playback
+                */
+                if (i2s->playback_ref_count == 1)
+                        tegra30_ahub_set_rx_cif_source(
+                                TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
+                                TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->dam_ifc);
+
+                /* enable the dam*/
+                tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_ENABLE,
+                                TEGRA30_DAM_CHIN1);
+        } else {
+
+                i2s->is_call_mode_rec = machine->is_call_mode;
+
+                if (!i2s->is_call_mode_rec)
+                        return 0;
+
+                if (machine->is_device_bt)
+                        codec_index = BT_SCO;
+                else
+                        codec_index = HIFI_CODEC;
+
+                codec_info = &machine->codec_info[codec_index];
+                bb_info = &machine->codec_info[BASEBAND];
+
+                /* allocate a dam for voice call recording */
+
+                i2s->call_record_dam_ifc = tegra30_dam_allocate_controller();
+                tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN0_SRC);
+                tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN1);
+                tegra30_dam_enable_clock(i2s->call_record_dam_ifc);
+
+                /* configure the dam */
+                tegra_aic326x_set_dam_cif(i2s->call_record_dam_ifc,
+                        codec_info->rate, codec_info->channels,
+                        codec_info->bitsize, 1, bb_info->rate,
+                        bb_info->channels, bb_info->bitsize);
+
+                /* setup the connections for voice call record */
+
+                tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
+                tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
+                        (i2s->call_record_dam_ifc*2),
+                        TEGRA30_AHUB_TXCIF_I2S0_TX0 + bb_info->i2s_id);
+                tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                        (i2s->call_record_dam_ifc*2),
+                        TEGRA30_AHUB_TXCIF_I2S0_TX0 + codec_info->i2s_id);
+                tegra30_ahub_set_rx_cif_source(i2s->rxcif,
+                        TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->call_record_dam_ifc);
+
+                /* enable the dam*/
+
+                tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
+                                TEGRA30_DAM_CHIN1);
+                tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
+                                TEGRA30_DAM_CHIN0_SRC);
+        }
+
+        return 0;
+}
+
+static void tegra_aic326x_shutdown(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+
+        if (!i2s->is_dam_used)
+                return;
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                /* disable the dam*/
+                tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_DISABLE,
+                                TEGRA30_DAM_CHIN1);
+
+                /* disconnect the ahub connections*/
+                tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                                        (i2s->dam_ifc*2));
+
+                /* disable the dam and free the controller */
+                tegra30_dam_disable_clock(i2s->dam_ifc);
+                tegra30_dam_free_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
+                i2s->dam_ch_refcount--;
+                if (!i2s->dam_ch_refcount)
+                        tegra30_dam_free_controller(i2s->dam_ifc);
+         } else {
+
+                if (!i2s->is_call_mode_rec)
+                        return 0;
+
+                i2s->is_call_mode_rec = 0;
+
+                /* disable the dam*/
+                tegra30_dam_enable(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN1);
+                tegra30_dam_enable(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
+
+                /* disconnect the ahub connections*/
+                tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
+                tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
+                        (i2s->call_record_dam_ifc*2));
+                tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                        (i2s->call_record_dam_ifc*2));
+
+                /* free the dam channels and dam controller */
+                tegra30_dam_disable_clock(i2s->call_record_dam_ifc);
+                tegra30_dam_free_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN1);
+                tegra30_dam_free_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN0_SRC);
+                tegra30_dam_free_controller(i2s->call_record_dam_ifc);
+         }
+
+        return;
+}
+#endif
+
+
+static int tegra_aic326x_hw_free(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(rtd->card);
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 0);
+
+        return 0;
+}
+
+static int tegra_aic326x_voice_call_hw_params(
+                        struct snd_pcm_substream *substream,
+                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk;
+        int err, pcmdiv, vxclkdiv;;
+
+        srate = params_rate(params);
+        mclk = tegra_aic326x_get_mclk(srate);
+        if (mclk < 0)
+                return mclk;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        if(machine_is_tegra_enterprise()) {
+                err = snd_soc_dai_set_fmt(codec_dai,
+                                        SND_SOC_DAIFMT_I2S |
+                                        SND_SOC_DAIFMT_NB_NF |
+                                        SND_SOC_DAIFMT_CBS_CFS);
+        } else {
+                err = snd_soc_dai_set_fmt(codec_dai,
+                                        SND_SOC_DAIFMT_DSP_B |
+                                        SND_SOC_DAIFMT_NB_NF |
+                                        SND_SOC_DAIFMT_CBS_CFS);
+        }
+
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+                                        SND_SOC_CLOCK_IN);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai clock not set\n");
+                return err;
+        }
+
+        if(!machine_is_tegra_enterprise()) {
+                if (params_rate(params) == 8000) {
+                        /* Change these Settings for 8KHz*/
+                        pcmdiv = 1;
+                        /* BB expecting 2048Khz bclk */
+                        vxclkdiv = 27;
+                } else if (params_rate(params) == 16000) {
+                        pcmdiv = 1;
+                        /* BB expecting 2048Khz bclk */
+                        vxclkdiv = 27;
+                } else {
+                        dev_err(card->dev, "codec_dai unsupported voice rate\n");
+                        return -EINVAL;
+                }
+        }
+
+        //snd_soc_dai_set_clkdiv(codec_dai, ASI2_BCLK_N, vxclkdiv);
+        //snd_soc_dai_set_clkdiv(codec_dai, ASI2_WCLK_N, pcmdiv);
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        /* codec configuration */
+        machine->codec_info[HIFI_CODEC].rate = params_rate(params);
+        machine->codec_info[HIFI_CODEC].channels = params_channels(params);
+        machine->codec_info[HIFI_CODEC].bitsize = 16;
+        machine->codec_info[HIFI_CODEC].is_i2smaster = 1;
+        machine->codec_info[HIFI_CODEC].is_format_dsp = 0;
+
+        /* baseband configuration */
+        machine->codec_info[BASEBAND].bitsize = 16;
+        machine->codec_info[BASEBAND].is_i2smaster = 1;
+        machine->codec_info[BASEBAND].is_format_dsp = 1;
+#endif
+
+        machine->is_device_bt = 0;
+
+        return 0;
+}
+
+static void tegra_aic326x_voice_call_shutdown(
+                                        struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_aic326x *machine  =
+                        snd_soc_card_get_drvdata(rtd->codec->card);
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        machine->codec_info[HIFI_CODEC].rate = 0;
+        machine->codec_info[HIFI_CODEC].channels = 0;
+#endif
+
+        machine->is_device_bt = 0;
+}
+
+static int tegra_aic326x_bt_voice_call_hw_params(
+                        struct snd_pcm_substream *substream,
+                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        int err, srate, mclk, min_mclk;
+
+        srate = params_rate(params);
+
+        mclk = tegra_aic326x_get_mclk(srate);
+        if (mclk < 0)
+                return mclk;
+
+        min_mclk = 64 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        /* codec configuration */
+        machine->codec_info[BT_SCO].rate = params_rate(params);
+        machine->codec_info[BT_SCO].channels = params_channels(params);
+        machine->codec_info[BT_SCO].bitsize = 16;
+        machine->codec_info[BT_SCO].is_i2smaster = 1;
+        machine->codec_info[BT_SCO].is_format_dsp = 1;
+
+        /* baseband configuration */
+        machine->codec_info[BASEBAND].bitsize = 16;
+        machine->codec_info[BASEBAND].is_i2smaster = 1;
+        machine->codec_info[BASEBAND].is_format_dsp = 1;
+#endif
+
+        machine->is_device_bt = 1;
+
+        return 0;
+}
+
+static void tegra_aic326x_bt_voice_call_shutdown(
+                                struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_aic326x *machine  =
+                        snd_soc_card_get_drvdata(rtd->codec->card);
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        machine->codec_info[BT_SCO].rate = 0;
+        machine->codec_info[BT_SCO].channels = 0;
+#endif
+
+        machine->is_device_bt = 0;
+}
+
+static struct snd_soc_ops tegra_aic326x_hifi_ops = {
+        .hw_params = tegra_aic326x_hw_params,
+        .hw_free = tegra_aic326x_hw_free,
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        .startup = tegra_aic326x_startup,
+        .shutdown = tegra_aic326x_shutdown,
+#endif
+};
+
+static struct snd_soc_ops tegra_aic326x_spdif_ops = {
+        .hw_params = tegra_aic326x_spdif_hw_params,
+        .hw_free = tegra_aic326x_hw_free,
+};
+
+static struct snd_soc_ops tegra_aic326x_voice_call_ops = {
+        .hw_params = tegra_aic326x_voice_call_hw_params,
+        .shutdown = tegra_aic326x_voice_call_shutdown,
+        .hw_free = tegra_aic326x_hw_free,
+};
+
+static struct snd_soc_ops tegra_aic326x_bt_voice_call_ops = {
+        .hw_params = tegra_aic326x_bt_voice_call_hw_params,
+        .shutdown = tegra_aic326x_bt_voice_call_shutdown,
+        .hw_free = tegra_aic326x_hw_free,
+};
+
+static struct snd_soc_ops tegra_aic326x_bt_ops = {
+        .hw_params = tegra_aic326x_bt_hw_params,
+        .hw_free = tegra_aic326x_hw_free,
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        .startup = tegra_aic326x_startup,
+        .shutdown = tegra_aic326x_shutdown,
+#endif
+};
+
+static struct snd_soc_jack tegra_aic326x_hp_jack;
+
+#ifdef CONFIG_SWITCH
+static struct switch_dev aic326x_wired_switch_dev = {
+        .name = "h2w",
+};
+
+/* These values are copied from WiredAccessoryObserver */
+enum headset_state {
+        BIT_NO_HEADSET = 0,
+        BIT_HEADSET = (1 << 0),
+        BIT_HEADSET_NO_MIC = (1 << 1),
+};
+
+static int aic326x_headset_switch_notify(struct notifier_block *self,
+        unsigned long action, void *dev)
+{
+        int state = 0;
+
+        switch (action) {
+        case SND_JACK_HEADPHONE:
+                state |= BIT_HEADSET_NO_MIC;
+                break;
+        case SND_JACK_HEADSET:
+                state |= BIT_HEADSET;
+                break;
+        default:
+                state |= BIT_NO_HEADSET;
+        }
+
+        switch_set_state(&aic326x_wired_switch_dev, state);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block aic326x_headset_switch_nb = {
+        .notifier_call = aic326x_headset_switch_notify,
+};
+#else
+static struct snd_soc_jack_pin tegra_aic326x_hp_jack_pins[] = {
+        {
+                .pin = "Headphone Jack",
+                .mask = SND_JACK_HEADPHONE,
+        },
+};
+#endif
+
+static int tegra_aic326x_event_int_spk(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_aic326x_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_SPKR_EN))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_spkr_en,
+                                SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static int tegra_aic326x_event_hp(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_aic326x_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_HP_MUTE))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_hp_mute,
+                                !SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget tegra_aic326x_dapm_widgets[] = {
+        SND_SOC_DAPM_SPK("Int Spk", tegra_aic326x_event_int_spk),
+        SND_SOC_DAPM_HP("Earpiece", NULL),
+        SND_SOC_DAPM_HP("Headphone Jack", tegra_aic326x_event_hp),
+        SND_SOC_DAPM_MIC("Mic Jack", NULL),
+        SND_SOC_DAPM_INPUT("Ext Mic"),
+        SND_SOC_DAPM_LINE("Linein", NULL),
+        SND_SOC_DAPM_MIC("Int Mic", NULL),
+};
+
+static const struct snd_soc_dapm_route aic326x_audio_map[] = {
+        {"Int Spk", NULL, "SPKL"},
+        {"Int Spk", NULL, "SPKR"},
+        {"Earpiece", NULL, "RECP"},
+        {"Earpiece", NULL, "RECM"},
+        {"Headphone Jack", NULL, "HPL"},
+        {"Headphone Jack", NULL, "HPR"},
+        /* internal (IN2L/IN2R) mic is stero */
+        {"Mic Bias Int" ,NULL, "Int Mic"},
+        {"IN2L", NULL, "Mic Bias Int"},
+        {"Mic Bias Int" ,NULL, "Int Mic"},
+        {"IN2R", NULL, "Mic Bias Int"},
+        {"Mic Bias Ext" ,NULL, "Mic Jack"},
+        {"CM1L" ,NULL, "Mic Jack"},
+        {"IN1L", NULL, "Mic Bias Ext"},
+        {"IN1L", NULL, "CM1L"},
+};
+
+static const struct snd_kcontrol_new tegra_aic326x_controls[] = {
+        SOC_DAPM_PIN_SWITCH("Int Spk"),
+        SOC_DAPM_PIN_SWITCH("Earpiece"),
+        SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+        SOC_DAPM_PIN_SWITCH("Mic Jack"),
+        SOC_DAPM_PIN_SWITCH("Ext Mic"),
+        SOC_DAPM_PIN_SWITCH("Linein"),
+        SOC_DAPM_PIN_SWITCH("Int Mic"),
+};
+
+static int tegra_aic326x_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_aic326x_platform_data *pdata = machine->pdata;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+#endif
+        int ret;
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        if (machine->codec_info[BASEBAND].i2s_id != -1)
+                i2s->is_dam_used = true;
+#endif
+
+        if (machine->init_done)
+                return 0;
+
+        machine->init_done = true;
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        machine->pcard = card;
+#endif
+
+        if (machine_is_whistler()) {
+                machine->audio_reg = regulator_get(NULL, "avddio_audio");
+                if (IS_ERR(machine->audio_reg)) {
+                        dev_err(card->dev, "cannot get avddio_audio reg\n");
+                        ret = PTR_ERR(machine->audio_reg);
+                        return ret;
+                }
+
+                ret = regulator_enable(machine->audio_reg);
+                if (ret) {
+                        dev_err(card->dev, "cannot enable avddio_audio reg\n");
+                        regulator_put(machine->audio_reg);
+                        machine->audio_reg = NULL;
+                        return ret;
+                }
+        }
+
+        if (gpio_is_valid(pdata->gpio_spkr_en)) {
+                ret = gpio_request(pdata->gpio_spkr_en, "spkr_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get spkr_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_SPKR_EN;
+
+                gpio_direction_output(pdata->gpio_spkr_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_hp_mute)) {
+                ret = gpio_request(pdata->gpio_hp_mute, "hp_mute");
+                if (ret) {
+                        dev_err(card->dev, "cannot get hp_mute gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_HP_MUTE;
+
+                gpio_direction_output(pdata->gpio_hp_mute, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_int_mic_en)) {
+                ret = gpio_request(pdata->gpio_int_mic_en, "int_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get int_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_INT_MIC_EN;
+
+                /* Disable int mic; enable signal is active-high */
+                gpio_direction_output(pdata->gpio_int_mic_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_ext_mic_en)) {
+                ret = gpio_request(pdata->gpio_ext_mic_en, "ext_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get ext_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_EXT_MIC_EN;
+
+                /* Enable ext mic; enable signal is active-low */
+                gpio_direction_output(pdata->gpio_ext_mic_en, 0);
+        }
+
+        ret = snd_soc_add_controls(codec, tegra_aic326x_controls,
+                                   ARRAY_SIZE(tegra_aic326x_controls));
+        if (ret < 0)
+                return ret;
+
+        snd_soc_dapm_new_controls(dapm, tegra_aic326x_dapm_widgets,
+                                        ARRAY_SIZE(tegra_aic326x_dapm_widgets));
+
+        snd_soc_dapm_add_routes(dapm, aic326x_audio_map,
+                                        ARRAY_SIZE(aic326x_audio_map));
+
+        ret = snd_soc_jack_new(codec, "Headset Jack", SND_JACK_HEADSET,
+                        &tegra_aic326x_hp_jack);
+        if (ret < 0)
+                return ret;
+
+#ifdef CONFIG_SWITCH
+        snd_soc_jack_notifier_register(&tegra_aic326x_hp_jack,
+                &aic326x_headset_switch_nb);
+#else /*gpio based headset detection*/
+        snd_soc_jack_add_pins(&tegra_aic326x_hp_jack,
+                ARRAY_SIZE(tegra_aic326x_hp_jack_pins),
+                tegra_aic326x_hp_jack_pins);
+#endif
+
+        aic326x_headset_detect(codec, &tegra_aic326x_hp_jack,
+                SND_JACK_HEADSET);
+
+        /* Add call mode switch control */
+        ret = snd_ctl_add(codec->card->snd_card,
+                        snd_ctl_new1(&tegra_aic326x_call_mode_control,
+                                machine));
+        if (ret < 0)
+                return ret;
+
+        snd_soc_dapm_force_enable_pin(dapm, "MICBIAS_EXT ON");
+        snd_soc_dapm_force_enable_pin(dapm,"MICBIAS_INT ON");
+        snd_soc_dapm_sync(dapm);
+
+        return 0;
+}
+
+static struct snd_soc_dai_link tegra_aic326x_dai[] = {
+        [DAI_LINK_HIFI] = {
+                .name = "AIC3262",
+                .stream_name = "AIC3262 PCM HIFI",
+                .codec_name = "aic3262-codec.4-0018",
+                .platform_name = "tegra-pcm-audio",
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+                .cpu_dai_name = "tegra20-i2s.0",
+#else
+                .cpu_dai_name = "tegra30-i2s.0",
+#endif
+                .codec_dai_name = "aic3262-asi1",
+                .init = tegra_aic326x_init,
+                .ops = &tegra_aic326x_hifi_ops,
+                },
+        [DAI_LINK_SPDIF] = {
+                .name = "SPDIF",
+                .stream_name = "SPDIF PCM",
+                .codec_name = "spdif-dit.0",
+                .platform_name = "tegra-pcm-audio",
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+                .cpu_dai_name = "tegra20-spdif",
+#else
+                .cpu_dai_name = "tegra30-spdif",
+#endif
+                .codec_dai_name = "dit-hifi",
+                .ops = &tegra_aic326x_spdif_ops,
+                },
+        [DAI_LINK_BTSCO] = {
+                .name = "BT-SCO",
+                .stream_name = "BT SCO PCM",
+                .codec_name = "spdif-dit.1",
+                .platform_name = "tegra-pcm-audio",
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+                .cpu_dai_name = "tegra20-i2s.1",
+#else
+                .cpu_dai_name = "tegra30-i2s.3",
+#endif
+                .codec_dai_name = "dit-hifi",
+                .init = tegra_aic326x_init,
+                .ops = &tegra_aic326x_bt_ops,
+                },
+        [DAI_LINK_VOICE_CALL] = {
+                        .name = "VOICE CALL",
+                        .stream_name = "VOICE CALL PCM",
+                        .codec_name = "aic3262-codec.4-0018",
+                        .platform_name = "tegra-pcm-audio",
+                        .cpu_dai_name = "dit-hifi",
+                        .codec_dai_name = "aic3262-asi2",
+                        .ops = &tegra_aic326x_voice_call_ops,
+                },
+        [DAI_LINK_BT_VOICE_CALL] = {
+                        .name = "BT VOICE CALL",
+                        .stream_name = "BT VOICE CALL PCM",
+                        .codec_name = "spdif-dit.2",
+                        .platform_name = "tegra-pcm-audio",
+                        .cpu_dai_name = "dit-hifi",
+                        .codec_dai_name = "dit-hifi",
+                        .ops = &tegra_aic326x_bt_voice_call_ops,
+                },
+};
+
+static struct snd_soc_card snd_soc_tegra_aic326x = {
+        .name = "tegra-aic326x",
+        .dai_link = tegra_aic326x_dai,
+        .num_links = ARRAY_SIZE(tegra_aic326x_dai),
+};
+
+static __devinit int tegra_aic326x_driver_probe(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = &snd_soc_tegra_aic326x;
+        struct tegra_aic326x *machine;
+        struct tegra_aic326x_platform_data *pdata;
+        int ret, i;
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platform data supplied\n");
+                return -EINVAL;
+        }
+
+        machine = kzalloc(sizeof(struct tegra_aic326x), GFP_KERNEL);
+        if (!machine) {
+                dev_err(&pdev->dev, "Can't allocate tegra_aic326x struct\n");
+                return -ENOMEM;
+        }
+
+        machine->pdata = pdata;
+
+        ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
+        if (ret)
+                goto err_free_machine;
+
+        card->dev = &pdev->dev;
+        platform_set_drvdata(pdev, card);
+        snd_soc_card_set_drvdata(card, machine);
+
+#ifdef CONFIG_SWITCH
+        /* Add h2w switch class support */
+        ret = switch_dev_register(&aic326x_wired_switch_dev);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "not able to register switch device %d\n",
+                        ret);
+                goto err_fini_utils;
+        }
+#endif
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        for (i = 0; i < NUM_I2S_DEVICES ; i++)
+                machine->codec_info[i].i2s_id = pdata->audio_port_id[i];
+
+        machine->codec_info[BASEBAND].rate = pdata->baseband_param.rate;
+        machine->codec_info[BASEBAND].channels = pdata->baseband_param.channels;
+
+        tegra_aic326x_dai[DAI_LINK_HIFI].cpu_dai_name =
+        tegra_i2s_dai_name[machine->codec_info[HIFI_CODEC].i2s_id];
+
+        tegra_aic326x_dai[DAI_LINK_BTSCO].cpu_dai_name =
+        tegra_i2s_dai_name[machine->codec_info[BT_SCO].i2s_id];
+#endif
+
+        if(machine_is_tegra_enterprise()) {
+                tegra_aic326x_dai[DAI_LINK_HIFI].codec_name = "aic3262-codec.0-0018";
+                tegra_aic326x_dai[DAI_LINK_VOICE_CALL].codec_name = "aic3262-codec.0-0018";
+                tegra_aic326x_dai[DAI_LINK_VOICE_CALL].codec_dai_name = "aic3262-asi1";
+        }
+
+        ret = snd_soc_register_card(card);
+        if (ret) {
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+                        ret);
+                goto err_switch_unregister;
+        }
+
+        if (!card->instantiated) {
+                dev_err(&pdev->dev, "No TI AIC3262 codec\n");
+                goto err_unregister_card;
+        }
+
+        return 0;
+
+err_unregister_card:
+        snd_soc_unregister_card(card);
+err_switch_unregister:
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&aic326x_wired_switch_dev);
+#endif
+err_fini_utils:
+        tegra_asoc_utils_fini(&machine->util_data);
+err_free_machine:
+        kfree(machine);
+        return ret;
+}
+
+static int __devexit tegra_aic326x_driver_remove(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = platform_get_drvdata(pdev);
+        struct tegra_aic326x *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_aic326x_platform_data *pdata = machine->pdata;
+
+        snd_soc_unregister_card(card);
+
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&aic326x_wired_switch_dev);
+#endif
+
+        tegra_asoc_utils_fini(&machine->util_data);
+
+        if (machine->gpio_requested & GPIO_EXT_MIC_EN)
+                gpio_free(pdata->gpio_ext_mic_en);
+        if (machine->gpio_requested & GPIO_INT_MIC_EN)
+                gpio_free(pdata->gpio_int_mic_en);
+        if (machine->gpio_requested & GPIO_HP_MUTE)
+                gpio_free(pdata->gpio_hp_mute);
+        if (machine->gpio_requested & GPIO_SPKR_EN)
+                gpio_free(pdata->gpio_spkr_en);
+
+        kfree(machine);
+
+        return 0;
+}
+
+static struct platform_driver tegra_aic326x_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+                .pm = &snd_soc_pm_ops,
+        },
+        .probe = tegra_aic326x_driver_probe,
+        .remove = __devexit_p(tegra_aic326x_driver_remove),
+};
+
+static int __init tegra_aic326x_modinit(void)
+{
+        return platform_driver_register(&tegra_aic326x_driver);
+}
+module_init(tegra_aic326x_modinit);
+
+static void __exit tegra_aic326x_modexit(void)
+{
+        platform_driver_unregister(&tegra_aic326x_driver);
+}
+module_exit(tegra_aic326x_modexit);
+
+/* Module information */
+MODULE_AUTHOR("Vinod G. <vinodg@nvidia.com>");
+MODULE_DESCRIPTION("Tegra+AIC3262 machine ASoC driver");
+MODULE_DESCRIPTION("Tegra ALSA SoC");
+MODULE_LICENSE("GPL");
+
diff --git a/sound/soc/tegra/tegra_max98088.c b/sound/soc/tegra/tegra_max98088.c
new file mode 100644
index 00000000000..bae2b783895
--- /dev/null
+++ b/sound/soc/tegra/tegra_max98088.c
@@ -0,0 +1,1233 @@
+/*
+ * tegra_max98088.c - Tegra machine ASoC driver for boards using MAX98088 codec.
+ *
+ * Author: Sumit Bhattacharya <sumitb@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ *
+ * (c) 2010, 2011 Nvidia Graphics Pvt. Ltd.
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <asm/mach-types.h>
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#ifdef CONFIG_SWITCH
+#include <linux/switch.h>
+#endif
+
+#include <mach/tegra_asoc_pdata.h>
+
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "../codecs/max98088.h"
+
+#include "tegra_pcm.h"
+#include "tegra_asoc_utils.h"
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+#include "tegra30_ahub.h"
+#include "tegra30_i2s.h"
+#include "tegra30_dam.h"
+#endif
+
+#define DRV_NAME "tegra-snd-max98088"
+
+#define GPIO_SPKR_EN    BIT(0)
+#define GPIO_HP_MUTE    BIT(1)
+#define GPIO_INT_MIC_EN BIT(2)
+#define GPIO_EXT_MIC_EN BIT(3)
+
+#define DAI_LINK_HIFI           0
+#define DAI_LINK_SPDIF          1
+#define DAI_LINK_BTSCO          2
+#define DAI_LINK_VOICE_CALL     3
+#define DAI_LINK_BT_VOICE_CALL  4
+#define NUM_DAI_LINKS   5
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+const char *tegra_max98088_i2s_dai_name[TEGRA30_NR_I2S_IFC] = {
+        "tegra30-i2s.0",
+        "tegra30-i2s.1",
+        "tegra30-i2s.2",
+        "tegra30-i2s.3",
+        "tegra30-i2s.4",
+};
+#endif
+
+extern int g_is_call_mode;
+
+struct tegra_max98088 {
+        struct tegra_asoc_utils_data util_data;
+        struct tegra_asoc_platform_data *pdata;
+        int gpio_requested;
+        bool init_done;
+        int is_call_mode;
+        int is_device_bt;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct codec_config codec_info[NUM_I2S_DEVICES];
+#endif
+        enum snd_soc_bias_level bias_level;
+        struct snd_soc_card *pcard;
+};
+
+static int tegra_call_mode_info(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_info *uinfo)
+{
+        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+        uinfo->count = 1;
+        uinfo->value.integer.min = 0;
+        uinfo->value.integer.max = 1;
+        return 0;
+}
+
+static int tegra_call_mode_get(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct tegra_max98088 *machine = snd_kcontrol_chip(kcontrol);
+
+        ucontrol->value.integer.value[0] = machine->is_call_mode;
+
+        return 0;
+}
+
+static int tegra_call_mode_put(struct snd_kcontrol *kcontrol,
+                struct snd_ctl_elem_value *ucontrol)
+{
+        struct tegra_max98088 *machine = snd_kcontrol_chip(kcontrol);
+        int is_call_mode_new = ucontrol->value.integer.value[0];
+        int codec_index;
+        unsigned int i;
+
+        if (machine->is_call_mode == is_call_mode_new)
+                return 0;
+
+        if (machine->is_device_bt)
+                codec_index = BT_SCO;
+        else
+                codec_index = HIFI_CODEC;
+
+        if (is_call_mode_new) {
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+                if (machine->codec_info[codec_index].rate == 0 ||
+                        machine->codec_info[codec_index].channels == 0)
+                                return -EINVAL;
+
+                for (i = 0; i < machine->pcard->num_links; i++)
+                        machine->pcard->dai_link[i].ignore_suspend = 1;
+
+                tegra30_make_voice_call_connections(
+                        &machine->codec_info[codec_index],
+                        &machine->codec_info[BASEBAND]);
+#endif
+        } else {
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+                tegra30_break_voice_call_connections(
+                        &machine->codec_info[codec_index],
+                        &machine->codec_info[BASEBAND]);
+
+                for (i = 0; i < machine->pcard->num_links; i++)
+                        machine->pcard->dai_link[i].ignore_suspend = 0;
+#endif
+        }
+
+        machine->is_call_mode = is_call_mode_new;
+        g_is_call_mode = machine->is_call_mode;
+
+        return 1;
+}
+
+struct snd_kcontrol_new tegra_call_mode_control = {
+        .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+        .name = "Call Mode Switch",
+        .private_value = 0xffff,
+        .info = tegra_call_mode_info,
+        .get = tegra_call_mode_get,
+        .put = tegra_call_mode_put
+};
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static int tegra_max98088_set_dam_cif(int dam_ifc, int srate,
+                        int channels, int bit_size, int src_on, int src_srate,
+                        int src_channels, int src_bit_size)
+{
+        tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN1, 0x1000);
+        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHOUT,
+                                srate);
+        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1,
+                                srate);
+        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
+                channels, bit_size, channels,
+                                bit_size);
+        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
+                channels, bit_size, channels,
+                                bit_size);
+
+        if (src_on) {
+                tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
+                tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+                        src_srate);
+                tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC,
+                        src_channels, src_bit_size, 1, 16);
+        }
+
+        return 0;
+}
+#endif
+
+static int tegra_max98088_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+#endif
+        int srate, mclk, sample_size, i2s_daifmt;
+        int err;
+        struct clk *clk;
+        int rate;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                sample_size = 16;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 8000:
+        case 16000:
+        case 24000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        default:
+                mclk = 12000000;
+                break;
+        }
+
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+        clk = clk_get_sys(NULL, "cdev1");
+#else
+        clk = clk_get_sys("extern1", NULL);
+#endif
+        if (IS_ERR(clk)) {
+                dev_err(card->dev, "Can't retrieve clk cdev1\n");
+                err = PTR_ERR(clk);
+                return err;
+        }
+
+        rate = clk_get_rate(clk);
+        printk("extern1 rate=%d\n",rate);
+
+#if TEGRA30_I2S_MASTER_PLAYBACK
+        i2s_daifmt = SND_SOC_DAIFMT_I2S |
+                                SND_SOC_DAIFMT_NB_NF |
+                                SND_SOC_DAIFMT_CBS_CFS;
+#else
+        i2s_daifmt = SND_SOC_DAIFMT_I2S |
+                                SND_SOC_DAIFMT_NB_NF |
+                                SND_SOC_DAIFMT_CBM_CFM;
+        mclk = rate;
+#endif
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        err = snd_soc_dai_set_fmt(codec_dai,i2s_daifmt);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_fmt(cpu_dai, i2s_daifmt);
+        if (err < 0) {
+                dev_err(card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+                                        SND_SOC_CLOCK_IN);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai clock not set\n");
+                return err;
+        }
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                tegra_max98088_set_dam_cif(i2s->dam_ifc, srate,
+                        params_channels(params), sample_size, 0, 0, 0, 0);
+#endif
+
+        return 0;
+}
+
+static int tegra_spdif_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk, min_mclk;
+        int err;
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        case 8000:
+        case 16000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        default:
+                return -EINVAL;
+        }
+        min_mclk = 128 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        return 0;
+}
+
+static int tegra_bt_hw_params(struct snd_pcm_substream *substream,
+                struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+#endif
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        int err, srate, mclk, min_mclk, sample_size;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                sample_size = 16;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        case 8000:
+        case 16000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        default:
+                return -EINVAL;
+        }
+        min_mclk = 64 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        err = snd_soc_dai_set_fmt(rtd->cpu_dai,
+                        SND_SOC_DAIFMT_DSP_A |
+                        SND_SOC_DAIFMT_NB_NF |
+                        SND_SOC_DAIFMT_CBS_CFS);
+        if (err < 0) {
+                dev_err(rtd->codec->card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                tegra_max98088_set_dam_cif(i2s->dam_ifc, params_rate(params),
+                        params_channels(params), sample_size, 0, 0, 0, 0);
+#endif
+
+        return 0;
+}
+
+static int tegra_hw_free(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(rtd->card);
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 0);
+
+        return 0;
+}
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static int tegra_max98088_startup(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(rtd->card);
+        struct codec_config *codec_info;
+        struct codec_config *bb_info;
+        int codec_index;
+
+        if (!i2s->is_dam_used)
+                return 0;
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                /*dam configuration*/
+                if (!i2s->dam_ch_refcount)
+                        i2s->dam_ifc = tegra30_dam_allocate_controller();
+
+                tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
+                i2s->dam_ch_refcount++;
+                tegra30_dam_enable_clock(i2s->dam_ifc);
+
+                tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                                (i2s->dam_ifc*2), i2s->txcif);
+
+                /*
+                *make the dam tx to i2s rx connection if this is the only client
+                *using i2s for playback
+                */
+                if (i2s->playback_ref_count == 1)
+                        tegra30_ahub_set_rx_cif_source(
+                                TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
+                                TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->dam_ifc);
+
+                /* enable the dam*/
+                tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_ENABLE,
+                                TEGRA30_DAM_CHIN1);
+        } else {
+
+                i2s->is_call_mode_rec = machine->is_call_mode;
+
+                if (!i2s->is_call_mode_rec)
+                        return 0;
+
+                if (machine->is_device_bt)
+                        codec_index = BT_SCO;
+                else
+                        codec_index = HIFI_CODEC;
+
+                codec_info = &machine->codec_info[codec_index];
+                bb_info = &machine->codec_info[BASEBAND];
+
+                /* allocate a dam for voice call recording */
+
+                i2s->call_record_dam_ifc = tegra30_dam_allocate_controller();
+                tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN0_SRC);
+                tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN1);
+                tegra30_dam_enable_clock(i2s->call_record_dam_ifc);
+
+                /* configure the dam */
+                tegra_max98088_set_dam_cif(i2s->call_record_dam_ifc,
+                        codec_info->rate, codec_info->channels,
+                        codec_info->bitsize, 1, bb_info->rate,
+                        bb_info->channels, bb_info->bitsize);
+
+                /* setup the connections for voice call record */
+
+                tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
+                tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
+                        (i2s->call_record_dam_ifc*2),
+                        TEGRA30_AHUB_TXCIF_I2S0_TX0 + bb_info->i2s_id);
+                tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                        (i2s->call_record_dam_ifc*2),
+                        TEGRA30_AHUB_TXCIF_I2S0_TX0 + codec_info->i2s_id);
+                tegra30_ahub_set_rx_cif_source(i2s->rxcif,
+                        TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->call_record_dam_ifc);
+
+                /* enable the dam*/
+
+                tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
+                                TEGRA30_DAM_CHIN1);
+                tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
+                                TEGRA30_DAM_CHIN0_SRC);
+        }
+
+        return 0;
+}
+
+static void tegra_max98088_shutdown(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+
+        if (!i2s->is_dam_used)
+                return;
+
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+                /* disable the dam*/
+                tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_DISABLE,
+                                TEGRA30_DAM_CHIN1);
+
+                /* disconnect the ahub connections*/
+                tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                                        (i2s->dam_ifc*2));
+
+                /* disable the dam and free the controller */
+                tegra30_dam_disable_clock(i2s->dam_ifc);
+                tegra30_dam_free_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
+                i2s->dam_ch_refcount--;
+                if (!i2s->dam_ch_refcount)
+                        tegra30_dam_free_controller(i2s->dam_ifc);
+         } else {
+
+                if (!i2s->is_call_mode_rec)
+                        return 0;
+
+                i2s->is_call_mode_rec = 0;
+
+                /* disable the dam*/
+                tegra30_dam_enable(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN1);
+                tegra30_dam_enable(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
+
+                /* disconnect the ahub connections*/
+                tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
+                tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
+                        (i2s->call_record_dam_ifc*2));
+                tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                        (i2s->call_record_dam_ifc*2));
+
+                /* free the dam channels and dam controller */
+                tegra30_dam_disable_clock(i2s->call_record_dam_ifc);
+                tegra30_dam_free_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN1);
+                tegra30_dam_free_channel(i2s->call_record_dam_ifc,
+                        TEGRA30_DAM_CHIN0_SRC);
+                tegra30_dam_free_controller(i2s->call_record_dam_ifc);
+         }
+
+        return;
+}
+#endif
+
+static int tegra_voice_call_hw_params(struct snd_pcm_substream *substream,
+                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk;
+        int err;
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 8000:
+        case 16000:
+        case 24000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        default:
+                return -EINVAL;
+                break;
+        }
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        err = snd_soc_dai_set_fmt(codec_dai,
+                                        SND_SOC_DAIFMT_I2S |
+                                        SND_SOC_DAIFMT_NB_NF |
+                                        SND_SOC_DAIFMT_CBS_CFS);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+                                        SND_SOC_CLOCK_IN);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai clock not set\n");
+                return err;
+        }
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        /* codec configuration */
+        machine->codec_info[HIFI_CODEC].rate = params_rate(params);
+        machine->codec_info[HIFI_CODEC].channels = params_channels(params);
+        machine->codec_info[HIFI_CODEC].bitsize = 16;
+        machine->codec_info[HIFI_CODEC].is_i2smaster = 1;
+        machine->codec_info[HIFI_CODEC].is_format_dsp = 0;
+
+        /* baseband configuration */
+        machine->codec_info[BASEBAND].bitsize = 16;
+        machine->codec_info[BASEBAND].is_i2smaster = 1;
+        machine->codec_info[BASEBAND].is_format_dsp = 1;
+#endif
+
+        machine->is_device_bt = 0;
+
+        return 0;
+}
+
+static void tegra_voice_call_shutdown(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_max98088 *machine  =
+                        snd_soc_card_get_drvdata(rtd->codec->card);
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        machine->codec_info[HIFI_CODEC].rate = 0;
+        machine->codec_info[HIFI_CODEC].channels = 0;
+#endif
+
+        return;
+}
+
+static int tegra_bt_voice_call_hw_params(struct snd_pcm_substream *substream,
+                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        int err, srate, mclk, min_mclk;
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        case 8000:
+        case 16000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        default:
+                return -EINVAL;
+        }
+        min_mclk = 64 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        /* codec configuration */
+        machine->codec_info[BT_SCO].rate = params_rate(params);
+        machine->codec_info[BT_SCO].channels = params_channels(params);
+        machine->codec_info[BT_SCO].bitsize = 16;
+        machine->codec_info[BT_SCO].is_i2smaster = 1;
+        machine->codec_info[BT_SCO].is_format_dsp = 1;
+
+        /* baseband configuration */
+        machine->codec_info[BASEBAND].bitsize = 16;
+        machine->codec_info[BASEBAND].is_i2smaster = 1;
+        machine->codec_info[BASEBAND].is_format_dsp = 1;
+#endif
+
+        machine->is_device_bt = 1;
+
+        return 0;
+}
+
+static void tegra_bt_voice_call_shutdown(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_max98088 *machine  =
+                        snd_soc_card_get_drvdata(rtd->codec->card);
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        machine->codec_info[BT_SCO].rate = 0;
+        machine->codec_info[BT_SCO].channels = 0;
+#endif
+
+        return;
+}
+
+static struct snd_soc_ops tegra_max98088_ops = {
+        .hw_params = tegra_max98088_hw_params,
+        .hw_free = tegra_hw_free,
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        .startup = tegra_max98088_startup,
+        .shutdown = tegra_max98088_shutdown,
+#endif
+};
+
+static struct snd_soc_ops tegra_spdif_ops = {
+        .hw_params = tegra_spdif_hw_params,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_ops tegra_voice_call_ops = {
+        .hw_params = tegra_voice_call_hw_params,
+        .shutdown = tegra_voice_call_shutdown,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_ops tegra_bt_voice_call_ops = {
+        .hw_params = tegra_bt_voice_call_hw_params,
+        .shutdown = tegra_bt_voice_call_shutdown,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_ops tegra_bt_ops = {
+        .hw_params = tegra_bt_hw_params,
+        .hw_free = tegra_hw_free,
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        .startup = tegra_max98088_startup,
+        .shutdown = tegra_max98088_shutdown,
+#endif
+};
+
+static struct snd_soc_jack tegra_max98088_hp_jack;
+
+#ifdef CONFIG_SWITCH
+static struct switch_dev wired_switch_dev = {
+        .name = "h2w",
+};
+
+/* These values are copied from WiredAccessoryObserver */
+enum headset_state {
+        BIT_NO_HEADSET = 0,
+        BIT_HEADSET = (1 << 0),
+        BIT_HEADSET_NO_MIC = (1 << 1),
+};
+
+static int headset_switch_notify(struct notifier_block *self,
+        unsigned long action, void *dev)
+{
+        int state = 0;
+
+        switch (action) {
+        case SND_JACK_HEADPHONE:
+                state |= BIT_HEADSET_NO_MIC;
+                break;
+        case SND_JACK_HEADSET:
+                state |= BIT_HEADSET;
+                break;
+        default:
+                state |= BIT_NO_HEADSET;
+        }
+
+        switch_set_state(&wired_switch_dev, state);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block headset_switch_nb = {
+        .notifier_call = headset_switch_notify,
+};
+#else
+static struct snd_soc_jack_pin tegra_max98088_hp_jack_pins[] = {
+        {
+                .pin = "Headphone Jack",
+                .mask = SND_JACK_HEADPHONE,
+        },
+};
+#endif
+
+static int tegra_max98088_event_int_spk(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_SPKR_EN))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_spkr_en,
+                                SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static int tegra_max98088_event_hp(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_HP_MUTE))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_hp_mute,
+                                !SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget tegra_max98088_dapm_widgets[] = {
+        SND_SOC_DAPM_SPK("Int Spk", tegra_max98088_event_int_spk),
+        SND_SOC_DAPM_OUTPUT("Earpiece"),
+        SND_SOC_DAPM_HP("Headphone Jack", tegra_max98088_event_hp),
+        SND_SOC_DAPM_MIC("Mic Jack", NULL),
+        SND_SOC_DAPM_INPUT("Int Mic"),
+};
+
+static const struct snd_soc_dapm_route enterprise_audio_map[] = {
+        {"Int Spk", NULL, "SPKL"},
+        {"Int Spk", NULL, "SPKR"},
+        {"Earpiece", NULL, "RECL"},
+        {"Earpiece", NULL, "RECR"},
+        {"Headphone Jack", NULL, "HPL"},
+        {"Headphone Jack", NULL, "HPR"},
+        {"MICBIAS", NULL, "Mic Jack"},
+        {"MIC2", NULL, "MICBIAS"},
+        {"MICBIAS", NULL, "Int Mic"},
+        {"MIC1", NULL, "MICBIAS"},
+};
+
+static const struct snd_kcontrol_new tegra_max98088_controls[] = {
+        SOC_DAPM_PIN_SWITCH("Int Spk"),
+        SOC_DAPM_PIN_SWITCH("Earpiece"),
+        SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+        SOC_DAPM_PIN_SWITCH("Mic Jack"),
+        SOC_DAPM_PIN_SWITCH("Int Mic"),
+};
+
+static int tegra_max98088_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+#endif
+        int ret;
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        if (machine->codec_info[BASEBAND].i2s_id != -1)
+                i2s->is_dam_used = true;
+#endif
+
+        if (machine->init_done)
+                return 0;
+
+        machine->init_done = true;
+
+        machine->pcard = card;
+        machine->bias_level = SND_SOC_BIAS_STANDBY;
+
+        if (gpio_is_valid(pdata->gpio_spkr_en)) {
+                ret = gpio_request(pdata->gpio_spkr_en, "spkr_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get spkr_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_SPKR_EN;
+
+                gpio_direction_output(pdata->gpio_spkr_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_hp_mute)) {
+                ret = gpio_request(pdata->gpio_hp_mute, "hp_mute");
+                if (ret) {
+                        dev_err(card->dev, "cannot get hp_mute gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_HP_MUTE;
+
+                gpio_direction_output(pdata->gpio_hp_mute, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_int_mic_en)) {
+                ret = gpio_request(pdata->gpio_int_mic_en, "int_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get int_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_INT_MIC_EN;
+
+                /* Disable int mic; enable signal is active-high */
+                gpio_direction_output(pdata->gpio_int_mic_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_ext_mic_en)) {
+                ret = gpio_request(pdata->gpio_ext_mic_en, "ext_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get ext_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_EXT_MIC_EN;
+
+                /* Enable ext mic; enable signal is active-low */
+                gpio_direction_output(pdata->gpio_ext_mic_en, 0);
+        }
+
+        ret = snd_soc_add_controls(codec, tegra_max98088_controls,
+                                   ARRAY_SIZE(tegra_max98088_controls));
+        if (ret < 0)
+                return ret;
+
+        snd_soc_dapm_new_controls(dapm, tegra_max98088_dapm_widgets,
+                                        ARRAY_SIZE(tegra_max98088_dapm_widgets));
+
+        snd_soc_dapm_add_routes(dapm, enterprise_audio_map,
+                                        ARRAY_SIZE(enterprise_audio_map));
+
+        ret = snd_soc_jack_new(codec, "Headset Jack", SND_JACK_HEADSET,
+                        &tegra_max98088_hp_jack);
+        if (ret < 0)
+                return ret;
+
+#ifdef CONFIG_SWITCH
+        snd_soc_jack_notifier_register(&tegra_max98088_hp_jack,
+                &headset_switch_nb);
+#else /*gpio based headset detection*/
+        snd_soc_jack_add_pins(&tegra_max98088_hp_jack,
+                ARRAY_SIZE(tegra_max98088_hp_jack_pins),
+                tegra_max98088_hp_jack_pins);
+#endif
+
+        max98088_headset_detect(codec, &tegra_max98088_hp_jack,
+                SND_JACK_HEADSET);
+
+       /* Add call mode switch control */
+        ret = snd_ctl_add(codec->card->snd_card,
+                        snd_ctl_new1(&tegra_call_mode_control, machine));
+        if (ret < 0)
+                return ret;
+
+        snd_soc_dapm_nc_pin(dapm, "INA1");
+        snd_soc_dapm_nc_pin(dapm, "INA2");
+        snd_soc_dapm_nc_pin(dapm, "INB1");
+        snd_soc_dapm_nc_pin(dapm, "INB2");
+        snd_soc_dapm_sync(dapm);
+
+        return 0;
+}
+
+static struct snd_soc_dai_link tegra_max98088_dai[NUM_DAI_LINKS] = {
+        [DAI_LINK_HIFI] = {
+                        .name = "MAX98088",
+                        .stream_name = "MAX98088 HIFI",
+                        .codec_name = "max98088.0-0010",
+                        .platform_name = "tegra-pcm-audio",
+                        .codec_dai_name = "HiFi",
+                        .init = tegra_max98088_init,
+                        .ops = &tegra_max98088_ops,
+                },
+        [DAI_LINK_SPDIF] = {
+                        .name = "SPDIF",
+                        .stream_name = "SPDIF PCM",
+                        .codec_name = "spdif-dit.0",
+                        .platform_name = "tegra-pcm-audio",
+                        .cpu_dai_name = "tegra30-spdif",
+                        .codec_dai_name = "dit-hifi",
+                        .ops = &tegra_spdif_ops,
+                },
+        [DAI_LINK_BTSCO] = {
+                        .name = "BT SCO",
+                        .stream_name = "BT SCO PCM",
+                        .codec_name = "spdif-dit.1",
+                        .platform_name = "tegra-pcm-audio",
+                        .codec_dai_name = "dit-hifi",
+                        .init = tegra_max98088_init,
+                        .ops = &tegra_bt_ops,
+                },
+        [DAI_LINK_VOICE_CALL] = {
+                        .name = "VOICE CALL",
+                        .stream_name = "VOICE CALL PCM",
+                        .codec_name = "max98088.0-0010",
+                        .platform_name = "tegra-pcm-audio",
+                        .cpu_dai_name = "dit-hifi",
+                        .codec_dai_name = "HiFi",
+                        .ops = &tegra_voice_call_ops,
+                },
+        [DAI_LINK_BT_VOICE_CALL] = {
+                        .name = "BT VOICE CALL",
+                        .stream_name = "BT VOICE CALL PCM",
+                        .codec_name = "spdif-dit.2",
+                        .platform_name = "tegra-pcm-audio",
+                        .cpu_dai_name = "dit-hifi",
+                        .codec_dai_name = "dit-hifi",
+                        .ops = &tegra_bt_voice_call_ops,
+                },
+};
+
+static int tegra30_soc_set_bias_level(struct snd_soc_card *card,
+                                        enum snd_soc_bias_level level)
+{
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+
+        if (machine->bias_level == SND_SOC_BIAS_OFF &&
+                level != SND_SOC_BIAS_OFF)
+                tegra_asoc_utils_clk_enable(&machine->util_data);
+
+        return 0;
+}
+
+static int tegra30_soc_set_bias_level_post(struct snd_soc_card *card,
+                                        enum snd_soc_bias_level level)
+{
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+
+        if (machine->bias_level != SND_SOC_BIAS_OFF &&
+                level == SND_SOC_BIAS_OFF)
+                tegra_asoc_utils_clk_disable(&machine->util_data);
+
+        machine->bias_level = level;
+
+        return 0 ;
+}
+
+static struct snd_soc_card snd_soc_tegra_max98088 = {
+        .name = "tegra-max98088",
+        .dai_link = tegra_max98088_dai,
+        .num_links = ARRAY_SIZE(tegra_max98088_dai),
+        .set_bias_level = tegra30_soc_set_bias_level,
+        .set_bias_level_post = tegra30_soc_set_bias_level_post,
+};
+
+static __devinit int tegra_max98088_driver_probe(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = &snd_soc_tegra_max98088;
+        struct tegra_max98088 *machine;
+        struct tegra_asoc_platform_data *pdata;
+        int ret, i;
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platform data supplied\n");
+                return -EINVAL;
+        }
+
+        machine = kzalloc(sizeof(struct tegra_max98088), GFP_KERNEL);
+        if (!machine) {
+                dev_err(&pdev->dev, "Can't allocate tegra_max98088 struct\n");
+                return -ENOMEM;
+        }
+
+        machine->pdata = pdata;
+
+        ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
+        if (ret)
+                goto err_free_machine;
+
+        card->dev = &pdev->dev;
+        platform_set_drvdata(pdev, card);
+        snd_soc_card_set_drvdata(card, machine);
+
+#ifdef CONFIG_SWITCH
+        /* Add h2w switch class support */
+        ret = switch_dev_register(&wired_switch_dev);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "not able to register switch device\n");
+                goto err_fini_utils;
+        }
+#endif
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        for (i = 0; i < NUM_I2S_DEVICES ; i++)
+                machine->codec_info[i].i2s_id = pdata->audio_port_id[i];
+
+        machine->codec_info[BASEBAND].rate = pdata->baseband_param.rate;
+        machine->codec_info[BASEBAND].channels = pdata->baseband_param.channels;
+
+        tegra_max98088_dai[DAI_LINK_HIFI].cpu_dai_name =
+        tegra_max98088_i2s_dai_name[machine->codec_info[HIFI_CODEC].i2s_id];
+
+        tegra_max98088_dai[DAI_LINK_BTSCO].cpu_dai_name =
+        tegra_max98088_i2s_dai_name[machine->codec_info[BT_SCO].i2s_id];
+#endif
+
+        ret = snd_soc_register_card(card);
+        if (ret) {
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+                        ret);
+                goto err_switch_unregister;
+        }
+
+        if (!card->instantiated) {
+                dev_err(&pdev->dev, "No MAX98088 codec\n");
+                goto err_unregister_card;
+        }
+
+        return 0;
+
+err_unregister_card:
+        snd_soc_unregister_card(card);
+err_switch_unregister:
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&wired_switch_dev);
+#endif
+err_fini_utils:
+        tegra_asoc_utils_fini(&machine->util_data);
+err_free_machine:
+        kfree(machine);
+        return ret;
+}
+
+static int __devexit tegra_max98088_driver_remove(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = platform_get_drvdata(pdev);
+        struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+
+        snd_soc_unregister_card(card);
+
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&wired_switch_dev);
+#endif
+
+        tegra_asoc_utils_fini(&machine->util_data);
+
+        if (machine->gpio_requested & GPIO_EXT_MIC_EN)
+                gpio_free(pdata->gpio_ext_mic_en);
+        if (machine->gpio_requested & GPIO_INT_MIC_EN)
+                gpio_free(pdata->gpio_int_mic_en);
+        if (machine->gpio_requested & GPIO_HP_MUTE)
+                gpio_free(pdata->gpio_hp_mute);
+        if (machine->gpio_requested & GPIO_SPKR_EN)
+                gpio_free(pdata->gpio_spkr_en);
+
+        kfree(machine);
+
+        return 0;
+}
+
+static struct platform_driver tegra_max98088_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+                .pm = &snd_soc_pm_ops,
+        },
+        .probe = tegra_max98088_driver_probe,
+        .remove = __devexit_p(tegra_max98088_driver_remove),
+};
+
+static int __init tegra_max98088_modinit(void)
+{
+        return platform_driver_register(&tegra_max98088_driver);
+}
+module_init(tegra_max98088_modinit);
+
+static void __exit tegra_max98088_modexit(void)
+{
+        platform_driver_unregister(&tegra_max98088_driver);
+}
+module_exit(tegra_max98088_modexit);
+
+MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
+MODULE_DESCRIPTION("Tegra+MAX98088 machine ASoC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/tegra/tegra_max98095.c b/sound/soc/tegra/tegra_max98095.c
new file mode 100644
index 00000000000..2104ba849cd
--- /dev/null
+++ b/sound/soc/tegra/tegra_max98095.c
@@ -0,0 +1,723 @@
+/*
+ * tegra_max98095.c - Tegra machine ASoC driver for boards using MAX98095 codec.
+ *
+ * Author: Ravindra Lokhande <rlokhande@nvidia.com>
+ * Copyright (C) 2012 - NVIDIA, Inc.
+ *
+ * Based on version from Sumit Bhattacharya <sumitb@nvidia.com>
+ *
+ * Based on code copyright/by:
+ *
+ * (c) 2010, 2011, 2012 Nvidia Graphics Pvt. Ltd.
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <asm/mach-types.h>
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#ifdef CONFIG_SWITCH
+#include <linux/switch.h>
+#endif
+
+#include <mach/tegra_asoc_pdata.h>
+
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "../codecs/max98095.h"
+
+#include "tegra_pcm.h"
+#include "tegra_asoc_utils.h"
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+#include "tegra30_ahub.h"
+#include "tegra30_i2s.h"
+#include "tegra30_dam.h"
+#endif
+
+#define DRV_NAME "tegra-snd-max98095"
+
+#define GPIO_SPKR_EN    BIT(0)
+#define GPIO_HP_MUTE    BIT(1)
+#define GPIO_INT_MIC_EN BIT(2)
+#define GPIO_EXT_MIC_EN BIT(3)
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+const char *tegra_max98095_i2s_dai_name[TEGRA30_NR_I2S_IFC] = {
+        "tegra30-i2s.0",
+        "tegra30-i2s.1",
+        "tegra30-i2s.2",
+        "tegra30-i2s.3",
+        "tegra30-i2s.4",
+};
+#endif
+
+struct tegra_max98095 {
+        struct tegra_asoc_utils_data util_data;
+        struct tegra_asoc_platform_data *pdata;
+        int gpio_requested;
+        bool init_done;
+        int is_call_mode;
+        int is_device_bt;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct codec_config codec_info[NUM_I2S_DEVICES];
+#endif
+        enum snd_soc_bias_level bias_level;
+};
+
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static int tegra_max98095_set_dam_cif(int dam_ifc, int srate,
+                        int channels, int bit_size)
+{
+        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHOUT,
+                                srate);
+        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1,
+                                srate);
+        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
+                channels, bit_size, channels,
+                                bit_size);
+        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
+                channels, bit_size, channels,
+                                bit_size);
+
+        return 0;
+}
+#endif
+
+static int tegra_max98095_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+#endif
+        unsigned int srate, mclk, sample_size;
+        int err;
+
+        switch (params_format(params)) {
+        case SNDRV_PCM_FORMAT_S16_LE:
+                sample_size = 16;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 8000:
+        case 16000:
+        case 24000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        default:
+                mclk = 12000000;
+                break;
+        }
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        err = snd_soc_dai_set_fmt(codec_dai,
+                                        SND_SOC_DAIFMT_I2S |
+                                        SND_SOC_DAIFMT_NB_NF |
+                                        SND_SOC_DAIFMT_CBS_CFS);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_fmt(cpu_dai,
+                                        SND_SOC_DAIFMT_I2S |
+                                        SND_SOC_DAIFMT_NB_NF |
+                                        SND_SOC_DAIFMT_CBS_CFS);
+        if (err < 0) {
+                dev_err(card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+                                        SND_SOC_CLOCK_IN);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai clock not set\n");
+                return err;
+        }
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+                tegra_max98095_set_dam_cif(i2s->dam_ifc, srate,
+                                params_channels(params), sample_size);
+#endif
+
+        return 0;
+}
+
+static int tegra_spdif_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+        unsigned int srate, mclk, min_mclk;
+        int err;
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        case 8000:
+        case 16000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        default:
+                return -EINVAL;
+        }
+        min_mclk = 128 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+
+
+        return 0;
+}
+
+static int tegra_hw_free(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(rtd->card);
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 0);
+
+        return 0;
+}
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static int tegra_max98095_startup(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+
+        if ((substream->stream != SNDRV_PCM_STREAM_PLAYBACK) ||
+                !(i2s->is_dam_used))
+                return 0;
+
+        /*dam configuration*/
+        if (!i2s->dam_ch_refcount)
+                i2s->dam_ifc = tegra30_dam_allocate_controller();
+
+        tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
+        i2s->dam_ch_refcount++;
+        tegra30_dam_enable_clock(i2s->dam_ifc);
+        tegra30_dam_set_gain(i2s->dam_ifc, TEGRA30_DAM_CHIN1, 0x1000);
+
+        tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                        (i2s->dam_ifc*2), i2s->txcif);
+
+        /*
+        *make the dam tx to i2s rx connection if this is the only client
+        *using i2s for playback
+        */
+        if (i2s->playback_ref_count == 1)
+                tegra30_ahub_set_rx_cif_source(
+                        TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
+                        TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->dam_ifc);
+
+        /* enable the dam*/
+        tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_ENABLE,
+                        TEGRA30_DAM_CHIN1);
+
+        return 0;
+}
+
+static void tegra_max98095_shutdown(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+
+        if ((substream->stream != SNDRV_PCM_STREAM_PLAYBACK) ||
+                !(i2s->is_dam_used))
+                return;
+
+        /* disable the dam*/
+        tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_DISABLE,
+                        TEGRA30_DAM_CHIN1);
+
+        /* disconnect the ahub connections*/
+        tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
+                                (i2s->dam_ifc*2));
+
+        /* disable the dam and free the controller */
+        tegra30_dam_disable_clock(i2s->dam_ifc);
+        tegra30_dam_free_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
+        i2s->dam_ch_refcount--;
+        if (!i2s->dam_ch_refcount)
+                tegra30_dam_free_controller(i2s->dam_ifc);
+
+        return;
+}
+#endif
+
+static struct snd_soc_ops tegra_max98095_ops = {
+        .hw_params = tegra_max98095_hw_params,
+        .hw_free = tegra_hw_free,
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        .startup = tegra_max98095_startup,
+        .shutdown = tegra_max98095_shutdown,
+#endif
+};
+
+static struct snd_soc_ops tegra_spdif_ops = {
+        .hw_params = tegra_spdif_hw_params,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_jack tegra_max98095_hp_jack;
+
+#ifdef CONFIG_SWITCH
+static struct switch_dev wired_switch_dev = {
+        .name = "h2w",
+};
+
+/* These values are copied from WiredAccessoryObserver */
+enum headset_state {
+        BIT_NO_HEADSET = 0,
+        BIT_HEADSET = (1 << 0),
+        BIT_HEADSET_NO_MIC = (1 << 1),
+};
+
+static int headset_switch_notify(struct notifier_block *self,
+        unsigned long action, void *dev)
+{
+        int state = 0;
+
+        switch (action) {
+        case SND_JACK_HEADPHONE:
+                state |= BIT_HEADSET_NO_MIC;
+                break;
+        case SND_JACK_HEADSET:
+                state |= BIT_HEADSET;
+                break;
+        default:
+                state |= BIT_NO_HEADSET;
+        }
+
+        switch_set_state(&wired_switch_dev, state);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block headset_switch_nb = {
+        .notifier_call = headset_switch_notify,
+};
+#else
+static struct snd_soc_jack_pin tegra_max98095_hp_jack_pins[] = {
+        {
+                .pin = "Headphone Jack",
+                .mask = SND_JACK_HEADPHONE,
+        },
+};
+#endif
+
+static int tegra_max98095_event_int_spk(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_SPKR_EN))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_spkr_en,
+                                SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static int tegra_max98095_event_hp(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_HP_MUTE))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_hp_mute,
+                                !SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget tegra_max98095_dapm_widgets[] = {
+        SND_SOC_DAPM_SPK("Int Spk", tegra_max98095_event_int_spk),
+        SND_SOC_DAPM_HP("Headphone Jack", tegra_max98095_event_hp),
+        SND_SOC_DAPM_MIC("Mic Jack", NULL),
+        SND_SOC_DAPM_INPUT("Int Mic"),
+        SND_SOC_DAPM_LINE("Line In", NULL),
+};
+
+static const struct snd_soc_dapm_route enterprise_audio_map[] = {
+        {"Int Spk", NULL, "SPKL"},
+        {"Int Spk", NULL, "SPKR"},
+        {"Headphone Jack", NULL, "HPL"},
+        {"Headphone Jack", NULL, "HPR"},
+        {"MICBIAS2", NULL, "Mic Jack"},
+        {"MIC2", NULL, "MICBIAS2"},
+        {"MIC1", NULL, "Int Mic"},
+        {"MIC1", NULL, "MICBIAS1"},
+        {"INB1", NULL, "Line In"},
+        {"INB2", NULL, "Line In"},
+};
+
+static const struct snd_kcontrol_new tegra_max98095_controls[] = {
+        SOC_DAPM_PIN_SWITCH("Int Spk"),
+        SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+        SOC_DAPM_PIN_SWITCH("Mic Jack"),
+        SOC_DAPM_PIN_SWITCH("Int Mic"),
+        SOC_DAPM_PIN_SWITCH("LineIn"),
+};
+
+static int tegra_max98095_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+#endif
+        int ret;
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        if (machine->codec_info[BASEBAND].i2s_id != -1)
+                i2s->is_dam_used = true;
+#endif
+
+        if (machine->init_done)
+                return 0;
+
+        machine->init_done = true;
+
+        if (gpio_is_valid(pdata->gpio_spkr_en)) {
+                ret = gpio_request(pdata->gpio_spkr_en, "spkr_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get spkr_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_SPKR_EN;
+
+                gpio_direction_output(pdata->gpio_spkr_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_hp_mute)) {
+                ret = gpio_request(pdata->gpio_hp_mute, "hp_mute");
+                if (ret) {
+                        dev_err(card->dev, "cannot get hp_mute gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_HP_MUTE;
+
+                gpio_direction_output(pdata->gpio_hp_mute, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_int_mic_en)) {
+                ret = gpio_request(pdata->gpio_int_mic_en, "int_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get int_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_INT_MIC_EN;
+
+                /* Disable int mic; enable signal is active-high */
+                gpio_direction_output(pdata->gpio_int_mic_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_ext_mic_en)) {
+                ret = gpio_request(pdata->gpio_ext_mic_en, "ext_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get ext_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_EXT_MIC_EN;
+
+                /* Enable ext mic; enable signal is active-low */
+                gpio_direction_output(pdata->gpio_ext_mic_en, 0);
+        }
+
+        ret = snd_soc_add_controls(codec, tegra_max98095_controls,
+                                   ARRAY_SIZE(tegra_max98095_controls));
+        if (ret < 0)
+                return ret;
+
+        snd_soc_dapm_new_controls(dapm, tegra_max98095_dapm_widgets,
+                        ARRAY_SIZE(tegra_max98095_dapm_widgets));
+
+        snd_soc_dapm_add_routes(dapm, enterprise_audio_map,
+                        ARRAY_SIZE(enterprise_audio_map));
+
+        ret = snd_soc_jack_new(codec, "Headset Jack", SND_JACK_HEADSET,
+                        &tegra_max98095_hp_jack);
+        if (ret < 0)
+                return ret;
+
+#ifdef CONFIG_SWITCH
+        snd_soc_jack_notifier_register(&tegra_max98095_hp_jack,
+                &headset_switch_nb);
+#else /*gpio based headset detection*/
+        snd_soc_jack_add_pins(&tegra_max98095_hp_jack,
+                ARRAY_SIZE(tegra_max98095_hp_jack_pins),
+                tegra_max98095_hp_jack_pins);
+#endif
+
+        /* max98095_headset_detect(codec, &tegra_max98095_hp_jack,
+                SND_JACK_HEADSET); */
+
+        snd_soc_dapm_nc_pin(dapm, "INA1");
+        snd_soc_dapm_nc_pin(dapm, "INA2");
+        snd_soc_dapm_nc_pin(dapm, "INB1");
+        snd_soc_dapm_nc_pin(dapm, "INB2");
+        snd_soc_dapm_sync(dapm);
+
+        return 0;
+}
+
+static struct snd_soc_dai_link tegra_max98095_dai[] = {
+        {
+                .name = "MAX98095",
+                .stream_name = "MAX98095 HIFI",
+                .codec_name = "max98095.4-0010",
+                .platform_name = "tegra-pcm-audio",
+                .cpu_dai_name = "tegra30-i2s.1",
+                .codec_dai_name = "HiFi",
+                .init = tegra_max98095_init,
+                .ops = &tegra_max98095_ops,
+        },
+        {
+                .name = "SPDIF",
+                .stream_name = "SPDIF PCM",
+                .codec_name = "spdif-dit.0",
+                .platform_name = "tegra-pcm-audio",
+                .cpu_dai_name = "tegra30-spdif",
+                .codec_dai_name = "dit-hifi",
+                .ops = &tegra_spdif_ops,
+        },
+};
+
+static int tegra30_soc_set_bias_level(struct snd_soc_card *card,
+                                        enum snd_soc_bias_level level)
+{
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+
+        if (machine->bias_level == SND_SOC_BIAS_OFF &&
+                level != SND_SOC_BIAS_OFF)
+                tegra_asoc_utils_clk_enable(&machine->util_data);
+
+        machine->bias_level = level;
+
+        return 0;
+}
+
+static int tegra30_soc_set_bias_level_post(struct snd_soc_card *card,
+                                        enum snd_soc_bias_level level)
+{
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+
+        if (level == SND_SOC_BIAS_OFF)
+                tegra_asoc_utils_clk_disable(&machine->util_data);
+
+        return 0 ;
+}
+
+static struct snd_soc_card snd_soc_tegra_max98095 = {
+        .name = "tegra-max98095",
+        .dai_link = tegra_max98095_dai,
+        .num_links = ARRAY_SIZE(tegra_max98095_dai),
+        .set_bias_level = tegra30_soc_set_bias_level,
+        .set_bias_level_post = tegra30_soc_set_bias_level_post,
+};
+
+static __devinit int tegra_max98095_driver_probe(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = &snd_soc_tegra_max98095;
+        struct tegra_max98095 *machine;
+        struct tegra_asoc_platform_data *pdata;
+        int ret;
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platform data supplied\n");
+                return -EINVAL;
+        }
+
+        machine = kzalloc(sizeof(struct tegra_max98095), GFP_KERNEL);
+        if (!machine) {
+                dev_err(&pdev->dev, "Can't allocate tegra_max98095 struct\n");
+                return -ENOMEM;
+        }
+
+        machine->pdata = pdata;
+
+        ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
+        if (ret)
+                goto err_free_machine;
+
+        card->dev = &pdev->dev;
+        platform_set_drvdata(pdev, card);
+        snd_soc_card_set_drvdata(card, machine);
+
+#ifdef CONFIG_SWITCH
+        /* Add h2w switch class support */
+        ret = switch_dev_register(&wired_switch_dev);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "not able to register switch device\n");
+                goto err_fini_utils;
+        }
+#endif
+
+        ret = snd_soc_register_card(card);
+        if (ret) {
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+                        ret);
+                goto err_switch_unregister;
+        }
+
+        return 0;
+
+err_switch_unregister:
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&wired_switch_dev);
+#endif
+err_fini_utils:
+        tegra_asoc_utils_fini(&machine->util_data);
+err_free_machine:
+        kfree(machine);
+        return ret;
+}
+
+static int __devexit tegra_max98095_driver_remove(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = platform_get_drvdata(pdev);
+        struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_asoc_platform_data *pdata = machine->pdata;
+
+        snd_soc_unregister_card(card);
+
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&wired_switch_dev);
+#endif
+
+        tegra_asoc_utils_fini(&machine->util_data);
+
+        if (machine->gpio_requested & GPIO_EXT_MIC_EN)
+                gpio_free(pdata->gpio_ext_mic_en);
+        if (machine->gpio_requested & GPIO_INT_MIC_EN)
+                gpio_free(pdata->gpio_int_mic_en);
+        if (machine->gpio_requested & GPIO_HP_MUTE)
+                gpio_free(pdata->gpio_hp_mute);
+        if (machine->gpio_requested & GPIO_SPKR_EN)
+                gpio_free(pdata->gpio_spkr_en);
+
+        kfree(machine);
+
+        return 0;
+}
+
+static struct platform_driver tegra_max98095_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+                .pm = &snd_soc_pm_ops,
+        },
+        .probe = tegra_max98095_driver_probe,
+        .remove = __devexit_p(tegra_max98095_driver_remove),
+};
+
+static int __init tegra_max98095_modinit(void)
+{
+        return platform_driver_register(&tegra_max98095_driver);
+}
+module_init(tegra_max98095_modinit);
+
+static void __exit tegra_max98095_modexit(void)
+{
+        platform_driver_unregister(&tegra_max98095_driver);
+}
+module_exit(tegra_max98095_modexit);
+
+MODULE_AUTHOR("Ravindra Lokhande <rlokhande@nvidia.com>");
+MODULE_DESCRIPTION("Tegra+MAX98095 machine ASoC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/tegra/tegra_p1852.c b/sound/soc/tegra/tegra_p1852.c
new file mode 100644
index 00000000000..27a1ea59034
--- /dev/null
+++ b/sound/soc/tegra/tegra_p1852.c
@@ -0,0 +1,272 @@
+/*
+ * tegra_p1852.c - Tegra machine ASoC driver for P1852 Boards.
+ *
+ * Author: Nitin Pai <npai@nvidia.com>
+ * Copyright (C) 2010-2012 - NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ * Stephen Warren <swarren@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <asm/mach-types.h>
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <mach/tegra_p1852_pdata.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "tegra_pcm.h"
+#include "tegra_asoc_utils.h"
+
+#define DRV_NAME "tegra-snd-p1852"
+
+struct tegra_p1852 {
+        struct tegra_asoc_utils_data util_data;
+        struct tegra_p1852_platform_data *pdata;
+};
+
+static int tegra_p1852_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_p1852 *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk;
+        int i2s_daifmt = 0;
+        int err;
+        struct tegra_p1852_platform_data *pdata;
+        int codec_id = codec_dai->id;
+
+        pdata = machine->pdata;
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 64000:
+        case 88200:
+        case 96000:
+                mclk = 128 * srate;
+                break;
+        default:
+                mclk = 256 * srate;
+                break;
+        }
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        if (pdata->codec_info[codec_id].master)
+                i2s_daifmt |= SND_SOC_DAIFMT_CBM_CFM;
+        else
+                i2s_daifmt |= SND_SOC_DAIFMT_CBS_CFS;
+
+        switch (pdata->codec_info[codec_id].i2s_format) {
+        case format_tdm:
+                i2s_daifmt |= SND_SOC_DAIFMT_DSP_A;
+                break;
+        case format_i2s:
+                i2s_daifmt |= SND_SOC_DAIFMT_I2S;
+                break;
+        case format_rjm:
+                i2s_daifmt |= SND_SOC_DAIFMT_RIGHT_J;
+                break;
+        case format_ljm:
+                i2s_daifmt |= SND_SOC_DAIFMT_LEFT_J;
+                break;
+        default:
+                break;
+        }
+
+        err = snd_soc_dai_set_fmt(codec_dai, i2s_daifmt);
+        if (err < 0)
+                dev_info(card->dev, "codec_dai fmt not set\n");
+
+        err = snd_soc_dai_set_fmt(cpu_dai, i2s_daifmt);
+        if (err < 0) {
+                dev_err(card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+                                        SND_SOC_CLOCK_IN);
+        if (err < 0)
+                dev_info(card->dev, "codec_dai clock not set\n");
+
+        return 0;
+}
+
+static int tegra_hw_free(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_p1852 *machine = snd_soc_card_get_drvdata(rtd->card);
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 0);
+
+        return 0;
+}
+
+static struct snd_soc_ops tegra_p1852_ops = {
+        .hw_params = tegra_p1852_hw_params,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_dai_link tegra_p1852_dai_link[] = {
+        {
+                .name = "I2S-TDM-1",
+                .stream_name = "TEGRA PCM",
+                .platform_name = "tegra-pcm-audio",
+                .ops = &tegra_p1852_ops,
+        },
+        {
+                .name = "I2S-TDM-2",
+                .stream_name = "TEGRA PCM",
+                .platform_name = "tegra-pcm-audio",
+                .ops = &tegra_p1852_ops,
+        }
+};
+
+static struct snd_soc_card snd_soc_tegra_p1852 = {
+        .name = "tegra-p1852",
+        .dai_link = tegra_p1852_dai_link,
+        .num_links = ARRAY_SIZE(tegra_p1852_dai_link),
+};
+
+static __devinit int tegra_p1852_driver_probe(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = &snd_soc_tegra_p1852;
+        struct tegra_p1852 *machine;
+        struct tegra_p1852_platform_data *pdata;
+        int ret;
+        int i;
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platform data supplied\n");
+                return -EINVAL;
+        }
+
+        machine = kzalloc(sizeof(struct tegra_p1852), GFP_KERNEL);
+        if (!machine) {
+                dev_err(&pdev->dev, "Can't allocate tegra_p1852 struct\n");
+                return -ENOMEM;
+        }
+
+        machine->pdata = pdata;
+
+        /* The codec driver and codec dai have to come from the system
+         * level board configuration file
+         * */
+        for (i = 0; i < ARRAY_SIZE(tegra_p1852_dai_link); i++) {
+                tegra_p1852_dai_link[i].codec_name =
+                                pdata->codec_info[i].codec_name;
+                tegra_p1852_dai_link[i].cpu_dai_name =
+                                pdata->codec_info[i].cpu_dai_name;
+                tegra_p1852_dai_link[i].codec_dai_name =
+                                pdata->codec_info[i].codec_dai_name;
+                tegra_p1852_dai_link[i].name =
+                                pdata->codec_info[i].name;
+        }
+
+        ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
+        if (ret)
+                goto err_free_machine;
+
+        card->dev = &pdev->dev;
+        platform_set_drvdata(pdev, card);
+        snd_soc_card_set_drvdata(card, machine);
+
+        ret = snd_soc_register_card(card);
+        if (ret) {
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+                        ret);
+        }
+
+        if (!card->instantiated) {
+                ret = -ENODEV;
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+                        ret);
+                goto err_unregister_card;
+        }
+
+        return 0;
+
+err_unregister_card:
+        snd_soc_unregister_card(card);
+        tegra_asoc_utils_fini(&machine->util_data);
+err_free_machine:
+        kfree(machine);
+        return ret;
+}
+
+static int __devexit tegra_p1852_driver_remove(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = platform_get_drvdata(pdev);
+        struct tegra_p1852 *machine = snd_soc_card_get_drvdata(card);
+
+        snd_soc_unregister_card(card);
+        tegra_asoc_utils_fini(&machine->util_data);
+        kfree(machine);
+
+        return 0;
+}
+
+static struct platform_driver tegra_p1852_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+                .pm = &snd_soc_pm_ops,
+        },
+        .probe = tegra_p1852_driver_probe,
+        .remove = __devexit_p(tegra_p1852_driver_remove),
+};
+
+static int __init tegra_p1852_modinit(void)
+{
+        return platform_driver_register(&tegra_p1852_driver);
+}
+module_init(tegra_p1852_modinit);
+
+static void __exit tegra_p1852_modexit(void)
+{
+        platform_driver_unregister(&tegra_p1852_driver);
+}
+module_exit(tegra_p1852_modexit);
+
+MODULE_AUTHOR("Nitin Pai <npai@nvidia.com>");
+MODULE_DESCRIPTION("Tegra+P1852 machine ASoC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/tegra/tegra_rt5640.c b/sound/soc/tegra/tegra_rt5640.c
new file mode 100644
index 00000000000..f6f4ed3d421
--- /dev/null
+++ b/sound/soc/tegra/tegra_rt5640.c
@@ -0,0 +1,738 @@
+/*
+ * tegra_rt5640.c - Tegra machine ASoC driver for boards using ALC5640 codec.
+ *
+ * Author: Johnny Qiu <joqiu@nvidia.com>
+ * Copyright (C) 2011-2012, NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <asm/mach-types.h>
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#ifdef CONFIG_SWITCH
+#include <linux/switch.h>
+#endif
+
+#include <mach/tegra_rt5640_pdata.h>
+
+#include <sound/core.h>
+#include <sound/jack.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "../codecs/rt5639.h"
+#include "../codecs/rt5640.h"
+
+#include "tegra_pcm.h"
+#include "tegra_asoc_utils.h"
+
+#define DRV_NAME "tegra-snd-rt5640"
+
+#define GPIO_SPKR_EN    BIT(0)
+#define GPIO_HP_MUTE    BIT(1)
+#define GPIO_INT_MIC_EN BIT(2)
+#define GPIO_EXT_MIC_EN BIT(3)
+#define GPIO_HP_DET     BIT(4)
+
+struct tegra_rt5640 {
+        struct tegra_asoc_utils_data util_data;
+        struct tegra_rt5640_platform_data *pdata;
+        struct regulator *spk_reg;
+        struct regulator *dmic_reg;
+        struct regulator *cdc_en;
+        int gpio_requested;
+#ifdef CONFIG_SWITCH
+        int jack_status;
+#endif
+};
+
+static int tegra_rt5640_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *codec_dai = rtd->codec_dai;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk, i2s_daifmt;
+        int err;
+
+        srate = params_rate(params);
+        mclk = 256 * srate;
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % mclk)) {
+                        mclk = machine->util_data.set_mclk;
+                } else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        i2s_daifmt = SND_SOC_DAIFMT_NB_NF |
+                     SND_SOC_DAIFMT_CBS_CFS;
+
+        i2s_daifmt |= SND_SOC_DAIFMT_I2S;
+
+        err = snd_soc_dai_set_fmt(codec_dai, i2s_daifmt);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_fmt(cpu_dai, i2s_daifmt);
+        if (err < 0) {
+                dev_err(card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+        err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+                                        SND_SOC_CLOCK_IN);
+        if (err < 0) {
+                dev_err(card->dev, "codec_dai clock not set\n");
+                return err;
+        }
+
+        return 0;
+}
+
+static int tegra_bt_sco_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk, min_mclk;
+        int err;
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        case 8000:
+        case 16000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        default:
+                return -EINVAL;
+        }
+        min_mclk = 64 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        err = snd_soc_dai_set_fmt(cpu_dai,
+                                        SND_SOC_DAIFMT_DSP_A |
+                                        SND_SOC_DAIFMT_NB_NF |
+                                        SND_SOC_DAIFMT_CBS_CFS);
+        if (err < 0) {
+                dev_err(card->dev, "cpu_dai fmt not set\n");
+                return err;
+        }
+
+        return 0;
+}
+
+static int tegra_spdif_hw_params(struct snd_pcm_substream *substream,
+                                        struct snd_pcm_hw_params *params)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct snd_soc_card *card = rtd->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        int srate, mclk, min_mclk;
+        int err;
+
+        srate = params_rate(params);
+        switch (srate) {
+        case 11025:
+        case 22050:
+        case 44100:
+        case 88200:
+                mclk = 11289600;
+                break;
+        case 8000:
+        case 16000:
+        case 32000:
+        case 48000:
+        case 64000:
+        case 96000:
+                mclk = 12288000;
+                break;
+        default:
+                return -EINVAL;
+        }
+        min_mclk = 128 * srate;
+
+        err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
+        if (err < 0) {
+                if (!(machine->util_data.set_mclk % min_mclk))
+                        mclk = machine->util_data.set_mclk;
+                else {
+                        dev_err(card->dev, "Can't configure clocks\n");
+                        return err;
+                }
+        }
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
+
+        return 0;
+}
+
+static int tegra_hw_free(struct snd_pcm_substream *substream)
+{
+        struct snd_soc_pcm_runtime *rtd = substream->private_data;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(rtd->card);
+
+        tegra_asoc_utils_lock_clk_rate(&machine->util_data, 0);
+
+        return 0;
+}
+
+static struct snd_soc_ops tegra_rt5640_ops = {
+        .hw_params = tegra_rt5640_hw_params,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_ops tegra_rt5640_bt_sco_ops = {
+        .hw_params = tegra_bt_sco_hw_params,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_ops tegra_spdif_ops = {
+        .hw_params = tegra_spdif_hw_params,
+        .hw_free = tegra_hw_free,
+};
+
+static struct snd_soc_jack tegra_rt5640_hp_jack;
+
+static struct snd_soc_jack_gpio tegra_rt5640_hp_jack_gpio = {
+        .name = "headphone detect",
+        .report = SND_JACK_HEADPHONE,
+        .debounce_time = 150,
+        .invert = 1,
+};
+
+#ifdef CONFIG_SWITCH
+/* These values are copied from Android WiredAccessoryObserver */
+enum headset_state {
+        BIT_NO_HEADSET = 0,
+        BIT_HEADSET = (1 << 0),
+        BIT_HEADSET_NO_MIC = (1 << 1),
+};
+
+static struct switch_dev tegra_rt5640_headset_switch = {
+        .name = "h2w",
+};
+
+static int tegra_rt5640_jack_notifier(struct notifier_block *self,
+                              unsigned long action, void *dev)
+{
+        struct snd_soc_jack *jack = dev;
+        struct snd_soc_codec *codec = jack->codec;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        enum headset_state state = BIT_NO_HEADSET;
+        unsigned char status_jack;
+
+        if (jack == &tegra_rt5640_hp_jack) {
+                if (action) {
+                        if (!strncmp(machine->pdata->codec_name, "rt5639", 6))
+                                status_jack = rt5639_headset_detect(codec, 1);
+                        else if (!strncmp(machine->pdata->codec_name, "rt5640",
+                                                                            6))
+                                status_jack = rt5640_headset_detect(codec, 1);
+
+                        machine->jack_status &= ~SND_JACK_HEADPHONE;
+                        machine->jack_status &= ~SND_JACK_MICROPHONE;
+                        if (status_jack == RT5639_HEADPHO_DET ||
+                            status_jack == RT5640_HEADPHO_DET)
+                                        machine->jack_status |=
+                                                        SND_JACK_HEADPHONE;
+                        else if (status_jack == RT5639_HEADSET_DET ||
+                                 status_jack == RT5640_HEADSET_DET) {
+                                        machine->jack_status |=
+                                                        SND_JACK_HEADPHONE;
+                                        machine->jack_status |=
+                                                        SND_JACK_MICROPHONE;
+                        }
+                } else {
+                        if (!strncmp(machine->pdata->codec_name, "rt5639", 6))
+                                rt5639_headset_detect(codec, 0);
+                        else if (!strncmp(machine->pdata->codec_name, "rt5640",
+                                                                            6))
+                                rt5640_headset_detect(codec, 0);
+
+                        machine->jack_status &= ~SND_JACK_HEADPHONE;
+                        machine->jack_status &= ~SND_JACK_MICROPHONE;
+                }
+        }
+
+        switch (machine->jack_status) {
+        case SND_JACK_HEADPHONE:
+                state = BIT_HEADSET_NO_MIC;
+                break;
+        case SND_JACK_HEADSET:
+                state = BIT_HEADSET;
+                break;
+        case SND_JACK_MICROPHONE:
+                /* mic: would not report */
+        default:
+                state = BIT_NO_HEADSET;
+        }
+
+        switch_set_state(&tegra_rt5640_headset_switch, state);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block tegra_rt5640_jack_detect_nb = {
+        .notifier_call = tegra_rt5640_jack_notifier,
+};
+#else
+static struct snd_soc_jack_pin tegra_rt5640_hp_jack_pins[] = {
+        {
+                .pin = "Headphone Jack",
+                .mask = SND_JACK_HEADPHONE,
+        },
+};
+
+#endif
+
+static int tegra_rt5640_event_int_spk(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_rt5640_platform_data *pdata = machine->pdata;
+
+        if (machine->spk_reg) {
+                if (SND_SOC_DAPM_EVENT_ON(event))
+                        regulator_enable(machine->spk_reg);
+                else
+                        regulator_disable(machine->spk_reg);
+        }
+
+        if (!(machine->gpio_requested & GPIO_SPKR_EN))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_spkr_en,
+                                SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static int tegra_rt5640_event_hp(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_rt5640_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_HP_MUTE))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_hp_mute,
+                                !SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static int tegra_rt5640_event_int_mic(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_rt5640_platform_data *pdata = machine->pdata;
+
+        if (machine->dmic_reg) {
+                if (SND_SOC_DAPM_EVENT_ON(event))
+                        regulator_enable(machine->dmic_reg);
+                else
+                        regulator_disable(machine->dmic_reg);
+        }
+
+        if (!(machine->gpio_requested & GPIO_INT_MIC_EN))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_int_mic_en,
+                                SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static int tegra_rt5640_event_ext_mic(struct snd_soc_dapm_widget *w,
+                                        struct snd_kcontrol *k, int event)
+{
+        struct snd_soc_dapm_context *dapm = w->dapm;
+        struct snd_soc_card *card = dapm->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_rt5640_platform_data *pdata = machine->pdata;
+
+        if (!(machine->gpio_requested & GPIO_EXT_MIC_EN))
+                return 0;
+
+        gpio_set_value_cansleep(pdata->gpio_ext_mic_en,
+                                !SND_SOC_DAPM_EVENT_ON(event));
+
+        return 0;
+}
+
+static const struct snd_soc_dapm_widget cardhu_dapm_widgets[] = {
+        SND_SOC_DAPM_SPK("Int Spk", tegra_rt5640_event_int_spk),
+        SND_SOC_DAPM_HP("Headphone Jack", tegra_rt5640_event_hp),
+        SND_SOC_DAPM_MIC("Mic Jack", tegra_rt5640_event_ext_mic),
+        SND_SOC_DAPM_MIC("Int Mic", tegra_rt5640_event_int_mic),
+};
+
+static const struct snd_soc_dapm_route cardhu_audio_map[] = {
+        {"Headphone Jack", NULL, "HPOR"},
+        {"Headphone Jack", NULL, "HPOL"},
+        {"Int Spk", NULL, "SPORP"},
+        {"Int Spk", NULL, "SPORN"},
+        {"Int Spk", NULL, "SPOLP"},
+        {"Int Spk", NULL, "SPOLN"},
+        {"micbias1", NULL, "Mic Jack"},
+        {"IN1P", NULL, "micbias1"},
+        {"IN1N", NULL, "micbias1"},
+        {"micbias1", NULL, "Int Mic"},
+        {"IN2P", NULL, "micbias1"},
+};
+
+static const struct snd_kcontrol_new cardhu_controls[] = {
+        SOC_DAPM_PIN_SWITCH("Int Spk"),
+        SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+        SOC_DAPM_PIN_SWITCH("Mic Jack"),
+        SOC_DAPM_PIN_SWITCH("Int Mic"),
+};
+
+static int tegra_rt5640_init(struct snd_soc_pcm_runtime *rtd)
+{
+        struct snd_soc_codec *codec = rtd->codec;
+        struct snd_soc_dapm_context *dapm = &codec->dapm;
+        struct snd_soc_card *card = codec->card;
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_rt5640_platform_data *pdata = machine->pdata;
+        int ret;
+
+        if (gpio_is_valid(pdata->gpio_spkr_en)) {
+                ret = gpio_request(pdata->gpio_spkr_en, "spkr_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get spkr_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_SPKR_EN;
+
+                gpio_direction_output(pdata->gpio_spkr_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_hp_mute)) {
+                ret = gpio_request(pdata->gpio_hp_mute, "hp_mute");
+                if (ret) {
+                        dev_err(card->dev, "cannot get hp_mute gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_HP_MUTE;
+
+                gpio_direction_output(pdata->gpio_hp_mute, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_int_mic_en)) {
+                ret = gpio_request(pdata->gpio_int_mic_en, "int_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get int_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_INT_MIC_EN;
+
+                /* Disable int mic; enable signal is active-high */
+                gpio_direction_output(pdata->gpio_int_mic_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_ext_mic_en)) {
+                ret = gpio_request(pdata->gpio_ext_mic_en, "ext_mic_en");
+                if (ret) {
+                        dev_err(card->dev, "cannot get ext_mic_en gpio\n");
+                        return ret;
+                }
+                machine->gpio_requested |= GPIO_EXT_MIC_EN;
+
+                /* Enable ext mic; enable signal is active-low */
+                gpio_direction_output(pdata->gpio_ext_mic_en, 0);
+        }
+
+        if (gpio_is_valid(pdata->gpio_hp_det)) {
+                tegra_rt5640_hp_jack_gpio.gpio = pdata->gpio_hp_det;
+                snd_soc_jack_new(codec, "Headphone Jack", SND_JACK_HEADPHONE,
+                                &tegra_rt5640_hp_jack);
+#ifndef CONFIG_SWITCH
+                snd_soc_jack_add_pins(&tegra_rt5640_hp_jack,
+                                        ARRAY_SIZE(tegra_rt5640_hp_jack_pins),
+                                        tegra_rt5640_hp_jack_pins);
+#else
+                snd_soc_jack_notifier_register(&tegra_rt5640_hp_jack,
+                                        &tegra_rt5640_jack_detect_nb);
+#endif
+                snd_soc_jack_add_gpios(&tegra_rt5640_hp_jack,
+                                        1,
+                                        &tegra_rt5640_hp_jack_gpio);
+                machine->gpio_requested |= GPIO_HP_DET;
+        }
+
+        ret = snd_soc_add_controls(codec, cardhu_controls,
+                        ARRAY_SIZE(cardhu_controls));
+        if (ret < 0)
+                return ret;
+
+        snd_soc_dapm_new_controls(dapm, cardhu_dapm_widgets,
+                        ARRAY_SIZE(cardhu_dapm_widgets));
+
+        snd_soc_dapm_add_routes(dapm, cardhu_audio_map,
+                                ARRAY_SIZE(cardhu_audio_map));
+        /* FIXME: Calculate automatically based on DAPM routes? */
+        snd_soc_dapm_nc_pin(dapm, "LOUTL");
+        snd_soc_dapm_nc_pin(dapm, "LOUTR");
+
+        snd_soc_dapm_sync(dapm);
+
+        return 0;
+}
+
+static struct snd_soc_dai_link tegra_rt5640_dai[] = {
+        {
+                .name = "RT5640",
+                .stream_name = "RT5640 PCM",
+                .codec_name = "rt5640.4-001c",
+                .platform_name = "tegra-pcm-audio",
+                .cpu_dai_name = "tegra30-i2s.1",
+                .codec_dai_name = "rt5640-aif1",
+                .init = tegra_rt5640_init,
+                .ops = &tegra_rt5640_ops,
+        },
+        {
+                .name = "SPDIF",
+                .stream_name = "SPDIF PCM",
+                .codec_name = "spdif-dit.0",
+                .platform_name = "tegra-pcm-audio",
+                .cpu_dai_name = "tegra30-spdif",
+                .codec_dai_name = "dit-hifi",
+                .ops = &tegra_spdif_ops,
+        },
+        {
+                .name = "BT-SCO",
+                .stream_name = "BT SCO PCM",
+                .codec_name = "spdif-dit.1",
+                .platform_name = "tegra-pcm-audio",
+                .cpu_dai_name = "tegra30-i2s.3",
+                .codec_dai_name = "dit-hifi",
+                .ops = &tegra_rt5640_bt_sco_ops,
+        },
+};
+
+static struct snd_soc_card snd_soc_tegra_rt5640 = {
+        .name = "tegra-rt5640",
+        .dai_link = tegra_rt5640_dai,
+        .num_links = ARRAY_SIZE(tegra_rt5640_dai),
+};
+
+static __devinit int tegra_rt5640_driver_probe(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = &snd_soc_tegra_rt5640;
+        struct tegra_rt5640 *machine;
+        struct tegra_rt5640_platform_data *pdata;
+        int ret;
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "No platform data supplied\n");
+                return -EINVAL;
+        }
+
+        if (pdata->codec_name)
+                card->dai_link->codec_name = pdata->codec_name;
+        if (pdata->codec_dai_name)
+                card->dai_link->codec_dai_name = pdata->codec_dai_name;
+
+        machine = kzalloc(sizeof(struct tegra_rt5640), GFP_KERNEL);
+        if (!machine) {
+                dev_err(&pdev->dev, "Can't allocate tegra_rt5640 struct\n");
+                return -ENOMEM;
+        }
+
+        machine->pdata = pdata;
+
+        ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev);
+        if (ret)
+                goto err_free_machine;
+
+        machine->cdc_en = regulator_get(NULL, "cdc_en");
+        if (WARN_ON(IS_ERR(machine->cdc_en))) {
+                dev_err(&pdev->dev, "Couldn't get regulator cdc_en: %ld\n",
+                                                PTR_ERR(machine->cdc_en));
+                machine->cdc_en = 0;
+        } else {
+                regulator_enable(machine->cdc_en);
+        }
+
+        machine->spk_reg = regulator_get(&pdev->dev, "vdd_spk_amp");
+        if (IS_ERR(machine->spk_reg)) {
+                dev_info(&pdev->dev, "No speaker regulator found\n");
+                machine->spk_reg = 0;
+        }
+
+#ifdef CONFIG_SWITCH
+        /* Addd h2w swith class support */
+        ret = switch_dev_register(&tegra_rt5640_headset_switch);
+        if (ret < 0)
+                goto err_fini_utils;
+#endif
+
+        card->dev = &pdev->dev;
+        platform_set_drvdata(pdev, card);
+        snd_soc_card_set_drvdata(card, machine);
+
+        ret = snd_soc_register_card(card);
+        if (ret) {
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+                        ret);
+                goto err_unregister_switch;
+        }
+
+        if (!card->instantiated) {
+                ret = -ENODEV;
+                dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+                        ret);
+                goto err_unregister_card;
+        }
+
+        return 0;
+
+err_unregister_card:
+        snd_soc_unregister_card(card);
+err_unregister_switch:
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&tegra_rt5640_headset_switch);
+err_fini_utils:
+#endif
+        tegra_asoc_utils_fini(&machine->util_data);
+err_free_machine:
+        kfree(machine);
+        return ret;
+}
+
+static int __devexit tegra_rt5640_driver_remove(struct platform_device *pdev)
+{
+        struct snd_soc_card *card = platform_get_drvdata(pdev);
+        struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card);
+        struct tegra_rt5640_platform_data *pdata = machine->pdata;
+
+        if (machine->gpio_requested & GPIO_HP_DET)
+                snd_soc_jack_free_gpios(&tegra_rt5640_hp_jack,
+                                        1,
+                                        &tegra_rt5640_hp_jack_gpio);
+        if (machine->gpio_requested & GPIO_EXT_MIC_EN)
+                gpio_free(pdata->gpio_ext_mic_en);
+        if (machine->gpio_requested & GPIO_INT_MIC_EN)
+                gpio_free(pdata->gpio_int_mic_en);
+        if (machine->gpio_requested & GPIO_HP_MUTE)
+                gpio_free(pdata->gpio_hp_mute);
+        if (machine->gpio_requested & GPIO_SPKR_EN)
+                gpio_free(pdata->gpio_spkr_en);
+        machine->gpio_requested = 0;
+
+        if (machine->spk_reg)
+                regulator_put(machine->spk_reg);
+        if (machine->dmic_reg)
+                regulator_put(machine->dmic_reg);
+
+        if (machine->cdc_en) {
+                regulator_disable(machine->cdc_en);
+                regulator_put(machine->cdc_en);
+        }
+
+        snd_soc_unregister_card(card);
+
+        tegra_asoc_utils_fini(&machine->util_data);
+
+#ifdef CONFIG_SWITCH
+        switch_dev_unregister(&tegra_rt5640_headset_switch);
+#endif
+        kfree(machine);
+
+        return 0;
+}
+
+static struct platform_driver tegra_rt5640_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+                .pm = &snd_soc_pm_ops,
+        },
+        .probe = tegra_rt5640_driver_probe,
+        .remove = __devexit_p(tegra_rt5640_driver_remove),
+};
+
+static int __init tegra_rt5640_modinit(void)
+{
+        return platform_driver_register(&tegra_rt5640_driver);
+}
+module_init(tegra_rt5640_modinit);
+
+static void __exit tegra_rt5640_modexit(void)
+{
+        platform_driver_unregister(&tegra_rt5640_driver);
+}
+module_exit(tegra_rt5640_modexit);
+
+MODULE_AUTHOR("Johnny Qiu <joqiu@nvidia.com>");
+MODULE_DESCRIPTION("Tegra+RT5640 machine ASoC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);