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Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.h')
-rw-r--r--sound/soc/codecs/tlv320aic3x.h19
1 files changed, 18 insertions, 1 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 6f097fb6068..5da5eb3f4cc 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -13,7 +13,7 @@
13#define _AIC3X_H 13#define _AIC3X_H
14 14
15/* AIC3X register space */ 15/* AIC3X register space */
16#define AIC3X_CACHEREGNUM 103 16#define AIC3X_CACHEREGNUM 110
17 17
18/* Page select register */ 18/* Page select register */
19#define AIC3X_PAGE_SELECT 0 19#define AIC3X_PAGE_SELECT 0
@@ -74,6 +74,8 @@
74#define HPLCOM_CFG 37 74#define HPLCOM_CFG 37
75/* Right High Power Output control registers */ 75/* Right High Power Output control registers */
76#define HPRCOM_CFG 38 76#define HPRCOM_CFG 38
77/* High Power Output Stage Control Register */
78#define HPOUT_SC 40
77/* DAC Output Switching control registers */ 79/* DAC Output Switching control registers */
78#define DAC_LINE_MUX 41 80#define DAC_LINE_MUX 41
79/* High Power Output Driver Pop Reduction registers */ 81/* High Power Output Driver Pop Reduction registers */
@@ -148,6 +150,17 @@
148#define AIC3X_GPIOB_REG 101 150#define AIC3X_GPIOB_REG 101
149/* Clock generation control register */ 151/* Clock generation control register */
150#define AIC3X_CLKGEN_CTRL_REG 102 152#define AIC3X_CLKGEN_CTRL_REG 102
153/* New AGC registers */
154#define LAGCN_ATTACK 103
155#define LAGCN_DECAY 104
156#define RAGCN_ATTACK 105
157#define RAGCN_DECAY 106
158/* New Programmable ADC Digital Path and I2C Bus Condition Register */
159#define NEW_ADC_DIGITALPATH 107
160/* Passive Analog Signal Bypass Selection During Powerdown Register */
161#define PASSIVE_BYPASS 108
162/* DAC Quiescent Current Adjustment Register */
163#define DAC_ICC_ADJ 109
151 164
152/* Page select register bits */ 165/* Page select register bits */
153#define PAGE0_SELECT 0 166#define PAGE0_SELECT 0
@@ -163,6 +176,10 @@
163#define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 176#define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
164#define LDAC2LCH (0x1 << 3) 177#define LDAC2LCH (0x1 << 3)
165#define RDAC2RCH (0x1 << 1) 178#define RDAC2RCH (0x1 << 1)
179#define LDAC2RCH (0x2 << 3)
180#define RDAC2LCH (0x2 << 1)
181#define LDAC2MONOMIX (0x3 << 3)
182#define RDAC2MONOMIX (0x3 << 1)
166 183
167/* PLL registers bitfields */ 184/* PLL registers bitfields */
168#define PLLP_SHIFT 0 185#define PLLP_SHIFT 0