aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/drm/drmP.h19
-rw-r--r--include/drm/drm_crtc.h2
-rw-r--r--include/drm/drm_crtc_helper.h4
-rw-r--r--include/drm/drm_encoder_slave.h2
-rw-r--r--include/drm/drm_mm.h93
-rw-r--r--include/drm/drm_pciids.h42
-rw-r--r--include/drm/i915_drm.h34
-rw-r--r--include/drm/intel-gtt.h8
-rw-r--r--include/drm/nouveau_drm.h94
-rw-r--r--include/drm/sis_drm.h8
-rw-r--r--include/drm/ttm/ttm_bo_driver.h3
-rw-r--r--include/linux/pci_regs.h5
12 files changed, 144 insertions, 170 deletions
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 31ad880ca2e..d6b67bb9075 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -348,7 +348,6 @@ struct drm_buf {
348 struct drm_buf *next; /**< Kernel-only: used for free list */ 348 struct drm_buf *next; /**< Kernel-only: used for free list */
349 __volatile__ int waiting; /**< On kernel DMA queue */ 349 __volatile__ int waiting; /**< On kernel DMA queue */
350 __volatile__ int pending; /**< On hardware DMA queue */ 350 __volatile__ int pending; /**< On hardware DMA queue */
351 wait_queue_head_t dma_wait; /**< Processes waiting */
352 struct drm_file *file_priv; /**< Private of holding file descr */ 351 struct drm_file *file_priv; /**< Private of holding file descr */
353 int context; /**< Kernel queue for this buffer */ 352 int context; /**< Kernel queue for this buffer */
354 int while_locked; /**< Dispatch this buffer while locked */ 353 int while_locked; /**< Dispatch this buffer while locked */
@@ -876,12 +875,6 @@ struct drm_driver {
876 void (*irq_preinstall) (struct drm_device *dev); 875 void (*irq_preinstall) (struct drm_device *dev);
877 int (*irq_postinstall) (struct drm_device *dev); 876 int (*irq_postinstall) (struct drm_device *dev);
878 void (*irq_uninstall) (struct drm_device *dev); 877 void (*irq_uninstall) (struct drm_device *dev);
879 void (*reclaim_buffers) (struct drm_device *dev,
880 struct drm_file * file_priv);
881 void (*reclaim_buffers_locked) (struct drm_device *dev,
882 struct drm_file *file_priv);
883 void (*reclaim_buffers_idlelocked) (struct drm_device *dev,
884 struct drm_file *file_priv);
885 void (*set_version) (struct drm_device *dev, 878 void (*set_version) (struct drm_device *dev,
886 struct drm_set_version *sv); 879 struct drm_set_version *sv);
887 880
@@ -1108,12 +1101,8 @@ struct drm_device {
1108 1101
1109 /*@} */ 1102 /*@} */
1110 1103
1111 /** \name DMA queues (contexts) */ 1104 /** \name DMA support */
1112 /*@{ */ 1105 /*@{ */
1113 int queue_count; /**< Number of active DMA queues */
1114 int queue_reserved; /**< Number of reserved DMA queues */
1115 int queue_slots; /**< Actual length of queuelist */
1116 struct drm_queue **queuelist; /**< Vector of pointers to DMA queues */
1117 struct drm_device_dma *dma; /**< Optional pointer for DMA support */ 1106 struct drm_device_dma *dma; /**< Optional pointer for DMA support */
1118 /*@} */ 1107 /*@} */
1119 1108
@@ -1540,7 +1529,6 @@ extern int drm_debugfs_cleanup(struct drm_minor *minor);
1540 /* Info file support */ 1529 /* Info file support */
1541extern int drm_name_info(struct seq_file *m, void *data); 1530extern int drm_name_info(struct seq_file *m, void *data);
1542extern int drm_vm_info(struct seq_file *m, void *data); 1531extern int drm_vm_info(struct seq_file *m, void *data);
1543extern int drm_queues_info(struct seq_file *m, void *data);
1544extern int drm_bufs_info(struct seq_file *m, void *data); 1532extern int drm_bufs_info(struct seq_file *m, void *data);
1545extern int drm_vblank_info(struct seq_file *m, void *data); 1533extern int drm_vblank_info(struct seq_file *m, void *data);
1546extern int drm_clients_info(struct seq_file *m, void* data); 1534extern int drm_clients_info(struct seq_file *m, void* data);
@@ -1761,6 +1749,11 @@ extern int drm_get_pci_dev(struct pci_dev *pdev,
1761 const struct pci_device_id *ent, 1749 const struct pci_device_id *ent,
1762 struct drm_driver *driver); 1750 struct drm_driver *driver);
1763 1751
1752#define DRM_PCIE_SPEED_25 1
1753#define DRM_PCIE_SPEED_50 2
1754#define DRM_PCIE_SPEED_80 4
1755
1756extern int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask);
1764 1757
1765/* platform section */ 1758/* platform section */
1766extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device); 1759extern int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index bac55c21511..a1a0386e016 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -676,8 +676,6 @@ struct drm_plane {
676 * This is used to set modes. 676 * This is used to set modes.
677 */ 677 */
678struct drm_mode_set { 678struct drm_mode_set {
679 struct list_head head;
680
681 struct drm_framebuffer *fb; 679 struct drm_framebuffer *fb;
682 struct drm_crtc *crtc; 680 struct drm_crtc *crtc;
683 struct drm_display_mode *mode; 681 struct drm_display_mode *mode;
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index 7988e55c98d..e01cc80c9c3 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -62,7 +62,7 @@ struct drm_crtc_helper_funcs {
62 62
63 /* Provider can fixup or change mode timings before modeset occurs */ 63 /* Provider can fixup or change mode timings before modeset occurs */
64 bool (*mode_fixup)(struct drm_crtc *crtc, 64 bool (*mode_fixup)(struct drm_crtc *crtc,
65 struct drm_display_mode *mode, 65 const struct drm_display_mode *mode,
66 struct drm_display_mode *adjusted_mode); 66 struct drm_display_mode *adjusted_mode);
67 /* Actually set the mode */ 67 /* Actually set the mode */
68 int (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode, 68 int (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode,
@@ -96,7 +96,7 @@ struct drm_encoder_helper_funcs {
96 void (*restore)(struct drm_encoder *encoder); 96 void (*restore)(struct drm_encoder *encoder);
97 97
98 bool (*mode_fixup)(struct drm_encoder *encoder, 98 bool (*mode_fixup)(struct drm_encoder *encoder,
99 struct drm_display_mode *mode, 99 const struct drm_display_mode *mode,
100 struct drm_display_mode *adjusted_mode); 100 struct drm_display_mode *adjusted_mode);
101 void (*prepare)(struct drm_encoder *encoder); 101 void (*prepare)(struct drm_encoder *encoder);
102 void (*commit)(struct drm_encoder *encoder); 102 void (*commit)(struct drm_encoder *encoder);
diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h
index 2f65633d28a..7dc38523380 100644
--- a/include/drm/drm_encoder_slave.h
+++ b/include/drm/drm_encoder_slave.h
@@ -54,7 +54,7 @@ struct drm_encoder_slave_funcs {
54 void (*save)(struct drm_encoder *encoder); 54 void (*save)(struct drm_encoder *encoder);
55 void (*restore)(struct drm_encoder *encoder); 55 void (*restore)(struct drm_encoder *encoder);
56 bool (*mode_fixup)(struct drm_encoder *encoder, 56 bool (*mode_fixup)(struct drm_encoder *encoder,
57 struct drm_display_mode *mode, 57 const struct drm_display_mode *mode,
58 struct drm_display_mode *adjusted_mode); 58 struct drm_display_mode *adjusted_mode);
59 int (*mode_valid)(struct drm_encoder *encoder, 59 int (*mode_valid)(struct drm_encoder *encoder,
60 struct drm_display_mode *mode); 60 struct drm_display_mode *mode);
diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h
index 564b14aa7e1..06d7f798a08 100644
--- a/include/drm/drm_mm.h
+++ b/include/drm/drm_mm.h
@@ -50,6 +50,7 @@ struct drm_mm_node {
50 unsigned scanned_next_free : 1; 50 unsigned scanned_next_free : 1;
51 unsigned scanned_preceeds_hole : 1; 51 unsigned scanned_preceeds_hole : 1;
52 unsigned allocated : 1; 52 unsigned allocated : 1;
53 unsigned long color;
53 unsigned long start; 54 unsigned long start;
54 unsigned long size; 55 unsigned long size;
55 struct drm_mm *mm; 56 struct drm_mm *mm;
@@ -66,6 +67,7 @@ struct drm_mm {
66 spinlock_t unused_lock; 67 spinlock_t unused_lock;
67 unsigned int scan_check_range : 1; 68 unsigned int scan_check_range : 1;
68 unsigned scan_alignment; 69 unsigned scan_alignment;
70 unsigned long scan_color;
69 unsigned long scan_size; 71 unsigned long scan_size;
70 unsigned long scan_hit_start; 72 unsigned long scan_hit_start;
71 unsigned scan_hit_size; 73 unsigned scan_hit_size;
@@ -73,6 +75,9 @@ struct drm_mm {
73 unsigned long scan_start; 75 unsigned long scan_start;
74 unsigned long scan_end; 76 unsigned long scan_end;
75 struct drm_mm_node *prev_scanned_node; 77 struct drm_mm_node *prev_scanned_node;
78
79 void (*color_adjust)(struct drm_mm_node *node, unsigned long color,
80 unsigned long *start, unsigned long *end);
76}; 81};
77 82
78static inline bool drm_mm_node_allocated(struct drm_mm_node *node) 83static inline bool drm_mm_node_allocated(struct drm_mm_node *node)
@@ -100,11 +105,13 @@ static inline bool drm_mm_initialized(struct drm_mm *mm)
100extern struct drm_mm_node *drm_mm_get_block_generic(struct drm_mm_node *node, 105extern struct drm_mm_node *drm_mm_get_block_generic(struct drm_mm_node *node,
101 unsigned long size, 106 unsigned long size,
102 unsigned alignment, 107 unsigned alignment,
108 unsigned long color,
103 int atomic); 109 int atomic);
104extern struct drm_mm_node *drm_mm_get_block_range_generic( 110extern struct drm_mm_node *drm_mm_get_block_range_generic(
105 struct drm_mm_node *node, 111 struct drm_mm_node *node,
106 unsigned long size, 112 unsigned long size,
107 unsigned alignment, 113 unsigned alignment,
114 unsigned long color,
108 unsigned long start, 115 unsigned long start,
109 unsigned long end, 116 unsigned long end,
110 int atomic); 117 int atomic);
@@ -112,13 +119,13 @@ static inline struct drm_mm_node *drm_mm_get_block(struct drm_mm_node *parent,
112 unsigned long size, 119 unsigned long size,
113 unsigned alignment) 120 unsigned alignment)
114{ 121{
115 return drm_mm_get_block_generic(parent, size, alignment, 0); 122 return drm_mm_get_block_generic(parent, size, alignment, 0, 0);
116} 123}
117static inline struct drm_mm_node *drm_mm_get_block_atomic(struct drm_mm_node *parent, 124static inline struct drm_mm_node *drm_mm_get_block_atomic(struct drm_mm_node *parent,
118 unsigned long size, 125 unsigned long size,
119 unsigned alignment) 126 unsigned alignment)
120{ 127{
121 return drm_mm_get_block_generic(parent, size, alignment, 1); 128 return drm_mm_get_block_generic(parent, size, alignment, 0, 1);
122} 129}
123static inline struct drm_mm_node *drm_mm_get_block_range( 130static inline struct drm_mm_node *drm_mm_get_block_range(
124 struct drm_mm_node *parent, 131 struct drm_mm_node *parent,
@@ -127,8 +134,19 @@ static inline struct drm_mm_node *drm_mm_get_block_range(
127 unsigned long start, 134 unsigned long start,
128 unsigned long end) 135 unsigned long end)
129{ 136{
130 return drm_mm_get_block_range_generic(parent, size, alignment, 137 return drm_mm_get_block_range_generic(parent, size, alignment, 0,
131 start, end, 0); 138 start, end, 0);
139}
140static inline struct drm_mm_node *drm_mm_get_color_block_range(
141 struct drm_mm_node *parent,
142 unsigned long size,
143 unsigned alignment,
144 unsigned long color,
145 unsigned long start,
146 unsigned long end)
147{
148 return drm_mm_get_block_range_generic(parent, size, alignment, color,
149 start, end, 0);
132} 150}
133static inline struct drm_mm_node *drm_mm_get_block_atomic_range( 151static inline struct drm_mm_node *drm_mm_get_block_atomic_range(
134 struct drm_mm_node *parent, 152 struct drm_mm_node *parent,
@@ -137,7 +155,7 @@ static inline struct drm_mm_node *drm_mm_get_block_atomic_range(
137 unsigned long start, 155 unsigned long start,
138 unsigned long end) 156 unsigned long end)
139{ 157{
140 return drm_mm_get_block_range_generic(parent, size, alignment, 158 return drm_mm_get_block_range_generic(parent, size, alignment, 0,
141 start, end, 1); 159 start, end, 1);
142} 160}
143extern int drm_mm_insert_node(struct drm_mm *mm, struct drm_mm_node *node, 161extern int drm_mm_insert_node(struct drm_mm *mm, struct drm_mm_node *node,
@@ -149,18 +167,59 @@ extern int drm_mm_insert_node_in_range(struct drm_mm *mm,
149extern void drm_mm_put_block(struct drm_mm_node *cur); 167extern void drm_mm_put_block(struct drm_mm_node *cur);
150extern void drm_mm_remove_node(struct drm_mm_node *node); 168extern void drm_mm_remove_node(struct drm_mm_node *node);
151extern void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new); 169extern void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new);
152extern struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm, 170extern struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm,
153 unsigned long size, 171 unsigned long size,
154 unsigned alignment, 172 unsigned alignment,
155 int best_match); 173 unsigned long color,
156extern struct drm_mm_node *drm_mm_search_free_in_range( 174 bool best_match);
175extern struct drm_mm_node *drm_mm_search_free_in_range_generic(
176 const struct drm_mm *mm,
177 unsigned long size,
178 unsigned alignment,
179 unsigned long color,
180 unsigned long start,
181 unsigned long end,
182 bool best_match);
183static inline struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm,
184 unsigned long size,
185 unsigned alignment,
186 bool best_match)
187{
188 return drm_mm_search_free_generic(mm,size, alignment, 0, best_match);
189}
190static inline struct drm_mm_node *drm_mm_search_free_in_range(
157 const struct drm_mm *mm, 191 const struct drm_mm *mm,
158 unsigned long size, 192 unsigned long size,
159 unsigned alignment, 193 unsigned alignment,
160 unsigned long start, 194 unsigned long start,
161 unsigned long end, 195 unsigned long end,
162 int best_match); 196 bool best_match)
163extern int drm_mm_init(struct drm_mm *mm, unsigned long start, 197{
198 return drm_mm_search_free_in_range_generic(mm, size, alignment, 0,
199 start, end, best_match);
200}
201static inline struct drm_mm_node *drm_mm_search_free_color(const struct drm_mm *mm,
202 unsigned long size,
203 unsigned alignment,
204 unsigned long color,
205 bool best_match)
206{
207 return drm_mm_search_free_generic(mm,size, alignment, color, best_match);
208}
209static inline struct drm_mm_node *drm_mm_search_free_in_range_color(
210 const struct drm_mm *mm,
211 unsigned long size,
212 unsigned alignment,
213 unsigned long color,
214 unsigned long start,
215 unsigned long end,
216 bool best_match)
217{
218 return drm_mm_search_free_in_range_generic(mm, size, alignment, color,
219 start, end, best_match);
220}
221extern int drm_mm_init(struct drm_mm *mm,
222 unsigned long start,
164 unsigned long size); 223 unsigned long size);
165extern void drm_mm_takedown(struct drm_mm *mm); 224extern void drm_mm_takedown(struct drm_mm *mm);
166extern int drm_mm_clean(struct drm_mm *mm); 225extern int drm_mm_clean(struct drm_mm *mm);
@@ -171,10 +230,14 @@ static inline struct drm_mm *drm_get_mm(struct drm_mm_node *block)
171 return block->mm; 230 return block->mm;
172} 231}
173 232
174void drm_mm_init_scan(struct drm_mm *mm, unsigned long size, 233void drm_mm_init_scan(struct drm_mm *mm,
175 unsigned alignment); 234 unsigned long size,
176void drm_mm_init_scan_with_range(struct drm_mm *mm, unsigned long size, 235 unsigned alignment,
236 unsigned long color);
237void drm_mm_init_scan_with_range(struct drm_mm *mm,
238 unsigned long size,
177 unsigned alignment, 239 unsigned alignment,
240 unsigned long color,
178 unsigned long start, 241 unsigned long start,
179 unsigned long end); 242 unsigned long end);
180int drm_mm_scan_add_block(struct drm_mm_node *node); 243int drm_mm_scan_add_block(struct drm_mm_node *node);
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index a7aec391b7b..7ff5c99b163 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -686,14 +686,6 @@
686 {0x8086, 0x1132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 686 {0x8086, 0x1132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
687 {0, 0, 0} 687 {0, 0, 0}
688 688
689#define i830_PCI_IDS \
690 {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
691 {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
692 {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
693 {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
694 {0x8086, 0x358e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
695 {0, 0, 0}
696
697#define gamma_PCI_IDS \ 689#define gamma_PCI_IDS \
698 {0x3d3d, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 690 {0x3d3d, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
699 {0, 0, 0} 691 {0, 0, 0}
@@ -726,37 +718,3 @@
726 718
727#define ffb_PCI_IDS \ 719#define ffb_PCI_IDS \
728 {0, 0, 0} 720 {0, 0, 0}
729
730#define i915_PCI_IDS \
731 {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
732 {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
733 {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
734 {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
735 {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
736 {0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
737 {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
738 {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
739 {0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
740 {0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
741 {0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
742 {0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
743 {0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
744 {0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
745 {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
746 {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
747 {0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
748 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
749 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
750 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
751 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
752 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
753 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
754 {0x8086, 0x2e32, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
755 {0x8086, 0x2e42, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
756 {0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
757 {0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
758 {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
759 {0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
760 {0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
761 {0x8086, 0x0102, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
762 {0, 0, 0}
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index f3f82242bf1..8cc70837f92 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -200,6 +200,9 @@ typedef struct _drm_i915_sarea {
200#define DRM_I915_GEM_EXECBUFFER2 0x29 200#define DRM_I915_GEM_EXECBUFFER2 0x29
201#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 201#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
202#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 202#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
203#define DRM_I915_GEM_WAIT 0x2c
204#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
205#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
203 206
204#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 207#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
205#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 208#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -243,6 +246,9 @@ typedef struct _drm_i915_sarea {
243#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 246#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
244#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 247#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
245#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 248#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
249#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
250#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
251#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
246 252
247/* Allow drivers to submit batchbuffers directly to hardware, relying 253/* Allow drivers to submit batchbuffers directly to hardware, relying
248 * on the security mechanisms provided by hardware. 254 * on the security mechanisms provided by hardware.
@@ -298,6 +304,7 @@ typedef struct drm_i915_irq_wait {
298#define I915_PARAM_HAS_GEN7_SOL_RESET 16 304#define I915_PARAM_HAS_GEN7_SOL_RESET 16
299#define I915_PARAM_HAS_LLC 17 305#define I915_PARAM_HAS_LLC 17
300#define I915_PARAM_HAS_ALIASING_PPGTT 18 306#define I915_PARAM_HAS_ALIASING_PPGTT 18
307#define I915_PARAM_HAS_WAIT_TIMEOUT 19
301 308
302typedef struct drm_i915_getparam { 309typedef struct drm_i915_getparam {
303 int param; 310 int param;
@@ -656,13 +663,19 @@ struct drm_i915_gem_execbuffer2 {
656#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 663#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
657#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 664#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
658 __u64 flags; 665 __u64 flags;
659 __u64 rsvd1; 666 __u64 rsvd1; /* now used for context info */
660 __u64 rsvd2; 667 __u64 rsvd2;
661}; 668};
662 669
663/** Resets the SO write offset registers for transform feedback on gen7. */ 670/** Resets the SO write offset registers for transform feedback on gen7. */
664#define I915_EXEC_GEN7_SOL_RESET (1<<8) 671#define I915_EXEC_GEN7_SOL_RESET (1<<8)
665 672
673#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
674#define i915_execbuffer2_set_context_id(eb2, context) \
675 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
676#define i915_execbuffer2_get_context_id(eb2) \
677 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
678
666struct drm_i915_gem_pin { 679struct drm_i915_gem_pin {
667 /** Handle of the buffer to be pinned. */ 680 /** Handle of the buffer to be pinned. */
668 __u32 handle; 681 __u32 handle;
@@ -886,4 +899,23 @@ struct drm_intel_sprite_colorkey {
886 __u32 flags; 899 __u32 flags;
887}; 900};
888 901
902struct drm_i915_gem_wait {
903 /** Handle of BO we shall wait on */
904 __u32 bo_handle;
905 __u32 flags;
906 /** Number of nanoseconds to wait, Returns time remaining. */
907 __s64 timeout_ns;
908};
909
910struct drm_i915_gem_context_create {
911 /* output: id of new context*/
912 __u32 ctx_id;
913 __u32 pad;
914};
915
916struct drm_i915_gem_context_destroy {
917 __u32 ctx_id;
918 __u32 pad;
919};
920
889#endif /* _I915_DRM_H_ */ 921#endif /* _I915_DRM_H_ */
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h
index 923afb5dcf0..8e29d551bb3 100644
--- a/include/drm/intel-gtt.h
+++ b/include/drm/intel-gtt.h
@@ -19,8 +19,16 @@ const struct intel_gtt {
19 dma_addr_t scratch_page_dma; 19 dma_addr_t scratch_page_dma;
20 /* for ppgtt PDE access */ 20 /* for ppgtt PDE access */
21 u32 __iomem *gtt; 21 u32 __iomem *gtt;
22 /* needed for ioremap in drm/i915 */
23 phys_addr_t gma_bus_addr;
22} *intel_gtt_get(void); 24} *intel_gtt_get(void);
23 25
26int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
27 struct agp_bridge_data *bridge);
28void intel_gmch_remove(void);
29
30bool intel_enable_gtt(void);
31
24void intel_gtt_chipset_flush(void); 32void intel_gtt_chipset_flush(void);
25void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg); 33void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg);
26void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); 34void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index 5edd3a76fff..2a5769fdf8b 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -25,70 +25,6 @@
25#ifndef __NOUVEAU_DRM_H__ 25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__ 26#define __NOUVEAU_DRM_H__
27 27
28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29
30struct drm_nouveau_channel_alloc {
31 uint32_t fb_ctxdma_handle;
32 uint32_t tt_ctxdma_handle;
33
34 int channel;
35 uint32_t pushbuf_domains;
36
37 /* Notifier memory */
38 uint32_t notifier_handle;
39
40 /* DRM-enforced subchannel assignments */
41 struct {
42 uint32_t handle;
43 uint32_t grclass;
44 } subchan[8];
45 uint32_t nr_subchan;
46};
47
48struct drm_nouveau_channel_free {
49 int channel;
50};
51
52struct drm_nouveau_grobj_alloc {
53 int channel;
54 uint32_t handle;
55 int class;
56};
57
58struct drm_nouveau_notifierobj_alloc {
59 uint32_t channel;
60 uint32_t handle;
61 uint32_t size;
62 uint32_t offset;
63};
64
65struct drm_nouveau_gpuobj_free {
66 int channel;
67 uint32_t handle;
68};
69
70/* FIXME : maybe unify {GET,SET}PARAMs */
71#define NOUVEAU_GETPARAM_PCI_VENDOR 3
72#define NOUVEAU_GETPARAM_PCI_DEVICE 4
73#define NOUVEAU_GETPARAM_BUS_TYPE 5
74#define NOUVEAU_GETPARAM_FB_SIZE 8
75#define NOUVEAU_GETPARAM_AGP_SIZE 9
76#define NOUVEAU_GETPARAM_CHIPSET_ID 11
77#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
78#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
79#define NOUVEAU_GETPARAM_PTIMER_TIME 14
80#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
81#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
82struct drm_nouveau_getparam {
83 uint64_t param;
84 uint64_t value;
85};
86
87struct drm_nouveau_setparam {
88 uint64_t param;
89 uint64_t value;
90};
91
92#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 28#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
93#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 29#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
94#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 30#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
@@ -180,35 +116,19 @@ struct drm_nouveau_gem_cpu_fini {
180 uint32_t handle; 116 uint32_t handle;
181}; 117};
182 118
183enum nouveau_bus_type { 119#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
184 NV_AGP = 0, 120#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
185 NV_PCI = 1, 121#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
186 NV_PCIE = 2, 122#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
187}; 123#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
188 124#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
189struct drm_nouveau_sarea { 125#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
190};
191
192#define DRM_NOUVEAU_GETPARAM 0x00
193#define DRM_NOUVEAU_SETPARAM 0x01
194#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
195#define DRM_NOUVEAU_CHANNEL_FREE 0x03
196#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
197#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
198#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
199#define DRM_NOUVEAU_GEM_NEW 0x40 126#define DRM_NOUVEAU_GEM_NEW 0x40
200#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 127#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
201#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 128#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
202#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 129#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
203#define DRM_NOUVEAU_GEM_INFO 0x44 130#define DRM_NOUVEAU_GEM_INFO 0x44
204 131
205#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
206#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
207#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
208#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
209#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
210#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
211#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
212#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 132#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
213#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 133#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
214#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 134#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h
index 035b804dda6..df3763222d7 100644
--- a/include/drm/sis_drm.h
+++ b/include/drm/sis_drm.h
@@ -51,17 +51,17 @@
51 51
52typedef struct { 52typedef struct {
53 int context; 53 int context;
54 unsigned int offset; 54 unsigned long offset;
55 unsigned int size; 55 unsigned long size;
56 unsigned long free; 56 unsigned long free;
57} drm_sis_mem_t; 57} drm_sis_mem_t;
58 58
59typedef struct { 59typedef struct {
60 unsigned int offset, size; 60 unsigned long offset, size;
61} drm_sis_agp_t; 61} drm_sis_agp_t;
62 62
63typedef struct { 63typedef struct {
64 unsigned int offset, size; 64 unsigned long offset, size;
65} drm_sis_fb_t; 65} drm_sis_fb_t;
66 66
67struct sis_file_private { 67struct sis_file_private {
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index a05f1b55714..084e8989a6e 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -39,8 +39,6 @@
39#include "linux/fs.h" 39#include "linux/fs.h"
40#include "linux/spinlock.h" 40#include "linux/spinlock.h"
41 41
42struct ttm_backend;
43
44struct ttm_backend_func { 42struct ttm_backend_func {
45 /** 43 /**
46 * struct ttm_backend_func member bind 44 * struct ttm_backend_func member bind
@@ -119,7 +117,6 @@ struct ttm_tt {
119 unsigned long num_pages; 117 unsigned long num_pages;
120 struct sg_table *sg; /* for SG objects via dma-buf */ 118 struct sg_table *sg; /* for SG objects via dma-buf */
121 struct ttm_bo_global *glob; 119 struct ttm_bo_global *glob;
122 struct ttm_backend *be;
123 struct file *swap_storage; 120 struct file *swap_storage;
124 enum ttm_caching_state caching_state; 121 enum ttm_caching_state caching_state;
125 enum { 122 enum {
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 53274bff577..7fb75b14375 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -543,6 +543,11 @@
543#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ 543#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
544#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ 544#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
545#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ 545#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
546#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
547#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
548#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
549#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
550#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
546#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 551#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
547#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ 552#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
548 553
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-09 06:37:24 -0400