4 files changed, 214 insertions, 2 deletions

diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 1e3481edf06..8d1e2bbee83 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -778,6 +778,7 @@ struct drm_event_vblank {
 #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
 #define DRM_CAP_DUMB_PREFER_SHADOW 0x4
 #define DRM_CAP_PRIME 0x5
+#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
 
 #define DRM_PRIME_CAP_IMPORT 0x1
 #define DRM_PRIME_CAP_EXPORT 0x2
diff --git a/include/uapi/drm/exynos_drm.h b/include/uapi/drm/exynos_drm.h
index c0494d586e2..e7f52c33400 100644
--- a/include/uapi/drm/exynos_drm.h
+++ b/include/uapi/drm/exynos_drm.h
@@ -133,17 +133,26 @@ struct drm_exynos_g2d_cmd {
         __u32   data;
 };
 
+enum drm_exynos_g2d_buf_type {
+        G2D_BUF_USERPTR = 1 << 31,
+};
+
 enum drm_exynos_g2d_event_type {
         G2D_EVENT_NOT,
         G2D_EVENT_NONSTOP,
         G2D_EVENT_STOP,         /* not yet */
 };
 
+struct drm_exynos_g2d_userptr {
+        unsigned long userptr;
+        unsigned long size;
+};
+
 struct drm_exynos_g2d_set_cmdlist {
         __u64                                   cmd;
-        __u64                                   cmd_gem;
+        __u64                                   cmd_buf;
         __u32                                   cmd_nr;
-        __u32                                   cmd_gem_nr;
+        __u32                                   cmd_buf_nr;
 
         /* for g2d event */
         __u64                                   event_type;
@@ -154,6 +163,170 @@ struct drm_exynos_g2d_exec {
         __u64                                   async;
 };
 
+enum drm_exynos_ops_id {
+        EXYNOS_DRM_OPS_SRC,
+        EXYNOS_DRM_OPS_DST,
+        EXYNOS_DRM_OPS_MAX,
+};
+
+struct drm_exynos_sz {
+        __u32   hsize;
+        __u32   vsize;
+};
+
+struct drm_exynos_pos {
+        __u32   x;
+        __u32   y;
+        __u32   w;
+        __u32   h;
+};
+
+enum drm_exynos_flip {
+        EXYNOS_DRM_FLIP_NONE = (0 << 0),
+        EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
+        EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
+};
+
+enum drm_exynos_degree {
+        EXYNOS_DRM_DEGREE_0,
+        EXYNOS_DRM_DEGREE_90,
+        EXYNOS_DRM_DEGREE_180,
+        EXYNOS_DRM_DEGREE_270,
+};
+
+enum drm_exynos_planer {
+        EXYNOS_DRM_PLANAR_Y,
+        EXYNOS_DRM_PLANAR_CB,
+        EXYNOS_DRM_PLANAR_CR,
+        EXYNOS_DRM_PLANAR_MAX,
+};
+
+/**
+ * A structure for ipp supported property list.
+ *
+ * @version: version of this structure.
+ * @ipp_id: id of ipp driver.
+ * @count: count of ipp driver.
+ * @writeback: flag of writeback supporting.
+ * @flip: flag of flip supporting.
+ * @degree: flag of degree information.
+ * @csc: flag of csc supporting.
+ * @crop: flag of crop supporting.
+ * @scale: flag of scale supporting.
+ * @refresh_min: min hz of refresh.
+ * @refresh_max: max hz of refresh.
+ * @crop_min: crop min resolution.
+ * @crop_max: crop max resolution.
+ * @scale_min: scale min resolution.
+ * @scale_max: scale max resolution.
+ */
+struct drm_exynos_ipp_prop_list {
+        __u32   version;
+        __u32   ipp_id;
+        __u32   count;
+        __u32   writeback;
+        __u32   flip;
+        __u32   degree;
+        __u32   csc;
+        __u32   crop;
+        __u32   scale;
+        __u32   refresh_min;
+        __u32   refresh_max;
+        __u32   reserved;
+        struct drm_exynos_sz    crop_min;
+        struct drm_exynos_sz    crop_max;
+        struct drm_exynos_sz    scale_min;
+        struct drm_exynos_sz    scale_max;
+};
+
+/**
+ * A structure for ipp config.
+ *
+ * @ops_id: property of operation directions.
+ * @flip: property of mirror, flip.
+ * @degree: property of rotation degree.
+ * @fmt: property of image format.
+ * @sz: property of image size.
+ * @pos: property of image position(src-cropped,dst-scaler).
+ */
+struct drm_exynos_ipp_config {
+        enum drm_exynos_ops_id ops_id;
+        enum drm_exynos_flip    flip;
+        enum drm_exynos_degree  degree;
+        __u32   fmt;
+        struct drm_exynos_sz    sz;
+        struct drm_exynos_pos   pos;
+};
+
+enum drm_exynos_ipp_cmd {
+        IPP_CMD_NONE,
+        IPP_CMD_M2M,
+        IPP_CMD_WB,
+        IPP_CMD_OUTPUT,
+        IPP_CMD_MAX,
+};
+
+/**
+ * A structure for ipp property.
+ *
+ * @config: source, destination config.
+ * @cmd: definition of command.
+ * @ipp_id: id of ipp driver.
+ * @prop_id: id of property.
+ * @refresh_rate: refresh rate.
+ */
+struct drm_exynos_ipp_property {
+        struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
+        enum drm_exynos_ipp_cmd cmd;
+        __u32   ipp_id;
+        __u32   prop_id;
+        __u32   refresh_rate;
+};
+
+enum drm_exynos_ipp_buf_type {
+        IPP_BUF_ENQUEUE,
+        IPP_BUF_DEQUEUE,
+};
+
+/**
+ * A structure for ipp buffer operations.
+ *
+ * @ops_id: operation directions.
+ * @buf_type: definition of buffer.
+ * @prop_id: id of property.
+ * @buf_id: id of buffer.
+ * @handle: Y, Cb, Cr each planar handle.
+ * @user_data: user data.
+ */
+struct drm_exynos_ipp_queue_buf {
+        enum drm_exynos_ops_id  ops_id;
+        enum drm_exynos_ipp_buf_type    buf_type;
+        __u32   prop_id;
+        __u32   buf_id;
+        __u32   handle[EXYNOS_DRM_PLANAR_MAX];
+        __u32   reserved;
+        __u64   user_data;
+};
+
+enum drm_exynos_ipp_ctrl {
+        IPP_CTRL_PLAY,
+        IPP_CTRL_STOP,
+        IPP_CTRL_PAUSE,
+        IPP_CTRL_RESUME,
+        IPP_CTRL_MAX,
+};
+
+/**
+ * A structure for ipp start/stop operations.
+ *
+ * @prop_id: id of property.
+ * @ctrl: definition of control.
+ */
+struct drm_exynos_ipp_cmd_ctrl {
+        __u32   prop_id;
+        enum drm_exynos_ipp_ctrl        ctrl;
+};
+
 #define DRM_EXYNOS_GEM_CREATE           0x00
 #define DRM_EXYNOS_GEM_MAP_OFFSET       0x01
 #define DRM_EXYNOS_GEM_MMAP             0x02
@@ -166,6 +339,12 @@ struct drm_exynos_g2d_exec {
 #define DRM_EXYNOS_G2D_SET_CMDLIST      0x21
 #define DRM_EXYNOS_G2D_EXEC             0x22
 
+/* IPP - Image Post Processing */
+#define DRM_EXYNOS_IPP_GET_PROPERTY     0x30
+#define DRM_EXYNOS_IPP_SET_PROPERTY     0x31
+#define DRM_EXYNOS_IPP_QUEUE_BUF        0x32
+#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
+
 #define DRM_IOCTL_EXYNOS_GEM_CREATE             DRM_IOWR(DRM_COMMAND_BASE + \
                 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
 
@@ -188,8 +367,18 @@ struct drm_exynos_g2d_exec {
 #define DRM_IOCTL_EXYNOS_G2D_EXEC               DRM_IOWR(DRM_COMMAND_BASE + \
                 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
 
+#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY       DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
+#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY       DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
+#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF  DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
+#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL           DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
+
 /* EXYNOS specific events */
 #define DRM_EXYNOS_G2D_EVENT            0x80000000
+#define DRM_EXYNOS_IPP_EVENT            0x80000001
 
 struct drm_exynos_g2d_event {
         struct drm_event        base;
@@ -200,4 +389,14 @@ struct drm_exynos_g2d_event {
         __u32                   reserved;
 };
 
+struct drm_exynos_ipp_event {
+        struct drm_event        base;
+        __u64                   user_data;
+        __u32                   tv_sec;
+        __u32                   tv_usec;
+        __u32                   prop_id;
+        __u32                   reserved;
+        __u32                   buf_id[EXYNOS_DRM_OPS_MAX];
+};
+
 #endif /* _UAPI_EXYNOS_DRM_H_ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 4322b1e7d2e..b746a3cf5fa 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -306,6 +306,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_SEMAPHORES        20
 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH  21
 #define I915_PARAM_RSVD_FOR_FUTURE_USE   22
+#define I915_PARAM_HAS_SECURE_BATCHES    23
 
 typedef struct drm_i915_getparam {
         int param;
@@ -671,6 +672,11 @@ struct drm_i915_gem_execbuffer2 {
 /** Resets the SO write offset registers for transform feedback on gen7. */
 #define I915_EXEC_GEN7_SOL_RESET        (1<<8)
 
+/** Request a privileged ("secure") batch buffer. Note only available for
+ * DRM_ROOT_ONLY | DRM_MASTER processes.
+ */
+#define I915_EXEC_SECURE                (1<<9)
+
 #define I915_EXEC_CONTEXT_ID_MASK       (0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
         (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 4766c0f6a83..eeda91774c8 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -913,9 +913,11 @@ struct drm_radeon_gem_va {
 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
 #define RADEON_CS_USE_VM            0x02
+#define RADEON_CS_END_OF_FRAME      0x04 /* a hint from userspace which CS is the last one */
 /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
 #define RADEON_CS_RING_GFX          0
 #define RADEON_CS_RING_COMPUTE      1
+#define RADEON_CS_RING_DMA          2
 /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
 /* 0 = normal, + = higher priority, - = lower priority */
 
@@ -966,6 +968,10 @@ struct drm_radeon_cs {
 #define RADEON_INFO_MAX_PIPES           0x10
 /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
 #define RADEON_INFO_TIMESTAMP           0x11
+/* max shader engines (SE) - needed for geometry shaders, etc. */
+#define RADEON_INFO_MAX_SE              0x12
+/* max SH per SE */
+#define RADEON_INFO_MAX_SH_PER_SE       0x13
 
 struct drm_radeon_info {
         uint32_t                request;