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-rw-r--r--include/linux/mtd/onenand_regs.h20
1 files changed, 18 insertions, 2 deletions
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
index 0c6bbe28f38..86a6bbef646 100644
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -67,6 +67,9 @@
67/* 67/*
68 * Device ID Register F001h (R) 68 * Device ID Register F001h (R)
69 */ 69 */
70#define DEVICE_IS_FLEXONENAND (1 << 9)
71#define FLEXONENAND_PI_MASK (0x3ff)
72#define FLEXONENAND_PI_UNLOCK_SHIFT (14)
70#define ONENAND_DEVICE_DENSITY_MASK (0xf) 73#define ONENAND_DEVICE_DENSITY_MASK (0xf)
71#define ONENAND_DEVICE_DENSITY_SHIFT (4) 74#define ONENAND_DEVICE_DENSITY_SHIFT (4)
72#define ONENAND_DEVICE_IS_DDP (1 << 3) 75#define ONENAND_DEVICE_IS_DDP (1 << 3)
@@ -84,6 +87,11 @@
84#define ONENAND_VERSION_PROCESS_SHIFT (8) 87#define ONENAND_VERSION_PROCESS_SHIFT (8)
85 88
86/* 89/*
90 * Technology Register F006h (R)
91 */
92#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0)
93
94/*
87 * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W) 95 * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
88 */ 96 */
89#define ONENAND_DDP_SHIFT (15) 97#define ONENAND_DDP_SHIFT (15)
@@ -93,7 +101,8 @@
93/* 101/*
94 * Start Address 8 F107h (R/W) 102 * Start Address 8 F107h (R/W)
95 */ 103 */
96#define ONENAND_FPA_MASK (0x3f) 104/* Note: It's actually 0x3f in case of SLC */
105#define ONENAND_FPA_MASK (0x7f)
97#define ONENAND_FPA_SHIFT (2) 106#define ONENAND_FPA_SHIFT (2)
98#define ONENAND_FSA_MASK (0x03) 107#define ONENAND_FSA_MASK (0x03)
99 108
@@ -105,7 +114,8 @@
105#define ONENAND_BSA_BOOTRAM (0 << 2) 114#define ONENAND_BSA_BOOTRAM (0 << 2)
106#define ONENAND_BSA_DATARAM0 (2 << 2) 115#define ONENAND_BSA_DATARAM0 (2 << 2)
107#define ONENAND_BSA_DATARAM1 (3 << 2) 116#define ONENAND_BSA_DATARAM1 (3 << 2)
108#define ONENAND_BSC_MASK (0x03) 117/* Note: It's actually 0x03 in case of SLC */
118#define ONENAND_BSC_MASK (0x07)
109 119
110/* 120/*
111 * Command Register F220h (R/W) 121 * Command Register F220h (R/W)
@@ -124,9 +134,13 @@
124#define ONENAND_CMD_RESET (0xF0) 134#define ONENAND_CMD_RESET (0xF0)
125#define ONENAND_CMD_OTP_ACCESS (0x65) 135#define ONENAND_CMD_OTP_ACCESS (0x65)
126#define ONENAND_CMD_READID (0x90) 136#define ONENAND_CMD_READID (0x90)
137#define FLEXONENAND_CMD_PI_UPDATE (0x05)
138#define FLEXONENAND_CMD_PI_ACCESS (0x66)
139#define FLEXONENAND_CMD_RECOVER_LSB (0x05)
127 140
128/* NOTE: Those are not *REAL* commands */ 141/* NOTE: Those are not *REAL* commands */
129#define ONENAND_CMD_BUFFERRAM (0x1978) 142#define ONENAND_CMD_BUFFERRAM (0x1978)
143#define FLEXONENAND_CMD_READ_PI (0x1985)
130 144
131/* 145/*
132 * System Configuration 1 Register F221h (R, R/W) 146 * System Configuration 1 Register F221h (R, R/W)
@@ -192,10 +206,12 @@
192#define ONENAND_ECC_1BIT_ALL (0x5555) 206#define ONENAND_ECC_1BIT_ALL (0x5555)
193#define ONENAND_ECC_2BIT (1 << 1) 207#define ONENAND_ECC_2BIT (1 << 1)
194#define ONENAND_ECC_2BIT_ALL (0xAAAA) 208#define ONENAND_ECC_2BIT_ALL (0xAAAA)
209#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
195 210
196/* 211/*
197 * One-Time Programmable (OTP) 212 * One-Time Programmable (OTP)
198 */ 213 */
214#define FLEXONENAND_OTP_LOCK_OFFSET (2048)
199#define ONENAND_OTP_LOCK_OFFSET (14) 215#define ONENAND_OTP_LOCK_OFFSET (14)
200 216
201#endif /* __ONENAND_REG_H */ 217#endif /* __ONENAND_REG_H */