9 files changed, 1278 insertions, 0 deletions

diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
new file mode 100644
index 00000000000..838c6b487cc
--- /dev/null
+++ b/include/linux/mfd/ab8500.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ */
+#ifndef MFD_AB8500_H
+#define MFD_AB8500_H
+
+#include <linux/device.h>
+
+/*
+ * AB8500 bank addresses
+ */
+#define AB8500_SYS_CTRL1_BLOCK  0x1
+#define AB8500_SYS_CTRL2_BLOCK  0x2
+#define AB8500_REGU_CTRL1       0x3
+#define AB8500_REGU_CTRL2       0x4
+#define AB8500_USB              0x5
+#define AB8500_TVOUT            0x6
+#define AB8500_DBI              0x7
+#define AB8500_ECI_AV_ACC       0x8
+#define AB8500_RESERVED         0x9
+#define AB8500_GPADC            0xA
+#define AB8500_CHARGER          0xB
+#define AB8500_GAS_GAUGE        0xC
+#define AB8500_AUDIO            0xD
+#define AB8500_INTERRUPT        0xE
+#define AB8500_RTC              0xF
+#define AB8500_MISC             0x10
+#define AB8500_DEVELOPMENT      0x11
+#define AB8500_DEBUG            0x12
+#define AB8500_PROD_TEST        0x13
+#define AB8500_OTP_EMUL         0x15
+
+/*
+ * Interrupts
+ */
+
+#define AB8500_INT_MAIN_EXT_CH_NOT_OK   0
+#define AB8500_INT_UN_PLUG_TV_DET       1
+#define AB8500_INT_PLUG_TV_DET          2
+#define AB8500_INT_TEMP_WARM            3
+#define AB8500_INT_PON_KEY2DB_F         4
+#define AB8500_INT_PON_KEY2DB_R         5
+#define AB8500_INT_PON_KEY1DB_F         6
+#define AB8500_INT_PON_KEY1DB_R         7
+#define AB8500_INT_BATT_OVV             8
+#define AB8500_INT_MAIN_CH_UNPLUG_DET   10
+#define AB8500_INT_MAIN_CH_PLUG_DET     11
+#define AB8500_INT_USB_ID_DET_F         12
+#define AB8500_INT_USB_ID_DET_R         13
+#define AB8500_INT_VBUS_DET_F           14
+#define AB8500_INT_VBUS_DET_R           15
+#define AB8500_INT_VBUS_CH_DROP_END     16
+#define AB8500_INT_RTC_60S              17
+#define AB8500_INT_RTC_ALARM            18
+#define AB8500_INT_BAT_CTRL_INDB        20
+#define AB8500_INT_CH_WD_EXP            21
+#define AB8500_INT_VBUS_OVV             22
+#define AB8500_INT_MAIN_CH_DROP_END     23
+#define AB8500_INT_CCN_CONV_ACC         24
+#define AB8500_INT_INT_AUD              25
+#define AB8500_INT_CCEOC                26
+#define AB8500_INT_CC_INT_CALIB         27
+#define AB8500_INT_LOW_BAT_F            28
+#define AB8500_INT_LOW_BAT_R            29
+#define AB8500_INT_BUP_CHG_NOT_OK       30
+#define AB8500_INT_BUP_CHG_OK           31
+#define AB8500_INT_GP_HW_ADC_CONV_END   32
+#define AB8500_INT_ACC_DETECT_1DB_F     33
+#define AB8500_INT_ACC_DETECT_1DB_R     34
+#define AB8500_INT_ACC_DETECT_22DB_F    35
+#define AB8500_INT_ACC_DETECT_22DB_R    36
+#define AB8500_INT_ACC_DETECT_21DB_F    37
+#define AB8500_INT_ACC_DETECT_21DB_R    38
+#define AB8500_INT_GP_SW_ADC_CONV_END   39
+#define AB8500_INT_GPIO6R               40
+#define AB8500_INT_GPIO7R               41
+#define AB8500_INT_GPIO8R               42
+#define AB8500_INT_GPIO9R               43
+#define AB8500_INT_GPIO10R              44
+#define AB8500_INT_GPIO11R              45
+#define AB8500_INT_GPIO12R              46
+#define AB8500_INT_GPIO13R              47
+#define AB8500_INT_GPIO24R              48
+#define AB8500_INT_GPIO25R              49
+#define AB8500_INT_GPIO36R              50
+#define AB8500_INT_GPIO37R              51
+#define AB8500_INT_GPIO38R              52
+#define AB8500_INT_GPIO39R              53
+#define AB8500_INT_GPIO40R              54
+#define AB8500_INT_GPIO41R              55
+#define AB8500_INT_GPIO6F               56
+#define AB8500_INT_GPIO7F               57
+#define AB8500_INT_GPIO8F               58
+#define AB8500_INT_GPIO9F               59
+#define AB8500_INT_GPIO10F              60
+#define AB8500_INT_GPIO11F              61
+#define AB8500_INT_GPIO12F              62
+#define AB8500_INT_GPIO13F              63
+#define AB8500_INT_GPIO24F              64
+#define AB8500_INT_GPIO25F              65
+#define AB8500_INT_GPIO36F              66
+#define AB8500_INT_GPIO37F              67
+#define AB8500_INT_GPIO38F              68
+#define AB8500_INT_GPIO39F              69
+#define AB8500_INT_GPIO40F              70
+#define AB8500_INT_GPIO41F              71
+#define AB8500_INT_ADP_SOURCE_ERROR     72
+#define AB8500_INT_ADP_SINK_ERROR       73
+#define AB8500_INT_ADP_PROBE_PLUG       74
+#define AB8500_INT_ADP_PROBE_UNPLUG     75
+#define AB8500_INT_ADP_SENSE_OFF        76
+#define AB8500_INT_USB_PHY_POWER_ERR    78
+#define AB8500_INT_USB_LINK_STATUS      79
+#define AB8500_INT_BTEMP_LOW            80
+#define AB8500_INT_BTEMP_LOW_MEDIUM     81
+#define AB8500_INT_BTEMP_MEDIUM_HIGH    82
+#define AB8500_INT_BTEMP_HIGH           83
+#define AB8500_INT_USB_CHARGER_NOT_OK   89
+#define AB8500_INT_ID_WAKEUP_R          90
+#define AB8500_INT_ID_DET_R1R           92
+#define AB8500_INT_ID_DET_R2R           93
+#define AB8500_INT_ID_DET_R3R           94
+#define AB8500_INT_ID_DET_R4R           95
+#define AB8500_INT_ID_WAKEUP_F          96
+#define AB8500_INT_ID_DET_R1F           98
+#define AB8500_INT_ID_DET_R2F           99
+#define AB8500_INT_ID_DET_R3F           100
+#define AB8500_INT_ID_DET_R4F           101
+#define AB8500_INT_USB_CHG_DET_DONE     102
+#define AB8500_INT_USB_CH_TH_PROT_F     104
+#define AB8500_INT_USB_CH_TH_PROT_R    105
+#define AB8500_INT_MAIN_CH_TH_PROT_F   106
+#define AB8500_INT_MAIN_CH_TH_PROT_R    107
+#define AB8500_INT_USB_CHARGER_NOT_OKF  111
+
+#define AB8500_NR_IRQS                  112
+#define AB8500_NUM_IRQ_REGS             14
+
+/**
+ * struct ab8500 - ab8500 internal structure
+ * @dev: parent device
+ * @lock: read/write operations lock
+ * @irq_lock: genirq bus lock
+ * @irq: irq line
+ * @chip_id: chip revision id
+ * @write: register write
+ * @read: register read
+ * @rx_buf: rx buf for SPI
+ * @tx_buf: tx buf for SPI
+ * @mask: cache of IRQ regs for bus lock
+ * @oldmask: cache of previous IRQ regs for bus lock
+ */
+struct ab8500 {
+        struct device   *dev;
+        struct mutex    lock;
+        struct mutex    irq_lock;
+
+        int             irq_base;
+        int             irq;
+        u8              chip_id;
+
+        int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
+        int (*read) (struct ab8500 *a8500, u16 addr);
+
+        unsigned long   tx_buf[4];
+        unsigned long   rx_buf[4];
+
+        u8 mask[AB8500_NUM_IRQ_REGS];
+        u8 oldmask[AB8500_NUM_IRQ_REGS];
+};
+
+struct regulator_reg_init;
+struct regulator_init_data;
+struct ab8500_gpio_platform_data;
+
+/**
+ * struct ab8500_platform_data - AB8500 platform data
+ * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
+ * @init: board-specific initialization after detection of ab8500
+ * @num_regulator_reg_init: number of regulator init registers
+ * @regulator_reg_init: regulator init registers
+ * @num_regulator: number of regulators
+ * @regulator: machine-specific constraints for regulators
+ */
+struct ab8500_platform_data {
+        int irq_base;
+        void (*init) (struct ab8500 *);
+        int num_regulator_reg_init;
+        struct ab8500_regulator_reg_init *regulator_reg_init;
+        int num_regulator;
+        struct regulator_init_data *regulator;
+        struct ab8500_gpio_platform_data *gpio;
+};
+
+extern int __devinit ab8500_init(struct ab8500 *ab8500);
+extern int __devexit ab8500_exit(struct ab8500 *ab8500);
+
+#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/ab8500/gpadc.h b/include/linux/mfd/ab8500/gpadc.h
new file mode 100644
index 00000000000..46b954011f1
--- /dev/null
+++ b/include/linux/mfd/ab8500/gpadc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2010 ST-Ericsson SA
+ * Licensed under GPLv2.
+ *
+ * Author: Arun R Murthy <arun.murthy@stericsson.com>
+ * Author: Daniel Willerud <daniel.willerud@stericsson.com>
+ */
+
+#ifndef _AB8500_GPADC_H
+#define _AB8500_GPADC_H
+
+/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2) */
+#define BAT_CTRL        0x01
+#define BTEMP_BALL      0x02
+#define MAIN_CHARGER_V  0x03
+#define ACC_DETECT1     0x04
+#define ACC_DETECT2     0x05
+#define ADC_AUX1        0x06
+#define ADC_AUX2        0x07
+#define MAIN_BAT_V      0x08
+#define VBUS_V          0x09
+#define MAIN_CHARGER_C  0x0A
+#define USB_CHARGER_C   0x0B
+#define BK_BAT_V        0x0C
+#define DIE_TEMP        0x0D
+
+struct ab8500_gpadc;
+
+struct ab8500_gpadc *ab8500_gpadc_get(char *name);
+int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 input);
+
+#endif /* _AB8500_GPADC_H */
diff --git a/include/linux/mfd/ab8500/gpio.h b/include/linux/mfd/ab8500/gpio.h
new file mode 100644
index 00000000000..488a8c920a2
--- /dev/null
+++ b/include/linux/mfd/ab8500/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright ST-Ericsson 2010.
+ *
+ * Author: Bibek Basu <bibek.basu@stericsson.com>
+ * Licensed under GPLv2.
+ */
+
+#ifndef _AB8500_GPIO_H
+#define _AB8500_GPIO_H
+
+/*
+ * Platform data to register a block: only the initial gpio/irq number.
+ */
+
+struct ab8500_gpio_platform_data {
+        int gpio_base;
+        u32 irq_base;
+        u8  config_reg[7];
+};
+
+#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/ab8500/sysctrl.h b/include/linux/mfd/ab8500/sysctrl.h
new file mode 100644
index 00000000000..10da0291f8f
--- /dev/null
+++ b/include/linux/mfd/ab8500/sysctrl.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __AB8500_SYSCTRL_H
+#define __AB8500_SYSCTRL_H
+
+#include <linux/bitops.h>
+
+#ifdef CONFIG_AB8500_CORE
+
+int ab8500_sysctrl_read(u16 reg, u8 *value);
+int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
+
+#else
+
+static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
+{
+        return 0;
+}
+
+static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
+{
+        return 0;
+}
+
+#endif /* CONFIG_AB8500_CORE */
+
+static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
+{
+        return ab8500_sysctrl_write(reg, bits, bits);
+}
+
+static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
+{
+        return ab8500_sysctrl_write(reg, bits, 0);
+}
+
+/* Registers */
+#define AB8500_TURNONSTATUS             0x100
+#define AB8500_RESETSTATUS              0x101
+#define AB8500_PONKEY1PRESSSTATUS       0x102
+#define AB8500_SYSCLKREQSTATUS          0x142
+#define AB8500_STW4500CTRL1             0x180
+#define AB8500_STW4500CTRL2             0x181
+#define AB8500_STW4500CTRL3             0x200
+#define AB8500_MAINWDOGCTRL             0x201
+#define AB8500_MAINWDOGTIMER            0x202
+#define AB8500_LOWBAT                   0x203
+#define AB8500_BATTOK                   0x204
+#define AB8500_SYSCLKTIMER              0x205
+#define AB8500_SMPSCLKCTRL              0x206
+#define AB8500_SMPSCLKSEL1              0x207
+#define AB8500_SMPSCLKSEL2              0x208
+#define AB8500_SMPSCLKSEL3              0x209
+#define AB8500_SYSULPCLKCONF            0x20A
+#define AB8500_SYSULPCLKCTRL1           0x20B
+#define AB8500_SYSCLKCTRL               0x20C
+#define AB8500_SYSCLKREQ1VALID          0x20D
+#define AB8500_SYSTEMCTRLSUP            0x20F
+#define AB8500_SYSCLKREQ1RFCLKBUF       0x210
+#define AB8500_SYSCLKREQ2RFCLKBUF       0x211
+#define AB8500_SYSCLKREQ3RFCLKBUF       0x212
+#define AB8500_SYSCLKREQ4RFCLKBUF       0x213
+#define AB8500_SYSCLKREQ5RFCLKBUF       0x214
+#define AB8500_SYSCLKREQ6RFCLKBUF       0x215
+#define AB8500_SYSCLKREQ7RFCLKBUF       0x216
+#define AB8500_SYSCLKREQ8RFCLKBUF       0x217
+#define AB8500_DITHERCLKCTRL            0x220
+#define AB8500_SWATCTRL                 0x230
+#define AB8500_HIQCLKCTRL               0x232
+#define AB8500_VSIMSYSCLKCTRL           0x233
+
+/* Bits */
+#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
+#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
+#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
+#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
+#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
+#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
+#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
+
+#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
+#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
+
+#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
+#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
+
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
+#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
+
+#define AB8500_STW4500CTRL1_SWOFF BIT(0)
+#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
+#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
+
+#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
+#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
+#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
+#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
+#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
+#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
+
+#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
+#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
+#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
+#define AB8500_STW4500CTRL3_THSDENA BIT(3)
+
+#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
+#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
+#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
+
+#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
+#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
+
+#define AB8500_LOWBAT_LOWBATENA BIT(0)
+#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
+#define AB8500_LOWBAT_LOWBAT_SHIFT 1
+
+#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
+#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
+#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
+#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
+
+#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
+#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
+#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
+#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
+
+#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
+#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
+#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
+
+#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
+
+#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
+
+#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
+#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
+#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
+#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
+
+#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
+#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
+#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
+#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
+#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
+#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
+#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
+#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
+
+#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
+#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
+#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
+#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
+#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
+#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
+
+#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
+#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
+#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
+
+#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
+#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
+#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
+
+#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
+#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
+#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
+#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
+#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
+
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
+
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
+#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
+
+#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
+#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
+#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
+#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
+#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
+#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
+#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
+#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
+
+#define AB8500_SWATCTRL_UPDATERF BIT(0)
+#define AB8500_SWATCTRL_SWATENABLE BIT(1)
+#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
+#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
+#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
+
+#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
+#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
+
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
+#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
+
+#endif /* __AB8500_SYSCTRL_H */
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
new file mode 100644
index 00000000000..f0977986402
--- /dev/null
+++ b/include/linux/mfd/db5500-prcmu.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * U5500 PRCMU API.
+ */
+#ifndef __MACH_PRCMU_U5500_H
+#define __MACH_PRCMU_U5500_H
+
+#ifdef CONFIG_UX500_SOC_DB5500
+
+void db5500_prcmu_early_init(void);
+
+int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+#else /* !CONFIG_UX500_SOC_DB5500 */
+
+static inline void db5500_prcmu_early_init(void)
+{
+}
+
+static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        return -ENOSYS;
+}
+
+static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        return -ENOSYS;
+}
+
+#endif /* CONFIG_UX500_SOC_DB5500 */
+
+static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
+{
+#ifdef CONFIG_MACH_U5500_SIMULATOR
+        return 0;
+#else
+        return -1;
+#endif
+}
+
+#endif /* __MACH_PRCMU_U5500_H */
diff --git a/include/linux/mfd/max77663-core.h b/include/linux/mfd/max77663-core.h
new file mode 100644
index 00000000000..acfe22aac53
--- /dev/null
+++ b/include/linux/mfd/max77663-core.h
@@ -0,0 +1,178 @@
+/*
+ * include/linux/mfd/max77663-core.h
+ *
+ * Copyright 2011 Maxim Integrated Products, Inc.
+ * Copyright (C) 2011-2012 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_MAX77663_CORE_H__
+#define __LINUX_MFD_MAX77663_CORE_H__
+
+#include <linux/irq.h>
+#include <linux/mfd/core.h>
+
+/*
+ * Interrupts
+ */
+enum {
+        MAX77663_IRQ_LBT_LB,            /* Low-Battery */
+        MAX77663_IRQ_LBT_THERM_ALRM1,   /* Thermal alarm status, > 120C */
+        MAX77663_IRQ_LBT_THERM_ALRM2,   /* Thermal alarm status, > 140C */
+
+        MAX77663_IRQ_GPIO0,             /* GPIO0 edge detection */
+        MAX77663_IRQ_GPIO1,             /* GPIO1 edge detection */
+        MAX77663_IRQ_GPIO2,             /* GPIO2 edge detection */
+        MAX77663_IRQ_GPIO3,             /* GPIO3 edge detection */
+        MAX77663_IRQ_GPIO4,             /* GPIO4 edge detection */
+        MAX77663_IRQ_GPIO5,             /* GPIO5 edge detection */
+        MAX77663_IRQ_GPIO6,             /* GPIO6 edge detection */
+        MAX77663_IRQ_GPIO7,             /* GPIO7 edge detection */
+
+        MAX77663_IRQ_ONOFF_HRDPOWRN,    /* Hard power off warnning */
+        MAX77663_IRQ_ONOFF_EN0_1SEC,    /* EN0 active for 1s */
+        MAX77663_IRQ_ONOFF_EN0_FALLING, /* EN0 falling */
+        MAX77663_IRQ_ONOFF_EN0_RISING,  /* EN0 rising */
+        MAX77663_IRQ_ONOFF_LID_FALLING, /* LID falling */
+        MAX77663_IRQ_ONOFF_LID_RISING,  /* LID rising */
+        MAX77663_IRQ_ONOFF_ACOK_FALLING,/* ACOK falling */
+        MAX77663_IRQ_ONOFF_ACOK_RISING, /* ACOK rising */
+
+        MAX77663_IRQ_RTC,               /* RTC */
+        MAX77663_IRQ_SD_PF,             /* SD power fail */
+        MAX77663_IRQ_LDO_PF,            /* LDO power fail */
+        MAX77663_IRQ_32K,               /* 32kHz oscillator */
+        MAX77663_IRQ_NVER,              /* Non-Volatile Event Recorder */
+
+        MAX77663_IRQ_NR,
+};
+
+/*
+ *GPIOs
+ */
+enum {
+        MAX77663_GPIO0,
+        MAX77663_GPIO1,
+        MAX77663_GPIO2,
+        MAX77663_GPIO3,
+        MAX77663_GPIO4,
+        MAX77663_GPIO5,
+        MAX77663_GPIO6,
+        MAX77663_GPIO7,
+
+        MAX77663_GPIO_NR,
+};
+
+/* Direction */
+enum max77663_gpio_dir {
+        GPIO_DIR_DEF,
+        GPIO_DIR_IN,
+        GPIO_DIR_OUT,
+};
+
+/* Data output */
+enum max77663_gpio_data_out {
+        GPIO_DOUT_DEF,
+        GPIO_DOUT_HIGH,
+        GPIO_DOUT_LOW,
+};
+
+/* Output drive */
+enum max77663_gpio_out_drv {
+        GPIO_OUT_DRV_DEF,
+        GPIO_OUT_DRV_PUSH_PULL,
+        GPIO_OUT_DRV_OPEN_DRAIN,
+};
+
+/* Pull-up */
+enum max77663_gpio_pull_up {
+        GPIO_PU_DEF,
+        GPIO_PU_ENABLE,
+        GPIO_PU_DISABLE,
+};
+
+/* Pull-down */
+enum max77663_gpio_pull_down {
+        GPIO_PD_DEF,
+        GPIO_PD_ENABLE,
+        GPIO_PD_DISABLE,
+};
+
+/* Alternate */
+enum max77663_gpio_alt {
+        GPIO_ALT_DEF,
+        GPIO_ALT_ENABLE,
+        GPIO_ALT_DISABLE,
+};
+
+/*
+ * Flags
+ */
+#define SLP_LPM_ENABLE          0x01
+
+struct max77663_gpio_config {
+        int gpio;       /* gpio number */
+        enum max77663_gpio_dir dir;
+        enum max77663_gpio_data_out dout;
+        enum max77663_gpio_out_drv out_drv;
+        enum max77663_gpio_pull_up pull_up;
+        enum max77663_gpio_pull_down pull_down;
+        enum max77663_gpio_alt alternate;
+};
+
+struct max77663_platform_data {
+        int irq_base;
+        int gpio_base;
+
+        int num_gpio_cfgs;
+        struct max77663_gpio_config *gpio_cfgs;
+
+        int num_subdevs;
+        struct mfd_cell *sub_devices;
+
+        unsigned int flags;
+
+        unsigned char rtc_i2c_addr;
+
+        bool use_power_off;
+};
+
+#if defined(CONFIG_MFD_MAX77663)
+int max77663_read(struct device *dev, u8 addr, void *values, u32 len,
+                  bool is_rtc);
+int max77663_write(struct device *dev, u8 addr, void *values, u32 len,
+                   bool is_rtc);
+int max77663_set_bits(struct device *dev, u8 addr, u8 mask, u8 value,
+                      bool is_rtc);
+int max77663_gpio_set_alternate(int gpio, int alternate);
+#else
+static inline int max77663_read(struct device *dev, u8 addr, void *values,
+                                u32 len, bool is_rtc)
+{
+        return 0;
+}
+
+static inline int max77663_write(struct device *dev, u8 addr, void *values,
+                                 u32 len, bool is_rtc)
+{
+        return 0;
+}
+
+static inline int max77663_set_bits(struct device *dev, u8 addr, u8 mask,
+                                    u8 value, bool is_rtc)
+{
+        return 0;
+}
+
+static inline int max77663_gpio_set_alternate(int gpio, int alternate)
+{
+        return 0;
+}
+#endif /* defined(CONFIG_MFD_MAX77663) */
+
+#endif /* __LINUX_MFD_MAX77663_CORE_H__ */
diff --git a/include/linux/mfd/max8907c.h b/include/linux/mfd/max8907c.h
new file mode 100644
index 00000000000..48014b0485c
--- /dev/null
+++ b/include/linux/mfd/max8907c.h
@@ -0,0 +1,259 @@
+/* linux/mfd/max8907c.h
+ *
+ * Functions to access MAX8907C power management chip.
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MFD_MAX8907C_H
+#define __LINUX_MFD_MAX8907C_H
+
+/* MAX8907C register map */
+#define MAX8907C_REG_SYSENSEL               0x00
+#define MAX8907C_REG_ON_OFF_IRQ1            0x01
+#define MAX8907C_REG_ON_OFF_IRQ1_MASK       0x02
+#define MAX8907C_REG_ON_OFF_STAT            0x03
+#define MAX8907C_REG_SDCTL1                 0x04
+#define MAX8907C_REG_SDSEQCNT1              0x05
+#define MAX8907C_REG_SDV1                   0x06
+#define MAX8907C_REG_SDCTL2                 0x07
+#define MAX8907C_REG_SDSEQCNT2              0x08
+#define MAX8907C_REG_SDV2                   0x09
+#define MAX8907C_REG_SDCTL3                 0x0A
+#define MAX8907C_REG_SDSEQCNT3              0x0B
+#define MAX8907C_REG_SDV3                   0x0C
+#define MAX8907C_REG_ON_OFF_IRQ2            0x0D
+#define MAX8907C_REG_ON_OFF_IRQ2_MASK       0x0E
+#define MAX8907C_REG_RESET_CNFG             0x0F
+#define MAX8907C_REG_LDOCTL16               0x10
+#define MAX8907C_REG_LDOSEQCNT16            0x11
+#define MAX8907C_REG_LDO16VOUT              0x12
+#define MAX8907C_REG_SDBYSEQCNT             0x13
+#define MAX8907C_REG_LDOCTL17               0x14
+#define MAX8907C_REG_LDOSEQCNT17            0x15
+#define MAX8907C_REG_LDO17VOUT              0x16
+#define MAX8907C_REG_LDOCTL1                0x18
+#define MAX8907C_REG_LDOSEQCNT1             0x19
+#define MAX8907C_REG_LDO1VOUT               0x1A
+#define MAX8907C_REG_LDOCTL2                0x1C
+#define MAX8907C_REG_LDOSEQCNT2             0x1D
+#define MAX8907C_REG_LDO2VOUT               0x1E
+#define MAX8907C_REG_LDOCTL3                0x20
+#define MAX8907C_REG_LDOSEQCNT3             0x21
+#define MAX8907C_REG_LDO3VOUT               0x22
+#define MAX8907C_REG_LDOCTL4                0x24
+#define MAX8907C_REG_LDOSEQCNT4             0x25
+#define MAX8907C_REG_LDO4VOUT               0x26
+#define MAX8907C_REG_LDOCTL5                0x28
+#define MAX8907C_REG_LDOSEQCNT5             0x29
+#define MAX8907C_REG_LDO5VOUT               0x2A
+#define MAX8907C_REG_LDOCTL6                0x2C
+#define MAX8907C_REG_LDOSEQCNT6             0x2D
+#define MAX8907C_REG_LDO6VOUT               0x2E
+#define MAX8907C_REG_LDOCTL7                0x30
+#define MAX8907C_REG_LDOSEQCNT7             0x31
+#define MAX8907C_REG_LDO7VOUT               0x32
+#define MAX8907C_REG_LDOCTL8                0x34
+#define MAX8907C_REG_LDOSEQCNT8             0x35
+#define MAX8907C_REG_LDO8VOUT               0x36
+#define MAX8907C_REG_LDOCTL9                0x38
+#define MAX8907C_REG_LDOSEQCNT9             0x39
+#define MAX8907C_REG_LDO9VOUT               0x3A
+#define MAX8907C_REG_LDOCTL10               0x3C
+#define MAX8907C_REG_LDOSEQCNT10            0x3D
+#define MAX8907C_REG_LDO10VOUT              0x3E
+#define MAX8907C_REG_LDOCTL11               0x40
+#define MAX8907C_REG_LDOSEQCNT11            0x41
+#define MAX8907C_REG_LDO11VOUT              0x42
+#define MAX8907C_REG_LDOCTL12               0x44
+#define MAX8907C_REG_LDOSEQCNT12            0x45
+#define MAX8907C_REG_LDO12VOUT              0x46
+#define MAX8907C_REG_LDOCTL13               0x48
+#define MAX8907C_REG_LDOSEQCNT13            0x49
+#define MAX8907C_REG_LDO13VOUT              0x4A
+#define MAX8907C_REG_LDOCTL14               0x4C
+#define MAX8907C_REG_LDOSEQCNT14            0x4D
+#define MAX8907C_REG_LDO14VOUT              0x4E
+#define MAX8907C_REG_LDOCTL15               0x50
+#define MAX8907C_REG_LDOSEQCNT15            0x51
+#define MAX8907C_REG_LDO15VOUT              0x52
+#define MAX8907C_REG_OUT5VEN                0x54
+#define MAX8907C_REG_OUT5VSEQ               0x55
+#define MAX8907C_REG_OUT33VEN               0x58
+#define MAX8907C_REG_OUT33VSEQ              0x59
+#define MAX8907C_REG_LDOCTL19               0x5C
+#define MAX8907C_REG_LDOSEQCNT19            0x5D
+#define MAX8907C_REG_LDO19VOUT              0x5E
+#define MAX8907C_REG_LBCNFG                 0x60
+#define MAX8907C_REG_SEQ1CNFG               0x64
+#define MAX8907C_REG_SEQ2CNFG               0x65
+#define MAX8907C_REG_SEQ3CNFG               0x66
+#define MAX8907C_REG_SEQ4CNFG               0x67
+#define MAX8907C_REG_SEQ5CNFG               0x68
+#define MAX8907C_REG_SEQ6CNFG               0x69
+#define MAX8907C_REG_SEQ7CNFG               0x6A
+#define MAX8907C_REG_LDOCTL18               0x72
+#define MAX8907C_REG_LDOSEQCNT18            0x73
+#define MAX8907C_REG_LDO18VOUT              0x74
+#define MAX8907C_REG_BBAT_CNFG              0x78
+#define MAX8907C_REG_CHG_CNTL1              0x7C
+#define MAX8907C_REG_CHG_CNTL2              0x7D
+#define MAX8907C_REG_CHG_IRQ1               0x7E
+#define MAX8907C_REG_CHG_IRQ2               0x7F
+#define MAX8907C_REG_CHG_IRQ1_MASK          0x80
+#define MAX8907C_REG_CHG_IRQ2_MASK          0x81
+#define MAX8907C_REG_CHG_STAT               0x82
+#define MAX8907C_REG_WLED_MODE_CNTL         0x84
+#define MAX8907C_REG_ILED_CNTL              0x84
+#define MAX8907C_REG_II1RR                  0x8E
+#define MAX8907C_REG_II2RR                  0x8F
+#define MAX8907C_REG_LDOCTL20               0x9C
+#define MAX8907C_REG_LDOSEQCNT20            0x9D
+#define MAX8907C_REG_LDO20VOUT              0x9E
+
+/* RTC register */
+#define MAX8907C_REG_RTC_SEC                0x00
+#define MAX8907C_REG_RTC_MIN                0x01
+#define MAX8907C_REG_RTC_HOURS              0x02
+#define MAX8907C_REG_RTC_WEEKDAY            0x03
+#define MAX8907C_REG_RTC_DATE               0x04
+#define MAX8907C_REG_RTC_MONTH              0x05
+#define MAX8907C_REG_RTC_YEAR1              0x06
+#define MAX8907C_REG_RTC_YEAR2              0x07
+#define MAX8907C_REG_ALARM0_SEC             0x08
+#define MAX8907C_REG_ALARM0_MIN             0x09
+#define MAX8907C_REG_ALARM0_HOURS           0x0A
+#define MAX8907C_REG_ALARM0_WEEKDAY         0x0B
+#define MAX8907C_REG_ALARM0_DATE            0x0C
+#define MAX8907C_REG_ALARM0_MONTH           0x0D
+#define MAX8907C_REG_ALARM0_YEAR1           0x0E
+#define MAX8907C_REG_ALARM0_YEAR2           0x0F
+#define MAX8907C_REG_ALARM1_SEC             0x10
+#define MAX8907C_REG_ALARM1_MIN             0x11
+#define MAX8907C_REG_ALARM1_HOURS           0x12
+#define MAX8907C_REG_ALARM1_WEEKDAY         0x13
+#define MAX8907C_REG_ALARM1_DATE            0x14
+#define MAX8907C_REG_ALARM1_MONTH           0x15
+#define MAX8907C_REG_ALARM1_YEAR1           0x16
+#define MAX8907C_REG_ALARM1_YEAR2           0x17
+#define MAX8907C_REG_ALARM0_CNTL            0x18
+#define MAX8907C_REG_ALARM1_CNTL            0x19
+#define MAX8907C_REG_RTC_STATUS             0x1A
+#define MAX8907C_REG_RTC_CNTL               0x1B
+#define MAX8907C_REG_RTC_IRQ                0x1C
+#define MAX8907C_REG_RTC_IRQ_MASK           0x1D
+#define MAX8907C_REG_MPL_CNTL               0x1E
+
+/* ADC and Touch Screen Controller register map */
+
+#define MAX8907C_CTL     0
+#define MAX8907C_SEQCNT  1
+#define MAX8907C_VOUT    2
+
+/* mask bit fields */
+#define MAX8907C_MASK_LDO_SEQ           0x1C
+#define MAX8907C_MASK_LDO_EN            0x01
+#define MAX8907C_MASK_VBBATTCV          0x03
+#define MAX8907C_MASK_OUT5V_VINEN       0x10
+#define MAX8907C_MASK_OUT5V_ENSRC       0x0E
+#define MAX8907C_MASK_OUT5V_EN          0x01
+
+/* Power off bit in RESET_CNFG reg */
+#define MAX8907C_MASK_POWER_OFF         0x40
+
+#define MAX8907C_MASK_PWR_EN            0x80
+#define MAX8907C_MASK_CTL_SEQ           0x1C
+
+#define MAX8907C_PWR_EN                 0x80
+#define MAX8907C_CTL_SEQ                0x04
+
+#define MAX8907C_SD_SEQ1                0x02
+#define MAX8907C_SD_SEQ2                0x06
+
+#define MAX8907C_DELAY_CNT0             0x00
+
+#define MAX8907C_POWER_UP_DELAY_CNT1    0x10
+#define MAX8907C_POWER_UP_DELAY_CNT12   0xC0
+
+#define MAX8907C_POWER_DOWN_DELAY_CNT12 0x0C
+
+#define RTC_I2C_ADDR                    0x68
+
+/*
+ * MAX8907B revision requires s/w WAR to connect PWREN input to
+ * sequencer 2 because of the bug in the silicon.
+ */
+#define MAX8907B_II2RR_PWREN_WAR                (0x12)
+
+/* Defines common for all supplies PWREN  sequencer selection */
+#define MAX8907B_SEQSEL_PWREN_LXX               1 /* SEQ2 (PWREN) */
+
+/* IRQ definitions */
+enum {
+        MAX8907C_IRQ_VCHG_DC_OVP,
+        MAX8907C_IRQ_VCHG_DC_F,
+        MAX8907C_IRQ_VCHG_DC_R,
+        MAX8907C_IRQ_VCHG_THM_OK_R,
+        MAX8907C_IRQ_VCHG_THM_OK_F,
+        MAX8907C_IRQ_VCHG_MBATTLOW_F,
+        MAX8907C_IRQ_VCHG_MBATTLOW_R,
+        MAX8907C_IRQ_VCHG_RST,
+        MAX8907C_IRQ_VCHG_DONE,
+        MAX8907C_IRQ_VCHG_TOPOFF,
+        MAX8907C_IRQ_VCHG_TMR_FAULT,
+        MAX8907C_IRQ_GPM_RSTIN,
+        MAX8907C_IRQ_GPM_MPL,
+        MAX8907C_IRQ_GPM_SW_3SEC,
+        MAX8907C_IRQ_GPM_EXTON_F,
+        MAX8907C_IRQ_GPM_EXTON_R,
+        MAX8907C_IRQ_GPM_SW_1SEC,
+        MAX8907C_IRQ_GPM_SW_F,
+        MAX8907C_IRQ_GPM_SW_R,
+        MAX8907C_IRQ_GPM_SYSCKEN_F,
+        MAX8907C_IRQ_GPM_SYSCKEN_R,
+        MAX8907C_IRQ_RTC_ALARM1,
+        MAX8907C_IRQ_RTC_ALARM0,
+        MAX8907C_NR_IRQS,
+};
+
+struct max8907c {
+        struct device           *dev;
+        struct mutex            io_lock;
+        struct mutex            irq_lock;
+        struct i2c_client       *i2c_power;
+        struct i2c_client       *i2c_rtc;
+        int                     irq_base;
+        int                     core_irq;
+
+        unsigned char           cache_chg[2];
+        unsigned char           cache_on[2];
+        unsigned char           cache_rtc;
+
+};
+
+struct max8907c_platform_data {
+        int num_subdevs;
+        struct platform_device **subdevs;
+        int irq_base;
+        int (*max8907c_setup)(void);
+        bool use_power_off;
+};
+
+int max8907c_reg_read(struct i2c_client *i2c, u8 reg);
+int max8907c_reg_bulk_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *val);
+int max8907c_reg_write(struct i2c_client *i2c, u8 reg, u8 val);
+int max8907c_reg_bulk_write(struct i2c_client *i2c, u8 reg, u8 count, u8 *val);
+int max8907c_set_bits(struct i2c_client *i2c, u8 reg, u8 mask, u8 val);
+
+int max8907c_irq_init(struct max8907c *chip, int irq, int irq_base);
+void max8907c_irq_free(struct max8907c *chip);
+int max8907c_suspend(struct i2c_client *i2c, pm_message_t state);
+int max8907c_resume(struct i2c_client *i2c);
+void max8907c_deep_sleep(int enter);
+int max8907c_pwr_en_config(void);
+int max8907c_pwr_en_attach(void);
+#endif
diff --git a/include/linux/mfd/ricoh583.h b/include/linux/mfd/ricoh583.h
new file mode 100644
index 00000000000..4e38cded0fa
--- /dev/null
+++ b/include/linux/mfd/ricoh583.h
@@ -0,0 +1,164 @@
+/* include/linux/mfd/ricoh583.h
+ *
+ * Core driver interface to access RICOH583 power management chip.
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_RICOH583_H
+#define __LINUX_MFD_RICOH583_H
+
+#include <linux/rtc.h>
+/* RICOH583 IRQ definitions */
+enum {
+        RICOH583_IRQ_ONKEY,
+        RICOH583_IRQ_ACOK,
+        RICOH583_IRQ_LIDOPEN,
+        RICOH583_IRQ_PREOT,
+        RICOH583_IRQ_CLKSTP,
+        RICOH583_IRQ_ONKEY_OFF,
+        RICOH583_IRQ_WD,
+        RICOH583_IRQ_EN_PWRREQ1,
+        RICOH583_IRQ_EN_PWRREQ2,
+        RICOH583_IRQ_PRE_VINDET,
+
+        RICOH583_IRQ_DC0LIM,
+        RICOH583_IRQ_DC1LIM,
+        RICOH583_IRQ_DC2LIM,
+        RICOH583_IRQ_DC3LIM,
+
+        RICOH583_IRQ_CTC,
+        RICOH583_IRQ_YALE,
+        RICOH583_IRQ_DALE,
+        RICOH583_IRQ_WALE,
+
+        RICOH583_IRQ_AIN1L,
+        RICOH583_IRQ_AIN2L,
+        RICOH583_IRQ_AIN3L,
+        RICOH583_IRQ_VBATL,
+        RICOH583_IRQ_VIN3L,
+        RICOH583_IRQ_VIN8L,
+        RICOH583_IRQ_AIN1H,
+        RICOH583_IRQ_AIN2H,
+        RICOH583_IRQ_AIN3H,
+        RICOH583_IRQ_VBATH,
+        RICOH583_IRQ_VIN3H,
+        RICOH583_IRQ_VIN8H,
+        RICOH583_IRQ_ADCEND,
+
+        RICOH583_IRQ_GPIO0,
+        RICOH583_IRQ_GPIO1,
+        RICOH583_IRQ_GPIO2,
+        RICOH583_IRQ_GPIO3,
+        RICOH583_IRQ_GPIO4,
+        RICOH583_IRQ_GPIO5,
+        RICOH583_IRQ_GPIO6,
+        RICOH583_IRQ_GPIO7,
+        RICOH583_NR_IRQS,
+};
+
+/* Ricoh583 gpio definitions */
+enum {
+        RICOH583_GPIO0,
+        RICOH583_GPIO1,
+        RICOH583_GPIO2,
+        RICOH583_GPIO3,
+        RICOH583_GPIO4,
+        RICOH583_GPIO5,
+        RICOH583_GPIO6,
+        RICOH583_GPIO7,
+
+        RICOH583_NR_GPIO,
+};
+
+enum ricoh583_deepsleep_control_id {
+        RICOH583_DS_NONE,
+        RICOH583_DS_DC0,
+        RICOH583_DS_DC1,
+        RICOH583_DS_DC2,
+        RICOH583_DS_DC3,
+        RICOH583_DS_LDO0,
+        RICOH583_DS_LDO1,
+        RICOH583_DS_LDO2,
+        RICOH583_DS_LDO3,
+        RICOH583_DS_LDO4,
+        RICOH583_DS_LDO5,
+        RICOH583_DS_LDO6,
+        RICOH583_DS_LDO7,
+        RICOH583_DS_LDO8,
+        RICOH583_DS_LDO9,
+        RICOH583_DS_PSO0,
+        RICOH583_DS_PSO1,
+        RICOH583_DS_PSO2,
+        RICOH583_DS_PSO3,
+        RICOH583_DS_PSO4,
+        RICOH583_DS_PSO5,
+        RICOH583_DS_PSO6,
+        RICOH583_DS_PSO7,
+};
+enum ricoh583_ext_pwrreq_control {
+        RICOH583_EXT_PWRREQ1_CONTROL = 0x1,
+        RICOH583_EXT_PWRREQ2_CONTROL = 0x2,
+};
+
+struct ricoh583_subdev_info {
+        int             id;
+        const char      *name;
+        void            *platform_data;
+};
+
+struct ricoh583_rtc_platform_data {
+        int irq;
+        struct rtc_time time;
+};
+
+struct ricoh583_gpio_init_data {
+        unsigned pulldn_en:1;   /* Enable pull down */
+        unsigned output_mode_en:1; /* Enable output mode during init */
+        unsigned output_val:1;  /* Output value if it is in output mode */
+        unsigned init_apply:1;  /* Apply init data on configuring gpios*/
+};
+
+struct ricoh583_platform_data {
+        int             num_subdevs;
+        struct  ricoh583_subdev_info *subdevs;
+        int             gpio_base;
+        int             irq_base;
+
+        struct ricoh583_gpio_init_data *gpio_init_data;
+        int num_gpioinit_data;
+        bool enable_shutdown_pin;
+};
+
+extern int ricoh583_read(struct device *dev, uint8_t reg, uint8_t *val);
+extern int ricoh583_bulk_reads(struct device *dev, u8 reg, u8 count,
+                                uint8_t *val);
+extern int ricoh583_write(struct device *dev, u8 reg, uint8_t val);
+extern int ricoh583_bulk_writes(struct device *dev, u8 reg, u8 count,
+                                uint8_t *val);
+extern int ricoh583_set_bits(struct device *dev, u8 reg, uint8_t bit_mask);
+extern int ricoh583_clr_bits(struct device *dev, u8 reg, uint8_t bit_mask);
+extern int ricoh583_update(struct device *dev, u8 reg, uint8_t val,
+                                        uint8_t mask);
+extern int ricoh583_ext_power_req_config(struct device *dev,
+                enum ricoh583_deepsleep_control_id control_id,
+                enum ricoh583_ext_pwrreq_control ext_pwr_req,
+                int deepsleep_slot_nr);
+extern int ricoh583_power_off(void);
+
+#endif
diff --git a/include/linux/mfd/tps6591x.h b/include/linux/mfd/tps6591x.h
new file mode 100644
index 00000000000..d0d829fc8ab
--- /dev/null
+++ b/include/linux/mfd/tps6591x.h
@@ -0,0 +1,124 @@
+/*
+ * include/linux/mfd/tps6591x.c
+ * Core driver interface for TI TPS6591x PMIC family
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#ifndef __LINUX_MFD_TPS6591X_H
+#define __LINUX_MFD_TPS6591X_H
+
+#include <linux/rtc.h>
+
+enum {
+        TPS6591X_INT_PWRHOLD_F,
+        TPS6591X_INT_VMBHI,
+        TPS6591X_INT_PWRON,
+        TPS6591X_INT_PWRON_LP,
+        TPS6591X_INT_PWRHOLD_R,
+        TPS6591X_INT_HOTDIE,
+        TPS6591X_INT_RTC_ALARM,
+        TPS6591X_INT_RTC_PERIOD,
+        TPS6591X_INT_GPIO0,
+        TPS6591X_INT_GPIO1,
+        TPS6591X_INT_GPIO2,
+        TPS6591X_INT_GPIO3,
+        TPS6591X_INT_GPIO4,
+        TPS6591X_INT_GPIO5,
+        TPS6591X_INT_WTCHDG,
+        TPS6591X_INT_VMBCH2_H,
+        TPS6591X_INT_VMBCH2_L,
+        TPS6591X_INT_PWRDN,
+
+        /* Last entry */
+        TPS6591X_INT_NR,
+};
+
+/* Gpio definitions */
+enum {
+        TPS6591X_GPIO_GP0 = 0,
+        TPS6591X_GPIO_GP1 = 1,
+        TPS6591X_GPIO_GP2 = 2,
+        TPS6591X_GPIO_GP3 = 3,
+        TPS6591X_GPIO_GP4 = 4,
+        TPS6591X_GPIO_GP5 = 5,
+        TPS6591X_GPIO_GP6 = 6,
+        TPS6591X_GPIO_GP7 = 7,
+        TPS6591X_GPIO_GP8 = 8,
+
+        /* Last entry */
+        TPS6591X_GPIO_NR,
+};
+
+struct tps6591x_subdev_info {
+        int             id;
+        const char      *name;
+        void            *platform_data;
+};
+
+struct tps6591x_rtc_platform_data {
+        int irq;
+        struct rtc_time time;
+};
+
+struct tps6591x_sleep_keepon_data {
+        /* set 1 to maintain the following on sleep mode */
+        unsigned therm_keepon:1;        /* themal monitoring */
+        unsigned clkout32k_keepon:1;    /* CLK32KOUT */
+        unsigned vrtc_keepon:1;         /* LD0 full load capability */
+        unsigned i2chs_keepon:1;        /* high speed internal clock */
+};
+
+struct tps6591x_gpio_init_data {
+        unsigned sleep_en:1;    /* Enable sleep mode */
+        unsigned pulldn_en:1;   /* Enable pull down */
+        unsigned output_mode_en:1; /* Enable output mode during init */
+        unsigned output_val:1;  /* Output value if it is in output mode */
+        unsigned init_apply:1;  /* Apply init data on configuring gpios*/
+};
+
+struct tps6591x_platform_data {
+        int gpio_base;
+        int irq_base;
+
+        int num_subdevs;
+        struct tps6591x_subdev_info *subdevs;
+
+        bool dev_slp_en;
+        struct tps6591x_sleep_keepon_data *slp_keepon;
+
+        struct tps6591x_gpio_init_data *gpio_init_data;
+        int num_gpioinit_data;
+
+        bool use_power_off;
+};
+
+/*
+ * NOTE: the functions below are not intended for use outside
+ * of the TPS6591X sub-device drivers
+ */
+extern int tps6591x_write(struct device *dev, int reg, uint8_t val);
+extern int tps6591x_writes(struct device *dev, int reg, int len, uint8_t *val);
+extern int tps6591x_read(struct device *dev, int reg, uint8_t *val);
+extern int tps6591x_reads(struct device *dev, int reg, int len, uint8_t *val);
+extern int tps6591x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
+extern int tps6591x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
+extern int tps6591x_update(struct device *dev, int reg, uint8_t val,
+                           uint8_t mask);
+
+#endif /*__LINUX_MFD_TPS6591X_H */