diff options
Diffstat (limited to 'include/linux/amba/pl08x.h')
-rw-r--r-- | include/linux/amba/pl08x.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h index e6e28f37d8e..a22662c9398 100644 --- a/include/linux/amba/pl08x.h +++ b/include/linux/amba/pl08x.h | |||
@@ -47,6 +47,9 @@ enum { | |||
47 | * @muxval: a number usually used to poke into some mux regiser to | 47 | * @muxval: a number usually used to poke into some mux regiser to |
48 | * mux in the signal to this channel | 48 | * mux in the signal to this channel |
49 | * @cctl_opt: default options for the channel control register | 49 | * @cctl_opt: default options for the channel control register |
50 | * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave | ||
51 | * channels. Fill with 'true' if peripheral should be flow controller. Direction | ||
52 | * will be selected at Runtime. | ||
50 | * @addr: source/target address in physical memory for this DMA channel, | 53 | * @addr: source/target address in physical memory for this DMA channel, |
51 | * can be the address of a FIFO register for burst requests for example. | 54 | * can be the address of a FIFO register for burst requests for example. |
52 | * This can be left undefined if the PrimeCell API is used for configuring | 55 | * This can be left undefined if the PrimeCell API is used for configuring |
@@ -65,6 +68,7 @@ struct pl08x_channel_data { | |||
65 | int max_signal; | 68 | int max_signal; |
66 | u32 muxval; | 69 | u32 muxval; |
67 | u32 cctl; | 70 | u32 cctl; |
71 | bool device_fc; | ||
68 | dma_addr_t addr; | 72 | dma_addr_t addr; |
69 | bool circular_buffer; | 73 | bool circular_buffer; |
70 | bool single; | 74 | bool single; |
@@ -77,13 +81,11 @@ struct pl08x_channel_data { | |||
77 | * @addr: current address | 81 | * @addr: current address |
78 | * @maxwidth: the maximum width of a transfer on this bus | 82 | * @maxwidth: the maximum width of a transfer on this bus |
79 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | 83 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 |
80 | * @fill_bytes: bytes required to fill to the next bus memory boundary | ||
81 | */ | 84 | */ |
82 | struct pl08x_bus_data { | 85 | struct pl08x_bus_data { |
83 | dma_addr_t addr; | 86 | dma_addr_t addr; |
84 | u8 maxwidth; | 87 | u8 maxwidth; |
85 | u8 buswidth; | 88 | u8 buswidth; |
86 | size_t fill_bytes; | ||
87 | }; | 89 | }; |
88 | 90 | ||
89 | /** | 91 | /** |
@@ -105,8 +107,16 @@ struct pl08x_phy_chan { | |||
105 | 107 | ||
106 | /** | 108 | /** |
107 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | 109 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor |
110 | * @tx: async tx descriptor | ||
111 | * @node: node for txd list for channels | ||
112 | * @src_addr: src address of txd | ||
113 | * @dst_addr: dst address of txd | ||
114 | * @len: transfer len in bytes | ||
115 | * @direction: direction of transfer | ||
108 | * @llis_bus: DMA memory address (physical) start for the LLIs | 116 | * @llis_bus: DMA memory address (physical) start for the LLIs |
109 | * @llis_va: virtual memory address start for the LLIs | 117 | * @llis_va: virtual memory address start for the LLIs |
118 | * @cctl: control reg values for current txd | ||
119 | * @ccfg: config reg values for current txd | ||
110 | */ | 120 | */ |
111 | struct pl08x_txd { | 121 | struct pl08x_txd { |
112 | struct dma_async_tx_descriptor tx; | 122 | struct dma_async_tx_descriptor tx; |