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Diffstat (limited to 'include/asm-cris/arch-v32/hwregs/dma_defs.h')
-rw-r--r--include/asm-cris/arch-v32/hwregs/dma_defs.h436
1 files changed, 0 insertions, 436 deletions
diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h
deleted file mode 100644
index 48ac8cef7eb..00000000000
--- a/include/asm-cris/arch-v32/hwregs/dma_defs.h
+++ /dev/null
@@ -1,436 +0,0 @@
1#ifndef __dma_defs_h
2#define __dma_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
7 * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
8 * last modfied: Mon Apr 11 16:06:51 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
11 * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope dma */
86
87/* Register rw_data, scope dma, type rw */
88typedef unsigned int reg_dma_rw_data;
89#define REG_RD_ADDR_dma_rw_data 0
90#define REG_WR_ADDR_dma_rw_data 0
91
92/* Register rw_data_next, scope dma, type rw */
93typedef unsigned int reg_dma_rw_data_next;
94#define REG_RD_ADDR_dma_rw_data_next 4
95#define REG_WR_ADDR_dma_rw_data_next 4
96
97/* Register rw_data_buf, scope dma, type rw */
98typedef unsigned int reg_dma_rw_data_buf;
99#define REG_RD_ADDR_dma_rw_data_buf 8
100#define REG_WR_ADDR_dma_rw_data_buf 8
101
102/* Register rw_data_ctrl, scope dma, type rw */
103typedef struct {
104 unsigned int eol : 1;
105 unsigned int dummy1 : 2;
106 unsigned int out_eop : 1;
107 unsigned int intr : 1;
108 unsigned int wait : 1;
109 unsigned int dummy2 : 26;
110} reg_dma_rw_data_ctrl;
111#define REG_RD_ADDR_dma_rw_data_ctrl 12
112#define REG_WR_ADDR_dma_rw_data_ctrl 12
113
114/* Register rw_data_stat, scope dma, type rw */
115typedef struct {
116 unsigned int dummy1 : 3;
117 unsigned int in_eop : 1;
118 unsigned int dummy2 : 28;
119} reg_dma_rw_data_stat;
120#define REG_RD_ADDR_dma_rw_data_stat 16
121#define REG_WR_ADDR_dma_rw_data_stat 16
122
123/* Register rw_data_md, scope dma, type rw */
124typedef struct {
125 unsigned int md : 16;
126 unsigned int dummy1 : 16;
127} reg_dma_rw_data_md;
128#define REG_RD_ADDR_dma_rw_data_md 20
129#define REG_WR_ADDR_dma_rw_data_md 20
130
131/* Register rw_data_md_s, scope dma, type rw */
132typedef struct {
133 unsigned int md_s : 16;
134 unsigned int dummy1 : 16;
135} reg_dma_rw_data_md_s;
136#define REG_RD_ADDR_dma_rw_data_md_s 24
137#define REG_WR_ADDR_dma_rw_data_md_s 24
138
139/* Register rw_data_after, scope dma, type rw */
140typedef unsigned int reg_dma_rw_data_after;
141#define REG_RD_ADDR_dma_rw_data_after 28
142#define REG_WR_ADDR_dma_rw_data_after 28
143
144/* Register rw_ctxt, scope dma, type rw */
145typedef unsigned int reg_dma_rw_ctxt;
146#define REG_RD_ADDR_dma_rw_ctxt 32
147#define REG_WR_ADDR_dma_rw_ctxt 32
148
149/* Register rw_ctxt_next, scope dma, type rw */
150typedef unsigned int reg_dma_rw_ctxt_next;
151#define REG_RD_ADDR_dma_rw_ctxt_next 36
152#define REG_WR_ADDR_dma_rw_ctxt_next 36
153
154/* Register rw_ctxt_ctrl, scope dma, type rw */
155typedef struct {
156 unsigned int eol : 1;
157 unsigned int dummy1 : 3;
158 unsigned int intr : 1;
159 unsigned int dummy2 : 1;
160 unsigned int store_mode : 1;
161 unsigned int en : 1;
162 unsigned int dummy3 : 24;
163} reg_dma_rw_ctxt_ctrl;
164#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
165#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
166
167/* Register rw_ctxt_stat, scope dma, type rw */
168typedef struct {
169 unsigned int dummy1 : 7;
170 unsigned int dis : 1;
171 unsigned int dummy2 : 24;
172} reg_dma_rw_ctxt_stat;
173#define REG_RD_ADDR_dma_rw_ctxt_stat 44
174#define REG_WR_ADDR_dma_rw_ctxt_stat 44
175
176/* Register rw_ctxt_md0, scope dma, type rw */
177typedef struct {
178 unsigned int md0 : 16;
179 unsigned int dummy1 : 16;
180} reg_dma_rw_ctxt_md0;
181#define REG_RD_ADDR_dma_rw_ctxt_md0 48
182#define REG_WR_ADDR_dma_rw_ctxt_md0 48
183
184/* Register rw_ctxt_md0_s, scope dma, type rw */
185typedef struct {
186 unsigned int md0_s : 16;
187 unsigned int dummy1 : 16;
188} reg_dma_rw_ctxt_md0_s;
189#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
190#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
191
192/* Register rw_ctxt_md1, scope dma, type rw */
193typedef unsigned int reg_dma_rw_ctxt_md1;
194#define REG_RD_ADDR_dma_rw_ctxt_md1 56
195#define REG_WR_ADDR_dma_rw_ctxt_md1 56
196
197/* Register rw_ctxt_md1_s, scope dma, type rw */
198typedef unsigned int reg_dma_rw_ctxt_md1_s;
199#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
200#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
201
202/* Register rw_ctxt_md2, scope dma, type rw */
203typedef unsigned int reg_dma_rw_ctxt_md2;
204#define REG_RD_ADDR_dma_rw_ctxt_md2 64
205#define REG_WR_ADDR_dma_rw_ctxt_md2 64
206
207/* Register rw_ctxt_md2_s, scope dma, type rw */
208typedef unsigned int reg_dma_rw_ctxt_md2_s;
209#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
210#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
211
212/* Register rw_ctxt_md3, scope dma, type rw */
213typedef unsigned int reg_dma_rw_ctxt_md3;
214#define REG_RD_ADDR_dma_rw_ctxt_md3 72
215#define REG_WR_ADDR_dma_rw_ctxt_md3 72
216
217/* Register rw_ctxt_md3_s, scope dma, type rw */
218typedef unsigned int reg_dma_rw_ctxt_md3_s;
219#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
220#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
221
222/* Register rw_ctxt_md4, scope dma, type rw */
223typedef unsigned int reg_dma_rw_ctxt_md4;
224#define REG_RD_ADDR_dma_rw_ctxt_md4 80
225#define REG_WR_ADDR_dma_rw_ctxt_md4 80
226
227/* Register rw_ctxt_md4_s, scope dma, type rw */
228typedef unsigned int reg_dma_rw_ctxt_md4_s;
229#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
230#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
231
232/* Register rw_saved_data, scope dma, type rw */
233typedef unsigned int reg_dma_rw_saved_data;
234#define REG_RD_ADDR_dma_rw_saved_data 88
235#define REG_WR_ADDR_dma_rw_saved_data 88
236
237/* Register rw_saved_data_buf, scope dma, type rw */
238typedef unsigned int reg_dma_rw_saved_data_buf;
239#define REG_RD_ADDR_dma_rw_saved_data_buf 92
240#define REG_WR_ADDR_dma_rw_saved_data_buf 92
241
242/* Register rw_group, scope dma, type rw */
243typedef unsigned int reg_dma_rw_group;
244#define REG_RD_ADDR_dma_rw_group 96
245#define REG_WR_ADDR_dma_rw_group 96
246
247/* Register rw_group_next, scope dma, type rw */
248typedef unsigned int reg_dma_rw_group_next;
249#define REG_RD_ADDR_dma_rw_group_next 100
250#define REG_WR_ADDR_dma_rw_group_next 100
251
252/* Register rw_group_ctrl, scope dma, type rw */
253typedef struct {
254 unsigned int eol : 1;
255 unsigned int tol : 1;
256 unsigned int bol : 1;
257 unsigned int dummy1 : 1;
258 unsigned int intr : 1;
259 unsigned int dummy2 : 2;
260 unsigned int en : 1;
261 unsigned int dummy3 : 24;
262} reg_dma_rw_group_ctrl;
263#define REG_RD_ADDR_dma_rw_group_ctrl 104
264#define REG_WR_ADDR_dma_rw_group_ctrl 104
265
266/* Register rw_group_stat, scope dma, type rw */
267typedef struct {
268 unsigned int dummy1 : 7;
269 unsigned int dis : 1;
270 unsigned int dummy2 : 24;
271} reg_dma_rw_group_stat;
272#define REG_RD_ADDR_dma_rw_group_stat 108
273#define REG_WR_ADDR_dma_rw_group_stat 108
274
275/* Register rw_group_md, scope dma, type rw */
276typedef struct {
277 unsigned int md : 16;
278 unsigned int dummy1 : 16;
279} reg_dma_rw_group_md;
280#define REG_RD_ADDR_dma_rw_group_md 112
281#define REG_WR_ADDR_dma_rw_group_md 112
282
283/* Register rw_group_md_s, scope dma, type rw */
284typedef struct {
285 unsigned int md_s : 16;
286 unsigned int dummy1 : 16;
287} reg_dma_rw_group_md_s;
288#define REG_RD_ADDR_dma_rw_group_md_s 116
289#define REG_WR_ADDR_dma_rw_group_md_s 116
290
291/* Register rw_group_up, scope dma, type rw */
292typedef unsigned int reg_dma_rw_group_up;
293#define REG_RD_ADDR_dma_rw_group_up 120
294#define REG_WR_ADDR_dma_rw_group_up 120
295
296/* Register rw_group_down, scope dma, type rw */
297typedef unsigned int reg_dma_rw_group_down;
298#define REG_RD_ADDR_dma_rw_group_down 124
299#define REG_WR_ADDR_dma_rw_group_down 124
300
301/* Register rw_cmd, scope dma, type rw */
302typedef struct {
303 unsigned int cont_data : 1;
304 unsigned int dummy1 : 31;
305} reg_dma_rw_cmd;
306#define REG_RD_ADDR_dma_rw_cmd 128
307#define REG_WR_ADDR_dma_rw_cmd 128
308
309/* Register rw_cfg, scope dma, type rw */
310typedef struct {
311 unsigned int en : 1;
312 unsigned int stop : 1;
313 unsigned int dummy1 : 30;
314} reg_dma_rw_cfg;
315#define REG_RD_ADDR_dma_rw_cfg 132
316#define REG_WR_ADDR_dma_rw_cfg 132
317
318/* Register rw_stat, scope dma, type rw */
319typedef struct {
320 unsigned int mode : 5;
321 unsigned int list_state : 3;
322 unsigned int stream_cmd_src : 8;
323 unsigned int dummy1 : 8;
324 unsigned int buf : 8;
325} reg_dma_rw_stat;
326#define REG_RD_ADDR_dma_rw_stat 136
327#define REG_WR_ADDR_dma_rw_stat 136
328
329/* Register rw_intr_mask, scope dma, type rw */
330typedef struct {
331 unsigned int group : 1;
332 unsigned int ctxt : 1;
333 unsigned int data : 1;
334 unsigned int in_eop : 1;
335 unsigned int stream_cmd : 1;
336 unsigned int dummy1 : 27;
337} reg_dma_rw_intr_mask;
338#define REG_RD_ADDR_dma_rw_intr_mask 140
339#define REG_WR_ADDR_dma_rw_intr_mask 140
340
341/* Register rw_ack_intr, scope dma, type rw */
342typedef struct {
343 unsigned int group : 1;
344 unsigned int ctxt : 1;
345 unsigned int data : 1;
346 unsigned int in_eop : 1;
347 unsigned int stream_cmd : 1;
348 unsigned int dummy1 : 27;
349} reg_dma_rw_ack_intr;
350#define REG_RD_ADDR_dma_rw_ack_intr 144
351#define REG_WR_ADDR_dma_rw_ack_intr 144
352
353/* Register r_intr, scope dma, type r */
354typedef struct {
355 unsigned int group : 1;
356 unsigned int ctxt : 1;
357 unsigned int data : 1;
358 unsigned int in_eop : 1;
359 unsigned int stream_cmd : 1;
360 unsigned int dummy1 : 27;
361} reg_dma_r_intr;
362#define REG_RD_ADDR_dma_r_intr 148
363
364/* Register r_masked_intr, scope dma, type r */
365typedef struct {
366 unsigned int group : 1;
367 unsigned int ctxt : 1;
368 unsigned int data : 1;
369 unsigned int in_eop : 1;
370 unsigned int stream_cmd : 1;
371 unsigned int dummy1 : 27;
372} reg_dma_r_masked_intr;
373#define REG_RD_ADDR_dma_r_masked_intr 152
374
375/* Register rw_stream_cmd, scope dma, type rw */
376typedef struct {
377 unsigned int cmd : 10;
378 unsigned int dummy1 : 6;
379 unsigned int n : 8;
380 unsigned int dummy2 : 7;
381 unsigned int busy : 1;
382} reg_dma_rw_stream_cmd;
383#define REG_RD_ADDR_dma_rw_stream_cmd 156
384#define REG_WR_ADDR_dma_rw_stream_cmd 156
385
386
387/* Constants */
388enum {
389 regk_dma_ack_pkt = 0x00000100,
390 regk_dma_anytime = 0x00000001,
391 regk_dma_array = 0x00000008,
392 regk_dma_burst = 0x00000020,
393 regk_dma_client = 0x00000002,
394 regk_dma_copy_next = 0x00000010,
395 regk_dma_copy_up = 0x00000020,
396 regk_dma_data_at_eol = 0x00000001,
397 regk_dma_dis_c = 0x00000010,
398 regk_dma_dis_g = 0x00000020,
399 regk_dma_idle = 0x00000001,
400 regk_dma_intern = 0x00000004,
401 regk_dma_load_c = 0x00000200,
402 regk_dma_load_c_n = 0x00000280,
403 regk_dma_load_c_next = 0x00000240,
404 regk_dma_load_d = 0x00000140,
405 regk_dma_load_g = 0x00000300,
406 regk_dma_load_g_down = 0x000003c0,
407 regk_dma_load_g_next = 0x00000340,
408 regk_dma_load_g_up = 0x00000380,
409 regk_dma_next_en = 0x00000010,
410 regk_dma_next_pkt = 0x00000010,
411 regk_dma_no = 0x00000000,
412 regk_dma_only_at_wait = 0x00000000,
413 regk_dma_restore = 0x00000020,
414 regk_dma_rst = 0x00000001,
415 regk_dma_running = 0x00000004,
416 regk_dma_rw_cfg_default = 0x00000000,
417 regk_dma_rw_cmd_default = 0x00000000,
418 regk_dma_rw_intr_mask_default = 0x00000000,
419 regk_dma_rw_stat_default = 0x00000101,
420 regk_dma_rw_stream_cmd_default = 0x00000000,
421 regk_dma_save_down = 0x00000020,
422 regk_dma_save_up = 0x00000020,
423 regk_dma_set_reg = 0x00000050,
424 regk_dma_set_w_size1 = 0x00000190,
425 regk_dma_set_w_size2 = 0x000001a0,
426 regk_dma_set_w_size4 = 0x000001c0,
427 regk_dma_stopped = 0x00000002,
428 regk_dma_store_c = 0x00000002,
429 regk_dma_store_descr = 0x00000000,
430 regk_dma_store_g = 0x00000004,
431 regk_dma_store_md = 0x00000001,
432 regk_dma_sw = 0x00000008,
433 regk_dma_update_down = 0x00000020,
434 regk_dma_yes = 0x00000001
435};
436#endif /* __dma_defs_h */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 22:19:57 -0400