aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf548
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h54
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h33
-rw-r--r--include/asm-blackfin/mach-bf548/defBF542.h4
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h4
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h31
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h62
-rw-r--r--include/asm-blackfin/mach-bf548/portmux.h2
9 files changed, 132 insertions, 64 deletions
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index c5b63759cde..850dc12eb7f 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List 10 * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -26,47 +26,59 @@
26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
27#define ANOMALY_05000272 (1) 27#define ANOMALY_05000272 (1)
28/* False Hardware Error Exception when ISR context is not restored */ 28/* False Hardware Error Exception when ISR context is not restored */
29#define ANOMALY_05000281 (1) 29#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
31#define ANOMALY_05000304 (1) 31#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
33#define ANOMALY_05000310 (1) 33#define ANOMALY_05000310 (1)
34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
35#define ANOMALY_05000312 (1) 35#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
36/* TWI Slave Boot Mode Is Not Functional */ 36/* TWI Slave Boot Mode Is Not Functional */
37#define ANOMALY_05000324 (1) 37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
38/* External FIFO Boot Mode Is Not Functional */ 38/* External FIFO Boot Mode Is Not Functional */
39#define ANOMALY_05000325 (1) 39#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ 40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
41#define ANOMALY_05000327 (1) 41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
42/* Incorrect Access of OTP_STATUS During otp_write() Function */ 42/* Incorrect Access of OTP_STATUS During otp_write() Function */
43#define ANOMALY_05000328 (1) 43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
44/* Synchronous Burst Flash Boot Mode Is Not Functional */ 44/* Synchronous Burst Flash Boot Mode Is Not Functional */
45#define ANOMALY_05000329 (1) 45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
46/* Host DMA Boot Mode Is Not Functional */ 46/* Host DMA Boot Mode Is Not Functional */
47#define ANOMALY_05000330 (1) 47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ 48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
49#define ANOMALY_05000334 (1) 49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
50/* Inadequate Rotary Debounce Logic Duration */ 50/* Inadequate Rotary Debounce Logic Duration */
51#define ANOMALY_05000335 (1) 51#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ 52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
53#define ANOMALY_05000336 (1) 53#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
55#define ANOMALY_05000337 (1) 55#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ 56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
57#define ANOMALY_05000338 (1) 57#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ 58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
59#define ANOMALY_05000340 (1) 59#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ 60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
61#define ANOMALY_05000344 (1) 61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
62/* USB Calibration Value Is Not Intialized */ 62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (1) 63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ 64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (1) 65#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
66/* Data Lost when Core Reads SDH Data FIFO */ 66/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (1) 67#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
68/* PLL Status Register Is Inaccurate */ 68/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (1) 69#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
70/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
71#define ANOMALY_05000357 (1)
72/* External Memory Read Access Hangs Core With PLL Bypass */
73#define ANOMALY_05000360 (1)
74/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
75#define ANOMALY_05000365 (1)
76/* Addressing Conflict between Boot ROM and Asynchronous Memory */
77#define ANOMALY_05000369 (1)
78/* Mobile DDR Operation Not Functional */
79#define ANOMALY_05000377 (1)
80/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
81#define ANOMALY_05000378 (1)
70 82
71/* Anomalies that don't exist on this proc */ 83/* Anomalies that don't exist on this proc */
72#define ANOMALY_05000125 (0) 84#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index f21a1620e6b..3770aa38ee9 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -186,7 +186,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
186 186
187 if (uart->rts_pin >= 0) { 187 if (uart->rts_pin >= 0) {
188 gpio_request(uart->rts_pin, DRIVER_NAME); 188 gpio_request(uart->rts_pin, DRIVER_NAME);
189 gpio_direction_output(uart->rts_pin); 189 gpio_direction_output(uart->rts_pin, 0);
190 } 190 }
191#endif 191#endif
192} 192}
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index aefab3f618c..19ddcd83c71 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) 244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) 245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
246 246
247#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
248#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
249#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
250#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
251#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
252#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
253#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
254#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
255#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
256#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
257#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
258#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
259#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
260#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
261#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
262#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
263#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
264#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
265#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
266#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
267#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
268#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
269#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
270#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
271#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
272#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
273#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
274#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
275#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
276#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
277#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
278#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
279
280/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ 247/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
281 248
282/* SPORT1 Registers */ 249/* SPORT1 Registers */
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index 32d07130200..a7c809f29ed 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -432,8 +432,8 @@
432 432
433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
435#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 435#define CMD_TIME_OUT 0x4 /* CMD Time Out */
436#define DAT_TIMEOUT 0x8 /* Data Time Out */ 436#define DAT_TIME_OUT 0x8 /* Data Time Out */
437#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 437#define TX_UNDERRUN 0x10 /* Transmit Underrun */
438#define RX_OVERRUN 0x20 /* Receive Overrun */ 438#define RX_OVERRUN 0x20 /* Receive Overrun */
439#define CMD_RESP_END 0x40 /* CMD Response End */ 439#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index ecbca952985..e46f56891e6 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1095,8 +1095,8 @@
1095 1095
1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1098#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 1098#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1099#define DAT_TIMEOUT 0x8 /* Data Time Out */ 1099#define DAT_TIME_OUT 0x8 /* Data Time Out */
1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1101#define RX_OVERRUN 0x20 /* Receive Overrun */ 1101#define RX_OVERRUN 0x20 /* Receive Overrun */
1102#define CMD_RESP_END 0x40 /* CMD Response End */ 1102#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 319a48590c9..08f90c21fe8 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1772,17 +1772,36 @@
1772#define TRP 0x3c0000 /* Pre charge-to-active command period */ 1772#define TRP 0x3c0000 /* Pre charge-to-active command period */
1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */ 1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1774#define TRC 0x3c000000 /* Active-to-active time */ 1774#define TRC 0x3c000000 /* Active-to-active time */
1775#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
1776#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
1777#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
1778#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
1779#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
1775 1780
1776/* Bit masks for EBIU_DDRCTL1 */ 1781/* Bit masks for EBIU_DDRCTL1 */
1777 1782
1778#define TRCD 0xf /* Active-to-Read/write delay */ 1783#define TRCD 0xf /* Active-to-Read/write delay */
1779#define MRD 0xf0 /* Mode register set to active */ 1784#define TMRD 0xf0 /* Mode register set to active */
1780#define TWR 0x300 /* Write Recovery time */ 1785#define TWR 0x300 /* Write Recovery time */
1781#define DDRDATWIDTH 0x3000 /* DDR data width */ 1786#define DDRDATWIDTH 0x3000 /* DDR data width */
1782#define EXTBANKS 0xc000 /* External banks */ 1787#define EXTBANKS 0xc000 /* External banks */
1783#define DDRDEVWIDTH 0x30000 /* DDR device width */ 1788#define DDRDEVWIDTH 0x30000 /* DDR device width */
1784#define DDRDEVSIZE 0xc0000 /* DDR device size */ 1789#define DDRDEVSIZE 0xc0000 /* DDR device size */
1785#define TWWTR 0xf0000000 /* Write-to-read delay */ 1790#define TWTR 0xf0000000 /* Write-to-read delay */
1791#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
1792#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
1793#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
1794#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
1795#define DDR_DATWIDTH 0x2000 /* DDR data width */
1796#define EXTBANK_1 0 /* 1 external bank */
1797#define EXTBANK_2 0x4000 /* 2 external banks */
1798#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
1799#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
1800#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
1801#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
1802#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
1803#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
1804#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
1786 1805
1787/* Bit masks for EBIU_DDRCTL2 */ 1806/* Bit masks for EBIU_DDRCTL2 */
1788 1807
@@ -1790,6 +1809,10 @@
1790#define CASLATENCY 0x70 /* CAS latency */ 1809#define CASLATENCY 0x70 /* CAS latency */
1791#define DLLRESET 0x100 /* DLL Reset */ 1810#define DLLRESET 0x100 /* DLL Reset */
1792#define REGE 0x1000 /* Register mode enable */ 1811#define REGE 0x1000 /* Register mode enable */
1812#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
1813#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
1814#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
1815#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
1793 1816
1794/* Bit masks for EBIU_DDRCTL3 */ 1817/* Bit masks for EBIU_DDRCTL3 */
1795 1818
@@ -2257,6 +2280,10 @@
2257 2280
2258#define CSEL 0x30 /* Core Select */ 2281#define CSEL 0x30 /* Core Select */
2259#define SSEL 0xf /* System Select */ 2282#define SSEL 0xf /* System Select */
2283#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2284#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2285#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2286#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2260 2287
2261/* Bit masks for PLL_CTL */ 2288/* Bit masks for PLL_CTL */
2262 2289
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 9fb7bc5399a..c34507a3f1d 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -88,7 +88,7 @@ Events (highest priority) EMU 0
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ 88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ 89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ 90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ 91#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ 92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ 93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ 94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
@@ -406,7 +406,7 @@ Events (highest priority) EMU 0
406#define IRQ_PINT1_POS 16 406#define IRQ_PINT1_POS 16
407#define IRQ_MDMAS0_POS 20 407#define IRQ_MDMAS0_POS 20
408#define IRQ_MDMAS1_POS 24 408#define IRQ_MDMAS1_POS 24
409#define IRQ_WATCHDOG_POS 28 409#define IRQ_WATCH_POS 28
410 410
411/* IAR3 BIT FIELDS */ 411/* IAR3 BIT FIELDS */
412#define IRQ_DMAC1_ERR_POS 0 412#define IRQ_DMAC1_ERR_POS 0
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index 0cb279e973d..befc2903d5a 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -28,8 +28,68 @@
28 * If not, write to the Free Software Foundation, 28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */ 30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32
33#if (CONFIG_MEM_MT46V32M16_6T)
34#define DDR_SIZE DEVSZ_512
35#define DDR_WIDTH DEVWD_16
36
37#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
38#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
39#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
40#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
41#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
42
43#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
44#define DDR_tWTR DDR_TWTR(1)
45#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
46#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
47#endif
48
49#if (CONFIG_MEM_MT46V32M16_5B)
50#define DDR_SIZE DEVSZ_512
51#define DDR_WIDTH DEVWD_16
52
53#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
54#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
55#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
56#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
57#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
58
59#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
60#define DDR_tWTR DDR_TWTR(2)
61#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
62#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
63#endif
64
65#if (CONFIG_MEM_GENERIC_BOARD)
66#define DDR_SIZE DEVSZ_512
67#define DDR_WIDTH DEVWD_16
68
69#define DDR_tRCD DDR_TRCD(3)
70#define DDR_tWTR DDR_TWTR(2)
71#define DDR_tWR DDR_TWR(2)
72#define DDR_tMRD DDR_TMRD(2)
73#define DDR_tRP DDR_TRP(3)
74#define DDR_tRAS DDR_TRAS(7)
75#define DDR_tRC DDR_TRC(10)
76#define DDR_tRFC DDR_TRFC(12)
77#define DDR_tREFI DDR_TREFI(1288)
78#endif
79
80#if (CONFIG_SCLK_HZ <= 133333333)
81#define DDR_CL CL_2
82#elif (CONFIG_SCLK_HZ <= 166666666)
83#define DDR_CL CL_2_5
84#else
85#define DDR_CL CL_3
86#endif
87
88#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
89#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
90 | DDR_tMRD | DDR_tWR | DDR_tRCD)
91#define mem_DDRCTL2 DDR_CL
31 92
32#if (CONFIG_MEM_MT46V32M16)
33 93
34#if defined CONFIG_CLKIN_HALF 94#if defined CONFIG_CLKIN_HALF
35#define CLKIN_HALF 1 95#define CLKIN_HALF 1
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
index 6b485120015..8177a567dcd 100644
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) 6#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
5#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) 7#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
6#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) 8#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 18:01:34 -0400