diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF544.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/defBF544.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index 8fc77ea12aa..dd955dcd39b 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h | |||
| @@ -538,21 +538,13 @@ | |||
| 538 | /* Bit masks for PIXC_CTL */ | 538 | /* Bit masks for PIXC_CTL */ |
| 539 | 539 | ||
| 540 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ | 540 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ |
| 541 | #define nPIXC_EN 0x0 | ||
| 542 | #define OVR_A_EN 0x2 /* Overlay A Enable */ | 541 | #define OVR_A_EN 0x2 /* Overlay A Enable */ |
| 543 | #define nOVR_A_EN 0x0 | ||
| 544 | #define OVR_B_EN 0x4 /* Overlay B Enable */ | 542 | #define OVR_B_EN 0x4 /* Overlay B Enable */ |
| 545 | #define nOVR_B_EN 0x0 | ||
| 546 | #define IMG_FORM 0x8 /* Image Data Format */ | 543 | #define IMG_FORM 0x8 /* Image Data Format */ |
| 547 | #define nIMG_FORM 0x0 | ||
| 548 | #define OVR_FORM 0x10 /* Overlay Data Format */ | 544 | #define OVR_FORM 0x10 /* Overlay Data Format */ |
| 549 | #define nOVR_FORM 0x0 | ||
| 550 | #define OUT_FORM 0x20 /* Output Data Format */ | 545 | #define OUT_FORM 0x20 /* Output Data Format */ |
| 551 | #define nOUT_FORM 0x0 | ||
| 552 | #define UDS_MOD 0x40 /* Resampling Mode */ | 546 | #define UDS_MOD 0x40 /* Resampling Mode */ |
| 553 | #define nUDS_MOD 0x0 | ||
| 554 | #define TC_EN 0x80 /* Transparent Color Enable */ | 547 | #define TC_EN 0x80 /* Transparent Color Enable */ |
| 555 | #define nTC_EN 0x0 | ||
| 556 | #define IMG_STAT 0x300 /* Image FIFO Status */ | 548 | #define IMG_STAT 0x300 /* Image FIFO Status */ |
| 557 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ | 549 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ |
| 558 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ | 550 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ |
| @@ -600,13 +592,9 @@ | |||
| 600 | /* Bit masks for PIXC_INTRSTAT */ | 592 | /* Bit masks for PIXC_INTRSTAT */ |
| 601 | 593 | ||
| 602 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ | 594 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ |
| 603 | #define nOVR_INT_EN 0x0 | ||
| 604 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ | 595 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ |
| 605 | #define nFRM_INT_EN 0x0 | ||
| 606 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ | 596 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ |
| 607 | #define nOVR_INT_STAT 0x0 | ||
| 608 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ | 597 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ |
| 609 | #define nFRM_INT_STAT 0x0 | ||
| 610 | 598 | ||
| 611 | /* Bit masks for PIXC_RYCON */ | 599 | /* Bit masks for PIXC_RYCON */ |
| 612 | 600 | ||
| @@ -614,7 +602,6 @@ | |||
| 614 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ | 602 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ |
| 615 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ | 603 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ |
| 616 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ | 604 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 617 | #define nRY_MULT4 0x0 | ||
| 618 | 605 | ||
| 619 | /* Bit masks for PIXC_GUCON */ | 606 | /* Bit masks for PIXC_GUCON */ |
| 620 | 607 | ||
| @@ -622,7 +609,6 @@ | |||
| 622 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ | 609 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ |
| 623 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ | 610 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ |
| 624 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ | 611 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 625 | #define nGU_MULT4 0x0 | ||
| 626 | 612 | ||
| 627 | /* Bit masks for PIXC_BVCON */ | 613 | /* Bit masks for PIXC_BVCON */ |
| 628 | 614 | ||
| @@ -630,7 +616,6 @@ | |||
| 630 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ | 616 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ |
| 631 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ | 617 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ |
| 632 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ | 618 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ |
| 633 | #define nBV_MULT4 0x0 | ||
| 634 | 619 | ||
| 635 | /* Bit masks for PIXC_CCBIAS */ | 620 | /* Bit masks for PIXC_CCBIAS */ |
| 636 | 621 | ||
| @@ -647,48 +632,28 @@ | |||
| 647 | /* Bit masks for HOST_CONTROL */ | 632 | /* Bit masks for HOST_CONTROL */ |
| 648 | 633 | ||
| 649 | #define HOST_EN 0x1 /* Host Enable */ | 634 | #define HOST_EN 0x1 /* Host Enable */ |
| 650 | #define nHOST_EN 0x0 | ||
| 651 | #define HOST_END 0x2 /* Host Endianess */ | 635 | #define HOST_END 0x2 /* Host Endianess */ |
| 652 | #define nHOST_END 0x0 | ||
| 653 | #define DATA_SIZE 0x4 /* Data Size */ | 636 | #define DATA_SIZE 0x4 /* Data Size */ |
| 654 | #define nDATA_SIZE 0x0 | ||
| 655 | #define HOST_RST 0x8 /* Host Reset */ | 637 | #define HOST_RST 0x8 /* Host Reset */ |
| 656 | #define nHOST_RST 0x0 | ||
| 657 | #define HRDY_OVR 0x20 /* Host Ready Override */ | 638 | #define HRDY_OVR 0x20 /* Host Ready Override */ |
| 658 | #define nHRDY_OVR 0x0 | ||
| 659 | #define INT_MODE 0x40 /* Interrupt Mode */ | 639 | #define INT_MODE 0x40 /* Interrupt Mode */ |
| 660 | #define nINT_MODE 0x0 | ||
| 661 | #define BT_EN 0x80 /* Bus Timeout Enable */ | 640 | #define BT_EN 0x80 /* Bus Timeout Enable */ |
| 662 | #define nBT_EN 0x0 | ||
| 663 | #define EHW 0x100 /* Enable Host Write */ | 641 | #define EHW 0x100 /* Enable Host Write */ |
| 664 | #define nEHW 0x0 | ||
| 665 | #define EHR 0x200 /* Enable Host Read */ | 642 | #define EHR 0x200 /* Enable Host Read */ |
| 666 | #define nEHR 0x0 | ||
| 667 | #define BDR 0x400 /* Burst DMA Requests */ | 643 | #define BDR 0x400 /* Burst DMA Requests */ |
| 668 | #define nBDR 0x0 | ||
| 669 | 644 | ||
| 670 | /* Bit masks for HOST_STATUS */ | 645 | /* Bit masks for HOST_STATUS */ |
| 671 | 646 | ||
| 672 | #define READY 0x1 /* DMA Ready */ | 647 | #define READY 0x1 /* DMA Ready */ |
| 673 | #define nREADY 0x0 | ||
| 674 | #define FIFOFULL 0x2 /* FIFO Full */ | 648 | #define FIFOFULL 0x2 /* FIFO Full */ |
| 675 | #define nFIFOFULL 0x0 | ||
| 676 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | 649 | #define FIFOEMPTY 0x4 /* FIFO Empty */ |
| 677 | #define nFIFOEMPTY 0x0 | ||
| 678 | #define COMPLETE 0x8 /* DMA Complete */ | 650 | #define COMPLETE 0x8 /* DMA Complete */ |
| 679 | #define nCOMPLETE 0x0 | ||
| 680 | #define HSHK 0x10 /* Host Handshake */ | 651 | #define HSHK 0x10 /* Host Handshake */ |
| 681 | #define nHSHK 0x0 | ||
| 682 | #define TIMEOUT 0x20 /* Host Timeout */ | 652 | #define TIMEOUT 0x20 /* Host Timeout */ |
| 683 | #define nTIMEOUT 0x0 | ||
| 684 | #define HIRQ 0x40 /* Host Interrupt Request */ | 653 | #define HIRQ 0x40 /* Host Interrupt Request */ |
| 685 | #define nHIRQ 0x0 | ||
| 686 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | 654 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ |
| 687 | #define nALLOW_CNFG 0x0 | ||
| 688 | #define DMA_DIR 0x100 /* DMA Direction */ | 655 | #define DMA_DIR 0x100 /* DMA Direction */ |
| 689 | #define nDMA_DIR 0x0 | ||
| 690 | #define BTE 0x200 /* Bus Timeout Enabled */ | 656 | #define BTE 0x200 /* Bus Timeout Enabled */ |
| 691 | #define nBTE 0x0 | ||
| 692 | 657 | ||
| 693 | /* Bit masks for HOST_TIMEOUT */ | 658 | /* Bit masks for HOST_TIMEOUT */ |
| 694 | 659 | ||
| @@ -697,67 +662,42 @@ | |||
| 697 | /* Bit masks for TIMER_ENABLE1 */ | 662 | /* Bit masks for TIMER_ENABLE1 */ |
| 698 | 663 | ||
| 699 | #define TIMEN8 0x1 /* Timer 8 Enable */ | 664 | #define TIMEN8 0x1 /* Timer 8 Enable */ |
| 700 | #define nTIMEN8 0x0 | ||
| 701 | #define TIMEN9 0x2 /* Timer 9 Enable */ | 665 | #define TIMEN9 0x2 /* Timer 9 Enable */ |
| 702 | #define nTIMEN9 0x0 | ||
| 703 | #define TIMEN10 0x4 /* Timer 10 Enable */ | 666 | #define TIMEN10 0x4 /* Timer 10 Enable */ |
| 704 | #define nTIMEN10 0x0 | ||
| 705 | 667 | ||
| 706 | /* Bit masks for TIMER_DISABLE1 */ | 668 | /* Bit masks for TIMER_DISABLE1 */ |
| 707 | 669 | ||
| 708 | #define TIMDIS8 0x1 /* Timer 8 Disable */ | 670 | #define TIMDIS8 0x1 /* Timer 8 Disable */ |
| 709 | #define nTIMDIS8 0x0 | ||
| 710 | #define TIMDIS9 0x2 /* Timer 9 Disable */ | 671 | #define TIMDIS9 0x2 /* Timer 9 Disable */ |
| 711 | #define nTIMDIS9 0x0 | ||
| 712 | #define TIMDIS10 0x4 /* Timer 10 Disable */ | 672 | #define TIMDIS10 0x4 /* Timer 10 Disable */ |
| 713 | #define nTIMDIS10 0x0 | ||
| 714 | 673 | ||
| 715 | /* Bit masks for TIMER_STATUS1 */ | 674 | /* Bit masks for TIMER_STATUS1 */ |
| 716 | 675 | ||
| 717 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ | 676 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ |
| 718 | #define nTIMIL8 0x0 | ||
| 719 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ | 677 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ |
| 720 | #define nTIMIL9 0x0 | ||
| 721 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ | 678 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ |
| 722 | #define nTIMIL10 0x0 | ||
| 723 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ | 679 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ |
| 724 | #define nTOVF_ERR8 0x0 | ||
| 725 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ | 680 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ |
| 726 | #define nTOVF_ERR9 0x0 | ||
| 727 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ | 681 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ |
| 728 | #define nTOVF_ERR10 0x0 | ||
| 729 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ | 682 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ |
| 730 | #define nTRUN8 0x0 | ||
| 731 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ | 683 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ |
| 732 | #define nTRUN9 0x0 | ||
| 733 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ | 684 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ |
| 734 | #define nTRUN10 0x0 | ||
| 735 | 685 | ||
| 736 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ | 686 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ |
| 737 | 687 | ||
| 738 | /* Bit masks for HMDMAx_CONTROL */ | 688 | /* Bit masks for HMDMAx_CONTROL */ |
| 739 | 689 | ||
| 740 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ | 690 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ |
| 741 | #define nHMDMAEN 0x0 | ||
| 742 | #define REP 0x2 /* Handshake MDMA Request Polarity */ | 691 | #define REP 0x2 /* Handshake MDMA Request Polarity */ |
| 743 | #define nREP 0x0 | ||
| 744 | #define UTE 0x8 /* Urgency Threshold Enable */ | 692 | #define UTE 0x8 /* Urgency Threshold Enable */ |
| 745 | #define nUTE 0x0 | ||
| 746 | #define OIE 0x10 /* Overflow Interrupt Enable */ | 693 | #define OIE 0x10 /* Overflow Interrupt Enable */ |
| 747 | #define nOIE 0x0 | ||
| 748 | #define BDIE 0x20 /* Block Done Interrupt Enable */ | 694 | #define BDIE 0x20 /* Block Done Interrupt Enable */ |
| 749 | #define nBDIE 0x0 | ||
| 750 | #define MBDI 0x40 /* Mask Block Done Interrupt */ | 695 | #define MBDI 0x40 /* Mask Block Done Interrupt */ |
| 751 | #define nMBDI 0x0 | ||
| 752 | #define DRQ 0x300 /* Handshake MDMA Request Type */ | 696 | #define DRQ 0x300 /* Handshake MDMA Request Type */ |
| 753 | #define RBC 0x1000 /* Force Reload of BCOUNT */ | 697 | #define RBC 0x1000 /* Force Reload of BCOUNT */ |
| 754 | #define nRBC 0x0 | ||
| 755 | #define PS 0x2000 /* Pin Status */ | 698 | #define PS 0x2000 /* Pin Status */ |
| 756 | #define nPS 0x0 | ||
| 757 | #define OI 0x4000 /* Overflow Interrupt Generated */ | 699 | #define OI 0x4000 /* Overflow Interrupt Generated */ |
| 758 | #define nOI 0x0 | ||
| 759 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | 700 | #define BDI 0x8000 /* Block Done Interrupt Generated */ |
| 760 | #define nBDI 0x0 | ||
| 761 | 701 | ||
| 762 | /* ******************************************* */ | 702 | /* ******************************************* */ |
| 763 | /* MULTI BIT MACRO ENUMERATIONS */ | 703 | /* MULTI BIT MACRO ENUMERATIONS */ |