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1/* linux/include/asm-arm/arch-s3c2410/bast-map.h
2 *
3 * (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine BAST - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics from arch/map.h
14 * 12-Mar-2004 BJD Fixed header include protection
15*/
16
17/* needs arch/map.h including with this */
18
19/* ok, we've used up to 0x13000000, now we need to find space for the
20 * peripherals that live in the nGCS[x] areas, which are quite numerous
21 * in their space. We also have the board's CPLD to find register space
22 * for.
23 */
24
25#ifndef __ASM_ARCH_BASTMAP_H
26#define __ASM_ARCH_BASTMAP_H
27
28#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
29
30/* we put the CPLD registers next, to get them out of the way */
31
32#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */
33#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
34
35#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */
36#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
37
38#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */
39#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
40
41#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */
42#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
43
44/* next, we have the PC104 ISA interrupt registers */
45
46#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
47#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
48
49#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
50#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
51
52#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
53#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
54
55#define BAST_PA_LCD_RCMD1 (0x8800000)
56#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
57
58#define BAST_PA_LCD_WCMD1 (0x8000000)
59#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
60
61#define BAST_PA_LCD_RDATA1 (0x9800000)
62#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
63
64#define BAST_PA_LCD_WDATA1 (0x9000000)
65#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
66
67#define BAST_PA_LCD_RCMD2 (0xA800000)
68#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
69
70#define BAST_PA_LCD_WCMD2 (0xA000000)
71#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
72
73#define BAST_PA_LCD_RDATA2 (0xB800000)
74#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
75
76#define BAST_PA_LCD_WDATA2 (0xB000000)
77#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
78
79
80/* 0xE0000000 contains the IO space that is split by speed and
81 * wether the access is for 8 or 16bit IO... this ensures that
82 * the correct access is made
83 *
84 * 0x10000000 of space, partitioned as so:
85 *
86 * 0x00000000 to 0x04000000 8bit, slow
87 * 0x04000000 to 0x08000000 16bit, slow
88 * 0x08000000 to 0x0C000000 16bit, net
89 * 0x0C000000 to 0x10000000 16bit, fast
90 *
91 * each of these spaces has the following in:
92 *
93 * 0x00000000 to 0x01000000 16MB ISA IO space
94 * 0x01000000 to 0x02000000 16MB ISA memory space
95 * 0x02000000 to 0x02100000 1MB IDE primary channel
96 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
97 * 0x02200000 to 0x02400000 1MB IDE secondary channel
98 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
99 * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
100 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
101 * 0x02600000 to 0x02700000 1MB PC SuperIO controller
102 *
103 * the phyiscal layout of the zones are:
104 * nGCS2 - 8bit, slow
105 * nGCS3 - 16bit, slow
106 * nGCS4 - 16bit, net
107 * nGCS5 - 16bit, fast
108 */
109
110#define BAST_VA_MULTISPACE (0xE0000000)
111
112#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
113#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
114#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
115#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
116#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
117#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
118#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
119#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
120#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
121
122#define BAST_VA_MULTISPACE (0xE0000000)
123
124#define BAST_VAM_CS2 (0x00000000)
125#define BAST_VAM_CS3 (0x04000000)
126#define BAST_VAM_CS4 (0x08000000)
127#define BAST_VAM_CS5 (0x0C000000)
128
129/* physical offset addresses for the peripherals */
130
131#define BAST_PA_ISAIO (0x00000000)
132#define BAST_PA_ASIXNET (0x01000000)
133#define BAST_PA_SUPERIO (0x01800000)
134#define BAST_PA_IDEPRI (0x02000000)
135#define BAST_PA_IDEPRIAUX (0x02800000)
136#define BAST_PA_IDESEC (0x03000000)
137#define BAST_PA_IDESECAUX (0x03800000)
138#define BAST_PA_ISAMEM (0x04000000)
139#define BAST_PA_DM9000 (0x05000000)
140
141/* some configurations for the peripherals */
142
143#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
144/* */
145
146#define BAST_ASIXNET_CS BAST_VAM_CS5
147#define BAST_IDE_CS BAST_VAM_CS5
148#define BAST_DM9000_CS BAST_VAM_CS4
149
150#endif /* __ASM_ARCH_BASTMAP_H */