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-rw-r--r--drivers/gpu/drm/radeon/r100.c5
-rw-r--r--drivers/gpu/drm/radeon/r100d.h2
-rw-r--r--drivers/gpu/drm/radeon/r300.c44
-rw-r--r--drivers/gpu/drm/radeon/r300d.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c13
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r30013
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r42014
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rs60013
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv51513
11 files changed, 66 insertions, 57 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 4c48df46435..e817a0bb5eb 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1803,6 +1803,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1803 return r; 1803 return r;
1804 break; 1804 break;
1805 /* triggers drawing using indices to vertex buffer */ 1805 /* triggers drawing using indices to vertex buffer */
1806 case PACKET3_3D_CLEAR_HIZ:
1807 case PACKET3_3D_CLEAR_ZMASK:
1808 if (p->rdev->hyperz_filp != p->filp)
1809 return -EINVAL;
1810 break;
1806 case PACKET3_NOP: 1811 case PACKET3_NOP:
1807 break; 1812 break;
1808 default: 1813 default:
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index d016b16fa11..b121b6c678d 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -48,10 +48,12 @@
48#define PACKET3_3D_DRAW_IMMD 0x29 48#define PACKET3_3D_DRAW_IMMD 0x29
49#define PACKET3_3D_DRAW_INDX 0x2A 49#define PACKET3_3D_DRAW_INDX 0x2A
50#define PACKET3_3D_LOAD_VBPNTR 0x2F 50#define PACKET3_3D_LOAD_VBPNTR 0x2F
51#define PACKET3_3D_CLEAR_ZMASK 0x32
51#define PACKET3_INDX_BUFFER 0x33 52#define PACKET3_INDX_BUFFER 0x33
52#define PACKET3_3D_DRAW_VBUF_2 0x34 53#define PACKET3_3D_DRAW_VBUF_2 0x34
53#define PACKET3_3D_DRAW_IMMD_2 0x35 54#define PACKET3_3D_DRAW_IMMD_2 0x35
54#define PACKET3_3D_DRAW_INDX_2 0x36 55#define PACKET3_3D_DRAW_INDX_2 0x36
56#define PACKET3_3D_CLEAR_HIZ 0x37
55#define PACKET3_BITBLT_MULTI 0x9B 57#define PACKET3_BITBLT_MULTI 0x9B
56 58
57#define PACKET0(reg, n) (CP_PACKET0 | \ 59#define PACKET0(reg, n) (CP_PACKET0 | \
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 58eab5d4730..c827738ad7d 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1048,14 +1048,47 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1048 /* RB3D_COLOR_CHANNEL_MASK */ 1048 /* RB3D_COLOR_CHANNEL_MASK */
1049 track->color_channel_mask = idx_value; 1049 track->color_channel_mask = idx_value;
1050 break; 1050 break;
1051 case 0x4d1c: 1051 case 0x43a4:
1052 /* SC_HYPERZ_EN */
1053 /* r300c emits this register - we need to disable hyperz for it
1054 * without complaining */
1055 if (p->rdev->hyperz_filp != p->filp) {
1056 if (idx_value & 0x1)
1057 ib[idx] = idx_value & ~1;
1058 }
1059 break;
1060 case 0x4f1c:
1052 /* ZB_BW_CNTL */ 1061 /* ZB_BW_CNTL */
1053 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1062 track->zb_cb_clear = !!(idx_value & (1 << 5));
1063 if (p->rdev->hyperz_filp != p->filp) {
1064 if (idx_value & (R300_HIZ_ENABLE |
1065 R300_RD_COMP_ENABLE |
1066 R300_WR_COMP_ENABLE |
1067 R300_FAST_FILL_ENABLE))
1068 goto fail;
1069 }
1054 break; 1070 break;
1055 case 0x4e04: 1071 case 0x4e04:
1056 /* RB3D_BLENDCNTL */ 1072 /* RB3D_BLENDCNTL */
1057 track->blend_read_enable = !!(idx_value & (1 << 2)); 1073 track->blend_read_enable = !!(idx_value & (1 << 2));
1058 break; 1074 break;
1075 case 0x4f28: /* ZB_DEPTHCLEARVALUE */
1076 break;
1077 case 0x4f30: /* ZB_MASK_OFFSET */
1078 case 0x4f34: /* ZB_ZMASK_PITCH */
1079 case 0x4f44: /* ZB_HIZ_OFFSET */
1080 case 0x4f54: /* ZB_HIZ_PITCH */
1081 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1082 goto fail;
1083 break;
1084 case 0x4028:
1085 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1086 goto fail;
1087 /* GB_Z_PEQ_CONFIG */
1088 if (p->rdev->family >= CHIP_RV350)
1089 break;
1090 goto fail;
1091 break;
1059 case 0x4be8: 1092 case 0x4be8:
1060 /* valid register only on RV530 */ 1093 /* valid register only on RV530 */
1061 if (p->rdev->family == CHIP_RV530) 1094 if (p->rdev->family == CHIP_RV530)
@@ -1066,8 +1099,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1066 } 1099 }
1067 return 0; 1100 return 0;
1068fail: 1101fail:
1069 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1102 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1070 reg, idx); 1103 reg, idx, idx_value);
1071 return -EINVAL; 1104 return -EINVAL;
1072} 1105}
1073 1106
@@ -1161,6 +1194,11 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1161 return r; 1194 return r;
1162 } 1195 }
1163 break; 1196 break;
1197 case PACKET3_3D_CLEAR_HIZ:
1198 case PACKET3_3D_CLEAR_ZMASK:
1199 if (p->rdev->hyperz_filp != p->filp)
1200 return -EINVAL;
1201 break;
1164 case PACKET3_NOP: 1202 case PACKET3_NOP:
1165 break; 1203 break;
1166 default: 1204 default:
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
index 968a33317fb..0c036c60d9d 100644
--- a/drivers/gpu/drm/radeon/r300d.h
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -48,10 +48,12 @@
48#define PACKET3_3D_DRAW_IMMD 0x29 48#define PACKET3_3D_DRAW_IMMD 0x29
49#define PACKET3_3D_DRAW_INDX 0x2A 49#define PACKET3_3D_DRAW_INDX 0x2A
50#define PACKET3_3D_LOAD_VBPNTR 0x2F 50#define PACKET3_3D_LOAD_VBPNTR 0x2F
51#define PACKET3_3D_CLEAR_ZMASK 0x32
51#define PACKET3_INDX_BUFFER 0x33 52#define PACKET3_INDX_BUFFER 0x33
52#define PACKET3_3D_DRAW_VBUF_2 0x34 53#define PACKET3_3D_DRAW_VBUF_2 0x34
53#define PACKET3_3D_DRAW_IMMD_2 0x35 54#define PACKET3_3D_DRAW_IMMD_2 0x35
54#define PACKET3_3D_DRAW_INDX_2 0x36 55#define PACKET3_3D_DRAW_INDX_2 0x36
56#define PACKET3_3D_CLEAR_HIZ 0x37
55#define PACKET3_BITBLT_MULTI 0x9B 57#define PACKET3_BITBLT_MULTI 0x9B
56 58
57#define PACKET0(reg, n) (CP_PACKET0 | \ 59#define PACKET0(reg, n) (CP_PACKET0 | \
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index c84f9a31155..368fecf0c2b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1098,6 +1098,8 @@ struct radeon_device {
1098 1098
1099 bool powered_down; 1099 bool powered_down;
1100 struct notifier_block acpi_nb; 1100 struct notifier_block acpi_nb;
1101 /* only one userspace can use Hyperz features at a time */
1102 struct drm_file *hyperz_filp;
1101}; 1103};
1102 1104
1103int radeon_device_init(struct radeon_device *rdev, 1105int radeon_device_init(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 6f8a2e57287..795403b0e2c 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -46,7 +46,7 @@
46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
47 * - 2.4.0 - add crtc id query 47 * - 2.4.0 - add crtc id query
48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
49 * - 2.6.0 - add tiling config query (r6xx+) 49 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
50 */ 50 */
51#define KMS_DRIVER_MAJOR 2 51#define KMS_DRIVER_MAJOR 2
52#define KMS_DRIVER_MINOR 6 52#define KMS_DRIVER_MINOR 6
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index dd0a78e954a..e5b70542738 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -159,6 +159,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
159 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 159 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
160 return -EINVAL; 160 return -EINVAL;
161 } 161 }
162 case RADEON_INFO_WANT_HYPERZ:
163 mutex_lock(&dev->struct_mutex);
164 if (rdev->hyperz_filp)
165 value = 0;
166 else {
167 rdev->hyperz_filp = filp;
168 value = 1;
169 }
170 mutex_unlock(&dev->struct_mutex);
162 break; 171 break;
163 default: 172 default:
164 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 173 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
@@ -199,9 +208,11 @@ void radeon_driver_postclose_kms(struct drm_device *dev,
199void radeon_driver_preclose_kms(struct drm_device *dev, 208void radeon_driver_preclose_kms(struct drm_device *dev,
200 struct drm_file *file_priv) 209 struct drm_file *file_priv)
201{ 210{
211 struct radeon_device *rdev = dev->dev_private;
212 if (rdev->hyperz_filp == file_priv)
213 rdev->hyperz_filp = NULL;
202} 214}
203 215
204
205/* 216/*
206 * VBlank related functions. 217 * VBlank related functions.
207 */ 218 */
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
index 1e97b2d129f..b506ec1cab4 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r300
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -187,7 +187,6 @@ r300 0x4f60
1870x4364 RS_INST_13 1870x4364 RS_INST_13
1880x4368 RS_INST_14 1880x4368 RS_INST_14
1890x436C RS_INST_15 1890x436C RS_INST_15
1900x43A4 SC_HYPERZ_EN
1910x43A8 SC_EDGERULE 1900x43A8 SC_EDGERULE
1920x43B0 SC_CLIP_0_A 1910x43B0 SC_CLIP_0_A
1930x43B4 SC_CLIP_0_B 1920x43B4 SC_CLIP_0_B
@@ -716,16 +715,4 @@ r300 0x4f60
7160x4F08 ZB_STENCILREFMASK 7150x4F08 ZB_STENCILREFMASK
7170x4F14 ZB_ZTOP 7160x4F14 ZB_ZTOP
7180x4F18 ZB_ZCACHE_CTLSTAT 7170x4F18 ZB_ZCACHE_CTLSTAT
7190x4F1C ZB_BW_CNTL
7200x4F28 ZB_DEPTHCLEARVALUE
7210x4F30 ZB_ZMASK_OFFSET
7220x4F34 ZB_ZMASK_PITCH
7230x4F38 ZB_ZMASK_WRINDEX
7240x4F3C ZB_ZMASK_DWORD
7250x4F40 ZB_ZMASK_RDINDEX
7260x4F44 ZB_HIZ_OFFSET
7270x4F48 ZB_HIZ_WRINDEX
7280x4F4C ZB_HIZ_DWORD
7290x4F50 ZB_HIZ_RDINDEX
7300x4F54 ZB_HIZ_PITCH
7310x4F58 ZB_ZPASS_DATA 7180x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
index e958980d00f..8c1214c2390 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r420
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -130,6 +130,7 @@ r420 0x4f60
1300x401C GB_SELECT 1300x401C GB_SELECT
1310x4020 GB_AA_CONFIG 1310x4020 GB_AA_CONFIG
1320x4024 GB_FIFO_SIZE 1320x4024 GB_FIFO_SIZE
1330x4028 GB_Z_PEQ_CONFIG
1330x4100 TX_INVALTAGS 1340x4100 TX_INVALTAGS
1340x4200 GA_POINT_S0 1350x4200 GA_POINT_S0
1350x4204 GA_POINT_T0 1360x4204 GA_POINT_T0
@@ -187,7 +188,6 @@ r420 0x4f60
1870x4364 RS_INST_13 1880x4364 RS_INST_13
1880x4368 RS_INST_14 1890x4368 RS_INST_14
1890x436C RS_INST_15 1900x436C RS_INST_15
1900x43A4 SC_HYPERZ_EN
1910x43A8 SC_EDGERULE 1910x43A8 SC_EDGERULE
1920x43B0 SC_CLIP_0_A 1920x43B0 SC_CLIP_0_A
1930x43B4 SC_CLIP_0_B 1930x43B4 SC_CLIP_0_B
@@ -782,16 +782,4 @@ r420 0x4f60
7820x4F08 ZB_STENCILREFMASK 7820x4F08 ZB_STENCILREFMASK
7830x4F14 ZB_ZTOP 7830x4F14 ZB_ZTOP
7840x4F18 ZB_ZCACHE_CTLSTAT 7840x4F18 ZB_ZCACHE_CTLSTAT
7850x4F1C ZB_BW_CNTL
7860x4F28 ZB_DEPTHCLEARVALUE
7870x4F30 ZB_ZMASK_OFFSET
7880x4F34 ZB_ZMASK_PITCH
7890x4F38 ZB_ZMASK_WRINDEX
7900x4F3C ZB_ZMASK_DWORD
7910x4F40 ZB_ZMASK_RDINDEX
7920x4F44 ZB_HIZ_OFFSET
7930x4F48 ZB_HIZ_WRINDEX
7940x4F4C ZB_HIZ_DWORD
7950x4F50 ZB_HIZ_RDINDEX
7960x4F54 ZB_HIZ_PITCH
7970x4F58 ZB_ZPASS_DATA 7850x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 83e8bc0c2bb..0828d80396f 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -187,7 +187,6 @@ rs600 0x6d40
1870x4364 RS_INST_13 1870x4364 RS_INST_13
1880x4368 RS_INST_14 1880x4368 RS_INST_14
1890x436C RS_INST_15 1890x436C RS_INST_15
1900x43A4 SC_HYPERZ_EN
1910x43A8 SC_EDGERULE 1900x43A8 SC_EDGERULE
1920x43B0 SC_CLIP_0_A 1910x43B0 SC_CLIP_0_A
1930x43B4 SC_CLIP_0_B 1920x43B4 SC_CLIP_0_B
@@ -782,16 +781,4 @@ rs600 0x6d40
7820x4F08 ZB_STENCILREFMASK 7810x4F08 ZB_STENCILREFMASK
7830x4F14 ZB_ZTOP 7820x4F14 ZB_ZTOP
7840x4F18 ZB_ZCACHE_CTLSTAT 7830x4F18 ZB_ZCACHE_CTLSTAT
7850x4F1C ZB_BW_CNTL
7860x4F28 ZB_DEPTHCLEARVALUE
7870x4F30 ZB_ZMASK_OFFSET
7880x4F34 ZB_ZMASK_PITCH
7890x4F38 ZB_ZMASK_WRINDEX
7900x4F3C ZB_ZMASK_DWORD
7910x4F40 ZB_ZMASK_RDINDEX
7920x4F44 ZB_HIZ_OFFSET
7930x4F48 ZB_HIZ_WRINDEX
7940x4F4C ZB_HIZ_DWORD
7950x4F50 ZB_HIZ_RDINDEX
7960x4F54 ZB_HIZ_PITCH
7970x4F58 ZB_ZPASS_DATA 7840x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 1e46233985e..8293855f5f0 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -235,7 +235,6 @@ rv515 0x6d40
2350x4354 RS_INST_13 2350x4354 RS_INST_13
2360x4358 RS_INST_14 2360x4358 RS_INST_14
2370x435C RS_INST_15 2370x435C RS_INST_15
2380x43A4 SC_HYPERZ_EN
2390x43A8 SC_EDGERULE 2380x43A8 SC_EDGERULE
2400x43B0 SC_CLIP_0_A 2390x43B0 SC_CLIP_0_A
2410x43B4 SC_CLIP_0_B 2400x43B4 SC_CLIP_0_B
@@ -479,17 +478,5 @@ rv515 0x6d40
4790x4F08 ZB_STENCILREFMASK 4780x4F08 ZB_STENCILREFMASK
4800x4F14 ZB_ZTOP 4790x4F14 ZB_ZTOP
4810x4F18 ZB_ZCACHE_CTLSTAT 4800x4F18 ZB_ZCACHE_CTLSTAT
4820x4F1C ZB_BW_CNTL
4830x4F28 ZB_DEPTHCLEARVALUE
4840x4F30 ZB_ZMASK_OFFSET
4850x4F34 ZB_ZMASK_PITCH
4860x4F38 ZB_ZMASK_WRINDEX
4870x4F3C ZB_ZMASK_DWORD
4880x4F40 ZB_ZMASK_RDINDEX
4890x4F44 ZB_HIZ_OFFSET
4900x4F48 ZB_HIZ_WRINDEX
4910x4F4C ZB_HIZ_DWORD
4920x4F50 ZB_HIZ_RDINDEX
4930x4F54 ZB_HIZ_PITCH
4940x4F58 ZB_ZPASS_DATA 4810x4F58 ZB_ZPASS_DATA
4950x4FD4 ZB_STENCILREFMASK_BF 4820x4FD4 ZB_STENCILREFMASK_BF
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 09:43:21 -0400