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-rw-r--r--drivers/gpu/drm/radeon/Makefile15
-rw-r--r--drivers/gpu/drm/radeon/r100.c811
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h124
-rw-r--r--drivers/gpu/drm/radeon/r200.c456
-rw-r--r--drivers/gpu/drm/radeon/r300.c363
-rw-r--r--drivers/gpu/drm/radeon/radeon.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h57
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r100105
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r200184
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rn5030
11 files changed, 1712 insertions, 440 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index b2213a576a8..6fb84296249 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -11,6 +11,15 @@ hostprogs-y := mkregtable
11quiet_cmd_mkregtable = MKREGTABLE $@ 11quiet_cmd_mkregtable = MKREGTABLE $@
12 cmd_mkregtable = $(obj)/mkregtable $< > $@ 12 cmd_mkregtable = $(obj)/mkregtable $< > $@
13 13
14$(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable
15 $(call if_changed,mkregtable)
16
17$(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable
18 $(call if_changed,mkregtable)
19
20$(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable
21 $(call if_changed,mkregtable)
22
14$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable 23$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
15 $(call if_changed,mkregtable) 24 $(call if_changed,mkregtable)
16 25
@@ -20,6 +29,10 @@ $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
20$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable 29$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
21 $(call if_changed,mkregtable) 30 $(call if_changed,mkregtable)
22 31
32$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
33
34$(obj)/r200.o: $(obj)/r200_reg_safe.h
35
23$(obj)/rv515.o: $(obj)/rv515_reg_safe.h 36$(obj)/rv515.o: $(obj)/rv515_reg_safe.h
24 37
25$(obj)/r300.o: $(obj)/r300_reg_safe.h 38$(obj)/r300.o: $(obj)/r300_reg_safe.h
@@ -34,7 +47,7 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
34 radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ 47 radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
35 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ 48 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
36 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ 49 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \
37 radeon_test.o 50 radeon_test.o r200.o
38 51
39radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 52radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
40 53
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 44f34f8e2b3..ee3ab62417e 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -34,6 +34,9 @@
34#include <linux/firmware.h> 34#include <linux/firmware.h>
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36 36
37#include "r100_reg_safe.h"
38#include "rn50_reg_safe.h"
39
37/* Firmware Names */ 40/* Firmware Names */
38#define FIRMWARE_R100 "radeon/R100_cp.bin" 41#define FIRMWARE_R100 "radeon/R100_cp.bin"
39#define FIRMWARE_R200 "radeon/R200_cp.bin" 42#define FIRMWARE_R200 "radeon/R200_cp.bin"
@@ -51,11 +54,14 @@ MODULE_FIRMWARE(FIRMWARE_RS690);
51MODULE_FIRMWARE(FIRMWARE_RS600); 54MODULE_FIRMWARE(FIRMWARE_RS600);
52MODULE_FIRMWARE(FIRMWARE_R520); 55MODULE_FIRMWARE(FIRMWARE_R520);
53 56
57#include "r100_track.h"
58
54/* This files gather functions specifics to: 59/* This files gather functions specifics to:
55 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 60 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
56 * 61 *
57 * Some of these functions might be used by newer ASICs. 62 * Some of these functions might be used by newer ASICs.
58 */ 63 */
64int r200_init(struct radeon_device *rdev);
59void r100_hdp_reset(struct radeon_device *rdev); 65void r100_hdp_reset(struct radeon_device *rdev);
60void r100_gpu_init(struct radeon_device *rdev); 66void r100_gpu_init(struct radeon_device *rdev);
61int r100_gui_wait_for_idle(struct radeon_device *rdev); 67int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -1017,147 +1023,356 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1017 return 0; 1023 return 0;
1018} 1024}
1019 1025
1026static int r100_get_vtx_size(uint32_t vtx_fmt)
1027{
1028 int vtx_size;
1029 vtx_size = 2;
1030 /* ordered according to bits in spec */
1031 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1032 vtx_size++;
1033 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1034 vtx_size += 3;
1035 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1036 vtx_size++;
1037 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1038 vtx_size++;
1039 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1040 vtx_size += 3;
1041 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1042 vtx_size++;
1043 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1044 vtx_size++;
1045 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1046 vtx_size += 2;
1047 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1048 vtx_size += 2;
1049 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1050 vtx_size++;
1051 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1052 vtx_size += 2;
1053 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1054 vtx_size++;
1055 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1056 vtx_size += 2;
1057 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1058 vtx_size++;
1059 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1060 vtx_size++;
1061 /* blend weight */
1062 if (vtx_fmt & (0x7 << 15))
1063 vtx_size += (vtx_fmt >> 15) & 0x7;
1064 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1065 vtx_size += 3;
1066 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1067 vtx_size += 2;
1068 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1069 vtx_size++;
1070 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1071 vtx_size++;
1072 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1073 vtx_size++;
1074 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1075 vtx_size++;
1076 return vtx_size;
1077}
1078
1020static int r100_packet0_check(struct radeon_cs_parser *p, 1079static int r100_packet0_check(struct radeon_cs_parser *p,
1021 struct radeon_cs_packet *pkt) 1080 struct radeon_cs_packet *pkt,
1081 unsigned idx, unsigned reg)
1022{ 1082{
1023 struct radeon_cs_chunk *ib_chunk; 1083 struct radeon_cs_chunk *ib_chunk;
1024 struct radeon_cs_reloc *reloc; 1084 struct radeon_cs_reloc *reloc;
1085 struct r100_cs_track *track;
1025 volatile uint32_t *ib; 1086 volatile uint32_t *ib;
1026 uint32_t tmp; 1087 uint32_t tmp;
1027 unsigned reg;
1028 unsigned i;
1029 unsigned idx;
1030 bool onereg;
1031 int r; 1088 int r;
1089 int i, face;
1032 u32 tile_flags = 0; 1090 u32 tile_flags = 0;
1033 1091
1034 ib = p->ib->ptr; 1092 ib = p->ib->ptr;
1035 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1093 ib_chunk = &p->chunks[p->chunk_ib_idx];
1036 idx = pkt->idx + 1; 1094 track = (struct r100_cs_track *)p->track;
1037 reg = pkt->reg; 1095
1038 onereg = false; 1096 switch (reg) {
1039 if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) { 1097 case RADEON_CRTC_GUI_TRIG_VLINE:
1040 onereg = true; 1098 r = r100_cs_packet_parse_vline(p);
1041 } 1099 if (r) {
1042 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 1100 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1043 switch (reg) { 1101 idx, reg);
1044 case RADEON_CRTC_GUI_TRIG_VLINE: 1102 r100_cs_dump_packet(p, pkt);
1045 r = r100_cs_packet_parse_vline(p); 1103 return r;
1046 if (r) { 1104 }
1047 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1105 break;
1048 idx, reg);
1049 r100_cs_dump_packet(p, pkt);
1050 return r;
1051 }
1052 break;
1053 /* FIXME: only allow PACKET3 blit? easier to check for out of 1106 /* FIXME: only allow PACKET3 blit? easier to check for out of
1054 * range access */ 1107 * range access */
1055 case RADEON_DST_PITCH_OFFSET: 1108 case RADEON_DST_PITCH_OFFSET:
1056 case RADEON_SRC_PITCH_OFFSET: 1109 case RADEON_SRC_PITCH_OFFSET:
1057 r = r100_cs_packet_next_reloc(p, &reloc); 1110 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1058 if (r) { 1111 if (r)
1059 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1112 return r;
1060 idx, reg); 1113 break;
1061 r100_cs_dump_packet(p, pkt); 1114 case RADEON_RB3D_DEPTHOFFSET:
1062 return r; 1115 r = r100_cs_packet_next_reloc(p, &reloc);
1063 } 1116 if (r) {
1064 tmp = ib_chunk->kdata[idx] & 0x003fffff; 1117 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1065 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1118 idx, reg);
1066 1119 r100_cs_dump_packet(p, pkt);
1067 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1120 return r;
1068 tile_flags |= RADEON_DST_TILE_MACRO; 1121 }
1069 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1122 track->zb.robj = reloc->robj;
1070 if (reg == RADEON_SRC_PITCH_OFFSET) { 1123 track->zb.offset = ib_chunk->kdata[idx];
1071 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1124 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1072 r100_cs_dump_packet(p, pkt); 1125 break;
1073 return -EINVAL; 1126 case RADEON_RB3D_COLOROFFSET:
1074 } 1127 r = r100_cs_packet_next_reloc(p, &reloc);
1075 tile_flags |= RADEON_DST_TILE_MICRO; 1128 if (r) {
1076 } 1129 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1130 idx, reg);
1131 r100_cs_dump_packet(p, pkt);
1132 return r;
1133 }
1134 track->cb[0].robj = reloc->robj;
1135 track->cb[0].offset = ib_chunk->kdata[idx];
1136 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1137 break;
1138 case RADEON_PP_TXOFFSET_0:
1139 case RADEON_PP_TXOFFSET_1:
1140 case RADEON_PP_TXOFFSET_2:
1141 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1142 r = r100_cs_packet_next_reloc(p, &reloc);
1143 if (r) {
1144 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1145 idx, reg);
1146 r100_cs_dump_packet(p, pkt);
1147 return r;
1148 }
1149 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1150 track->textures[i].robj = reloc->robj;
1151 break;
1152 case RADEON_PP_CUBIC_OFFSET_T0_0:
1153 case RADEON_PP_CUBIC_OFFSET_T0_1:
1154 case RADEON_PP_CUBIC_OFFSET_T0_2:
1155 case RADEON_PP_CUBIC_OFFSET_T0_3:
1156 case RADEON_PP_CUBIC_OFFSET_T0_4:
1157 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1158 r = r100_cs_packet_next_reloc(p, &reloc);
1159 if (r) {
1160 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1161 idx, reg);
1162 r100_cs_dump_packet(p, pkt);
1163 return r;
1164 }
1165 track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx];
1166 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1167 track->textures[0].cube_info[i].robj = reloc->robj;
1168 break;
1169 case RADEON_PP_CUBIC_OFFSET_T1_0:
1170 case RADEON_PP_CUBIC_OFFSET_T1_1:
1171 case RADEON_PP_CUBIC_OFFSET_T1_2:
1172 case RADEON_PP_CUBIC_OFFSET_T1_3:
1173 case RADEON_PP_CUBIC_OFFSET_T1_4:
1174 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1175 r = r100_cs_packet_next_reloc(p, &reloc);
1176 if (r) {
1177 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1178 idx, reg);
1179 r100_cs_dump_packet(p, pkt);
1180 return r;
1181 }
1182 track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx];
1183 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1184 track->textures[1].cube_info[i].robj = reloc->robj;
1185 break;
1186 case RADEON_PP_CUBIC_OFFSET_T2_0:
1187 case RADEON_PP_CUBIC_OFFSET_T2_1:
1188 case RADEON_PP_CUBIC_OFFSET_T2_2:
1189 case RADEON_PP_CUBIC_OFFSET_T2_3:
1190 case RADEON_PP_CUBIC_OFFSET_T2_4:
1191 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1192 r = r100_cs_packet_next_reloc(p, &reloc);
1193 if (r) {
1194 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1195 idx, reg);
1196 r100_cs_dump_packet(p, pkt);
1197 return r;
1198 }
1199 track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx];
1200 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1201 track->textures[2].cube_info[i].robj = reloc->robj;
1202 break;
1203 case RADEON_RE_WIDTH_HEIGHT:
1204 track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
1205 break;
1206 case RADEON_RB3D_COLORPITCH:
1207 r = r100_cs_packet_next_reloc(p, &reloc);
1208 if (r) {
1209 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1210 idx, reg);
1211 r100_cs_dump_packet(p, pkt);
1212 return r;
1213 }
1077 1214
1078 tmp |= tile_flags; 1215 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1079 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; 1216 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1080 break; 1217 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1081 case RADEON_RB3D_DEPTHOFFSET: 1218 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1082 case RADEON_RB3D_COLOROFFSET:
1083 case R300_RB3D_COLOROFFSET0:
1084 case R300_ZB_DEPTHOFFSET:
1085 case R200_PP_TXOFFSET_0:
1086 case R200_PP_TXOFFSET_1:
1087 case R200_PP_TXOFFSET_2:
1088 case R200_PP_TXOFFSET_3:
1089 case R200_PP_TXOFFSET_4:
1090 case R200_PP_TXOFFSET_5:
1091 case RADEON_PP_TXOFFSET_0:
1092 case RADEON_PP_TXOFFSET_1:
1093 case RADEON_PP_TXOFFSET_2:
1094 case R300_TX_OFFSET_0:
1095 case R300_TX_OFFSET_0+4:
1096 case R300_TX_OFFSET_0+8:
1097 case R300_TX_OFFSET_0+12:
1098 case R300_TX_OFFSET_0+16:
1099 case R300_TX_OFFSET_0+20:
1100 case R300_TX_OFFSET_0+24:
1101 case R300_TX_OFFSET_0+28:
1102 case R300_TX_OFFSET_0+32:
1103 case R300_TX_OFFSET_0+36:
1104 case R300_TX_OFFSET_0+40:
1105 case R300_TX_OFFSET_0+44:
1106 case R300_TX_OFFSET_0+48:
1107 case R300_TX_OFFSET_0+52:
1108 case R300_TX_OFFSET_0+56:
1109 case R300_TX_OFFSET_0+60:
1110 /* rn50 has no 3D engine so fail on any 3d setup */
1111 if (ASIC_IS_RN50(p->rdev)) {
1112 DRM_ERROR("attempt to use RN50 3D engine failed\n");
1113 return -EINVAL;
1114 }
1115 r = r100_cs_packet_next_reloc(p, &reloc);
1116 if (r) {
1117 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1118 idx, reg);
1119 r100_cs_dump_packet(p, pkt);
1120 return r;
1121 }
1122 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1123 break;
1124 case R300_RB3D_COLORPITCH0:
1125 case RADEON_RB3D_COLORPITCH:
1126 r = r100_cs_packet_next_reloc(p, &reloc);
1127 if (r) {
1128 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1129 idx, reg);
1130 r100_cs_dump_packet(p, pkt);
1131 return r;
1132 }
1133 1219
1134 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1220 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1135 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1221 tmp |= tile_flags;
1136 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1222 ib[idx] = tmp;
1137 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1138 1223
1139 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); 1224 track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
1140 tmp |= tile_flags; 1225 break;
1141 ib[idx] = tmp; 1226 case RADEON_RB3D_DEPTHPITCH:
1227 track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
1228 break;
1229 case RADEON_RB3D_CNTL:
1230 switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1231 case 7:
1232 case 8:
1233 case 9:
1234 case 11:
1235 case 12:
1236 track->cb[0].cpp = 1;
1142 break; 1237 break;
1143 case RADEON_RB3D_ZPASS_ADDR: 1238 case 3:
1144 r = r100_cs_packet_next_reloc(p, &reloc); 1239 case 4:
1145 if (r) { 1240 case 15:
1146 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1241 track->cb[0].cpp = 2;
1147 idx, reg); 1242 break;
1148 r100_cs_dump_packet(p, pkt); 1243 case 6:
1149 return r; 1244 track->cb[0].cpp = 4;
1150 } 1245 break;
1151 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1246 default:
1247 DRM_ERROR("Invalid color buffer format (%d) !\n",
1248 ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1249 return -EINVAL;
1250 }
1251 track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
1252 break;
1253 case RADEON_RB3D_ZSTENCILCNTL:
1254 switch (ib_chunk->kdata[idx] & 0xf) {
1255 case 0:
1256 track->zb.cpp = 2;
1257 break;
1258 case 2:
1259 case 3:
1260 case 4:
1261 case 5:
1262 case 9:
1263 case 11:
1264 track->zb.cpp = 4;
1152 break; 1265 break;
1153 default: 1266 default:
1154 /* FIXME: we don't want to allow anyothers packet */
1155 break; 1267 break;
1156 } 1268 }
1157 if (onereg) { 1269 break;
1158 /* FIXME: forbid onereg write to register on relocate */ 1270 case RADEON_RB3D_ZPASS_ADDR:
1271 r = r100_cs_packet_next_reloc(p, &reloc);
1272 if (r) {
1273 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1274 idx, reg);
1275 r100_cs_dump_packet(p, pkt);
1276 return r;
1277 }
1278 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1279 break;
1280 case RADEON_PP_CNTL:
1281 {
1282 uint32_t temp = ib_chunk->kdata[idx] >> 4;
1283 for (i = 0; i < track->num_texture; i++)
1284 track->textures[i].enabled = !!(temp & (1 << i));
1285 }
1286 break;
1287 case RADEON_SE_VF_CNTL:
1288 track->vap_vf_cntl = ib_chunk->kdata[idx];
1289 break;
1290 case RADEON_SE_VTX_FMT:
1291 track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]);
1292 break;
1293 case RADEON_PP_TEX_SIZE_0:
1294 case RADEON_PP_TEX_SIZE_1:
1295 case RADEON_PP_TEX_SIZE_2:
1296 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1297 track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
1298 track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1299 break;
1300 case RADEON_PP_TEX_PITCH_0:
1301 case RADEON_PP_TEX_PITCH_1:
1302 case RADEON_PP_TEX_PITCH_2:
1303 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1304 track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
1305 break;
1306 case RADEON_PP_TXFILTER_0:
1307 case RADEON_PP_TXFILTER_1:
1308 case RADEON_PP_TXFILTER_2:
1309 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1310 track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK)
1311 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1312 tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
1313 if (tmp == 2 || tmp == 6)
1314 track->textures[i].roundup_w = false;
1315 tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
1316 if (tmp == 2 || tmp == 6)
1317 track->textures[i].roundup_h = false;
1318 break;
1319 case RADEON_PP_TXFORMAT_0:
1320 case RADEON_PP_TXFORMAT_1:
1321 case RADEON_PP_TXFORMAT_2:
1322 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1323 if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) {
1324 track->textures[i].use_pitch = 1;
1325 } else {
1326 track->textures[i].use_pitch = 0;
1327 track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1328 track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1329 }
1330 if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1331 track->textures[i].tex_coord_type = 2;
1332 switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
1333 case RADEON_TXFORMAT_I8:
1334 case RADEON_TXFORMAT_RGB332:
1335 case RADEON_TXFORMAT_Y8:
1336 track->textures[i].cpp = 1;
1337 break;
1338 case RADEON_TXFORMAT_AI88:
1339 case RADEON_TXFORMAT_ARGB1555:
1340 case RADEON_TXFORMAT_RGB565:
1341 case RADEON_TXFORMAT_ARGB4444:
1342 case RADEON_TXFORMAT_VYUY422:
1343 case RADEON_TXFORMAT_YVYU422:
1344 case RADEON_TXFORMAT_DXT1:
1345 case RADEON_TXFORMAT_SHADOW16:
1346 case RADEON_TXFORMAT_LDUDV655:
1347 case RADEON_TXFORMAT_DUDV88:
1348 track->textures[i].cpp = 2;
1159 break; 1349 break;
1350 case RADEON_TXFORMAT_ARGB8888:
1351 case RADEON_TXFORMAT_RGBA8888:
1352 case RADEON_TXFORMAT_DXT23:
1353 case RADEON_TXFORMAT_DXT45:
1354 case RADEON_TXFORMAT_SHADOW32:
1355 case RADEON_TXFORMAT_LDUDUV8888:
1356 track->textures[i].cpp = 4;
1357 break;
1358 }
1359 track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
1360 track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
1361 break;
1362 case RADEON_PP_CUBIC_FACES_0:
1363 case RADEON_PP_CUBIC_FACES_1:
1364 case RADEON_PP_CUBIC_FACES_2:
1365 tmp = ib_chunk->kdata[idx];
1366 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1367 for (face = 0; face < 4; face++) {
1368 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1369 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1160 } 1370 }
1371 break;
1372 default:
1373 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1374 reg, idx);
1375 return -EINVAL;
1161 } 1376 }
1162 return 0; 1377 return 0;
1163} 1378}
@@ -1186,6 +1401,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1186{ 1401{
1187 struct radeon_cs_chunk *ib_chunk; 1402 struct radeon_cs_chunk *ib_chunk;
1188 struct radeon_cs_reloc *reloc; 1403 struct radeon_cs_reloc *reloc;
1404 struct r100_cs_track *track;
1189 unsigned idx; 1405 unsigned idx;
1190 unsigned i, c; 1406 unsigned i, c;
1191 volatile uint32_t *ib; 1407 volatile uint32_t *ib;
@@ -1194,9 +1410,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1194 ib = p->ib->ptr; 1410 ib = p->ib->ptr;
1195 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1411 ib_chunk = &p->chunks[p->chunk_ib_idx];
1196 idx = pkt->idx + 1; 1412 idx = pkt->idx + 1;
1413 track = (struct r100_cs_track *)p->track;
1197 switch (pkt->opcode) { 1414 switch (pkt->opcode) {
1198 case PACKET3_3D_LOAD_VBPNTR: 1415 case PACKET3_3D_LOAD_VBPNTR:
1199 c = ib_chunk->kdata[idx++]; 1416 c = ib_chunk->kdata[idx++];
1417 track->num_arrays = c;
1200 for (i = 0; i < (c - 1); i += 2, idx += 3) { 1418 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1201 r = r100_cs_packet_next_reloc(p, &reloc); 1419 r = r100_cs_packet_next_reloc(p, &reloc);
1202 if (r) { 1420 if (r) {
@@ -1206,6 +1424,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1206 return r; 1424 return r;
1207 } 1425 }
1208 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); 1426 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1427 track->arrays[i + 0].robj = reloc->robj;
1428 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1429 track->arrays[i + 0].esize &= 0x7F;
1209 r = r100_cs_packet_next_reloc(p, &reloc); 1430 r = r100_cs_packet_next_reloc(p, &reloc);
1210 if (r) { 1431 if (r) {
1211 DRM_ERROR("No reloc for packet3 %d\n", 1432 DRM_ERROR("No reloc for packet3 %d\n",
@@ -1214,6 +1435,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1214 return r; 1435 return r;
1215 } 1436 }
1216 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); 1437 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1438 track->arrays[i + 1].robj = reloc->robj;
1439 track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1440 track->arrays[i + 1].esize &= 0x7F;
1217 } 1441 }
1218 if (c & 1) { 1442 if (c & 1) {
1219 r = r100_cs_packet_next_reloc(p, &reloc); 1443 r = r100_cs_packet_next_reloc(p, &reloc);
@@ -1224,6 +1448,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1224 return r; 1448 return r;
1225 } 1449 }
1226 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); 1450 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1451 track->arrays[i + 0].robj = reloc->robj;
1452 track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1453 track->arrays[i + 0].esize &= 0x7F;
1227 } 1454 }
1228 break; 1455 break;
1229 case PACKET3_INDX_BUFFER: 1456 case PACKET3_INDX_BUFFER:
@@ -1240,7 +1467,6 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1240 } 1467 }
1241 break; 1468 break;
1242 case 0x23: 1469 case 0x23:
1243 /* FIXME: cleanup */
1244 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1470 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1245 r = r100_cs_packet_next_reloc(p, &reloc); 1471 r = r100_cs_packet_next_reloc(p, &reloc);
1246 if (r) { 1472 if (r) {
@@ -1249,18 +1475,71 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1249 return r; 1475 return r;
1250 } 1476 }
1251 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1477 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1478 track->num_arrays = 1;
1479 track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]);
1480
1481 track->arrays[0].robj = reloc->robj;
1482 track->arrays[0].esize = track->vtx_size;
1483
1484 track->max_indx = ib_chunk->kdata[idx+1];
1485
1486 track->vap_vf_cntl = ib_chunk->kdata[idx+3];
1487 track->immd_dwords = pkt->count - 1;
1488 r = r100_cs_track_check(p->rdev, track);
1489 if (r)
1490 return r;
1252 break; 1491 break;
1253 case PACKET3_3D_DRAW_IMMD: 1492 case PACKET3_3D_DRAW_IMMD:
1493 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1494 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1495 return -EINVAL;
1496 }
1497 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1498 track->immd_dwords = pkt->count - 1;
1499 r = r100_cs_track_check(p->rdev, track);
1500 if (r)
1501 return r;
1502 break;
1254 /* triggers drawing using in-packet vertex data */ 1503 /* triggers drawing using in-packet vertex data */
1255 case PACKET3_3D_DRAW_IMMD_2: 1504 case PACKET3_3D_DRAW_IMMD_2:
1505 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1506 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1507 return -EINVAL;
1508 }
1509 track->vap_vf_cntl = ib_chunk->kdata[idx];
1510 track->immd_dwords = pkt->count;
1511 r = r100_cs_track_check(p->rdev, track);
1512 if (r)
1513 return r;
1514 break;
1256 /* triggers drawing using in-packet vertex data */ 1515 /* triggers drawing using in-packet vertex data */
1257 case PACKET3_3D_DRAW_VBUF_2: 1516 case PACKET3_3D_DRAW_VBUF_2:
1517 track->vap_vf_cntl = ib_chunk->kdata[idx];
1518 r = r100_cs_track_check(p->rdev, track);
1519 if (r)
1520 return r;
1521 break;
1258 /* triggers drawing of vertex buffers setup elsewhere */ 1522 /* triggers drawing of vertex buffers setup elsewhere */
1259 case PACKET3_3D_DRAW_INDX_2: 1523 case PACKET3_3D_DRAW_INDX_2:
1524 track->vap_vf_cntl = ib_chunk->kdata[idx];
1525 r = r100_cs_track_check(p->rdev, track);
1526 if (r)
1527 return r;
1528 break;
1260 /* triggers drawing using indices to vertex buffer */ 1529 /* triggers drawing using indices to vertex buffer */
1261 case PACKET3_3D_DRAW_VBUF: 1530 case PACKET3_3D_DRAW_VBUF:
1531 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1532 r = r100_cs_track_check(p->rdev, track);
1533 if (r)
1534 return r;
1535 break;
1262 /* triggers drawing of vertex buffers setup elsewhere */ 1536 /* triggers drawing of vertex buffers setup elsewhere */
1263 case PACKET3_3D_DRAW_INDX: 1537 case PACKET3_3D_DRAW_INDX:
1538 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1539 r = r100_cs_track_check(p->rdev, track);
1540 if (r)
1541 return r;
1542 break;
1264 /* triggers drawing using indices to vertex buffer */ 1543 /* triggers drawing using indices to vertex buffer */
1265 case PACKET3_NOP: 1544 case PACKET3_NOP:
1266 break; 1545 break;
@@ -1274,8 +1553,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1274int r100_cs_parse(struct radeon_cs_parser *p) 1553int r100_cs_parse(struct radeon_cs_parser *p)
1275{ 1554{
1276 struct radeon_cs_packet pkt; 1555 struct radeon_cs_packet pkt;
1556 struct r100_cs_track track;
1277 int r; 1557 int r;
1278 1558
1559 r100_cs_track_clear(p->rdev, &track);
1560 p->track = &track;
1279 do { 1561 do {
1280 r = r100_cs_packet_parse(p, &pkt, p->idx); 1562 r = r100_cs_packet_parse(p, &pkt, p->idx);
1281 if (r) { 1563 if (r) {
@@ -1284,7 +1566,16 @@ int r100_cs_parse(struct radeon_cs_parser *p)
1284 p->idx += pkt.count + 2; 1566 p->idx += pkt.count + 2;
1285 switch (pkt.type) { 1567 switch (pkt.type) {
1286 case PACKET_TYPE0: 1568 case PACKET_TYPE0:
1287 r = r100_packet0_check(p, &pkt); 1569 if (p->rdev->family >= CHIP_R200)
1570 r = r100_cs_parse_packet0(p, &pkt,
1571 p->rdev->config.r100.reg_safe_bm,
1572 p->rdev->config.r100.reg_safe_bm_size,
1573 &r200_packet0_check);
1574 else
1575 r = r100_cs_parse_packet0(p, &pkt,
1576 p->rdev->config.r100.reg_safe_bm,
1577 p->rdev->config.r100.reg_safe_bm_size,
1578 &r100_packet0_check);
1288 break; 1579 break;
1289 case PACKET_TYPE2: 1580 case PACKET_TYPE2:
1290 break; 1581 break;
@@ -1683,6 +1974,15 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1683 1974
1684int r100_init(struct radeon_device *rdev) 1975int r100_init(struct radeon_device *rdev)
1685{ 1976{
1977 if (ASIC_IS_RN50(rdev)) {
1978 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1979 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1980 } else if (rdev->family < CHIP_R200) {
1981 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1982 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1983 } else {
1984 return r200_init(rdev);
1985 }
1686 return 0; 1986 return 0;
1687} 1987}
1688 1988
@@ -2383,3 +2683,274 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2383 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 2683 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2384 } 2684 }
2385} 2685}
2686
2687static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2688{
2689 DRM_ERROR("pitch %d\n", t->pitch);
2690 DRM_ERROR("width %d\n", t->width);
2691 DRM_ERROR("height %d\n", t->height);
2692 DRM_ERROR("num levels %d\n", t->num_levels);
2693 DRM_ERROR("depth %d\n", t->txdepth);
2694 DRM_ERROR("bpp %d\n", t->cpp);
2695 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2696 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2697 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2698}
2699
2700static int r100_cs_track_cube(struct radeon_device *rdev,
2701 struct r100_cs_track *track, unsigned idx)
2702{
2703 unsigned face, w, h;
2704 struct radeon_object *cube_robj;
2705 unsigned long size;
2706
2707 for (face = 0; face < 5; face++) {
2708 cube_robj = track->textures[idx].cube_info[face].robj;
2709 w = track->textures[idx].cube_info[face].width;
2710 h = track->textures[idx].cube_info[face].height;
2711
2712 size = w * h;
2713 size *= track->textures[idx].cpp;
2714
2715 size += track->textures[idx].cube_info[face].offset;
2716
2717 if (size > radeon_object_size(cube_robj)) {
2718 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2719 size, radeon_object_size(cube_robj));
2720 r100_cs_track_texture_print(&track->textures[idx]);
2721 return -1;
2722 }
2723 }
2724 return 0;
2725}
2726
2727static int r100_cs_track_texture_check(struct radeon_device *rdev,
2728 struct r100_cs_track *track)
2729{
2730 struct radeon_object *robj;
2731 unsigned long size;
2732 unsigned u, i, w, h;
2733 int ret;
2734
2735 for (u = 0; u < track->num_texture; u++) {
2736 if (!track->textures[u].enabled)
2737 continue;
2738 robj = track->textures[u].robj;
2739 if (robj == NULL) {
2740 DRM_ERROR("No texture bound to unit %u\n", u);
2741 return -EINVAL;
2742 }
2743 size = 0;
2744 for (i = 0; i <= track->textures[u].num_levels; i++) {
2745 if (track->textures[u].use_pitch) {
2746 if (rdev->family < CHIP_R300)
2747 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2748 else
2749 w = track->textures[u].pitch / (1 << i);
2750 } else {
2751 w = track->textures[u].width / (1 << i);
2752 if (rdev->family >= CHIP_RV515)
2753 w |= track->textures[u].width_11;
2754 if (track->textures[u].roundup_w)
2755 w = roundup_pow_of_two(w);
2756 }
2757 h = track->textures[u].height / (1 << i);
2758 if (rdev->family >= CHIP_RV515)
2759 h |= track->textures[u].height_11;
2760 if (track->textures[u].roundup_h)
2761 h = roundup_pow_of_two(h);
2762 size += w * h;
2763 }
2764 size *= track->textures[u].cpp;
2765 switch (track->textures[u].tex_coord_type) {
2766 case 0:
2767 break;
2768 case 1:
2769 size *= (1 << track->textures[u].txdepth);
2770 break;
2771 case 2:
2772 if (track->separate_cube) {
2773 ret = r100_cs_track_cube(rdev, track, u);
2774 if (ret)
2775 return ret;
2776 } else
2777 size *= 6;
2778 break;
2779 default:
2780 DRM_ERROR("Invalid texture coordinate type %u for unit "
2781 "%u\n", track->textures[u].tex_coord_type, u);
2782 return -EINVAL;
2783 }
2784 if (size > radeon_object_size(robj)) {
2785 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2786 "%lu\n", u, size, radeon_object_size(robj));
2787 r100_cs_track_texture_print(&track->textures[u]);
2788 return -EINVAL;
2789 }
2790 }
2791 return 0;
2792}
2793
2794int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2795{
2796 unsigned i;
2797 unsigned long size;
2798 unsigned prim_walk;
2799 unsigned nverts;
2800
2801 for (i = 0; i < track->num_cb; i++) {
2802 if (track->cb[i].robj == NULL) {
2803 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2804 return -EINVAL;
2805 }
2806 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2807 size += track->cb[i].offset;
2808 if (size > radeon_object_size(track->cb[i].robj)) {
2809 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2810 "(need %lu have %lu) !\n", i, size,
2811 radeon_object_size(track->cb[i].robj));
2812 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2813 i, track->cb[i].pitch, track->cb[i].cpp,
2814 track->cb[i].offset, track->maxy);
2815 return -EINVAL;
2816 }
2817 }
2818 if (track->z_enabled) {
2819 if (track->zb.robj == NULL) {
2820 DRM_ERROR("[drm] No buffer for z buffer !\n");
2821 return -EINVAL;
2822 }
2823 size = track->zb.pitch * track->zb.cpp * track->maxy;
2824 size += track->zb.offset;
2825 if (size > radeon_object_size(track->zb.robj)) {
2826 DRM_ERROR("[drm] Buffer too small for z buffer "
2827 "(need %lu have %lu) !\n", size,
2828 radeon_object_size(track->zb.robj));
2829 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2830 track->zb.pitch, track->zb.cpp,
2831 track->zb.offset, track->maxy);
2832 return -EINVAL;
2833 }
2834 }
2835 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2836 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2837 switch (prim_walk) {
2838 case 1:
2839 for (i = 0; i < track->num_arrays; i++) {
2840 size = track->arrays[i].esize * track->max_indx * 4;
2841 if (track->arrays[i].robj == NULL) {
2842 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2843 "bound\n", prim_walk, i);
2844 return -EINVAL;
2845 }
2846 if (size > radeon_object_size(track->arrays[i].robj)) {
2847 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2848 "have %lu dwords\n", prim_walk, i,
2849 size >> 2,
2850 radeon_object_size(track->arrays[i].robj) >> 2);
2851 DRM_ERROR("Max indices %u\n", track->max_indx);
2852 return -EINVAL;
2853 }
2854 }
2855 break;
2856 case 2:
2857 for (i = 0; i < track->num_arrays; i++) {
2858 size = track->arrays[i].esize * (nverts - 1) * 4;
2859 if (track->arrays[i].robj == NULL) {
2860 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2861 "bound\n", prim_walk, i);
2862 return -EINVAL;
2863 }
2864 if (size > radeon_object_size(track->arrays[i].robj)) {
2865 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2866 "have %lu dwords\n", prim_walk, i, size >> 2,
2867 radeon_object_size(track->arrays[i].robj) >> 2);
2868 return -EINVAL;
2869 }
2870 }
2871 break;
2872 case 3:
2873 size = track->vtx_size * nverts;
2874 if (size != track->immd_dwords) {
2875 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2876 track->immd_dwords, size);
2877 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2878 nverts, track->vtx_size);
2879 return -EINVAL;
2880 }
2881 break;
2882 default:
2883 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2884 prim_walk);
2885 return -EINVAL;
2886 }
2887 return r100_cs_track_texture_check(rdev, track);
2888}
2889
2890void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2891{
2892 unsigned i, face;
2893
2894 if (rdev->family < CHIP_R300) {
2895 track->num_cb = 1;
2896 if (rdev->family <= CHIP_RS200)
2897 track->num_texture = 3;
2898 else
2899 track->num_texture = 6;
2900 track->maxy = 2048;
2901 track->separate_cube = 1;
2902 } else {
2903 track->num_cb = 4;
2904 track->num_texture = 16;
2905 track->maxy = 4096;
2906 track->separate_cube = 0;
2907 }
2908
2909 for (i = 0; i < track->num_cb; i++) {
2910 track->cb[i].robj = NULL;
2911 track->cb[i].pitch = 8192;
2912 track->cb[i].cpp = 16;
2913 track->cb[i].offset = 0;
2914 }
2915 track->z_enabled = true;
2916 track->zb.robj = NULL;
2917 track->zb.pitch = 8192;
2918 track->zb.cpp = 4;
2919 track->zb.offset = 0;
2920 track->vtx_size = 0x7F;
2921 track->immd_dwords = 0xFFFFFFFFUL;
2922 track->num_arrays = 11;
2923 track->max_indx = 0x00FFFFFFUL;
2924 for (i = 0; i < track->num_arrays; i++) {
2925 track->arrays[i].robj = NULL;
2926 track->arrays[i].esize = 0x7F;
2927 }
2928 for (i = 0; i < track->num_texture; i++) {
2929 track->textures[i].pitch = 16536;
2930 track->textures[i].width = 16536;
2931 track->textures[i].height = 16536;
2932 track->textures[i].width_11 = 1 << 11;
2933 track->textures[i].height_11 = 1 << 11;
2934 track->textures[i].num_levels = 12;
2935 if (rdev->family <= CHIP_RS200) {
2936 track->textures[i].tex_coord_type = 0;
2937 track->textures[i].txdepth = 0;
2938 } else {
2939 track->textures[i].txdepth = 16;
2940 track->textures[i].tex_coord_type = 1;
2941 }
2942 track->textures[i].cpp = 64;
2943 track->textures[i].robj = NULL;
2944 /* CS IB emission code makes sure texture unit are disabled */
2945 track->textures[i].enabled = false;
2946 track->textures[i].roundup_w = true;
2947 track->textures[i].roundup_h = true;
2948 if (track->separate_cube)
2949 for (face = 0; face < 5; face++) {
2950 track->textures[i].cube_info[face].robj = NULL;
2951 track->textures[i].cube_info[face].width = 16536;
2952 track->textures[i].cube_info[face].height = 16536;
2953 track->textures[i].cube_info[face].offset = 0;
2954 }
2955 }
2956}
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
new file mode 100644
index 00000000000..70a82eda394
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -0,0 +1,124 @@
1
2#define R100_TRACK_MAX_TEXTURE 3
3#define R200_TRACK_MAX_TEXTURE 6
4#define R300_TRACK_MAX_TEXTURE 16
5
6#define R100_MAX_CB 1
7#define R300_MAX_CB 4
8
9/*
10 * CS functions
11 */
12struct r100_cs_track_cb {
13 struct radeon_object *robj;
14 unsigned pitch;
15 unsigned cpp;
16 unsigned offset;
17};
18
19struct r100_cs_track_array {
20 struct radeon_object *robj;
21 unsigned esize;
22};
23
24struct r100_cs_cube_info {
25 struct radeon_object *robj;
26 unsigned offset;
27 unsigned width;
28 unsigned height;
29};
30
31struct r100_cs_track_texture {
32 struct radeon_object *robj;
33 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
34 unsigned pitch;
35 unsigned width;
36 unsigned height;
37 unsigned num_levels;
38 unsigned cpp;
39 unsigned tex_coord_type;
40 unsigned txdepth;
41 unsigned width_11;
42 unsigned height_11;
43 bool use_pitch;
44 bool enabled;
45 bool roundup_w;
46 bool roundup_h;
47};
48
49struct r100_cs_track_limits {
50 unsigned num_cb;
51 unsigned num_texture;
52 unsigned max_levels;
53};
54
55struct r100_cs_track {
56 struct radeon_device *rdev;
57 unsigned num_cb;
58 unsigned num_texture;
59 unsigned maxy;
60 unsigned vtx_size;
61 unsigned vap_vf_cntl;
62 unsigned immd_dwords;
63 unsigned num_arrays;
64 unsigned max_indx;
65 struct r100_cs_track_array arrays[11];
66 struct r100_cs_track_cb cb[R300_MAX_CB];
67 struct r100_cs_track_cb zb;
68 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
69 bool z_enabled;
70 bool separate_cube;
71
72};
73
74int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
75void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
76int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
77 struct radeon_cs_reloc **cs_reloc);
78void r100_cs_dump_packet(struct radeon_cs_parser *p,
79 struct radeon_cs_packet *pkt);
80
81int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
82
83int r200_packet0_check(struct radeon_cs_parser *p,
84 struct radeon_cs_packet *pkt,
85 unsigned idx, unsigned reg);
86
87static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
88 struct radeon_cs_packet *pkt,
89 unsigned idx,
90 unsigned reg)
91{
92 int r;
93 u32 tile_flags = 0;
94 u32 tmp;
95 struct radeon_cs_reloc *reloc;
96 struct radeon_cs_chunk *ib_chunk;
97
98 ib_chunk = &p->chunks[p->chunk_ib_idx];
99
100 r = r100_cs_packet_next_reloc(p, &reloc);
101 if (r) {
102 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
103 idx, reg);
104 r100_cs_dump_packet(p, pkt);
105 return r;
106 }
107 tmp = ib_chunk->kdata[idx] & 0x003fffff;
108 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
109
110 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
111 tile_flags |= RADEON_DST_TILE_MACRO;
112 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
113 if (reg == RADEON_SRC_PITCH_OFFSET) {
114 DRM_ERROR("Cannot src blit from microtiled surface\n");
115 r100_cs_dump_packet(p, pkt);
116 return -EINVAL;
117 }
118 tile_flags |= RADEON_DST_TILE_MICRO;
119 }
120
121 tmp |= tile_flags;
122 p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
123 return 0;
124}
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
new file mode 100644
index 00000000000..568c74bfba3
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -0,0 +1,456 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "drm.h"
30#include "radeon_drm.h"
31#include "radeon_reg.h"
32#include "radeon.h"
33
34#include "r200_reg_safe.h"
35
36#include "r100_track.h"
37
38static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
39{
40 int vtx_size, i;
41 vtx_size = 2;
42
43 if (vtx_fmt_0 & R200_VTX_Z0)
44 vtx_size++;
45 if (vtx_fmt_0 & R200_VTX_W0)
46 vtx_size++;
47 /* blend weight */
48 if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
49 vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
50 if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
51 vtx_size++;
52 if (vtx_fmt_0 & R200_VTX_N0)
53 vtx_size += 3;
54 if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
55 vtx_size++;
56 if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
57 vtx_size++;
58 if (vtx_fmt_0 & R200_VTX_SHININESS_0)
59 vtx_size++;
60 if (vtx_fmt_0 & R200_VTX_SHININESS_1)
61 vtx_size++;
62 for (i = 0; i < 8; i++) {
63 int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
64 switch (color_size) {
65 case 0: break;
66 case 1: vtx_size++; break;
67 case 2: vtx_size += 3; break;
68 case 3: vtx_size += 4; break;
69 }
70 }
71 if (vtx_fmt_0 & R200_VTX_XY1)
72 vtx_size += 2;
73 if (vtx_fmt_0 & R200_VTX_Z1)
74 vtx_size++;
75 if (vtx_fmt_0 & R200_VTX_W1)
76 vtx_size++;
77 if (vtx_fmt_0 & R200_VTX_N1)
78 vtx_size += 3;
79 return vtx_size;
80}
81
82static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
83{
84 int vtx_size, i, tex_size;
85 vtx_size = 0;
86 for (i = 0; i < 6; i++) {
87 tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
88 if (tex_size > 4)
89 continue;
90 vtx_size += tex_size;
91 }
92 return vtx_size;
93}
94
95int r200_packet0_check(struct radeon_cs_parser *p,
96 struct radeon_cs_packet *pkt,
97 unsigned idx, unsigned reg)
98{
99 struct radeon_cs_chunk *ib_chunk;
100 struct radeon_cs_reloc *reloc;
101 struct r100_cs_track *track;
102 volatile uint32_t *ib;
103 uint32_t tmp;
104 int r;
105 int i;
106 int face;
107 u32 tile_flags = 0;
108
109 ib = p->ib->ptr;
110 ib_chunk = &p->chunks[p->chunk_ib_idx];
111 track = (struct r100_cs_track *)p->track;
112
113 switch (reg) {
114 case RADEON_CRTC_GUI_TRIG_VLINE:
115 r = r100_cs_packet_parse_vline(p);
116 if (r) {
117 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
118 idx, reg);
119 r100_cs_dump_packet(p, pkt);
120 return r;
121 }
122 break;
123 /* FIXME: only allow PACKET3 blit? easier to check for out of
124 * range access */
125 case RADEON_DST_PITCH_OFFSET:
126 case RADEON_SRC_PITCH_OFFSET:
127 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
128 if (r)
129 return r;
130 break;
131 case RADEON_RB3D_DEPTHOFFSET:
132 r = r100_cs_packet_next_reloc(p, &reloc);
133 if (r) {
134 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
135 idx, reg);
136 r100_cs_dump_packet(p, pkt);
137 return r;
138 }
139 track->zb.robj = reloc->robj;
140 track->zb.offset = ib_chunk->kdata[idx];
141 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
142 break;
143 case RADEON_RB3D_COLOROFFSET:
144 r = r100_cs_packet_next_reloc(p, &reloc);
145 if (r) {
146 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
147 idx, reg);
148 r100_cs_dump_packet(p, pkt);
149 return r;
150 }
151 track->cb[0].robj = reloc->robj;
152 track->cb[0].offset = ib_chunk->kdata[idx];
153 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
154 break;
155 case R200_PP_TXOFFSET_0:
156 case R200_PP_TXOFFSET_1:
157 case R200_PP_TXOFFSET_2:
158 case R200_PP_TXOFFSET_3:
159 case R200_PP_TXOFFSET_4:
160 case R200_PP_TXOFFSET_5:
161 i = (reg - R200_PP_TXOFFSET_0) / 24;
162 r = r100_cs_packet_next_reloc(p, &reloc);
163 if (r) {
164 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
165 idx, reg);
166 r100_cs_dump_packet(p, pkt);
167 return r;
168 }
169 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
170 track->textures[i].robj = reloc->robj;
171 break;
172 case R200_PP_CUBIC_OFFSET_F1_0:
173 case R200_PP_CUBIC_OFFSET_F2_0:
174 case R200_PP_CUBIC_OFFSET_F3_0:
175 case R200_PP_CUBIC_OFFSET_F4_0:
176 case R200_PP_CUBIC_OFFSET_F5_0:
177 case R200_PP_CUBIC_OFFSET_F1_1:
178 case R200_PP_CUBIC_OFFSET_F2_1:
179 case R200_PP_CUBIC_OFFSET_F3_1:
180 case R200_PP_CUBIC_OFFSET_F4_1:
181 case R200_PP_CUBIC_OFFSET_F5_1:
182 case R200_PP_CUBIC_OFFSET_F1_2:
183 case R200_PP_CUBIC_OFFSET_F2_2:
184 case R200_PP_CUBIC_OFFSET_F3_2:
185 case R200_PP_CUBIC_OFFSET_F4_2:
186 case R200_PP_CUBIC_OFFSET_F5_2:
187 case R200_PP_CUBIC_OFFSET_F1_3:
188 case R200_PP_CUBIC_OFFSET_F2_3:
189 case R200_PP_CUBIC_OFFSET_F3_3:
190 case R200_PP_CUBIC_OFFSET_F4_3:
191 case R200_PP_CUBIC_OFFSET_F5_3:
192 case R200_PP_CUBIC_OFFSET_F1_4:
193 case R200_PP_CUBIC_OFFSET_F2_4:
194 case R200_PP_CUBIC_OFFSET_F3_4:
195 case R200_PP_CUBIC_OFFSET_F4_4:
196 case R200_PP_CUBIC_OFFSET_F5_4:
197 case R200_PP_CUBIC_OFFSET_F1_5:
198 case R200_PP_CUBIC_OFFSET_F2_5:
199 case R200_PP_CUBIC_OFFSET_F3_5:
200 case R200_PP_CUBIC_OFFSET_F4_5:
201 case R200_PP_CUBIC_OFFSET_F5_5:
202 i = (reg - R200_PP_TXOFFSET_0) / 24;
203 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
204 r = r100_cs_packet_next_reloc(p, &reloc);
205 if (r) {
206 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
207 idx, reg);
208 r100_cs_dump_packet(p, pkt);
209 return r;
210 }
211 track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx];
212 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
213 track->textures[i].cube_info[face - 1].robj = reloc->robj;
214 break;
215 case RADEON_RE_WIDTH_HEIGHT:
216 track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
217 break;
218 case RADEON_RB3D_COLORPITCH:
219 r = r100_cs_packet_next_reloc(p, &reloc);
220 if (r) {
221 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
222 idx, reg);
223 r100_cs_dump_packet(p, pkt);
224 return r;
225 }
226
227 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
228 tile_flags |= RADEON_COLOR_TILE_ENABLE;
229 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
230 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
231
232 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
233 tmp |= tile_flags;
234 ib[idx] = tmp;
235
236 track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
237 break;
238 case RADEON_RB3D_DEPTHPITCH:
239 track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
240 break;
241 case RADEON_RB3D_CNTL:
242 switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
243 case 7:
244 case 8:
245 case 9:
246 case 11:
247 case 12:
248 track->cb[0].cpp = 1;
249 break;
250 case 3:
251 case 4:
252 case 15:
253 track->cb[0].cpp = 2;
254 break;
255 case 6:
256 track->cb[0].cpp = 4;
257 break;
258 default:
259 DRM_ERROR("Invalid color buffer format (%d) !\n",
260 ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
261 return -EINVAL;
262 }
263 if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) {
264 DRM_ERROR("No support for depth xy offset in kms\n");
265 return -EINVAL;
266 }
267
268 track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
269 break;
270 case RADEON_RB3D_ZSTENCILCNTL:
271 switch (ib_chunk->kdata[idx] & 0xf) {
272 case 0:
273 track->zb.cpp = 2;
274 break;
275 case 2:
276 case 3:
277 case 4:
278 case 5:
279 case 9:
280 case 11:
281 track->zb.cpp = 4;
282 break;
283 default:
284 break;
285 }
286 break;
287 case RADEON_RB3D_ZPASS_ADDR:
288 r = r100_cs_packet_next_reloc(p, &reloc);
289 if (r) {
290 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
291 idx, reg);
292 r100_cs_dump_packet(p, pkt);
293 return r;
294 }
295 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
296 break;
297 case RADEON_PP_CNTL:
298 {
299 uint32_t temp = ib_chunk->kdata[idx] >> 4;
300 for (i = 0; i < track->num_texture; i++)
301 track->textures[i].enabled = !!(temp & (1 << i));
302 }
303 break;
304 case RADEON_SE_VF_CNTL:
305 track->vap_vf_cntl = ib_chunk->kdata[idx];
306 break;
307 case 0x210c:
308 /* VAP_VF_MAX_VTX_INDX */
309 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
310 break;
311 case R200_SE_VTX_FMT_0:
312 track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]);
313 break;
314 case R200_SE_VTX_FMT_1:
315 track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]);
316 break;
317 case R200_PP_TXSIZE_0:
318 case R200_PP_TXSIZE_1:
319 case R200_PP_TXSIZE_2:
320 case R200_PP_TXSIZE_3:
321 case R200_PP_TXSIZE_4:
322 case R200_PP_TXSIZE_5:
323 i = (reg - R200_PP_TXSIZE_0) / 32;
324 track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
325 track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
326 break;
327 case R200_PP_TXPITCH_0:
328 case R200_PP_TXPITCH_1:
329 case R200_PP_TXPITCH_2:
330 case R200_PP_TXPITCH_3:
331 case R200_PP_TXPITCH_4:
332 case R200_PP_TXPITCH_5:
333 i = (reg - R200_PP_TXPITCH_0) / 32;
334 track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
335 break;
336 case R200_PP_TXFILTER_0:
337 case R200_PP_TXFILTER_1:
338 case R200_PP_TXFILTER_2:
339 case R200_PP_TXFILTER_3:
340 case R200_PP_TXFILTER_4:
341 case R200_PP_TXFILTER_5:
342 i = (reg - R200_PP_TXFILTER_0) / 32;
343 track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK)
344 >> R200_MAX_MIP_LEVEL_SHIFT);
345 tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
346 if (tmp == 2 || tmp == 6)
347 track->textures[i].roundup_w = false;
348 tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
349 if (tmp == 2 || tmp == 6)
350 track->textures[i].roundup_h = false;
351 break;
352 case R200_PP_TXMULTI_CTL_0:
353 case R200_PP_TXMULTI_CTL_1:
354 case R200_PP_TXMULTI_CTL_2:
355 case R200_PP_TXMULTI_CTL_3:
356 case R200_PP_TXMULTI_CTL_4:
357 case R200_PP_TXMULTI_CTL_5:
358 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
359 break;
360 case R200_PP_TXFORMAT_X_0:
361 case R200_PP_TXFORMAT_X_1:
362 case R200_PP_TXFORMAT_X_2:
363 case R200_PP_TXFORMAT_X_3:
364 case R200_PP_TXFORMAT_X_4:
365 case R200_PP_TXFORMAT_X_5:
366 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
367 track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7;
368 tmp = (ib_chunk->kdata[idx] >> 16) & 0x3;
369 /* 2D, 3D, CUBE */
370 switch (tmp) {
371 case 0:
372 case 5:
373 case 6:
374 case 7:
375 track->textures[i].tex_coord_type = 0;
376 break;
377 case 1:
378 track->textures[i].tex_coord_type = 1;
379 break;
380 case 2:
381 track->textures[i].tex_coord_type = 2;
382 break;
383 }
384 break;
385 case R200_PP_TXFORMAT_0:
386 case R200_PP_TXFORMAT_1:
387 case R200_PP_TXFORMAT_2:
388 case R200_PP_TXFORMAT_3:
389 case R200_PP_TXFORMAT_4:
390 case R200_PP_TXFORMAT_5:
391 i = (reg - R200_PP_TXFORMAT_0) / 32;
392 if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) {
393 track->textures[i].use_pitch = 1;
394 } else {
395 track->textures[i].use_pitch = 0;
396 track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
397 track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
398 }
399 switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
400 case R200_TXFORMAT_I8:
401 case R200_TXFORMAT_RGB332:
402 case R200_TXFORMAT_Y8:
403 track->textures[i].cpp = 1;
404 break;
405 case R200_TXFORMAT_DXT1:
406 case R200_TXFORMAT_AI88:
407 case R200_TXFORMAT_ARGB1555:
408 case R200_TXFORMAT_RGB565:
409 case R200_TXFORMAT_ARGB4444:
410 case R200_TXFORMAT_VYUY422:
411 case R200_TXFORMAT_YVYU422:
412 case R200_TXFORMAT_LDVDU655:
413 case R200_TXFORMAT_DVDU88:
414 case R200_TXFORMAT_AVYU4444:
415 track->textures[i].cpp = 2;
416 break;
417 case R200_TXFORMAT_ARGB8888:
418 case R200_TXFORMAT_RGBA8888:
419 case R200_TXFORMAT_ABGR8888:
420 case R200_TXFORMAT_BGR111110:
421 case R200_TXFORMAT_LDVDU8888:
422 case R200_TXFORMAT_DXT23:
423 case R200_TXFORMAT_DXT45:
424 track->textures[i].cpp = 4;
425 break;
426 }
427 track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
428 track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
429 break;
430 case R200_PP_CUBIC_FACES_0:
431 case R200_PP_CUBIC_FACES_1:
432 case R200_PP_CUBIC_FACES_2:
433 case R200_PP_CUBIC_FACES_3:
434 case R200_PP_CUBIC_FACES_4:
435 case R200_PP_CUBIC_FACES_5:
436 tmp = ib_chunk->kdata[idx];
437 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
438 for (face = 0; face < 4; face++) {
439 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
440 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
441 }
442 break;
443 default:
444 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
445 reg, idx);
446 return -EINVAL;
447 }
448 return 0;
449}
450
451int r200_init(struct radeon_device *rdev)
452{
453 rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
454 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
455 return 0;
456}
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 9f2460cf9db..33a2c557eac 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -32,6 +32,7 @@
32#include "radeon.h" 32#include "radeon.h"
33#include "radeon_drm.h" 33#include "radeon_drm.h"
34#include "radeon_share.h" 34#include "radeon_share.h"
35#include "r100_track.h"
35 36
36#include "r300_reg_safe.h" 37#include "r300_reg_safe.h"
37 38
@@ -49,14 +50,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p,
49 struct radeon_cs_packet *pkt, 50 struct radeon_cs_packet *pkt,
50 unsigned idx); 51 unsigned idx);
51int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 52int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
52int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
53 struct radeon_cs_reloc **cs_reloc);
54int r100_cs_parse_packet0(struct radeon_cs_parser *p, 53int r100_cs_parse_packet0(struct radeon_cs_parser *p,
55 struct radeon_cs_packet *pkt, 54 struct radeon_cs_packet *pkt,
56 const unsigned *auth, unsigned n, 55 const unsigned *auth, unsigned n,
57 radeon_packet0_check_t check); 56 radeon_packet0_check_t check);
58void r100_cs_dump_packet(struct radeon_cs_parser *p,
59 struct radeon_cs_packet *pkt);
60int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 57int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
61 struct radeon_cs_packet *pkt, 58 struct radeon_cs_packet *pkt,
62 struct radeon_object *robj); 59 struct radeon_object *robj);
@@ -706,264 +703,13 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
706/* 703/*
707 * CS functions 704 * CS functions
708 */ 705 */
709struct r300_cs_track_cb {
710 struct radeon_object *robj;
711 unsigned pitch;
712 unsigned cpp;
713 unsigned offset;
714};
715
716struct r300_cs_track_array {
717 struct radeon_object *robj;
718 unsigned esize;
719};
720
721struct r300_cs_track_texture {
722 struct radeon_object *robj;
723 unsigned pitch;
724 unsigned width;
725 unsigned height;
726 unsigned num_levels;
727 unsigned cpp;
728 unsigned tex_coord_type;
729 unsigned txdepth;
730 unsigned width_11;
731 unsigned height_11;
732 bool use_pitch;
733 bool enabled;
734 bool roundup_w;
735 bool roundup_h;
736};
737
738struct r300_cs_track {
739 unsigned num_cb;
740 unsigned maxy;
741 unsigned vtx_size;
742 unsigned vap_vf_cntl;
743 unsigned immd_dwords;
744 unsigned num_arrays;
745 unsigned max_indx;
746 struct r300_cs_track_array arrays[11];
747 struct r300_cs_track_cb cb[4];
748 struct r300_cs_track_cb zb;
749 struct r300_cs_track_texture textures[16];
750 bool z_enabled;
751};
752
753static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
754{
755 DRM_ERROR("pitch %d\n", t->pitch);
756 DRM_ERROR("width %d\n", t->width);
757 DRM_ERROR("height %d\n", t->height);
758 DRM_ERROR("num levels %d\n", t->num_levels);
759 DRM_ERROR("depth %d\n", t->txdepth);
760 DRM_ERROR("bpp %d\n", t->cpp);
761 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
762 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
763 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
764}
765
766static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
767 struct r300_cs_track *track)
768{
769 struct radeon_object *robj;
770 unsigned long size;
771 unsigned u, i, w, h;
772
773 for (u = 0; u < 16; u++) {
774 if (!track->textures[u].enabled)
775 continue;
776 robj = track->textures[u].robj;
777 if (robj == NULL) {
778 DRM_ERROR("No texture bound to unit %u\n", u);
779 return -EINVAL;
780 }
781 size = 0;
782 for (i = 0; i <= track->textures[u].num_levels; i++) {
783 if (track->textures[u].use_pitch) {
784 w = track->textures[u].pitch / (1 << i);
785 } else {
786 w = track->textures[u].width / (1 << i);
787 if (rdev->family >= CHIP_RV515)
788 w |= track->textures[u].width_11;
789 if (track->textures[u].roundup_w)
790 w = roundup_pow_of_two(w);
791 }
792 h = track->textures[u].height / (1 << i);
793 if (rdev->family >= CHIP_RV515)
794 h |= track->textures[u].height_11;
795 if (track->textures[u].roundup_h)
796 h = roundup_pow_of_two(h);
797 size += w * h;
798 }
799 size *= track->textures[u].cpp;
800 switch (track->textures[u].tex_coord_type) {
801 case 0:
802 break;
803 case 1:
804 size *= (1 << track->textures[u].txdepth);
805 break;
806 case 2:
807 size *= 6;
808 break;
809 default:
810 DRM_ERROR("Invalid texture coordinate type %u for unit "
811 "%u\n", track->textures[u].tex_coord_type, u);
812 return -EINVAL;
813 }
814 if (size > radeon_object_size(robj)) {
815 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
816 "%lu\n", u, size, radeon_object_size(robj));
817 r300_cs_track_texture_print(&track->textures[u]);
818 return -EINVAL;
819 }
820 }
821 return 0;
822}
823
824int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
825{
826 unsigned i;
827 unsigned long size;
828 unsigned prim_walk;
829 unsigned nverts;
830
831 for (i = 0; i < track->num_cb; i++) {
832 if (track->cb[i].robj == NULL) {
833 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
834 return -EINVAL;
835 }
836 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
837 size += track->cb[i].offset;
838 if (size > radeon_object_size(track->cb[i].robj)) {
839 DRM_ERROR("[drm] Buffer too small for color buffer %d "
840 "(need %lu have %lu) !\n", i, size,
841 radeon_object_size(track->cb[i].robj));
842 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
843 i, track->cb[i].pitch, track->cb[i].cpp,
844 track->cb[i].offset, track->maxy);
845 return -EINVAL;
846 }
847 }
848 if (track->z_enabled) {
849 if (track->zb.robj == NULL) {
850 DRM_ERROR("[drm] No buffer for z buffer !\n");
851 return -EINVAL;
852 }
853 size = track->zb.pitch * track->zb.cpp * track->maxy;
854 size += track->zb.offset;
855 if (size > radeon_object_size(track->zb.robj)) {
856 DRM_ERROR("[drm] Buffer too small for z buffer "
857 "(need %lu have %lu) !\n", size,
858 radeon_object_size(track->zb.robj));
859 return -EINVAL;
860 }
861 }
862 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
863 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
864 switch (prim_walk) {
865 case 1:
866 for (i = 0; i < track->num_arrays; i++) {
867 size = track->arrays[i].esize * track->max_indx * 4;
868 if (track->arrays[i].robj == NULL) {
869 DRM_ERROR("(PW %u) Vertex array %u no buffer "
870 "bound\n", prim_walk, i);
871 return -EINVAL;
872 }
873 if (size > radeon_object_size(track->arrays[i].robj)) {
874 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
875 "have %lu dwords\n", prim_walk, i,
876 size >> 2,
877 radeon_object_size(track->arrays[i].robj) >> 2);
878 DRM_ERROR("Max indices %u\n", track->max_indx);
879 return -EINVAL;
880 }
881 }
882 break;
883 case 2:
884 for (i = 0; i < track->num_arrays; i++) {
885 size = track->arrays[i].esize * (nverts - 1) * 4;
886 if (track->arrays[i].robj == NULL) {
887 DRM_ERROR("(PW %u) Vertex array %u no buffer "
888 "bound\n", prim_walk, i);
889 return -EINVAL;
890 }
891 if (size > radeon_object_size(track->arrays[i].robj)) {
892 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
893 "have %lu dwords\n", prim_walk, i, size >> 2,
894 radeon_object_size(track->arrays[i].robj) >> 2);
895 return -EINVAL;
896 }
897 }
898 break;
899 case 3:
900 size = track->vtx_size * nverts;
901 if (size != track->immd_dwords) {
902 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
903 track->immd_dwords, size);
904 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
905 nverts, track->vtx_size);
906 return -EINVAL;
907 }
908 break;
909 default:
910 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
911 prim_walk);
912 return -EINVAL;
913 }
914 return r300_cs_track_texture_check(rdev, track);
915}
916
917static inline void r300_cs_track_clear(struct r300_cs_track *track)
918{
919 unsigned i;
920
921 track->num_cb = 4;
922 track->maxy = 4096;
923 for (i = 0; i < track->num_cb; i++) {
924 track->cb[i].robj = NULL;
925 track->cb[i].pitch = 8192;
926 track->cb[i].cpp = 16;
927 track->cb[i].offset = 0;
928 }
929 track->z_enabled = true;
930 track->zb.robj = NULL;
931 track->zb.pitch = 8192;
932 track->zb.cpp = 4;
933 track->zb.offset = 0;
934 track->vtx_size = 0x7F;
935 track->immd_dwords = 0xFFFFFFFFUL;
936 track->num_arrays = 11;
937 track->max_indx = 0x00FFFFFFUL;
938 for (i = 0; i < track->num_arrays; i++) {
939 track->arrays[i].robj = NULL;
940 track->arrays[i].esize = 0x7F;
941 }
942 for (i = 0; i < 16; i++) {
943 track->textures[i].pitch = 16536;
944 track->textures[i].width = 16536;
945 track->textures[i].height = 16536;
946 track->textures[i].width_11 = 1 << 11;
947 track->textures[i].height_11 = 1 << 11;
948 track->textures[i].num_levels = 12;
949 track->textures[i].txdepth = 16;
950 track->textures[i].cpp = 64;
951 track->textures[i].tex_coord_type = 1;
952 track->textures[i].robj = NULL;
953 /* CS IB emission code makes sure texture unit are disabled */
954 track->textures[i].enabled = false;
955 track->textures[i].roundup_w = true;
956 track->textures[i].roundup_h = true;
957 }
958}
959
960static int r300_packet0_check(struct radeon_cs_parser *p, 706static int r300_packet0_check(struct radeon_cs_parser *p,
961 struct radeon_cs_packet *pkt, 707 struct radeon_cs_packet *pkt,
962 unsigned idx, unsigned reg) 708 unsigned idx, unsigned reg)
963{ 709{
964 struct radeon_cs_chunk *ib_chunk; 710 struct radeon_cs_chunk *ib_chunk;
965 struct radeon_cs_reloc *reloc; 711 struct radeon_cs_reloc *reloc;
966 struct r300_cs_track *track; 712 struct r100_cs_track *track;
967 volatile uint32_t *ib; 713 volatile uint32_t *ib;
968 uint32_t tmp, tile_flags = 0; 714 uint32_t tmp, tile_flags = 0;
969 unsigned i; 715 unsigned i;
@@ -971,7 +717,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
971 717
972 ib = p->ib->ptr; 718 ib = p->ib->ptr;
973 ib_chunk = &p->chunks[p->chunk_ib_idx]; 719 ib_chunk = &p->chunks[p->chunk_ib_idx];
974 track = (struct r300_cs_track*)p->track; 720 track = (struct r100_cs_track *)p->track;
975 switch(reg) { 721 switch(reg) {
976 case AVIVO_D1MODE_VLINE_START_END: 722 case AVIVO_D1MODE_VLINE_START_END:
977 case RADEON_CRTC_GUI_TRIG_VLINE: 723 case RADEON_CRTC_GUI_TRIG_VLINE:
@@ -985,28 +731,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
985 break; 731 break;
986 case RADEON_DST_PITCH_OFFSET: 732 case RADEON_DST_PITCH_OFFSET:
987 case RADEON_SRC_PITCH_OFFSET: 733 case RADEON_SRC_PITCH_OFFSET:
988 r = r100_cs_packet_next_reloc(p, &reloc); 734 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
989 if (r) { 735 if (r)
990 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
991 idx, reg);
992 r100_cs_dump_packet(p, pkt);
993 return r; 736 return r;
994 }
995 tmp = ib_chunk->kdata[idx] & 0x003fffff;
996 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
997
998 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
999 tile_flags |= RADEON_DST_TILE_MACRO;
1000 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1001 if (reg == RADEON_SRC_PITCH_OFFSET) {
1002 DRM_ERROR("Cannot src blit from microtiled surface\n");
1003 r100_cs_dump_packet(p, pkt);
1004 return -EINVAL;
1005 }
1006 tile_flags |= RADEON_DST_TILE_MICRO;
1007 }
1008 tmp |= tile_flags;
1009 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
1010 break; 737 break;
1011 case R300_RB3D_COLOROFFSET0: 738 case R300_RB3D_COLOROFFSET0:
1012 case R300_RB3D_COLOROFFSET1: 739 case R300_RB3D_COLOROFFSET1:
@@ -1215,42 +942,41 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1215 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; 942 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
1216 track->textures[i].tex_coord_type = tmp; 943 track->textures[i].tex_coord_type = tmp;
1217 switch ((ib_chunk->kdata[idx] & 0x1F)) { 944 switch ((ib_chunk->kdata[idx] & 0x1F)) {
1218 case 0: 945 case R300_TX_FORMAT_X8:
1219 case 2: 946 case R300_TX_FORMAT_Y4X4:
1220 case 5: 947 case R300_TX_FORMAT_Z3Y3X2:
1221 case 18:
1222 case 20:
1223 case 21:
1224 track->textures[i].cpp = 1; 948 track->textures[i].cpp = 1;
1225 break; 949 break;
1226 case 1: 950 case R300_TX_FORMAT_X16:
1227 case 3: 951 case R300_TX_FORMAT_Y8X8:
1228 case 6: 952 case R300_TX_FORMAT_Z5Y6X5:
1229 case 7: 953 case R300_TX_FORMAT_Z6Y5X5:
1230 case 10: 954 case R300_TX_FORMAT_W4Z4Y4X4:
1231 case 11: 955 case R300_TX_FORMAT_W1Z5Y5X5:
1232 case 19: 956 case R300_TX_FORMAT_DXT1:
1233 case 22: 957 case R300_TX_FORMAT_D3DMFT_CxV8U8:
1234 case 24: 958 case R300_TX_FORMAT_B8G8_B8G8:
959 case R300_TX_FORMAT_G8R8_G8B8:
1235 track->textures[i].cpp = 2; 960 track->textures[i].cpp = 2;
1236 break; 961 break;
1237 case 4: 962 case R300_TX_FORMAT_Y16X16:
1238 case 8: 963 case R300_TX_FORMAT_Z11Y11X10:
1239 case 9: 964 case R300_TX_FORMAT_Z10Y11X11:
1240 case 12: 965 case R300_TX_FORMAT_W8Z8Y8X8:
1241 case 13: 966 case R300_TX_FORMAT_W2Z10Y10X10:
1242 case 23: 967 case 0x17:
1243 case 25: 968 case R300_TX_FORMAT_FL_I32:
1244 case 27: 969 case 0x1e:
1245 case 30: 970 case R300_TX_FORMAT_DXT3:
971 case R300_TX_FORMAT_DXT5:
1246 track->textures[i].cpp = 4; 972 track->textures[i].cpp = 4;
1247 break; 973 break;
1248 case 14: 974 case R300_TX_FORMAT_W16Z16Y16X16:
1249 case 26: 975 case R300_TX_FORMAT_FL_R16G16B16A16:
1250 case 28: 976 case R300_TX_FORMAT_FL_I32A32:
1251 track->textures[i].cpp = 8; 977 track->textures[i].cpp = 8;
1252 break; 978 break;
1253 case 29: 979 case R300_TX_FORMAT_FL_R32G32B32A32:
1254 track->textures[i].cpp = 16; 980 track->textures[i].cpp = 16;
1255 break; 981 break;
1256 default: 982 default:
@@ -1278,11 +1004,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1278 case 0x443C: 1004 case 0x443C:
1279 /* TX_FILTER0_[0-15] */ 1005 /* TX_FILTER0_[0-15] */
1280 i = (reg - 0x4400) >> 2; 1006 i = (reg - 0x4400) >> 2;
1281 tmp = ib_chunk->kdata[idx] & 0x7;; 1007 tmp = ib_chunk->kdata[idx] & 0x7;
1282 if (tmp == 2 || tmp == 4 || tmp == 6) { 1008 if (tmp == 2 || tmp == 4 || tmp == 6) {
1283 track->textures[i].roundup_w = false; 1009 track->textures[i].roundup_w = false;
1284 } 1010 }
1285 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; 1011 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;
1286 if (tmp == 2 || tmp == 4 || tmp == 6) { 1012 if (tmp == 2 || tmp == 4 || tmp == 6) {
1287 track->textures[i].roundup_h = false; 1013 track->textures[i].roundup_h = false;
1288 } 1014 }
@@ -1370,8 +1096,9 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1370 struct radeon_cs_packet *pkt) 1096 struct radeon_cs_packet *pkt)
1371{ 1097{
1372 struct radeon_cs_chunk *ib_chunk; 1098 struct radeon_cs_chunk *ib_chunk;
1099
1373 struct radeon_cs_reloc *reloc; 1100 struct radeon_cs_reloc *reloc;
1374 struct r300_cs_track *track; 1101 struct r100_cs_track *track;
1375 volatile uint32_t *ib; 1102 volatile uint32_t *ib;
1376 unsigned idx; 1103 unsigned idx;
1377 unsigned i, c; 1104 unsigned i, c;
@@ -1380,7 +1107,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1380 ib = p->ib->ptr; 1107 ib = p->ib->ptr;
1381 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1108 ib_chunk = &p->chunks[p->chunk_ib_idx];
1382 idx = pkt->idx + 1; 1109 idx = pkt->idx + 1;
1383 track = (struct r300_cs_track*)p->track; 1110 track = (struct r100_cs_track *)p->track;
1384 switch(pkt->opcode) { 1111 switch(pkt->opcode) {
1385 case PACKET3_3D_LOAD_VBPNTR: 1112 case PACKET3_3D_LOAD_VBPNTR:
1386 c = ib_chunk->kdata[idx++] & 0x1F; 1113 c = ib_chunk->kdata[idx++] & 0x1F;
@@ -1447,7 +1174,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1447 } 1174 }
1448 track->vap_vf_cntl = ib_chunk->kdata[idx+1]; 1175 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1449 track->immd_dwords = pkt->count - 1; 1176 track->immd_dwords = pkt->count - 1;
1450 r = r300_cs_track_check(p->rdev, track); 1177 r = r100_cs_track_check(p->rdev, track);
1451 if (r) { 1178 if (r) {
1452 return r; 1179 return r;
1453 } 1180 }
@@ -1462,35 +1189,35 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1462 } 1189 }
1463 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1190 track->vap_vf_cntl = ib_chunk->kdata[idx];
1464 track->immd_dwords = pkt->count; 1191 track->immd_dwords = pkt->count;
1465 r = r300_cs_track_check(p->rdev, track); 1192 r = r100_cs_track_check(p->rdev, track);
1466 if (r) { 1193 if (r) {
1467 return r; 1194 return r;
1468 } 1195 }
1469 break; 1196 break;
1470 case PACKET3_3D_DRAW_VBUF: 1197 case PACKET3_3D_DRAW_VBUF:
1471 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1198 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1472 r = r300_cs_track_check(p->rdev, track); 1199 r = r100_cs_track_check(p->rdev, track);
1473 if (r) { 1200 if (r) {
1474 return r; 1201 return r;
1475 } 1202 }
1476 break; 1203 break;
1477 case PACKET3_3D_DRAW_VBUF_2: 1204 case PACKET3_3D_DRAW_VBUF_2:
1478 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1205 track->vap_vf_cntl = ib_chunk->kdata[idx];
1479 r = r300_cs_track_check(p->rdev, track); 1206 r = r100_cs_track_check(p->rdev, track);
1480 if (r) { 1207 if (r) {
1481 return r; 1208 return r;
1482 } 1209 }
1483 break; 1210 break;
1484 case PACKET3_3D_DRAW_INDX: 1211 case PACKET3_3D_DRAW_INDX:
1485 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1212 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1486 r = r300_cs_track_check(p->rdev, track); 1213 r = r100_cs_track_check(p->rdev, track);
1487 if (r) { 1214 if (r) {
1488 return r; 1215 return r;
1489 } 1216 }
1490 break; 1217 break;
1491 case PACKET3_3D_DRAW_INDX_2: 1218 case PACKET3_3D_DRAW_INDX_2:
1492 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1219 track->vap_vf_cntl = ib_chunk->kdata[idx];
1493 r = r300_cs_track_check(p->rdev, track); 1220 r = r100_cs_track_check(p->rdev, track);
1494 if (r) { 1221 if (r) {
1495 return r; 1222 return r;
1496 } 1223 }
@@ -1507,10 +1234,10 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1507int r300_cs_parse(struct radeon_cs_parser *p) 1234int r300_cs_parse(struct radeon_cs_parser *p)
1508{ 1235{
1509 struct radeon_cs_packet pkt; 1236 struct radeon_cs_packet pkt;
1510 struct r300_cs_track track; 1237 struct r100_cs_track track;
1511 int r; 1238 int r;
1512 1239
1513 r300_cs_track_clear(&track); 1240 r100_cs_track_clear(p->rdev, &track);
1514 p->track = &track; 1241 p->track = &track;
1515 do { 1242 do {
1516 r = r100_cs_packet_parse(p, &pkt, p->idx); 1243 r = r100_cs_packet_parse(p, &pkt, p->idx);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 149974d13aa..6c35c3c2919 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -604,8 +604,14 @@ struct radeon_asic {
604 void (*bandwidth_update)(struct radeon_device *rdev); 604 void (*bandwidth_update)(struct radeon_device *rdev);
605}; 605};
606 606
607struct r100_asic {
608 const unsigned *reg_safe_bm;
609 unsigned reg_safe_bm_size;
610};
611
607union radeon_asic_config { 612union radeon_asic_config {
608 struct r300_asic r300; 613 struct r300_asic r300;
614 struct r100_asic r100;
609}; 615};
610 616
611 617
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 8ace15156c4..c9cbd8ae1f9 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -42,6 +42,7 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43 */ 43 */
44int r100_init(struct radeon_device *rdev); 44int r100_init(struct radeon_device *rdev);
45int r200_init(struct radeon_device *rdev);
45uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 46uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
46void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 47void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
47void r100_errata(struct radeon_device *rdev); 48void r100_errata(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 4df43f62c67..404b39bf343 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -1945,6 +1945,11 @@
1945# define RADEON_TXFORMAT_DXT1 (12 << 0) 1945# define RADEON_TXFORMAT_DXT1 (12 << 0)
1946# define RADEON_TXFORMAT_DXT23 (14 << 0) 1946# define RADEON_TXFORMAT_DXT23 (14 << 0)
1947# define RADEON_TXFORMAT_DXT45 (15 << 0) 1947# define RADEON_TXFORMAT_DXT45 (15 << 0)
1948# define RADEON_TXFORMAT_SHADOW16 (16 << 0)
1949# define RADEON_TXFORMAT_SHADOW32 (17 << 0)
1950# define RADEON_TXFORMAT_DUDV88 (18 << 0)
1951# define RADEON_TXFORMAT_LDUDV655 (19 << 0)
1952# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)
1948# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) 1953# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
1949# define RADEON_TXFORMAT_FORMAT_SHIFT 0 1954# define RADEON_TXFORMAT_FORMAT_SHIFT 0
1950# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) 1955# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
@@ -2203,7 +2208,7 @@
2203# define RADEON_ROP_ENABLE (1 << 6) 2208# define RADEON_ROP_ENABLE (1 << 6)
2204# define RADEON_STENCIL_ENABLE (1 << 7) 2209# define RADEON_STENCIL_ENABLE (1 << 7)
2205# define RADEON_Z_ENABLE (1 << 8) 2210# define RADEON_Z_ENABLE (1 << 8)
2206# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 2211# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)
2207# define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 2212# define RADEON_RB3D_COLOR_FORMAT_SHIFT 10
2208 2213
2209# define RADEON_COLOR_FORMAT_ARGB1555 3 2214# define RADEON_COLOR_FORMAT_ARGB1555 3
@@ -2773,7 +2778,12 @@
2773# define R200_TXFORMAT_DXT1 (12 << 0) 2778# define R200_TXFORMAT_DXT1 (12 << 0)
2774# define R200_TXFORMAT_DXT23 (14 << 0) 2779# define R200_TXFORMAT_DXT23 (14 << 0)
2775# define R200_TXFORMAT_DXT45 (15 << 0) 2780# define R200_TXFORMAT_DXT45 (15 << 0)
2781# define R200_TXFORMAT_DVDU88 (18 << 0)
2782# define R200_TXFORMAT_LDVDU655 (19 << 0)
2783# define R200_TXFORMAT_LDVDU8888 (20 << 0)
2784# define R200_TXFORMAT_GR1616 (21 << 0)
2776# define R200_TXFORMAT_ABGR8888 (22 << 0) 2785# define R200_TXFORMAT_ABGR8888 (22 << 0)
2786# define R200_TXFORMAT_BGR111110 (23 << 0)
2777# define R200_TXFORMAT_FORMAT_MASK (31 << 0) 2787# define R200_TXFORMAT_FORMAT_MASK (31 << 0)
2778# define R200_TXFORMAT_FORMAT_SHIFT 0 2788# define R200_TXFORMAT_FORMAT_SHIFT 0
2779# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) 2789# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)
@@ -2818,6 +2828,13 @@
2818#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ 2828#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */
2819#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ 2829#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */
2820 2830
2831#define R200_PP_CUBIC_FACES_0 0x2c18
2832#define R200_PP_CUBIC_FACES_1 0x2c38
2833#define R200_PP_CUBIC_FACES_2 0x2c58
2834#define R200_PP_CUBIC_FACES_3 0x2c78
2835#define R200_PP_CUBIC_FACES_4 0x2c98
2836#define R200_PP_CUBIC_FACES_5 0x2cb8
2837
2821#define R200_PP_TXOFFSET_0 0x2d00 2838#define R200_PP_TXOFFSET_0 0x2d00
2822# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) 2839# define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
2823# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) 2840# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
@@ -2829,11 +2846,44 @@
2829# define R200_TXO_MICRO_TILE (1 << 3) 2846# define R200_TXO_MICRO_TILE (1 << 3)
2830# define R200_TXO_OFFSET_MASK 0xffffffe0 2847# define R200_TXO_OFFSET_MASK 0xffffffe0
2831# define R200_TXO_OFFSET_SHIFT 5 2848# define R200_TXO_OFFSET_SHIFT 5
2849#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
2850#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
2851#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
2852#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
2853#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
2854
2832#define R200_PP_TXOFFSET_1 0x2d18 2855#define R200_PP_TXOFFSET_1 0x2d18
2856#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
2857#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
2858#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
2859#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
2860#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
2861
2833#define R200_PP_TXOFFSET_2 0x2d30 2862#define R200_PP_TXOFFSET_2 0x2d30
2863#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
2864#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
2865#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
2866#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
2867#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
2868
2834#define R200_PP_TXOFFSET_3 0x2d48 2869#define R200_PP_TXOFFSET_3 0x2d48
2870#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
2871#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
2872#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
2873#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
2874#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
2835#define R200_PP_TXOFFSET_4 0x2d60 2875#define R200_PP_TXOFFSET_4 0x2d60
2876#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
2877#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
2878#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
2879#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
2880#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
2836#define R200_PP_TXOFFSET_5 0x2d78 2881#define R200_PP_TXOFFSET_5 0x2d78
2882#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
2883#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
2884#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
2885#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
2886#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
2837 2887
2838#define R200_PP_TFACTOR_0 0x2ee0 2888#define R200_PP_TFACTOR_0 0x2ee0
2839#define R200_PP_TFACTOR_1 0x2ee4 2889#define R200_PP_TFACTOR_1 0x2ee4
@@ -3175,6 +3225,11 @@
3175# define R200_FORCE_INORDER_PROC (1<<31) 3225# define R200_FORCE_INORDER_PROC (1<<31)
3176#define R200_PP_CNTL_X 0x2cc4 3226#define R200_PP_CNTL_X 0x2cc4
3177#define R200_PP_TXMULTI_CTL_0 0x2c1c 3227#define R200_PP_TXMULTI_CTL_0 0x2c1c
3228#define R200_PP_TXMULTI_CTL_1 0x2c3c
3229#define R200_PP_TXMULTI_CTL_2 0x2c5c
3230#define R200_PP_TXMULTI_CTL_3 0x2c7c
3231#define R200_PP_TXMULTI_CTL_4 0x2c9c
3232#define R200_PP_TXMULTI_CTL_5 0x2cbc
3178#define R200_SE_VTX_STATE_CNTL 0x2180 3233#define R200_SE_VTX_STATE_CNTL 0x2180
3179# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) 3234# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
3180 3235
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r100 b/drivers/gpu/drm/radeon/reg_srcs/r100
new file mode 100644
index 00000000000..f7ee062f118
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r100
@@ -0,0 +1,105 @@
1r100 0x3294
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1810 FOG_3D_TABLE_START
320x1814 FOG_3D_TABLE_END
330x1a14 FOG_TABLE_INDEX
340x1a18 FOG_TABLE_DATA
350x1c14 PP_MISC
360x1c18 PP_FOG_COLOR
370x1c1c RE_SOLID_COLOR
380x1c20 RB3D_BLENDCNTL
390x1c4c SE_CNTL
400x1c50 SE_COORD_FMT
410x1c60 PP_TXCBLEND_0
420x1c64 PP_TXABLEND_0
430x1c68 PP_TFACTOR_0
440x1c78 PP_TXCBLEND_1
450x1c7c PP_TXABLEND_1
460x1c80 PP_TFACTOR_1
470x1c90 PP_TXCBLEND_2
480x1c94 PP_TXABLEND_2
490x1c98 PP_TFACTOR_2
500x1cc8 RE_STIPPLE_ADDR
510x1ccc RE_STIPPLE_DATA
520x1cd0 RE_LINE_PATTERN
530x1cd4 RE_LINE_STATE
540x1d40 PP_BORDER_COLOR0
550x1d44 PP_BORDER_COLOR1
560x1d48 PP_BORDER_COLOR2
570x1d7c RB3D_STENCILREFMASK
580x1d80 RB3D_ROPCNTL
590x1d84 RB3D_PLANEMASK
600x1d98 VAP_VPORT_XSCALE
610x1d9C VAP_VPORT_XOFFSET
620x1da0 VAP_VPORT_YSCALE
630x1da4 VAP_VPORT_YOFFSET
640x1da8 VAP_VPORT_ZSCALE
650x1dac VAP_VPORT_ZOFFSET
660x1db0 SE_ZBIAS_FACTOR
670x1db4 SE_ZBIAS_CONSTANT
680x1db8 SE_LINE_WIDTH
690x2140 SE_CNTL_STATUS
700x2200 SE_TCL_VECTOR_INDX_REG
710x2204 SE_TCL_VECTOR_DATA_REG
720x2208 SE_TCL_SCALAR_INDX_REG
730x220c SE_TCL_SCALAR_DATA_REG
740x2210 SE_TCL_MATERIAL_EMISSIVE_RED
750x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN
760x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE
770x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA
780x2220 SE_TCL_MATERIAL_AMBIENT_RED
790x2224 SE_TCL_MATERIAL_AMBIENT_GREEN
800x2228 SE_TCL_MATERIAL_AMBIENT_BLUE
810x222c SE_TCL_MATERIAL_AMBIENT_ALPHA
820x2230 SE_TCL_MATERIAL_DIFFUSE_RED
830x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN
840x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE
850x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA
860x2240 SE_TCL_MATERIAL_SPECULAR_RED
870x2244 SE_TCL_MATERIAL_SPECULAR_GREEN
880x2248 SE_TCL_MATERIAL_SPECULAR_BLUE
890x224c SE_TCL_MATERIAL_SPECULAR_ALPHA
900x2250 SE_TCL_SHININESS
910x2254 SE_TCL_OUTPUT_VTX_FMT
920x2258 SE_TCL_OUTPUT_VTX_SEL
930x225c SE_TCL_MATRIX_SELECT_0
940x2260 SE_TCL_MATRIX_SELECT_1
950x2264 SE_TCL_UCP_VERT_BLEND_CNTL
960x2268 SE_TCL_TEXTURE_PROC_CTL
970x226c SE_TCL_LIGHT_MODEL_CTL
980x2270 SE_TCL_PER_LIGHT_CTL_0
990x2274 SE_TCL_PER_LIGHT_CTL_1
1000x2278 SE_TCL_PER_LIGHT_CTL_2
1010x227c SE_TCL_PER_LIGHT_CTL_3
1020x2284 SE_TCL_STATE_FLUSH
1030x26c0 RE_TOP_LEFT
1040x26c4 RE_MISC
1050x3290 RB3D_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
new file mode 100644
index 00000000000..6021c8849a1
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -0,0 +1,184 @@
1r200 0x3294
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1c14 PP_MISC
320x1c18 PP_FOG_COLOR
330x1c1c RE_SOLID_COLOR
340x1c20 RB3D_BLENDCNTL
350x1c4c SE_CNTL
360x1c50 RE_CNTL
370x1cc8 RE_STIPPLE_ADDR
380x1ccc RE_STIPPLE_DATA
390x1cd0 RE_LINE_PATTERN
400x1cd4 RE_LINE_STATE
410x1cd8 RE_SCISSOR_TL_0
420x1cdc RE_SCISSOR_BR_0
430x1ce0 RE_SCISSOR_TL_1
440x1ce4 RE_SCISSOR_BR_1
450x1ce8 RE_SCISSOR_TL_2
460x1cec RE_SCISSOR_BR_2
470x1d60 RB3D_DEPTHXY_OFFSET
480x1d7c RB3D_STENCILREFMASK
490x1d80 RB3D_ROPCNTL
500x1d84 RB3D_PLANEMASK
510x1d98 VAP_VPORT_XSCALE
520x1d9c VAP_VPORT_XOFFSET
530x1da0 VAP_VPORT_YSCALE
540x1da4 VAP_VPORT_YOFFSET
550x1da8 VAP_VPORT_ZSCALE
560x1dac VAP_VPORT_ZOFFSET
570x1db0 SE_ZBIAS_FACTOR
580x1db4 SE_ZBIAS_CONSTANT
590x1db8 SE_LINE_WIDTH
600x2080 SE_VAP_CNTL
610x2090 SE_TCL_OUTPUT_VTX_FMT_0
620x2094 SE_TCL_OUTPUT_VTX_FMT_1
630x20b0 SE_VTE_CNTL
640x2140 SE_CNTL_STATUS
650x2180 SE_VTX_STATE_CNTL
660x2200 SE_TCL_VECTOR_INDX_REG
670x2204 SE_TCL_VECTOR_DATA_REG
680x2208 SE_TCL_SCALAR_INDX_REG
690x220c SE_TCL_SCALAR_DATA_REG
700x2230 SE_TCL_MATRIX_SEL_0
710x2234 SE_TCL_MATRIX_SEL_1
720x2238 SE_TCL_MATRIX_SEL_2
730x223c SE_TCL_MATRIX_SEL_3
740x2240 SE_TCL_MATRIX_SEL_4
750x2250 SE_TCL_OUTPUT_VTX_COMP_SEL
760x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0
770x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1
780x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2
790x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3
800x2268 SE_TCL_LIGHT_MODEL_CTL_0
810x226c SE_TCL_LIGHT_MODEL_CTL_1
820x2270 SE_TCL_PER_LIGHT_CTL_0
830x2274 SE_TCL_PER_LIGHT_CTL_1
840x2278 SE_TCL_PER_LIGHT_CTL_2
850x227c SE_TCL_PER_LIGHT_CTL_3
860x2284 VAP_PVS_STATE_FLUSH_REG
870x22a8 SE_TCL_TEX_PROC_CTL_2
880x22ac SE_TCL_TEX_PROC_CTL_3
890x22b0 SE_TCL_TEX_PROC_CTL_0
900x22b4 SE_TCL_TEX_PROC_CTL_1
910x22b8 SE_TCL_TEX_CYL_WRAP_CTL
920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
930x22c4 SE_TCL_POINT_SPRITE_CNTL
940x2648 RE_POINTSIZE
950x26c0 RE_TOP_LEFT
960x26c4 RE_MISC
970x26f0 RE_AUX_SCISSOR_CNTL
980x2c14 PP_BORDER_COLOR_0
990x2c34 PP_BORDER_COLOR_1
1000x2c54 PP_BORDER_COLOR_2
1010x2c74 PP_BORDER_COLOR_3
1020x2c94 PP_BORDER_COLOR_4
1030x2cb4 PP_BORDER_COLOR_5
1040x2cc4 PP_CNTL_X
1050x2cf8 PP_TRI_PERF
1060x2cfc PP_PERF_CNTL
1070x2d9c PP_TAM_DEBUG3
1080x2ee0 PP_TFACTOR_0
1090x2ee4 PP_TFACTOR_1
1100x2ee8 PP_TFACTOR_2
1110x2eec PP_TFACTOR_3
1120x2ef0 PP_TFACTOR_4
1130x2ef4 PP_TFACTOR_5
1140x2ef8 PP_TFACTOR_6
1150x2efc PP_TFACTOR_7
1160x2f00 PP_TXCBLEND_0
1170x2f04 PP_TXCBLEND2_0
1180x2f08 PP_TXABLEND_0
1190x2f0c PP_TXABLEND2_0
1200x2f10 PP_TXCBLEND_1
1210x2f14 PP_TXCBLEND2_1
1220x2f18 PP_TXABLEND_1
1230x2f1c PP_TXABLEND2_1
1240x2f20 PP_TXCBLEND_2
1250x2f24 PP_TXCBLEND2_2
1260x2f28 PP_TXABLEND_2
1270x2f2c PP_TXABLEND2_2
1280x2f30 PP_TXCBLEND_3
1290x2f34 PP_TXCBLEND2_3
1300x2f38 PP_TXABLEND_3
1310x2f3c PP_TXABLEND2_3
1320x2f40 PP_TXCBLEND_4
1330x2f44 PP_TXCBLEND2_4
1340x2f48 PP_TXABLEND_4
1350x2f4c PP_TXABLEND2_4
1360x2f50 PP_TXCBLEND_5
1370x2f54 PP_TXCBLEND2_5
1380x2f58 PP_TXABLEND_5
1390x2f5c PP_TXABLEND2_5
1400x2f60 PP_TXCBLEND_6
1410x2f64 PP_TXCBLEND2_6
1420x2f68 PP_TXABLEND_6
1430x2f6c PP_TXABLEND2_6
1440x2f70 PP_TXCBLEND_7
1450x2f74 PP_TXCBLEND2_7
1460x2f78 PP_TXABLEND_7
1470x2f7c PP_TXABLEND2_7
1480x2f80 PP_TXCBLEND_8
1490x2f84 PP_TXCBLEND2_8
1500x2f88 PP_TXABLEND_8
1510x2f8c PP_TXABLEND2_8
1520x2f90 PP_TXCBLEND_9
1530x2f94 PP_TXCBLEND2_9
1540x2f98 PP_TXABLEND_9
1550x2f9c PP_TXABLEND2_9
1560x2fa0 PP_TXCBLEND_10
1570x2fa4 PP_TXCBLEND2_10
1580x2fa8 PP_TXABLEND_10
1590x2fac PP_TXABLEND2_10
1600x2fb0 PP_TXCBLEND_11
1610x2fb4 PP_TXCBLEND2_11
1620x2fb8 PP_TXABLEND_11
1630x2fbc PP_TXABLEND2_11
1640x2fc0 PP_TXCBLEND_12
1650x2fc4 PP_TXCBLEND2_12
1660x2fc8 PP_TXABLEND_12
1670x2fcc PP_TXABLEND2_12
1680x2fd0 PP_TXCBLEND_13
1690x2fd4 PP_TXCBLEND2_13
1700x2fd8 PP_TXABLEND_13
1710x2fdc PP_TXABLEND2_13
1720x2fe0 PP_TXCBLEND_14
1730x2fe4 PP_TXCBLEND2_14
1740x2fe8 PP_TXABLEND_14
1750x2fec PP_TXABLEND2_14
1760x2ff0 PP_TXCBLEND_15
1770x2ff4 PP_TXCBLEND2_15
1780x2ff8 PP_TXABLEND_15
1790x2ffc PP_TXABLEND2_15
1800x3218 RB3D_BLENCOLOR
1810x321c RB3D_ABLENDCNTL
1820x3220 RB3D_CBLENDCNTL
1830x3290 RB3D_ZPASS_DATA
184
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rn50 b/drivers/gpu/drm/radeon/reg_srcs/rn50
new file mode 100644
index 00000000000..2687b630726
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rn50
@@ -0,0 +1,30 @@
1rn50 0x3294
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 12:27:45 -0400