diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-prph.h | 327 |
1 files changed, 0 insertions, 327 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h index 81c464747f5..448b0eab54a 100644 --- a/drivers/net/wireless/iwlwifi/iwl-prph.h +++ b/drivers/net/wireless/iwlwifi/iwl-prph.h | |||
@@ -98,142 +98,6 @@ | |||
98 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) | 98 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) |
99 | 99 | ||
100 | /** | 100 | /** |
101 | * BSM (Bootstrap State Machine) | ||
102 | * | ||
103 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | ||
104 | * in special SRAM that does not power down when the embedded control | ||
105 | * processor is sleeping (e.g. for periodic power-saving shutdowns of radio). | ||
106 | * | ||
107 | * When powering back up after sleeps (or during initial uCode load), the BSM | ||
108 | * internally loads the short bootstrap program from the special SRAM into the | ||
109 | * embedded processor's instruction SRAM, and starts the processor so it runs | ||
110 | * the bootstrap program. | ||
111 | * | ||
112 | * This bootstrap program loads (via PCI busmaster DMA) instructions and data | ||
113 | * images for a uCode program from host DRAM locations. The host driver | ||
114 | * indicates DRAM locations and sizes for instruction and data images via the | ||
115 | * four BSM_DRAM_* registers. Once the bootstrap program loads the new program, | ||
116 | * the new program starts automatically. | ||
117 | * | ||
118 | * The uCode used for open-source drivers includes two programs: | ||
119 | * | ||
120 | * 1) Initialization -- performs hardware calibration and sets up some | ||
121 | * internal data, then notifies host via "initialize alive" notification | ||
122 | * (struct iwl_init_alive_resp) that it has completed all of its work. | ||
123 | * After signal from host, it then loads and starts the runtime program. | ||
124 | * The initialization program must be used when initially setting up the | ||
125 | * NIC after loading the driver. | ||
126 | * | ||
127 | * 2) Runtime/Protocol -- performs all normal runtime operations. This | ||
128 | * notifies host via "alive" notification (struct iwl_alive_resp) that it | ||
129 | * is ready to be used. | ||
130 | * | ||
131 | * When initializing the NIC, the host driver does the following procedure: | ||
132 | * | ||
133 | * 1) Load bootstrap program (instructions only, no data image for bootstrap) | ||
134 | * into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND | ||
135 | * | ||
136 | * 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction | ||
137 | * images in host DRAM. | ||
138 | * | ||
139 | * 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked: | ||
140 | * BSM_WR_MEM_SRC_REG = 0 | ||
141 | * BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND | ||
142 | * BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image | ||
143 | * | ||
144 | * 4) Load bootstrap into instruction SRAM: | ||
145 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START | ||
146 | * | ||
147 | * 5) Wait for load completion: | ||
148 | * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0 | ||
149 | * | ||
150 | * 6) Enable future boot loads whenever NIC's power management triggers it: | ||
151 | * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN | ||
152 | * | ||
153 | * 7) Start the NIC by removing all reset bits: | ||
154 | * CSR_RESET = 0 | ||
155 | * | ||
156 | * The bootstrap uCode (already in instruction SRAM) loads initialization | ||
157 | * uCode. Initialization uCode performs data initialization, sends | ||
158 | * "initialize alive" notification to host, and waits for a signal from | ||
159 | * host to load runtime code. | ||
160 | * | ||
161 | * 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction | ||
162 | * images in host DRAM. The last register loaded must be the instruction | ||
163 | * byte count register ("1" in MSbit tells initialization uCode to load | ||
164 | * the runtime uCode): | ||
165 | * BSM_DRAM_INST_BYTECOUNT_REG = byte count | BSM_DRAM_INST_LOAD | ||
166 | * | ||
167 | * 5) Wait for "alive" notification, then issue normal runtime commands. | ||
168 | * | ||
169 | * Data caching during power-downs: | ||
170 | * | ||
171 | * Just before the embedded controller powers down (e.g for automatic | ||
172 | * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA) | ||
173 | * a current snapshot of the embedded processor's data SRAM into host DRAM. | ||
174 | * This caches the data while the embedded processor's memory is powered down. | ||
175 | * Location and size are controlled by BSM_DRAM_DATA_* registers. | ||
176 | * | ||
177 | * NOTE: Instruction SRAM does not need to be saved, since that doesn't | ||
178 | * change during operation; the original image (from uCode distribution | ||
179 | * file) can be used for reload. | ||
180 | * | ||
181 | * When powering back up, the BSM loads the bootstrap program. Bootstrap looks | ||
182 | * at the BSM_DRAM_* registers, which now point to the runtime instruction | ||
183 | * image and the cached (modified) runtime data (*not* the initialization | ||
184 | * uCode). Bootstrap reloads these runtime images into SRAM, and restarts the | ||
185 | * uCode from where it left off before the power-down. | ||
186 | * | ||
187 | * NOTE: Initialization uCode does *not* run as part of the save/restore | ||
188 | * procedure. | ||
189 | * | ||
190 | * This save/restore method is mostly for autonomous power management during | ||
191 | * normal operation (result of POWER_TABLE_CMD). Platform suspend/resume and | ||
192 | * RFKILL should use complete restarts (with total re-initialization) of uCode, | ||
193 | * allowing total shutdown (including BSM memory). | ||
194 | * | ||
195 | * Note that, during normal operation, the host DRAM that held the initial | ||
196 | * startup data for the runtime code is now being used as a backup data cache | ||
197 | * for modified data! If you need to completely re-initialize the NIC, make | ||
198 | * sure that you use the runtime data image from the uCode distribution file, | ||
199 | * not the modified/saved runtime data. You may want to store a separate | ||
200 | * "clean" runtime data image in DRAM to avoid disk reads of distribution file. | ||
201 | */ | ||
202 | |||
203 | /* BSM bit fields */ | ||
204 | #define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */ | ||
205 | #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup*/ | ||
206 | #define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */ | ||
207 | |||
208 | /* BSM addresses */ | ||
209 | #define BSM_BASE (PRPH_BASE + 0x3400) | ||
210 | #define BSM_END (PRPH_BASE + 0x3800) | ||
211 | |||
212 | #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ | ||
213 | #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ | ||
214 | #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ | ||
215 | #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ | ||
216 | #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ | ||
217 | |||
218 | /* | ||
219 | * Pointers and size regs for bootstrap load and data SRAM save/restore. | ||
220 | * NOTE: 3945 pointers use bits 31:0 of DRAM address. | ||
221 | * 4965 pointers use bits 35:4 of DRAM address. | ||
222 | */ | ||
223 | #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) | ||
224 | #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) | ||
225 | #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) | ||
226 | #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) | ||
227 | |||
228 | /* | ||
229 | * BSM special memory, stays powered on during power-save sleeps. | ||
230 | * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1) | ||
231 | */ | ||
232 | #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) | ||
233 | #define BSM_SRAM_SIZE (1024) /* bytes */ | ||
234 | |||
235 | |||
236 | /** | ||
237 | * Tx Scheduler | 101 | * Tx Scheduler |
238 | * | 102 | * |
239 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs | 103 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
@@ -319,201 +183,10 @@ | |||
319 | * Max Tx window size is the max number of contiguous TFDs that the scheduler | 183 | * Max Tx window size is the max number of contiguous TFDs that the scheduler |
320 | * can keep track of at one time when creating block-ack chains of frames. | 184 | * can keep track of at one time when creating block-ack chains of frames. |
321 | * Note that "64" matches the number of ack bits in a block-ack packet. | 185 | * Note that "64" matches the number of ack bits in a block-ack packet. |
322 | * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize | ||
323 | * IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) values. | ||
324 | */ | 186 | */ |
325 | #define SCD_WIN_SIZE 64 | 187 | #define SCD_WIN_SIZE 64 |
326 | #define SCD_FRAME_LIMIT 64 | 188 | #define SCD_FRAME_LIMIT 64 |
327 | 189 | ||
328 | /* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */ | ||
329 | #define IWL49_SCD_START_OFFSET 0xa02c00 | ||
330 | |||
331 | /* | ||
332 | * 4965 tells driver SRAM address for internal scheduler structs via this reg. | ||
333 | * Value is valid only after "Alive" response from uCode. | ||
334 | */ | ||
335 | #define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x0) | ||
336 | |||
337 | /* | ||
338 | * Driver may need to update queue-empty bits after changing queue's | ||
339 | * write and read pointers (indexes) during (re-)initialization (i.e. when | ||
340 | * scheduler is not tracking what's happening). | ||
341 | * Bit fields: | ||
342 | * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit | ||
343 | * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty | ||
344 | * NOTE: This register is not used by Linux driver. | ||
345 | */ | ||
346 | #define IWL49_SCD_EMPTY_BITS (IWL49_SCD_START_OFFSET + 0x4) | ||
347 | |||
348 | /* | ||
349 | * Physical base address of array of byte count (BC) circular buffers (CBs). | ||
350 | * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. | ||
351 | * This register points to BC CB for queue 0, must be on 1024-byte boundary. | ||
352 | * Others are spaced by 1024 bytes. | ||
353 | * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. | ||
354 | * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff). | ||
355 | * Bit fields: | ||
356 | * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. | ||
357 | */ | ||
358 | #define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_START_OFFSET + 0x10) | ||
359 | |||
360 | /* | ||
361 | * Enables any/all Tx DMA/FIFO channels. | ||
362 | * Scheduler generates requests for only the active channels. | ||
363 | * Set this to 0xff to enable all 8 channels (normal usage). | ||
364 | * Bit fields: | ||
365 | * 7- 0: Enable (1), disable (0), one bit for each channel 0-7 | ||
366 | */ | ||
367 | #define IWL49_SCD_TXFACT (IWL49_SCD_START_OFFSET + 0x1c) | ||
368 | /* | ||
369 | * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. | ||
370 | * Initialized and updated by driver as new TFDs are added to queue. | ||
371 | * NOTE: If using Block Ack, index must correspond to frame's | ||
372 | * Start Sequence Number; index = (SSN & 0xff) | ||
373 | * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? | ||
374 | */ | ||
375 | #define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_START_OFFSET + 0x24 + (x) * 4) | ||
376 | |||
377 | /* | ||
378 | * Queue (x) Read Pointers (indexes, really!), one for each Tx queue. | ||
379 | * For FIFO mode, index indicates next frame to transmit. | ||
380 | * For Scheduler-ACK mode, index indicates first frame in Tx window. | ||
381 | * Initialized by driver, updated by scheduler. | ||
382 | */ | ||
383 | #define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_START_OFFSET + 0x64 + (x) * 4) | ||
384 | |||
385 | /* | ||
386 | * Select which queues work in chain mode (1) vs. not (0). | ||
387 | * Use chain mode to build chains of aggregated frames. | ||
388 | * Bit fields: | ||
389 | * 31-16: Reserved | ||
390 | * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time | ||
391 | * NOTE: If driver sets up queue for chain mode, it should be also set up | ||
392 | * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). | ||
393 | */ | ||
394 | #define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_START_OFFSET + 0xd0) | ||
395 | |||
396 | /* | ||
397 | * Select which queues interrupt driver when scheduler increments | ||
398 | * a queue's read pointer (index). | ||
399 | * Bit fields: | ||
400 | * 31-16: Reserved | ||
401 | * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled | ||
402 | * NOTE: This functionality is apparently a no-op; driver relies on interrupts | ||
403 | * from Rx queue to read Tx command responses and update Tx queues. | ||
404 | */ | ||
405 | #define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_START_OFFSET + 0xe4) | ||
406 | |||
407 | /* | ||
408 | * Queue search status registers. One for each queue. | ||
409 | * Sets up queue mode and assigns queue to Tx DMA channel. | ||
410 | * Bit fields: | ||
411 | * 19-10: Write mask/enable bits for bits 0-9 | ||
412 | * 9: Driver should init to "0" | ||
413 | * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). | ||
414 | * Driver should init to "1" for aggregation mode, or "0" otherwise. | ||
415 | * 7-6: Driver should init to "0" | ||
416 | * 5: Window Size Left; indicates whether scheduler can request | ||
417 | * another TFD, based on window size, etc. Driver should init | ||
418 | * this bit to "1" for aggregation mode, or "0" for non-agg. | ||
419 | * 4-1: Tx FIFO to use (range 0-7). | ||
420 | * 0: Queue is active (1), not active (0). | ||
421 | * Other bits should be written as "0" | ||
422 | * | ||
423 | * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled | ||
424 | * via SCD_QUEUECHAIN_SEL. | ||
425 | */ | ||
426 | #define IWL49_SCD_QUEUE_STATUS_BITS(x)\ | ||
427 | (IWL49_SCD_START_OFFSET + 0x104 + (x) * 4) | ||
428 | |||
429 | /* Bit field positions */ | ||
430 | #define IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0) | ||
431 | #define IWL49_SCD_QUEUE_STTS_REG_POS_TXF (1) | ||
432 | #define IWL49_SCD_QUEUE_STTS_REG_POS_WSL (5) | ||
433 | #define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) | ||
434 | |||
435 | /* Write masks */ | ||
436 | #define IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) | ||
437 | #define IWL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00) | ||
438 | |||
439 | /** | ||
440 | * 4965 internal SRAM structures for scheduler, shared with driver ... | ||
441 | * | ||
442 | * Driver should clear and initialize the following areas after receiving | ||
443 | * "Alive" response from 4965 uCode, i.e. after initial | ||
444 | * uCode load, or after a uCode load done for error recovery: | ||
445 | * | ||
446 | * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) | ||
447 | * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) | ||
448 | * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) | ||
449 | * | ||
450 | * Driver accesses SRAM via HBUS_TARG_MEM_* registers. | ||
451 | * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. | ||
452 | * All OFFSET values must be added to this base address. | ||
453 | */ | ||
454 | |||
455 | /* | ||
456 | * Queue context. One 8-byte entry for each of 16 queues. | ||
457 | * | ||
458 | * Driver should clear this entire area (size 0x80) to 0 after receiving | ||
459 | * "Alive" notification from uCode. Additionally, driver should init | ||
460 | * each queue's entry as follows: | ||
461 | * | ||
462 | * LS Dword bit fields: | ||
463 | * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64. | ||
464 | * | ||
465 | * MS Dword bit fields: | ||
466 | * 16-22: Frame limit. Driver should init to 10 (0xa). | ||
467 | * | ||
468 | * Driver should init all other bits to 0. | ||
469 | * | ||
470 | * Init must be done after driver receives "Alive" response from 4965 uCode, | ||
471 | * and when setting up queue for aggregation. | ||
472 | */ | ||
473 | #define IWL49_SCD_CONTEXT_DATA_OFFSET 0x380 | ||
474 | #define IWL49_SCD_CONTEXT_QUEUE_OFFSET(x) \ | ||
475 | (IWL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) | ||
476 | |||
477 | #define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) | ||
478 | #define IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) | ||
479 | #define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) | ||
480 | #define IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) | ||
481 | |||
482 | /* | ||
483 | * Tx Status Bitmap | ||
484 | * | ||
485 | * Driver should clear this entire area (size 0x100) to 0 after receiving | ||
486 | * "Alive" notification from uCode. Area is used only by device itself; | ||
487 | * no other support (besides clearing) is required from driver. | ||
488 | */ | ||
489 | #define IWL49_SCD_TX_STTS_BITMAP_OFFSET 0x400 | ||
490 | |||
491 | /* | ||
492 | * RAxTID to queue translation mapping. | ||
493 | * | ||
494 | * When queue is in Scheduler-ACK mode, frames placed in a that queue must be | ||
495 | * for only one combination of receiver address (RA) and traffic ID (TID), i.e. | ||
496 | * one QOS priority level destined for one station (for this wireless link, | ||
497 | * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit | ||
498 | * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK | ||
499 | * mode, the device ignores the mapping value. | ||
500 | * | ||
501 | * Bit fields, for each 16-bit map: | ||
502 | * 15-9: Reserved, set to 0 | ||
503 | * 8-4: Index into device's station table for recipient station | ||
504 | * 3-0: Traffic ID (tid), range 0-15 | ||
505 | * | ||
506 | * Driver should clear this entire area (size 32 bytes) to 0 after receiving | ||
507 | * "Alive" notification from uCode. To update a 16-bit map value, driver | ||
508 | * must read a dword-aligned value from device SRAM, replace the 16-bit map | ||
509 | * value of interest, and write the dword value back into device SRAM. | ||
510 | */ | ||
511 | #define IWL49_SCD_TRANSLATE_TBL_OFFSET 0x500 | ||
512 | |||
513 | /* Find translation table dword to read/write for given queue */ | ||
514 | #define IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ | ||
515 | ((IWL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) | ||
516 | |||
517 | #define IWL_SCD_TXFIFO_POS_TID (0) | 190 | #define IWL_SCD_TXFIFO_POS_TID (0) |
518 | #define IWL_SCD_TXFIFO_POS_RA (4) | 191 | #define IWL_SCD_TXFIFO_POS_RA (4) |
519 | #define IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) | 192 | #define IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) |