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-rw-r--r--drivers/staging/tidspbridge/core/_tiomap.h6
-rw-r--r--drivers/staging/tidspbridge/core/chnl_sm.c22
-rw-r--r--drivers/staging/tidspbridge/core/io_sm.c34
-rw-r--r--drivers/staging/tidspbridge/core/tiomap3430.c2
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h4
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h4
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h6
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/dbdefs.h6
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/dspdefs.h12
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h2
-rw-r--r--drivers/staging/tidspbridge/pmgr/cmm.c44
-rw-r--r--drivers/staging/tidspbridge/pmgr/dev.c16
-rw-r--r--drivers/staging/tidspbridge/rmgr/node.c6
-rw-r--r--drivers/staging/tidspbridge/rmgr/proc.c6
-rw-r--r--drivers/staging/tidspbridge/rmgr/strm.c2
15 files changed, 86 insertions, 86 deletions
diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h
index 5a14e6f8050..60d98764af1 100644
--- a/drivers/staging/tidspbridge/core/_tiomap.h
+++ b/drivers/staging/tidspbridge/core/_tiomap.h
@@ -332,9 +332,9 @@ struct bridge_dev_context {
332 u32 dsp_clk_m2_base; /* DSP Clock Module m2 */ 332 u32 dsp_clk_m2_base; /* DSP Clock Module m2 */
333 u32 public_rhea; /* Pub Rhea */ 333 u32 public_rhea; /* Pub Rhea */
334 u32 int_addr; /* MB INTR reg */ 334 u32 int_addr; /* MB INTR reg */
335 u32 dw_tc_endianism; /* TC Endianism register */ 335 u32 tc_endianism; /* TC Endianism register */
336 u32 dw_test_base; /* DSP MMU Mapped registers */ 336 u32 test_base; /* DSP MMU Mapped registers */
337 u32 dw_self_loop; /* Pointer to the selfloop */ 337 u32 self_loop; /* Pointer to the selfloop */
338 u32 dsp_start_add; /* API Boot vector */ 338 u32 dsp_start_add; /* API Boot vector */
339 u32 internal_size; /* Internal memory size */ 339 u32 internal_size; /* Internal memory size */
340 340
diff --git a/drivers/staging/tidspbridge/core/chnl_sm.c b/drivers/staging/tidspbridge/core/chnl_sm.c
index 59b8d556939..c20431553aa 100644
--- a/drivers/staging/tidspbridge/core/chnl_sm.c
+++ b/drivers/staging/tidspbridge/core/chnl_sm.c
@@ -115,7 +115,7 @@ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *host_buf,
115 * Check the channel state: only queue chirp if channel state 115 * Check the channel state: only queue chirp if channel state
116 * allows it. 116 * allows it.
117 */ 117 */
118 dw_state = pchnl->dw_state; 118 dw_state = pchnl->state;
119 if (dw_state != CHNL_STATEREADY) { 119 if (dw_state != CHNL_STATEREADY) {
120 if (dw_state & CHNL_STATECANCEL) 120 if (dw_state & CHNL_STATECANCEL)
121 return -ECANCELED; 121 return -ECANCELED;
@@ -207,7 +207,7 @@ func_cont:
207 * more IOR's. 207 * more IOR's.
208 */ 208 */
209 if (is_eos) 209 if (is_eos)
210 pchnl->dw_state |= CHNL_STATEEOS; 210 pchnl->state |= CHNL_STATEEOS;
211 211
212 /* Legacy DSM Processor-Copy */ 212 /* Legacy DSM Processor-Copy */
213 DBC_ASSERT(pchnl->chnl_type == CHNL_PCPY); 213 DBC_ASSERT(pchnl->chnl_type == CHNL_PCPY);
@@ -258,7 +258,7 @@ int bridge_chnl_cancel_io(struct chnl_object *chnl_obj)
258 * IORequests or dispatching. */ 258 * IORequests or dispatching. */
259 spin_lock_bh(&chnl_mgr_obj->chnl_mgr_lock); 259 spin_lock_bh(&chnl_mgr_obj->chnl_mgr_lock);
260 260
261 pchnl->dw_state |= CHNL_STATECANCEL; 261 pchnl->state |= CHNL_STATECANCEL;
262 262
263 if (list_empty(&pchnl->pio_requests)) { 263 if (list_empty(&pchnl->pio_requests)) {
264 spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock); 264 spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
@@ -312,7 +312,7 @@ int bridge_chnl_close(struct chnl_object *chnl_obj)
312 if (status) 312 if (status)
313 return status; 313 return status;
314 /* Assert I/O on this channel is now cancelled: Protects from io_dpc */ 314 /* Assert I/O on this channel is now cancelled: Protects from io_dpc */
315 DBC_ASSERT((pchnl->dw_state & CHNL_STATECANCEL)); 315 DBC_ASSERT((pchnl->state & CHNL_STATECANCEL));
316 /* Invalidate channel object: Protects from CHNL_GetIOCompletion() */ 316 /* Invalidate channel object: Protects from CHNL_GetIOCompletion() */
317 /* Free the slot in the channel manager: */ 317 /* Free the slot in the channel manager: */
318 pchnl->chnl_mgr_obj->ap_channel[pchnl->chnl_id] = NULL; 318 pchnl->chnl_mgr_obj->ap_channel[pchnl->chnl_id] = NULL;
@@ -381,7 +381,7 @@ int bridge_chnl_create(struct chnl_mgr **channel_mgr,
381 * max_channels, GFP_KERNEL); 381 * max_channels, GFP_KERNEL);
382 if (chnl_mgr_obj->ap_channel) { 382 if (chnl_mgr_obj->ap_channel) {
383 /* Initialize chnl_mgr object */ 383 /* Initialize chnl_mgr object */
384 chnl_mgr_obj->dw_type = CHNL_TYPESM; 384 chnl_mgr_obj->type = CHNL_TYPESM;
385 chnl_mgr_obj->word_size = mgr_attrts->word_size; 385 chnl_mgr_obj->word_size = mgr_attrts->word_size;
386 /* Total # chnls supported */ 386 /* Total # chnls supported */
387 chnl_mgr_obj->max_channels = max_channels; 387 chnl_mgr_obj->max_channels = max_channels;
@@ -488,7 +488,7 @@ int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 timeout)
488 } else { 488 } else {
489 status = bridge_chnl_cancel_io(chnl_obj); 489 status = bridge_chnl_cancel_io(chnl_obj);
490 /* Now, leave the channel in the ready state: */ 490 /* Now, leave the channel in the ready state: */
491 pchnl->dw_state &= ~CHNL_STATECANCEL; 491 pchnl->state &= ~CHNL_STATECANCEL;
492 } 492 }
493 } 493 }
494 DBC_ENSURE(status || list_empty(&pchnl->pio_requests)); 494 DBC_ENSURE(status || list_empty(&pchnl->pio_requests));
@@ -517,7 +517,7 @@ int bridge_chnl_get_info(struct chnl_object *chnl_obj,
517 channel_info->sync_event = pchnl->sync_event; 517 channel_info->sync_event = pchnl->sync_event;
518 channel_info->cio_cs = pchnl->cio_cs; 518 channel_info->cio_cs = pchnl->cio_cs;
519 channel_info->cio_reqs = pchnl->cio_reqs; 519 channel_info->cio_reqs = pchnl->cio_reqs;
520 channel_info->dw_state = pchnl->dw_state; 520 channel_info->state = pchnl->state;
521 } else { 521 } else {
522 status = -EFAULT; 522 status = -EFAULT;
523 } 523 }
@@ -687,7 +687,7 @@ int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 ch_id,
687 /* Return the requested information: */ 687 /* Return the requested information: */
688 mgr_info->chnl_obj = chnl_mgr_obj->ap_channel[ch_id]; 688 mgr_info->chnl_obj = chnl_mgr_obj->ap_channel[ch_id];
689 mgr_info->open_channels = chnl_mgr_obj->open_channels; 689 mgr_info->open_channels = chnl_mgr_obj->open_channels;
690 mgr_info->dw_type = chnl_mgr_obj->dw_type; 690 mgr_info->type = chnl_mgr_obj->type;
691 /* total # of chnls */ 691 /* total # of chnls */
692 mgr_info->max_channels = chnl_mgr_obj->max_channels; 692 mgr_info->max_channels = chnl_mgr_obj->max_channels;
693 693
@@ -718,7 +718,7 @@ int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 timeout,
718 718
719 /* Reset the byte count and put channel back in ready state. */ 719 /* Reset the byte count and put channel back in ready state. */
720 chnl_obj->bytes_moved = 0; 720 chnl_obj->bytes_moved = 0;
721 chnl_obj->dw_state &= ~CHNL_STATECANCEL; 721 chnl_obj->state &= ~CHNL_STATECANCEL;
722 } 722 }
723 723
724 return status; 724 return status;
@@ -769,7 +769,7 @@ int bridge_chnl_open(struct chnl_object **chnl,
769 return -ENOMEM; 769 return -ENOMEM;
770 770
771 /* Protect queues from io_dpc: */ 771 /* Protect queues from io_dpc: */
772 pchnl->dw_state = CHNL_STATECANCEL; 772 pchnl->state = CHNL_STATECANCEL;
773 773
774 /* Allocate initial IOR and IOC queues: */ 774 /* Allocate initial IOR and IOC queues: */
775 status = create_chirp_list(&pchnl->free_packets_list, 775 status = create_chirp_list(&pchnl->free_packets_list,
@@ -817,7 +817,7 @@ int bridge_chnl_open(struct chnl_object **chnl,
817 chnl_mgr_obj->open_channels++; 817 chnl_mgr_obj->open_channels++;
818 spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock); 818 spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
819 /* Return result... */ 819 /* Return result... */
820 pchnl->dw_state = CHNL_STATEREADY; 820 pchnl->state = CHNL_STATEREADY;
821 *chnl = pchnl; 821 *chnl = pchnl;
822 822
823 return status; 823 return status;
diff --git a/drivers/staging/tidspbridge/core/io_sm.c b/drivers/staging/tidspbridge/core/io_sm.c
index e89052c8c0e..38c59dee50a 100644
--- a/drivers/staging/tidspbridge/core/io_sm.c
+++ b/drivers/staging/tidspbridge/core/io_sm.c
@@ -483,7 +483,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
483 1)) == 0)) { 483 1)) == 0)) {
484 status = 484 status =
485 hio_mgr->intf_fxns-> 485 hio_mgr->intf_fxns->
486 pfn_brd_mem_map(hio_mgr->hbridge_context, 486 brd_mem_map(hio_mgr->hbridge_context,
487 pa_curr, va_curr, 487 pa_curr, va_curr,
488 page_size[i], map_attrs, 488 page_size[i], map_attrs,
489 NULL); 489 NULL);
@@ -549,7 +549,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
549 } else { 549 } else {
550 status = 550 status =
551 hio_mgr->intf_fxns-> 551 hio_mgr->intf_fxns->
552 pfn_brd_mem_map(hio_mgr->hbridge_context, 552 brd_mem_map(hio_mgr->hbridge_context,
553 pa_curr, va_curr, 553 pa_curr, va_curr,
554 page_size[i], map_attrs, 554 page_size[i], map_attrs,
555 NULL); 555 NULL);
@@ -615,7 +615,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
615 ae_proc[ndx].ul_dsp_va); 615 ae_proc[ndx].ul_dsp_va);
616 ndx++; 616 ndx++;
617 } else { 617 } else {
618 status = hio_mgr->intf_fxns->pfn_brd_mem_map 618 status = hio_mgr->intf_fxns->brd_mem_map
619 (hio_mgr->hbridge_context, 619 (hio_mgr->hbridge_context,
620 hio_mgr->ext_proc_info.ty_tlb[i]. 620 hio_mgr->ext_proc_info.ty_tlb[i].
621 ul_gpp_phys, 621 ul_gpp_phys,
@@ -637,7 +637,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
637 /* Map the L4 peripherals */ 637 /* Map the L4 peripherals */
638 i = 0; 638 i = 0;
639 while (l4_peripheral_table[i].phys_addr) { 639 while (l4_peripheral_table[i].phys_addr) {
640 status = hio_mgr->intf_fxns->pfn_brd_mem_map 640 status = hio_mgr->intf_fxns->brd_mem_map
641 (hio_mgr->hbridge_context, l4_peripheral_table[i].phys_addr, 641 (hio_mgr->hbridge_context, l4_peripheral_table[i].phys_addr,
642 l4_peripheral_table[i].dsp_virt_addr, HW_PAGE_SIZE4KB, 642 l4_peripheral_table[i].dsp_virt_addr, HW_PAGE_SIZE4KB,
643 map_attrs, NULL); 643 map_attrs, NULL);
@@ -977,8 +977,8 @@ void io_request_chnl(struct io_mgr *io_manager, struct chnl_object *pchnl,
977 * Assertion fires if CHNL_AddIOReq() called on a stream 977 * Assertion fires if CHNL_AddIOReq() called on a stream
978 * which was cancelled, or attached to a dead board. 978 * which was cancelled, or attached to a dead board.
979 */ 979 */
980 DBC_ASSERT((pchnl->dw_state == CHNL_STATEREADY) || 980 DBC_ASSERT((pchnl->state == CHNL_STATEREADY) ||
981 (pchnl->dw_state == CHNL_STATEEOS)); 981 (pchnl->state == CHNL_STATEEOS));
982 /* Indicate to the DSP we have a buffer available for input */ 982 /* Indicate to the DSP we have a buffer available for input */
983 set_chnl_busy(sm, pchnl->chnl_id); 983 set_chnl_busy(sm, pchnl->chnl_id);
984 *mbx_val = MBX_PCPY_CLASS; 984 *mbx_val = MBX_PCPY_CLASS;
@@ -987,7 +987,7 @@ void io_request_chnl(struct io_mgr *io_manager, struct chnl_object *pchnl,
987 * This assertion fails if CHNL_AddIOReq() was called on a 987 * This assertion fails if CHNL_AddIOReq() was called on a
988 * stream which was cancelled, or attached to a dead board. 988 * stream which was cancelled, or attached to a dead board.
989 */ 989 */
990 DBC_ASSERT((pchnl->dw_state & ~CHNL_STATEEOS) == 990 DBC_ASSERT((pchnl->state & ~CHNL_STATEEOS) ==
991 CHNL_STATEREADY); 991 CHNL_STATEREADY);
992 /* 992 /*
993 * Record the fact that we have a buffer available for 993 * Record the fact that we have a buffer available for
@@ -1092,7 +1092,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
1092 } 1092 }
1093 pchnl = chnl_mgr_obj->ap_channel[chnl_id]; 1093 pchnl = chnl_mgr_obj->ap_channel[chnl_id];
1094 if ((pchnl != NULL) && CHNL_IS_INPUT(pchnl->chnl_mode)) { 1094 if ((pchnl != NULL) && CHNL_IS_INPUT(pchnl->chnl_mode)) {
1095 if ((pchnl->dw_state & ~CHNL_STATEEOS) == CHNL_STATEREADY) { 1095 if ((pchnl->state & ~CHNL_STATEEOS) == CHNL_STATEREADY) {
1096 /* Get the I/O request, and attempt a transfer */ 1096 /* Get the I/O request, and attempt a transfer */
1097 if (!list_empty(&pchnl->pio_requests)) { 1097 if (!list_empty(&pchnl->pio_requests)) {
1098 if (!pchnl->cio_reqs) 1098 if (!pchnl->cio_reqs)
@@ -1122,7 +1122,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
1122 * sends EOS more than once on this 1122 * sends EOS more than once on this
1123 * channel. 1123 * channel.
1124 */ 1124 */
1125 if (pchnl->dw_state & CHNL_STATEEOS) 1125 if (pchnl->state & CHNL_STATEEOS)
1126 goto func_end; 1126 goto func_end;
1127 /* 1127 /*
1128 * Zero bytes indicates EOS. Update 1128 * Zero bytes indicates EOS. Update
@@ -1131,7 +1131,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
1131 */ 1131 */
1132 chnl_packet_obj->status |= 1132 chnl_packet_obj->status |=
1133 CHNL_IOCSTATEOS; 1133 CHNL_IOCSTATEOS;
1134 pchnl->dw_state |= CHNL_STATEEOS; 1134 pchnl->state |= CHNL_STATEEOS;
1135 /* 1135 /*
1136 * Notify that end of stream has 1136 * Notify that end of stream has
1137 * occurred. 1137 * occurred.
@@ -1329,7 +1329,7 @@ static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
1329 if (sm->output_full) 1329 if (sm->output_full)
1330 goto func_end; 1330 goto func_end;
1331 1331
1332 if (pchnl && !((pchnl->dw_state & ~CHNL_STATEEOS) == CHNL_STATEREADY)) 1332 if (pchnl && !((pchnl->state & ~CHNL_STATEEOS) == CHNL_STATEREADY))
1333 goto func_end; 1333 goto func_end;
1334 1334
1335 /* Look to see if both a PC and DSP output channel are ready */ 1335 /* Look to see if both a PC and DSP output channel are ready */
@@ -1810,7 +1810,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context)
1810 psz_buf = kzalloc(ul_num_bytes + 2, GFP_ATOMIC); 1810 psz_buf = kzalloc(ul_num_bytes + 2, GFP_ATOMIC);
1811 if (psz_buf != NULL) { 1811 if (psz_buf != NULL) {
1812 /* Read trace buffer data */ 1812 /* Read trace buffer data */
1813 status = (*intf_fxns->pfn_brd_read)(pbridge_context, 1813 status = (*intf_fxns->brd_read)(pbridge_context,
1814 (u8 *)psz_buf, (u32)ul_trace_begin, 1814 (u8 *)psz_buf, (u32)ul_trace_begin,
1815 ul_num_bytes, 0); 1815 ul_num_bytes, 0);
1816 1816
@@ -1825,7 +1825,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context)
1825 __func__, psz_buf); 1825 __func__, psz_buf);
1826 1826
1827 /* Read the value at the DSP address in trace_cur_pos. */ 1827 /* Read the value at the DSP address in trace_cur_pos. */
1828 status = (*intf_fxns->pfn_brd_read)(pbridge_context, 1828 status = (*intf_fxns->brd_read)(pbridge_context,
1829 (u8 *)&trace_cur_pos, (u32)trace_cur_pos, 1829 (u8 *)&trace_cur_pos, (u32)trace_cur_pos,
1830 4, 0); 1830 4, 0);
1831 if (status) 1831 if (status)
@@ -1992,7 +1992,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context)
1992 poll_cnt < POLL_MAX) { 1992 poll_cnt < POLL_MAX) {
1993 1993
1994 /* Read DSP dump size from the DSP trace buffer... */ 1994 /* Read DSP dump size from the DSP trace buffer... */
1995 status = (*intf_fxns->pfn_brd_read)(bridge_context, 1995 status = (*intf_fxns->brd_read)(bridge_context,
1996 (u8 *)&mmu_fault_dbg_info, (u32)trace_begin, 1996 (u8 *)&mmu_fault_dbg_info, (u32)trace_begin,
1997 sizeof(mmu_fault_dbg_info), 0); 1997 sizeof(mmu_fault_dbg_info), 0);
1998 1998
@@ -2028,7 +2028,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context)
2028 buffer_end = buffer + total_size / 4; 2028 buffer_end = buffer + total_size / 4;
2029 2029
2030 /* Read bytes from the DSP trace buffer... */ 2030 /* Read bytes from the DSP trace buffer... */
2031 status = (*intf_fxns->pfn_brd_read)(bridge_context, 2031 status = (*intf_fxns->brd_read)(bridge_context,
2032 (u8 *)buffer, (u32)trace_begin, 2032 (u8 *)buffer, (u32)trace_begin,
2033 total_size, 0); 2033 total_size, 0);
2034 if (status) { 2034 if (status) {
@@ -2189,7 +2189,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context)
2189 pr_debug("%s: _DLModules at 0x%x\n", __func__, module_dsp_addr); 2189 pr_debug("%s: _DLModules at 0x%x\n", __func__, module_dsp_addr);
2190 2190
2191 /* Copy the modules_header structure from DSP memory. */ 2191 /* Copy the modules_header structure from DSP memory. */
2192 status = (*intf_fxns->pfn_brd_read)(bridge_context, (u8 *) &modules_hdr, 2192 status = (*intf_fxns->brd_read)(bridge_context, (u8 *) &modules_hdr,
2193 (u32) module_dsp_addr, sizeof(modules_hdr), 0); 2193 (u32) module_dsp_addr, sizeof(modules_hdr), 0);
2194 2194
2195 if (status) { 2195 if (status) {
@@ -2224,7 +2224,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context)
2224 goto func_end; 2224 goto func_end;
2225 } 2225 }
2226 /* Copy the dll_module structure from DSP memory */ 2226 /* Copy the dll_module structure from DSP memory */
2227 status = (*intf_fxns->pfn_brd_read)(bridge_context, 2227 status = (*intf_fxns->brd_read)(bridge_context,
2228 (u8 *)module_struct, module_dsp_addr, module_size, 0); 2228 (u8 *)module_struct, module_dsp_addr, module_size, 0);
2229 2229
2230 if (status) { 2230 if (status) {
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c
index 5964a13d0b8..8f39e11e726 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -765,7 +765,7 @@ static int bridge_dev_create(struct bridge_dev_context
765 } 765 }
766 766
767 dev_context->dsp_start_add = (u32) OMAP_GEM_BASE; 767 dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
768 dev_context->dw_self_loop = (u32) NULL; 768 dev_context->self_loop = (u32) NULL;
769 dev_context->dsp_per_clks = 0; 769 dev_context->dsp_per_clks = 0;
770 dev_context->internal_size = OMAP_DSP_SIZE; 770 dev_context->internal_size = OMAP_DSP_SIZE;
771 /* Clear dev context MMU table entries. 771 /* Clear dev context MMU table entries.
diff --git a/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h b/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h
index ea547380012..318f6b007d5 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h
@@ -127,7 +127,7 @@ struct chnl_mgr {
127 u8 max_channels; /* Total number of channels */ 127 u8 max_channels; /* Total number of channels */
128 u8 open_channels; /* Total number of open channels */ 128 u8 open_channels; /* Total number of open channels */
129 struct chnl_object **ap_channel; /* Array of channels */ 129 struct chnl_object **ap_channel; /* Array of channels */
130 u8 dw_type; /* Type of channel class library */ 130 u8 type; /* Type of channel class library */
131 /* If no shm syms, return for CHNL_Open */ 131 /* If no shm syms, return for CHNL_Open */
132 int chnl_open_status; 132 int chnl_open_status;
133}; 133};
@@ -140,7 +140,7 @@ struct chnl_object {
140 /* Pointer back to channel manager */ 140 /* Pointer back to channel manager */
141 struct chnl_mgr *chnl_mgr_obj; 141 struct chnl_mgr *chnl_mgr_obj;
142 u32 chnl_id; /* Channel id */ 142 u32 chnl_id; /* Channel id */
143 u8 dw_state; /* Current channel state */ 143 u8 state; /* Current channel state */
144 s8 chnl_mode; /* Chnl mode and attributes */ 144 s8 chnl_mode; /* Chnl mode and attributes */
145 /* Chnl I/O completion event (user mode) */ 145 /* Chnl I/O completion event (user mode) */
146 void *user_event; 146 void *user_event;
diff --git a/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h b/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h
index 29e66dd525e..e79cbd583c0 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h
@@ -59,7 +59,7 @@ struct chnl_info {
59 /*Abstraction of I/O completion event. */ 59 /*Abstraction of I/O completion event. */
60 struct sync_object *sync_event; 60 struct sync_object *sync_event;
61 s8 mode; /* Channel mode. */ 61 s8 mode; /* Channel mode. */
62 u8 dw_state; /* Current channel state. */ 62 u8 state; /* Current channel state. */
63 u32 bytes_tx; /* Total bytes transferred. */ 63 u32 bytes_tx; /* Total bytes transferred. */
64 u32 cio_cs; /* Number of IOCs in queue. */ 64 u32 cio_cs; /* Number of IOCs in queue. */
65 u32 cio_reqs; /* Number of IO Requests in queue. */ 65 u32 cio_reqs; /* Number of IO Requests in queue. */
@@ -68,7 +68,7 @@ struct chnl_info {
68 68
69/* Channel manager info: */ 69/* Channel manager info: */
70struct chnl_mgrinfo { 70struct chnl_mgrinfo {
71 u8 dw_type; /* Type of channel class library. */ 71 u8 type; /* Type of channel class library. */
72 /* Channel handle, given the channel id. */ 72 /* Channel handle, given the channel id. */
73 struct chnl_object *chnl_obj; 73 struct chnl_object *chnl_obj;
74 u8 open_channels; /* Number of open channels. */ 74 u8 open_channels; /* Number of open channels. */
diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h b/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h
index 8cd1494ccc8..719628e0e60 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h
@@ -60,7 +60,7 @@ struct cmm_seginfo {
60 u32 ul_dsp_size; /* DSP seg size in bytes */ 60 u32 ul_dsp_size; /* DSP seg size in bytes */
61 /* # of current GPP allocations from this segment */ 61 /* # of current GPP allocations from this segment */
62 u32 ul_in_use_cnt; 62 u32 ul_in_use_cnt;
63 u32 dw_seg_base_va; /* Start Virt address of SM seg */ 63 u32 seg_base_va; /* Start Virt address of SM seg */
64 64
65}; 65};
66 66
@@ -83,8 +83,8 @@ struct cmm_xlatorattrs {
83 u32 dsp_buf_size; /* size of DSP-side bufs in GPP bytes */ 83 u32 dsp_buf_size; /* size of DSP-side bufs in GPP bytes */
84 /* Vm base address alloc'd in client process context */ 84 /* Vm base address alloc'd in client process context */
85 void *vm_base; 85 void *vm_base;
86 /* dw_vm_size must be >= (dwMaxNumBufs * dwMaxSize) */ 86 /* vm_size must be >= (dwMaxNumBufs * dwMaxSize) */
87 u32 dw_vm_size; 87 u32 vm_size;
88}; 88};
89 89
90/* 90/*
diff --git a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h
index 6ba66c500e7..7a0573dd91f 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/dbdefs.h
@@ -369,9 +369,9 @@ struct dsp_processorinfo {
369/* Error information of last DSP exception signalled to the GPP */ 369/* Error information of last DSP exception signalled to the GPP */
370struct dsp_errorinfo { 370struct dsp_errorinfo {
371 u32 err_mask; 371 u32 err_mask;
372 u32 dw_val1; 372 u32 val1;
373 u32 dw_val2; 373 u32 val2;
374 u32 dw_val3; 374 u32 val3;
375}; 375};
376 376
377/* The dsp_processorstate structure describes the state of a DSP processor */ 377/* The dsp_processorstate structure describes the state of a DSP processor */
diff --git a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h
index 4eaeb21727b..380d8884307 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/dspdefs.h
@@ -978,17 +978,17 @@ struct bridge_drv_interface {
978 fxn_dev_create pfn_dev_create; /* Create device context */ 978 fxn_dev_create pfn_dev_create; /* Create device context */
979 fxn_dev_destroy pfn_dev_destroy; /* Destroy device context */ 979 fxn_dev_destroy pfn_dev_destroy; /* Destroy device context */
980 fxn_dev_ctrl pfn_dev_cntrl; /* Optional vendor interface */ 980 fxn_dev_ctrl pfn_dev_cntrl; /* Optional vendor interface */
981 fxn_brd_monitor pfn_brd_monitor; /* Load and/or start monitor */ 981 fxn_brd_monitor brd_monitor; /* Load and/or start monitor */
982 fxn_brd_start pfn_brd_start; /* Start DSP program. */ 982 fxn_brd_start pfn_brd_start; /* Start DSP program. */
983 fxn_brd_stop pfn_brd_stop; /* Stop/reset board. */ 983 fxn_brd_stop pfn_brd_stop; /* Stop/reset board. */
984 fxn_brd_status pfn_brd_status; /* Get current board status. */ 984 fxn_brd_status pfn_brd_status; /* Get current board status. */
985 fxn_brd_read pfn_brd_read; /* Read board memory */ 985 fxn_brd_read brd_read; /* Read board memory */
986 fxn_brd_write pfn_brd_write; /* Write board memory. */ 986 fxn_brd_write pfn_brd_write; /* Write board memory. */
987 fxn_brd_setstate pfn_brd_set_state; /* Sets the Board State */ 987 fxn_brd_setstate pfn_brd_set_state; /* Sets the Board State */
988 fxn_brd_memcopy pfn_brd_mem_copy; /* Copies DSP Memory */ 988 fxn_brd_memcopy brd_mem_copy; /* Copies DSP Memory */
989 fxn_brd_memwrite pfn_brd_mem_write; /* Write DSP Memory w/o halt */ 989 fxn_brd_memwrite brd_mem_write; /* Write DSP Memory w/o halt */
990 fxn_brd_memmap pfn_brd_mem_map; /* Maps MPU mem to DSP mem */ 990 fxn_brd_memmap brd_mem_map; /* Maps MPU mem to DSP mem */
991 fxn_brd_memunmap pfn_brd_mem_un_map; /* Unmaps MPU mem to DSP mem */ 991 fxn_brd_memunmap brd_mem_un_map; /* Unmaps MPU mem to DSP mem */
992 fxn_chnl_create pfn_chnl_create; /* Create channel manager. */ 992 fxn_chnl_create pfn_chnl_create; /* Create channel manager. */
993 fxn_chnl_destroy pfn_chnl_destroy; /* Destroy channel manager. */ 993 fxn_chnl_destroy pfn_chnl_destroy; /* Destroy channel manager. */
994 fxn_chnl_open pfn_chnl_open; /* Create a new channel. */ 994 fxn_chnl_open pfn_chnl_open; /* Create a new channel. */
diff --git a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h
index c85d3da3fe2..b1a9072a1ff 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h
@@ -280,7 +280,7 @@ typedef int(*nldr_unloadfxn) (struct nldr_nodeobject *nldr_node_obj,
280 * ======== node_ldr_fxns ======== 280 * ======== node_ldr_fxns ========
281 */ 281 */
282struct node_ldr_fxns { 282struct node_ldr_fxns {
283 nldr_allocatefxn pfn_allocate; 283 nldr_allocatefxn allocate;
284 nldr_createfxn pfn_create; 284 nldr_createfxn pfn_create;
285 nldr_deletefxn pfn_delete; 285 nldr_deletefxn pfn_delete;
286 nldr_exitfxn pfn_exit; 286 nldr_exitfxn pfn_exit;
diff --git a/drivers/staging/tidspbridge/pmgr/cmm.c b/drivers/staging/tidspbridge/pmgr/cmm.c
index d2fb6a4c0e3..bc8571b53be 100644
--- a/drivers/staging/tidspbridge/pmgr/cmm.c
+++ b/drivers/staging/tidspbridge/pmgr/cmm.c
@@ -64,7 +64,7 @@
64struct cmm_allocator { /* sma */ 64struct cmm_allocator { /* sma */
65 unsigned int shm_base; /* Start of physical SM block */ 65 unsigned int shm_base; /* Start of physical SM block */
66 u32 ul_sm_size; /* Size of SM block in bytes */ 66 u32 ul_sm_size; /* Size of SM block in bytes */
67 unsigned int dw_vm_base; /* Start of VM block. (Dev driver 67 unsigned int vm_base; /* Start of VM block. (Dev driver
68 * context for 'sma') */ 68 * context for 'sma') */
69 u32 dsp_phys_addr_offset; /* DSP PA to GPP PA offset for this 69 u32 dsp_phys_addr_offset; /* DSP PA to GPP PA offset for this
70 * SM space */ 70 * SM space */
@@ -86,7 +86,7 @@ struct cmm_xlator { /* Pa<->Va translator object */
86 * base address for translator's ul_seg_id. 86 * base address for translator's ul_seg_id.
87 * Only 1 segment ID currently supported. 87 * Only 1 segment ID currently supported.
88 */ 88 */
89 unsigned int dw_virt_base; /* virtual base address */ 89 unsigned int virt_base; /* virtual base address */
90 u32 ul_virt_size; /* size of virt space in bytes */ 90 u32 ul_virt_size; /* size of virt space in bytes */
91 u32 ul_seg_id; /* Segment Id */ 91 u32 ul_seg_id; /* Segment Id */
92}; 92};
@@ -122,14 +122,14 @@ static struct cmm_xlatorattrs cmm_dfltxlatorattrs = {
122 0, /* dsp_bufs */ 122 0, /* dsp_bufs */
123 0, /* dsp_buf_size */ 123 0, /* dsp_buf_size */
124 NULL, /* vm_base */ 124 NULL, /* vm_base */
125 0, /* dw_vm_size */ 125 0, /* vm_size */
126}; 126};
127 127
128/* SM node representing a block of memory. */ 128/* SM node representing a block of memory. */
129struct cmm_mnode { 129struct cmm_mnode {
130 struct list_head link; /* must be 1st element */ 130 struct list_head link; /* must be 1st element */
131 u32 pa; /* Phys addr */ 131 u32 pa; /* Phys addr */
132 u32 dw_va; /* Virtual address in device process context */ 132 u32 va; /* Virtual address in device process context */
133 u32 ul_size; /* SM block size in bytes */ 133 u32 ul_size; /* SM block size in bytes */
134 u32 client_proc; /* Process that allocated this mem block */ 134 u32 client_proc; /* Process that allocated this mem block */
135}; 135};
@@ -200,7 +200,7 @@ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize,
200 * add to freelist */ 200 * add to freelist */
201 new_node = 201 new_node =
202 get_node(cmm_mgr_obj, pnode->pa + usize, 202 get_node(cmm_mgr_obj, pnode->pa + usize,
203 pnode->dw_va + usize, 203 pnode->va + usize,
204 (u32) delta_size); 204 (u32) delta_size);
205 /* leftovers go free */ 205 /* leftovers go free */
206 add_to_free_list(allocator, new_node); 206 add_to_free_list(allocator, new_node);
@@ -218,13 +218,13 @@ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize,
218 list_add_tail(&pnode->link, &allocator->in_use_list); 218 list_add_tail(&pnode->link, &allocator->in_use_list);
219 buf_pa = (void *)pnode->pa; /* physical address */ 219 buf_pa = (void *)pnode->pa; /* physical address */
220 /* clear mem */ 220 /* clear mem */
221 pbyte = (u8 *) pnode->dw_va; 221 pbyte = (u8 *) pnode->va;
222 for (cnt = 0; cnt < (s32) usize; cnt++, pbyte++) 222 for (cnt = 0; cnt < (s32) usize; cnt++, pbyte++)
223 *pbyte = 0; 223 *pbyte = 0;
224 224
225 if (pp_buf_va != NULL) { 225 if (pp_buf_va != NULL) {
226 /* Virtual address */ 226 /* Virtual address */
227 *pp_buf_va = (void *)pnode->dw_va; 227 *pp_buf_va = (void *)pnode->va;
228 } 228 }
229 } 229 }
230 mutex_unlock(&cmm_mgr_obj->cmm_lock); 230 mutex_unlock(&cmm_mgr_obj->cmm_lock);
@@ -450,8 +450,8 @@ int cmm_get_info(struct cmm_object *hcmm_mgr,
450 altr->dsp_base; 450 altr->dsp_base;
451 cmm_info_obj->seg_info[ul_seg - 1].ul_dsp_size = 451 cmm_info_obj->seg_info[ul_seg - 1].ul_dsp_size =
452 altr->ul_dsp_size; 452 altr->ul_dsp_size;
453 cmm_info_obj->seg_info[ul_seg - 1].dw_seg_base_va = 453 cmm_info_obj->seg_info[ul_seg - 1].seg_base_va =
454 altr->dw_vm_base - altr->ul_dsp_size; 454 altr->vm_base - altr->ul_dsp_size;
455 cmm_info_obj->seg_info[ul_seg - 1].ul_in_use_cnt = 0; 455 cmm_info_obj->seg_info[ul_seg - 1].ul_in_use_cnt = 0;
456 456
457 list_for_each_entry(curr, &altr->in_use_list, link) { 457 list_for_each_entry(curr, &altr->in_use_list, link) {
@@ -539,12 +539,12 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr,
539 psma->hcmm_mgr = hcmm_mgr; /* ref to parent */ 539 psma->hcmm_mgr = hcmm_mgr; /* ref to parent */
540 psma->shm_base = dw_gpp_base_pa; /* SM Base phys */ 540 psma->shm_base = dw_gpp_base_pa; /* SM Base phys */
541 psma->ul_sm_size = ul_size; /* SM segment size in bytes */ 541 psma->ul_sm_size = ul_size; /* SM segment size in bytes */
542 psma->dw_vm_base = gpp_base_va; 542 psma->vm_base = gpp_base_va;
543 psma->dsp_phys_addr_offset = dsp_addr_offset; 543 psma->dsp_phys_addr_offset = dsp_addr_offset;
544 psma->c_factor = c_factor; 544 psma->c_factor = c_factor;
545 psma->dsp_base = dw_dsp_base; 545 psma->dsp_base = dw_dsp_base;
546 psma->ul_dsp_size = ul_dsp_size; 546 psma->ul_dsp_size = ul_dsp_size;
547 if (psma->dw_vm_base == 0) { 547 if (psma->vm_base == 0) {
548 status = -EPERM; 548 status = -EPERM;
549 goto func_end; 549 goto func_end;
550 } 550 }
@@ -556,7 +556,7 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr,
556 556
557 /* Get a mem node for this hunk-o-memory */ 557 /* Get a mem node for this hunk-o-memory */
558 new_node = get_node(cmm_mgr_obj, dw_gpp_base_pa, 558 new_node = get_node(cmm_mgr_obj, dw_gpp_base_pa,
559 psma->dw_vm_base, ul_size); 559 psma->vm_base, ul_size);
560 /* Place node on the SM allocator's free list */ 560 /* Place node on the SM allocator's free list */
561 if (new_node) { 561 if (new_node) {
562 list_add_tail(&new_node->link, &psma->free_list); 562 list_add_tail(&new_node->link, &psma->free_list);
@@ -649,8 +649,8 @@ static void un_register_gppsm_seg(struct cmm_allocator *psma)
649 kfree(curr); 649 kfree(curr);
650 } 650 }
651 651
652 if ((void *)psma->dw_vm_base != NULL) 652 if ((void *)psma->vm_base != NULL)
653 MEM_UNMAP_LINEAR_ADDRESS((void *)psma->dw_vm_base); 653 MEM_UNMAP_LINEAR_ADDRESS((void *)psma->vm_base);
654 654
655 /* Free allocator itself */ 655 /* Free allocator itself */
656 kfree(psma); 656 kfree(psma);
@@ -705,7 +705,7 @@ static struct cmm_mnode *get_node(struct cmm_object *cmm_mgr_obj, u32 dw_pa,
705 } 705 }
706 706
707 pnode->pa = dw_pa; 707 pnode->pa = dw_pa;
708 pnode->dw_va = dw_va; 708 pnode->va = dw_va;
709 pnode->ul_size = ul_size; 709 pnode->ul_size = ul_size;
710 710
711 return pnode; 711 return pnode;
@@ -770,7 +770,7 @@ static void add_to_free_list(struct cmm_allocator *allocator,
770 } 770 }
771 if (curr->pa == NEXT_PA(node)) { 771 if (curr->pa == NEXT_PA(node)) {
772 curr->pa = node->pa; 772 curr->pa = node->pa;
773 curr->dw_va = node->dw_va; 773 curr->va = node->va;
774 curr->ul_size += node->ul_size; 774 curr->ul_size += node->ul_size;
775 delete_node(allocator->hcmm_mgr, node); 775 delete_node(allocator->hcmm_mgr, node);
776 return; 776 return;
@@ -925,10 +925,10 @@ int cmm_xlator_info(struct cmm_xlatorobject *xlator, u8 ** paddr,
925 if (xlator_obj) { 925 if (xlator_obj) {
926 if (set_info) { 926 if (set_info) {
927 /* set translators virtual address range */ 927 /* set translators virtual address range */
928 xlator_obj->dw_virt_base = (u32) *paddr; 928 xlator_obj->virt_base = (u32) *paddr;
929 xlator_obj->ul_virt_size = ul_size; 929 xlator_obj->ul_virt_size = ul_size;
930 } else { /* return virt base address */ 930 } else { /* return virt base address */
931 *paddr = (u8 *) xlator_obj->dw_virt_base; 931 *paddr = (u8 *) xlator_obj->virt_base;
932 } 932 }
933 } else { 933 } else {
934 status = -EFAULT; 934 status = -EFAULT;
@@ -969,18 +969,18 @@ void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, void *paddr,
969 dw_offset = (u8 *) paddr - (u8 *) (allocator->shm_base - 969 dw_offset = (u8 *) paddr - (u8 *) (allocator->shm_base -
970 allocator-> 970 allocator->
971 ul_dsp_size); 971 ul_dsp_size);
972 dw_addr_xlate = xlator_obj->dw_virt_base + dw_offset; 972 dw_addr_xlate = xlator_obj->virt_base + dw_offset;
973 /* Check if translated Va base is in range */ 973 /* Check if translated Va base is in range */
974 if ((dw_addr_xlate < xlator_obj->dw_virt_base) || 974 if ((dw_addr_xlate < xlator_obj->virt_base) ||
975 (dw_addr_xlate >= 975 (dw_addr_xlate >=
976 (xlator_obj->dw_virt_base + 976 (xlator_obj->virt_base +
977 xlator_obj->ul_virt_size))) { 977 xlator_obj->ul_virt_size))) {
978 dw_addr_xlate = 0; /* bad address */ 978 dw_addr_xlate = 0; /* bad address */
979 } 979 }
980 } else { 980 } else {
981 /* Gpp PA = Gpp Base + offset */ 981 /* Gpp PA = Gpp Base + offset */
982 dw_offset = 982 dw_offset =
983 (u8 *) paddr - (u8 *) xlator_obj->dw_virt_base; 983 (u8 *) paddr - (u8 *) xlator_obj->virt_base;
984 dw_addr_xlate = 984 dw_addr_xlate =
985 allocator->shm_base - allocator->ul_dsp_size + 985 allocator->shm_base - allocator->ul_dsp_size +
986 dw_offset; 986 dw_offset;
diff --git a/drivers/staging/tidspbridge/pmgr/dev.c b/drivers/staging/tidspbridge/pmgr/dev.c
index e328dc1e169..63ca8c7c550 100644
--- a/drivers/staging/tidspbridge/pmgr/dev.c
+++ b/drivers/staging/tidspbridge/pmgr/dev.c
@@ -1082,17 +1082,17 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns,
1082 STORE_FXN(fxn_dev_create, pfn_dev_create); 1082 STORE_FXN(fxn_dev_create, pfn_dev_create);
1083 STORE_FXN(fxn_dev_destroy, pfn_dev_destroy); 1083 STORE_FXN(fxn_dev_destroy, pfn_dev_destroy);
1084 STORE_FXN(fxn_dev_ctrl, pfn_dev_cntrl); 1084 STORE_FXN(fxn_dev_ctrl, pfn_dev_cntrl);
1085 STORE_FXN(fxn_brd_monitor, pfn_brd_monitor); 1085 STORE_FXN(fxn_brd_monitor, brd_monitor);
1086 STORE_FXN(fxn_brd_start, pfn_brd_start); 1086 STORE_FXN(fxn_brd_start, pfn_brd_start);
1087 STORE_FXN(fxn_brd_stop, pfn_brd_stop); 1087 STORE_FXN(fxn_brd_stop, pfn_brd_stop);
1088 STORE_FXN(fxn_brd_status, pfn_brd_status); 1088 STORE_FXN(fxn_brd_status, pfn_brd_status);
1089 STORE_FXN(fxn_brd_read, pfn_brd_read); 1089 STORE_FXN(fxn_brd_read, brd_read);
1090 STORE_FXN(fxn_brd_write, pfn_brd_write); 1090 STORE_FXN(fxn_brd_write, pfn_brd_write);
1091 STORE_FXN(fxn_brd_setstate, pfn_brd_set_state); 1091 STORE_FXN(fxn_brd_setstate, pfn_brd_set_state);
1092 STORE_FXN(fxn_brd_memcopy, pfn_brd_mem_copy); 1092 STORE_FXN(fxn_brd_memcopy, brd_mem_copy);
1093 STORE_FXN(fxn_brd_memwrite, pfn_brd_mem_write); 1093 STORE_FXN(fxn_brd_memwrite, brd_mem_write);
1094 STORE_FXN(fxn_brd_memmap, pfn_brd_mem_map); 1094 STORE_FXN(fxn_brd_memmap, brd_mem_map);
1095 STORE_FXN(fxn_brd_memunmap, pfn_brd_mem_un_map); 1095 STORE_FXN(fxn_brd_memunmap, brd_mem_un_map);
1096 STORE_FXN(fxn_chnl_create, pfn_chnl_create); 1096 STORE_FXN(fxn_chnl_create, pfn_chnl_create);
1097 STORE_FXN(fxn_chnl_destroy, pfn_chnl_destroy); 1097 STORE_FXN(fxn_chnl_destroy, pfn_chnl_destroy);
1098 STORE_FXN(fxn_chnl_open, pfn_chnl_open); 1098 STORE_FXN(fxn_chnl_open, pfn_chnl_open);
@@ -1123,11 +1123,11 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns,
1123 DBC_ENSURE(intf_fxns->pfn_dev_create != NULL); 1123 DBC_ENSURE(intf_fxns->pfn_dev_create != NULL);
1124 DBC_ENSURE(intf_fxns->pfn_dev_destroy != NULL); 1124 DBC_ENSURE(intf_fxns->pfn_dev_destroy != NULL);
1125 DBC_ENSURE(intf_fxns->pfn_dev_cntrl != NULL); 1125 DBC_ENSURE(intf_fxns->pfn_dev_cntrl != NULL);
1126 DBC_ENSURE(intf_fxns->pfn_brd_monitor != NULL); 1126 DBC_ENSURE(intf_fxns->brd_monitor != NULL);
1127 DBC_ENSURE(intf_fxns->pfn_brd_start != NULL); 1127 DBC_ENSURE(intf_fxns->pfn_brd_start != NULL);
1128 DBC_ENSURE(intf_fxns->pfn_brd_stop != NULL); 1128 DBC_ENSURE(intf_fxns->pfn_brd_stop != NULL);
1129 DBC_ENSURE(intf_fxns->pfn_brd_status != NULL); 1129 DBC_ENSURE(intf_fxns->pfn_brd_status != NULL);
1130 DBC_ENSURE(intf_fxns->pfn_brd_read != NULL); 1130 DBC_ENSURE(intf_fxns->brd_read != NULL);
1131 DBC_ENSURE(intf_fxns->pfn_brd_write != NULL); 1131 DBC_ENSURE(intf_fxns->pfn_brd_write != NULL);
1132 DBC_ENSURE(intf_fxns->pfn_chnl_create != NULL); 1132 DBC_ENSURE(intf_fxns->pfn_chnl_create != NULL);
1133 DBC_ENSURE(intf_fxns->pfn_chnl_destroy != NULL); 1133 DBC_ENSURE(intf_fxns->pfn_chnl_destroy != NULL);
diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c
index 454fcc82584..8dd05783059 100644
--- a/drivers/staging/tidspbridge/rmgr/node.c
+++ b/drivers/staging/tidspbridge/rmgr/node.c
@@ -575,7 +575,7 @@ func_cont:
575 if (!status) { 575 if (!status) {
576 /* Create object for dynamic loading */ 576 /* Create object for dynamic loading */
577 577
578 status = hnode_mgr->nldr_fxns.pfn_allocate(hnode_mgr->nldr_obj, 578 status = hnode_mgr->nldr_fxns.allocate(hnode_mgr->nldr_obj,
579 (void *)pnode, 579 (void *)pnode,
580 &pnode->dcd_props. 580 &pnode->dcd_props.
581 obj_data.node_obj, 581 obj_data.node_obj,
@@ -3075,7 +3075,7 @@ static u32 ovly(void *priv_ref, u32 dsp_run_addr, u32 dsp_load_addr,
3075 status = dev_get_bridge_context(hnode_mgr->hdev_obj, &hbridge_context); 3075 status = dev_get_bridge_context(hnode_mgr->hdev_obj, &hbridge_context);
3076 if (!status) { 3076 if (!status) {
3077 status = 3077 status =
3078 (*intf_fxns->pfn_brd_mem_copy) (hbridge_context, 3078 (*intf_fxns->brd_mem_copy) (hbridge_context,
3079 dsp_run_addr, dsp_load_addr, 3079 dsp_run_addr, dsp_load_addr,
3080 ul_num_bytes, (u32) mem_space); 3080 ul_num_bytes, (u32) mem_space);
3081 if (!status) 3081 if (!status)
@@ -3117,7 +3117,7 @@ static u32 mem_write(void *priv_ref, u32 dsp_add, void *pbuf,
3117 /* Call new MemWrite function */ 3117 /* Call new MemWrite function */
3118 intf_fxns = hnode_mgr->intf_fxns; 3118 intf_fxns = hnode_mgr->intf_fxns;
3119 status = dev_get_bridge_context(hnode_mgr->hdev_obj, &hbridge_context); 3119 status = dev_get_bridge_context(hnode_mgr->hdev_obj, &hbridge_context);
3120 status = (*intf_fxns->pfn_brd_mem_write) (hbridge_context, pbuf, 3120 status = (*intf_fxns->brd_mem_write) (hbridge_context, pbuf,
3121 dsp_add, ul_num_bytes, mem_sect_type); 3121 dsp_add, ul_num_bytes, mem_sect_type);
3122 3122
3123 return ul_num_bytes; 3123 return ul_num_bytes;
diff --git a/drivers/staging/tidspbridge/rmgr/proc.c b/drivers/staging/tidspbridge/rmgr/proc.c
index d5f6719774d..03bc2140325 100644
--- a/drivers/staging/tidspbridge/rmgr/proc.c
+++ b/drivers/staging/tidspbridge/rmgr/proc.c
@@ -1397,7 +1397,7 @@ int proc_map(void *hprocessor, void *pmpu_addr, u32 ul_size,
1397 if (!map_obj) 1397 if (!map_obj)
1398 status = -ENOMEM; 1398 status = -ENOMEM;
1399 else 1399 else
1400 status = (*p_proc_object->intf_fxns->pfn_brd_mem_map) 1400 status = (*p_proc_object->intf_fxns->brd_mem_map)
1401 (p_proc_object->hbridge_context, pa_align, va_align, 1401 (p_proc_object->hbridge_context, pa_align, va_align,
1402 size_align, ul_map_attr, map_obj->pages); 1402 size_align, ul_map_attr, map_obj->pages);
1403 } 1403 }
@@ -1720,7 +1720,7 @@ int proc_un_map(void *hprocessor, void *map_addr,
1720 status = dmm_un_map_memory(dmm_mgr, (u32) va_align, &size_align); 1720 status = dmm_un_map_memory(dmm_mgr, (u32) va_align, &size_align);
1721 /* Remove mapping from the page tables. */ 1721 /* Remove mapping from the page tables. */
1722 if (!status) { 1722 if (!status) {
1723 status = (*p_proc_object->intf_fxns->pfn_brd_mem_un_map) 1723 status = (*p_proc_object->intf_fxns->brd_mem_un_map)
1724 (p_proc_object->hbridge_context, va_align, size_align); 1724 (p_proc_object->hbridge_context, va_align, size_align);
1725 } 1725 }
1726 1726
@@ -1828,7 +1828,7 @@ static int proc_monitor(struct proc_object *proc_obj)
1828 } 1828 }
1829 } 1829 }
1830 /* Place the Board in the Monitor State */ 1830 /* Place the Board in the Monitor State */
1831 if (!((*proc_obj->intf_fxns->pfn_brd_monitor) 1831 if (!((*proc_obj->intf_fxns->brd_monitor)
1832 (proc_obj->hbridge_context))) { 1832 (proc_obj->hbridge_context))) {
1833 status = 0; 1833 status = 0;
1834 if (!((*proc_obj->intf_fxns->pfn_brd_status) 1834 if (!((*proc_obj->intf_fxns->pfn_brd_status)
diff --git a/drivers/staging/tidspbridge/rmgr/strm.c b/drivers/staging/tidspbridge/rmgr/strm.c
index d36b3165989..4adb7a00cf7 100644
--- a/drivers/staging/tidspbridge/rmgr/strm.c
+++ b/drivers/staging/tidspbridge/rmgr/strm.c
@@ -344,7 +344,7 @@ int strm_get_info(struct strm_object *stream_obj,
344 stream_info->user_strm->ul_number_bytes = chnl_info_obj.bytes_tx; 344 stream_info->user_strm->ul_number_bytes = chnl_info_obj.bytes_tx;
345 stream_info->user_strm->sync_object_handle = chnl_info_obj.event_obj; 345 stream_info->user_strm->sync_object_handle = chnl_info_obj.event_obj;
346 /* Determine stream state based on channel state and info */ 346 /* Determine stream state based on channel state and info */
347 if (chnl_info_obj.dw_state & CHNL_STATEEOS) { 347 if (chnl_info_obj.state & CHNL_STATEEOS) {
348 stream_info->user_strm->ss_stream_state = STREAM_DONE; 348 stream_info->user_strm->ss_stream_state = STREAM_DONE;
349 } else { 349 } else {
350 if (chnl_info_obj.cio_cs > 0) 350 if (chnl_info_obj.cio_cs > 0)