59 files changed, 11427 insertions, 0 deletions
diff --git a/drivers/video/tegra/host/Makefile b/drivers/video/tegra/host/Makefile
new file mode 100644
index 00000000000..0180885af4d
--- /dev/null
+++ b/drivers/video/tegra/host/Makefile
@@ -0,0 +1,23 @@
+GCOV_PROFILE := y
+nvhost-objs = \
+        nvhost_acm.o \
+        nvhost_syncpt.o \
+        nvhost_cdma.o \
+        nvhost_intr.o \
+        nvhost_channel.o \
+        nvhost_job.o \
+        bus.o \
+        dev.o \
+        debug.o \
+        bus_client.o
+obj-$(CONFIG_TEGRA_GRHOST) += mpe/
+obj-$(CONFIG_TEGRA_GRHOST) += gr3d/
+obj-$(CONFIG_TEGRA_GRHOST) += host1x/
+obj-$(CONFIG_TEGRA_GRHOST) += t20/
+obj-$(CONFIG_TEGRA_GRHOST) += t30/
+obj-$(CONFIG_TEGRA_GRHOST) += dsi/
+obj-$(CONFIG_TEGRA_GRHOST) += gr2d/
+obj-$(CONFIG_TEGRA_GRHOST) += isp/
+obj-$(CONFIG_TEGRA_GRHOST) += vi/
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost.o
diff --git a/drivers/video/tegra/host/bus.c b/drivers/video/tegra/host/bus.c
new file mode 100644
index 00000000000..774aac7bd43
--- /dev/null
+++ b/drivers/video/tegra/host/bus.c
@@ -0,0 +1,569 @@
+/*
+ * drivers/video/tegra/host/bus.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Erik Gilling <konkers@google.com>
+ *
+ * Copyright (C) 2010-2012 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/pm_runtime.h>
+#include <linux/nvhost.h>
+#include "dev.h"
+struct nvhost_master *nvhost;
+struct resource *nvhost_get_resource(struct nvhost_device *dev,
+                                       unsigned int type, unsigned int num)
+{
+        int i;
+        for (i = 0; i < dev->num_resources; i++) {
+                struct resource *r = &dev->resource[i];
+                if (type == resource_type(r) && num-- == 0)
+                        return r;
+        }
+        return NULL;
+}
+EXPORT_SYMBOL_GPL(nvhost_get_resource);
+int nvhost_get_irq(struct nvhost_device *dev, unsigned int num)
+{
+        struct resource *r = nvhost_get_resource(dev, IORESOURCE_IRQ, num);
+        return r ? r->start : -ENXIO;
+}
+EXPORT_SYMBOL_GPL(nvhost_get_irq);
+struct resource *nvhost_get_resource_byname(struct nvhost_device *dev,
+                                              unsigned int type,
+                                              const char *name)
+{
+        int i;
+        for (i = 0; i < dev->num_resources; i++) {
+                struct resource *r = &dev->resource[i];
+                if (type == resource_type(r) && !strcmp(r->name, name))
+                        return r;
+        }
+        return NULL;
+}
+EXPORT_SYMBOL_GPL(nvhost_get_resource_byname);
+int nvhost_get_irq_byname(struct nvhost_device *dev, const char *name)
+{
+        struct resource *r = nvhost_get_resource_byname(dev, IORESOURCE_IRQ,
+                                                          name);
+        return r ? r->start : -ENXIO;
+}
+EXPORT_SYMBOL_GPL(nvhost_get_irq_byname);
+static int nvhost_drv_probe(struct device *_dev)
+{
+        struct nvhost_driver *drv = to_nvhost_driver(_dev->driver);
+        struct nvhost_device *dev = to_nvhost_device(_dev);
+        return drv->probe(dev);
+}
+static int nvhost_drv_remove(struct device *_dev)
+{
+        struct nvhost_driver *drv = to_nvhost_driver(_dev->driver);
+        struct nvhost_device *dev = to_nvhost_device(_dev);
+        return drv->remove(dev);
+}
+static void nvhost_drv_shutdown(struct device *_dev)
+{
+        struct nvhost_driver *drv = to_nvhost_driver(_dev->driver);
+        struct nvhost_device *dev = to_nvhost_device(_dev);
+        drv->shutdown(dev);
+}
+int nvhost_driver_register(struct nvhost_driver *drv)
+{
+        drv->driver.bus = &nvhost_bus_type;
+        if (drv->probe)
+                drv->driver.probe = nvhost_drv_probe;
+        if (drv->remove)
+                drv->driver.remove = nvhost_drv_remove;
+        if (drv->shutdown)
+                drv->driver.shutdown = nvhost_drv_shutdown;
+        return driver_register(&drv->driver);
+}
+EXPORT_SYMBOL(nvhost_driver_register);
+void nvhost_driver_unregister(struct nvhost_driver *drv)
+{
+        driver_unregister(&drv->driver);
+}
+EXPORT_SYMBOL_GPL(nvhost_driver_unregister);
+int nvhost_device_register(struct nvhost_device *dev)
+{
+        int i, ret = 0;
+        if (!dev)
+                return -EINVAL;
+        device_initialize(&dev->dev);
+        /*  If the dev does not have a parent, assign host1x as parent */
+        if (!dev->dev.parent && nvhost && nvhost->dev != dev)
+                dev->dev.parent = &nvhost->dev->dev;
+        dev->dev.bus = &nvhost_bus_type;
+        if (dev->id != -1)
+                dev_set_name(&dev->dev, "%s.%d", dev->name,  dev->id);
+        else
+                dev_set_name(&dev->dev, "%s", dev->name);
+        for (i = 0; i < dev->num_resources; i++) {
+                struct resource *p, *r = &dev->resource[i];
+                if (r->name == NULL)
+                        r->name = dev_name(&dev->dev);
+                p = r->parent;
+                if (!p) {
+                        if (resource_type(r) == IORESOURCE_MEM)
+                                p = &iomem_resource;
+                        else if (resource_type(r) == IORESOURCE_IO)
+                                p = &ioport_resource;
+                }
+                if (p && insert_resource(p, r)) {
+                        pr_err("%s: failed to claim resource %d\n",
+                               dev_name(&dev->dev), i);
+                        ret = -EBUSY;
+                        goto failed;
+                }
+        }
+        ret = device_add(&dev->dev);
+        if (ret == 0)
+                return ret;
+failed:
+        while (--i >= 0) {
+                struct resource *r = &dev->resource[i];
+                unsigned long type = resource_type(r);
+                if (type == IORESOURCE_MEM || type == IORESOURCE_IO)
+                        release_resource(r);
+        }
+        return ret;
+}
+EXPORT_SYMBOL_GPL(nvhost_device_register);
+void nvhost_device_unregister(struct nvhost_device *dev)
+{
+        int i;
+        if (dev) {
+                device_del(&dev->dev);
+                for (i = 0; i < dev->num_resources; i++) {
+                        struct resource *r = &dev->resource[i];
+                        unsigned long type = resource_type(r);
+                        if (type == IORESOURCE_MEM || type == IORESOURCE_IO)
+                                release_resource(r);
+                }
+                put_device(&dev->dev);
+        }
+}
+EXPORT_SYMBOL_GPL(nvhost_device_unregister);
+static int nvhost_bus_match(struct device *_dev, struct device_driver *drv)
+{
+        struct nvhost_device *dev = to_nvhost_device(_dev);
+        return !strncmp(dev->name, drv->name, strlen(drv->name));
+}
+#ifdef CONFIG_PM_SLEEP
+static int nvhost_legacy_suspend(struct device *dev, pm_message_t mesg)
+{
+        struct nvhost_driver *pdrv = to_nvhost_driver(dev->driver);
+        struct nvhost_device *pdev = to_nvhost_device(dev);
+        int ret = 0;
+        if (dev->driver && pdrv->suspend)
+                ret = pdrv->suspend(pdev, mesg);
+        return ret;
+}
+static int nvhost_legacy_resume(struct device *dev)
+{
+        struct nvhost_driver *pdrv = to_nvhost_driver(dev->driver);
+        struct nvhost_device *pdev = to_nvhost_device(dev);
+        int ret = 0;
+        if (dev->driver && pdrv->resume)
+                ret = pdrv->resume(pdev);
+        return ret;
+}
+static int nvhost_pm_prepare(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (drv && drv->pm && drv->pm->prepare)
+                ret = drv->pm->prepare(dev);
+        return ret;
+}
+static void nvhost_pm_complete(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        if (drv && drv->pm && drv->pm->complete)
+                drv->pm->complete(dev);
+}
+#else /* !CONFIG_PM_SLEEP */
+#define nvhost_pm_prepare               NULL
+#define nvhost_pm_complete              NULL
+#endif /* !CONFIG_PM_SLEEP */
+#ifdef CONFIG_SUSPEND
+int __weak nvhost_pm_suspend(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->suspend)
+                        ret = drv->pm->suspend(dev);
+        } else {
+                ret = nvhost_legacy_suspend(dev, PMSG_SUSPEND);
+        }
+        return ret;
+}
+int __weak nvhost_pm_suspend_noirq(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->suspend_noirq)
+                        ret = drv->pm->suspend_noirq(dev);
+        }
+        return ret;
+}
+int __weak nvhost_pm_resume(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->resume)
+                        ret = drv->pm->resume(dev);
+        } else {
+                ret = nvhost_legacy_resume(dev);
+        }
+        return ret;
+}
+int __weak nvhost_pm_resume_noirq(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->resume_noirq)
+                        ret = drv->pm->resume_noirq(dev);
+        }
+        return ret;
+}
+#else /* !CONFIG_SUSPEND */
+#define nvhost_pm_suspend               NULL
+#define nvhost_pm_resume                NULL
+#define nvhost_pm_suspend_noirq NULL
+#define nvhost_pm_resume_noirq  NULL
+#endif /* !CONFIG_SUSPEND */
+#ifdef CONFIG_HIBERNATION
+static int nvhost_pm_freeze(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->freeze)
+                        ret = drv->pm->freeze(dev);
+        } else {
+                ret = nvhost_legacy_suspend(dev, PMSG_FREEZE);
+        }
+        return ret;
+}
+static int nvhost_pm_freeze_noirq(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->freeze_noirq)
+                        ret = drv->pm->freeze_noirq(dev);
+        }
+        return ret;
+}
+static int nvhost_pm_thaw(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->thaw)
+                        ret = drv->pm->thaw(dev);
+        } else {
+                ret = nvhost_legacy_resume(dev);
+        }
+        return ret;
+}
+static int nvhost_pm_thaw_noirq(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->thaw_noirq)
+                        ret = drv->pm->thaw_noirq(dev);
+        }
+        return ret;
+}
+static int nvhost_pm_poweroff(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->poweroff)
+                        ret = drv->pm->poweroff(dev);
+        } else {
+                ret = nvhost_legacy_suspend(dev, PMSG_HIBERNATE);
+        }
+        return ret;
+}
+static int nvhost_pm_poweroff_noirq(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->poweroff_noirq)
+                        ret = drv->pm->poweroff_noirq(dev);
+        }
+        return ret;
+}
+static int nvhost_pm_restore(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->restore)
+                        ret = drv->pm->restore(dev);
+        } else {
+                ret = nvhost_legacy_resume(dev);
+        }
+        return ret;
+}
+static int nvhost_pm_restore_noirq(struct device *dev)
+{
+        struct device_driver *drv = dev->driver;
+        int ret = 0;
+        if (!drv)
+                return 0;
+        if (drv->pm) {
+                if (drv->pm->restore_noirq)
+                        ret = drv->pm->restore_noirq(dev);
+        }
+        return ret;
+}
+#else /* !CONFIG_HIBERNATION */
+#define nvhost_pm_freeze                NULL
+#define nvhost_pm_thaw          NULL
+#define nvhost_pm_poweroff              NULL
+#define nvhost_pm_restore               NULL
+#define nvhost_pm_freeze_noirq  NULL
+#define nvhost_pm_thaw_noirq            NULL
+#define nvhost_pm_poweroff_noirq        NULL
+#define nvhost_pm_restore_noirq NULL
+#endif /* !CONFIG_HIBERNATION */
+#ifdef CONFIG_PM_RUNTIME
+int __weak nvhost_pm_runtime_suspend(struct device *dev)
+{
+        return pm_generic_runtime_suspend(dev);
+};
+int __weak nvhost_pm_runtime_resume(struct device *dev)
+{
+        return pm_generic_runtime_resume(dev);
+};
+int __weak nvhost_pm_runtime_idle(struct device *dev)
+{
+        return pm_generic_runtime_idle(dev);
+};
+#else /* !CONFIG_PM_RUNTIME */
+#define nvhost_pm_runtime_suspend NULL
+#define nvhost_pm_runtime_resume NULL
+#define nvhost_pm_runtime_idle NULL
+#endif /* !CONFIG_PM_RUNTIME */
+static const struct dev_pm_ops nvhost_dev_pm_ops = {
+        .prepare = nvhost_pm_prepare,
+        .complete = nvhost_pm_complete,
+        .suspend = nvhost_pm_suspend,
+        .resume = nvhost_pm_resume,
+        .freeze = nvhost_pm_freeze,
+        .thaw = nvhost_pm_thaw,
+        .poweroff = nvhost_pm_poweroff,
+        .restore = nvhost_pm_restore,
+        .suspend_noirq = nvhost_pm_suspend_noirq,
+        .resume_noirq = nvhost_pm_resume_noirq,
+        .freeze_noirq = nvhost_pm_freeze_noirq,
+        .thaw_noirq = nvhost_pm_thaw_noirq,
+        .poweroff_noirq = nvhost_pm_poweroff_noirq,
+        .restore_noirq = nvhost_pm_restore_noirq,
+        .runtime_suspend = nvhost_pm_runtime_suspend,
+        .runtime_resume = nvhost_pm_runtime_resume,
+        .runtime_idle = nvhost_pm_runtime_idle,
+};
+struct bus_type nvhost_bus_type = {
+        .name           = "nvhost",
+        .match          = nvhost_bus_match,
+        .pm             = &nvhost_dev_pm_ops,
+};
+EXPORT_SYMBOL(nvhost_bus_type);
+static int set_parent(struct device *dev, void *data)
+{
+        struct nvhost_device *ndev = to_nvhost_device(dev);
+        struct nvhost_master *host = data;
+        if (!dev->parent && ndev != host->dev)
+                dev->parent = &host->dev->dev;
+        return 0;
+}
+int nvhost_bus_add_host(struct nvhost_master *host)
+{
+        nvhost = host;
+        /*  Assign host1x as parent to all devices in nvhost bus */
+        bus_for_each_dev(&nvhost_bus_type, NULL, host, set_parent);
+        return 0;
+}
+int nvhost_bus_init(void)
+{
+        int err;
+        pr_info("host1x bus init\n");
+        err = bus_register(&nvhost_bus_type);
+        return err;
+}
+postcore_initcall(nvhost_bus_init);
diff --git a/drivers/video/tegra/host/bus_client.c b/drivers/video/tegra/host/bus_client.c
new file mode 100644
index 00000000000..940f04a40e8
--- /dev/null
+++ b/drivers/video/tegra/host/bus_client.c
@@ -0,0 +1,606 @@
+/*
+ * drivers/video/tegra/host/bus_client.c
+ *
+ * Tegra Graphics Host Client Module
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/spinlock.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#include <linux/file.h>
+#include <linux/clk.h>
+#include <linux/hrtimer.h>
+#include <trace/events/nvhost.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/nvhost.h>
+#include <linux/nvhost_ioctl.h>
+#include <mach/nvmap.h>
+#include <mach/gpufuse.h>
+#include <mach/hardware.h>
+#include <mach/iomap.h>
+#include "debug.h"
+#include "bus_client.h"
+#include "dev.h"
+void nvhost_read_module_regs(struct nvhost_device *ndev,
+                        u32 offset, int count, u32 *values)
+{
+        void __iomem *p = ndev->aperture + offset;
+        nvhost_module_busy(ndev);
+        while (count--) {
+                *(values++) = readl(p);
+                p += 4;
+        }
+        rmb();
+        nvhost_module_idle(ndev);
+}
+void nvhost_write_module_regs(struct nvhost_device *ndev,
+                        u32 offset, int count, const u32 *values)
+{
+        void __iomem *p = ndev->aperture + offset;
+        nvhost_module_busy(ndev);
+        while (count--) {
+                writel(*(values++), p);
+                p += 4;
+        }
+        wmb();
+        nvhost_module_idle(ndev);
+}
+struct nvhost_channel_userctx {
+        struct nvhost_channel *ch;
+        struct nvhost_hwctx *hwctx;
+        struct nvhost_submit_hdr_ext hdr;
+        int num_relocshifts;
+        struct nvhost_job *job;
+        struct nvmap_client *nvmap;
+        u32 timeout;
+        u32 priority;
+        int clientid;
+};
+/*
+ * Write cmdbuf to ftrace output. Checks if cmdbuf contents should be output
+ * and mmaps the cmdbuf contents if required.
+ */
+static void trace_write_cmdbufs(struct nvhost_job *job)
+{
+        struct nvmap_handle_ref handle;
+        void *mem = NULL;
+        int i = 0;
+        for (i = 0; i < job->num_gathers; i++) {
+                struct nvhost_channel_gather *gather = &job->gathers[i];
+                if (nvhost_debug_trace_cmdbuf) {
+                        handle.handle = nvmap_id_to_handle(gather->mem_id);
+                        mem = nvmap_mmap(&handle);
+                        if (IS_ERR_OR_NULL(mem))
+                                mem = NULL;
+                };
+                if (mem) {
+                        u32 i;
+                        /*
+                         * Write in batches of 128 as there seems to be a limit
+                         * of how much you can output to ftrace at once.
+                         */
+                        for (i = 0; i < gather->words; i += TRACE_MAX_LENGTH) {
+                                trace_nvhost_channel_write_cmdbuf_data(
+                                        job->ch->dev->name,
+                                        gather->mem_id,
+                                        min(gather->words - i,
+                                            TRACE_MAX_LENGTH),
+                                        gather->offset + i * sizeof(u32),
+                                        mem);
+                        }
+                        nvmap_munmap(&handle, mem);
+                }
+        }
+}
+static int nvhost_channelrelease(struct inode *inode, struct file *filp)
+{
+        struct nvhost_channel_userctx *priv = filp->private_data;
+        trace_nvhost_channel_release(priv->ch->dev->name);
+        filp->private_data = NULL;
+        nvhost_module_remove_client(priv->ch->dev, priv);
+        nvhost_putchannel(priv->ch, priv->hwctx);
+        if (priv->hwctx)
+                priv->ch->ctxhandler->put(priv->hwctx);
+        if (priv->job)
+                nvhost_job_put(priv->job);
+        nvmap_client_put(priv->nvmap);
+        kfree(priv);
+        return 0;
+}
+static int nvhost_channelopen(struct inode *inode, struct file *filp)
+{
+        struct nvhost_channel_userctx *priv;
+        struct nvhost_channel *ch;
+        ch = container_of(inode->i_cdev, struct nvhost_channel, cdev);
+        ch = nvhost_getchannel(ch);
+        if (!ch)
+                return -ENOMEM;
+        trace_nvhost_channel_open(ch->dev->name);
+        priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+        if (!priv) {
+                nvhost_putchannel(ch, NULL);
+                return -ENOMEM;
+        }
+        filp->private_data = priv;
+        priv->ch = ch;
+        nvhost_module_add_client(ch->dev, priv);
+        if (ch->ctxhandler && ch->ctxhandler->alloc) {
+                priv->hwctx = ch->ctxhandler->alloc(ch->ctxhandler, ch);
+                if (!priv->hwctx)
+                        goto fail;
+        }
+        priv->priority = NVHOST_PRIORITY_MEDIUM;
+        priv->clientid = atomic_add_return(1,
+                        &nvhost_get_host(ch->dev)->clientid);
+        priv->job = nvhost_job_alloc(ch, priv->hwctx, &priv->hdr,
+                        NULL, priv->priority, priv->clientid);
+        if (!priv->job)
+                goto fail;
+        return 0;
+fail:
+        nvhost_channelrelease(inode, filp);
+        return -ENOMEM;
+}
+static int set_submit(struct nvhost_channel_userctx *ctx)
+{
+        struct device *device = &ctx->ch->dev->dev;
+        /* submit should have at least 1 cmdbuf */
+        if (!ctx->hdr.num_cmdbufs)
+                return -EIO;
+        if (!ctx->nvmap) {
+                dev_err(device, "no nvmap context set\n");
+                return -EFAULT;
+        }
+        ctx->job = nvhost_job_realloc(ctx->job,
+                        ctx->hwctx,
+                        &ctx->hdr,
+                        ctx->nvmap,
+                        ctx->priority,
+                        ctx->clientid);
+        if (!ctx->job)
+                return -ENOMEM;
+        ctx->job->timeout = ctx->timeout;
+        if (ctx->hdr.submit_version >= NVHOST_SUBMIT_VERSION_V2)
+                ctx->num_relocshifts = ctx->hdr.num_relocs;
+        return 0;
+}
+static void reset_submit(struct nvhost_channel_userctx *ctx)
+{
+        ctx->hdr.num_cmdbufs = 0;
+        ctx->hdr.num_relocs = 0;
+        ctx->num_relocshifts = 0;
+        ctx->hdr.num_waitchks = 0;
+}
+static ssize_t nvhost_channelwrite(struct file *filp, const char __user *buf,
+                                size_t count, loff_t *offp)
+{
+        struct nvhost_channel_userctx *priv = filp->private_data;
+        size_t remaining = count;
+        int err = 0;
+        struct nvhost_job *job = priv->job;
+        struct nvhost_submit_hdr_ext *hdr = &priv->hdr;
+        const char *chname = priv->ch->dev->name;
+        if (!job)
+                return -EIO;
+        while (remaining) {
+                size_t consumed;
+                if (!hdr->num_relocs &&
+                    !priv->num_relocshifts &&
+                    !hdr->num_cmdbufs &&
+                    !hdr->num_waitchks) {
+                        consumed = sizeof(struct nvhost_submit_hdr);
+                        if (remaining < consumed)
+                                break;
+                        if (copy_from_user(hdr, buf, consumed)) {
+                                err = -EFAULT;
+                                break;
+                        }
+                        hdr->submit_version = NVHOST_SUBMIT_VERSION_V0;
+                        err = set_submit(priv);
+                        if (err)
+                                break;
+                        trace_nvhost_channel_write_submit(chname,
+                          count, hdr->num_cmdbufs, hdr->num_relocs,
+                          hdr->syncpt_id, hdr->syncpt_incrs);
+                } else if (hdr->num_cmdbufs) {
+                        struct nvhost_cmdbuf cmdbuf;
+                        consumed = sizeof(cmdbuf);
+                        if (remaining < consumed)
+                                break;
+                        if (copy_from_user(&cmdbuf, buf, consumed)) {
+                                err = -EFAULT;
+                                break;
+                        }
+                        trace_nvhost_channel_write_cmdbuf(chname,
+                                cmdbuf.mem, cmdbuf.words, cmdbuf.offset);
+                        nvhost_job_add_gather(job,
+                                cmdbuf.mem, cmdbuf.words, cmdbuf.offset);
+                        hdr->num_cmdbufs--;
+                } else if (hdr->num_relocs) {
+                        consumed = sizeof(struct nvhost_reloc);
+                        if (remaining < consumed)
+                                break;
+                        if (copy_from_user(&job->pinarray[job->num_pins],
+                                        buf, consumed)) {
+                                err = -EFAULT;
+                                break;
+                        }
+                        trace_nvhost_channel_write_reloc(chname);
+                        job->num_pins++;
+                        hdr->num_relocs--;
+                } else if (hdr->num_waitchks) {
+                        int numwaitchks =
+                                (remaining / sizeof(struct nvhost_waitchk));
+                        if (!numwaitchks)
+                                break;
+                        numwaitchks = min_t(int,
+                                numwaitchks, hdr->num_waitchks);
+                        consumed = numwaitchks * sizeof(struct nvhost_waitchk);
+                        if (copy_from_user(&job->waitchk[job->num_waitchk],
+                                        buf, consumed)) {
+                                err = -EFAULT;
+                                break;
+                        }
+                        trace_nvhost_channel_write_waitchks(
+                          chname, numwaitchks,
+                          hdr->waitchk_mask);
+                        job->num_waitchk += numwaitchks;
+                        hdr->num_waitchks -= numwaitchks;
+                } else if (priv->num_relocshifts) {
+                        int next_shift =
+                                job->num_pins - priv->num_relocshifts;
+                        consumed = sizeof(struct nvhost_reloc_shift);
+                        if (remaining < consumed)
+                                break;
+                        if (copy_from_user(
+                                        &job->pinarray[next_shift].reloc_shift,
+                                        buf, consumed)) {
+                                err = -EFAULT;
+                                break;
+                        }
+                        priv->num_relocshifts--;
+                } else {
+                        err = -EFAULT;
+                        break;
+                }
+                remaining -= consumed;
+                buf += consumed;
+        }
+        if (err < 0) {
+                dev_err(&priv->ch->dev->dev, "channel write error\n");
+                reset_submit(priv);
+                return err;
+        }
+        return count - remaining;
+}
+static int nvhost_ioctl_channel_flush(
+        struct nvhost_channel_userctx *ctx,
+        struct nvhost_get_param_args *args,
+        int null_kickoff)
+{
+        struct device *device = &ctx->ch->dev->dev;
+        int err;
+        trace_nvhost_ioctl_channel_flush(ctx->ch->dev->name);
+        if (!ctx->job ||
+            ctx->hdr.num_relocs ||
+            ctx->hdr.num_cmdbufs ||
+            ctx->hdr.num_waitchks) {
+                reset_submit(ctx);
+                dev_err(device, "channel submit out of sync\n");
+                return -EFAULT;
+        }
+        err = nvhost_job_pin(ctx->job);
+        if (err) {
+                dev_warn(device, "nvhost_job_pin failed: %d\n", err);
+                return err;
+        }
+        if (nvhost_debug_null_kickoff_pid == current->tgid)
+                null_kickoff = 1;
+        ctx->job->null_kickoff = null_kickoff;
+        if ((nvhost_debug_force_timeout_pid == current->tgid) &&
+            (nvhost_debug_force_timeout_channel == ctx->ch->chid)) {
+                ctx->timeout = nvhost_debug_force_timeout_val;
+        }
+        trace_write_cmdbufs(ctx->job);
+        /* context switch if needed, and submit user's gathers to the channel */
+        err = nvhost_channel_submit(ctx->job);
+        args->value = ctx->job->syncpt_end;
+        if (err)
+                nvhost_job_unpin(ctx->job);
+        return err;
+}
+static int nvhost_ioctl_channel_read_3d_reg(
+        struct nvhost_channel_userctx *ctx,
+        struct nvhost_read_3d_reg_args *args)
+{
+        BUG_ON(!channel_op(ctx->ch).read3dreg);
+        return channel_op(ctx->ch).read3dreg(ctx->ch, ctx->hwctx,
+                        args->offset, &args->value);
+}
+static long nvhost_channelctl(struct file *filp,
+        unsigned int cmd, unsigned long arg)
+{
+        struct nvhost_channel_userctx *priv = filp->private_data;
+        u8 buf[NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE];
+        int err = 0;
+        if ((_IOC_TYPE(cmd) != NVHOST_IOCTL_MAGIC) ||
+                (_IOC_NR(cmd) == 0) ||
+                (_IOC_NR(cmd) > NVHOST_IOCTL_CHANNEL_LAST))
+                return -EFAULT;
+        BUG_ON(_IOC_SIZE(cmd) > NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE);
+        if (_IOC_DIR(cmd) & _IOC_WRITE) {
+                if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd)))
+                        return -EFAULT;
+        }
+        switch (cmd) {
+        case NVHOST_IOCTL_CHANNEL_FLUSH:
+                err = nvhost_ioctl_channel_flush(priv, (void *)buf, 0);
+                break;
+        case NVHOST_IOCTL_CHANNEL_NULL_KICKOFF:
+                err = nvhost_ioctl_channel_flush(priv, (void *)buf, 1);
+                break;
+        case NVHOST_IOCTL_CHANNEL_SUBMIT_EXT:
+        {
+                struct nvhost_submit_hdr_ext *hdr;
+                if (priv->hdr.num_relocs ||
+                    priv->num_relocshifts ||
+                    priv->hdr.num_cmdbufs ||
+                    priv->hdr.num_waitchks) {
+                        reset_submit(priv);
+                        dev_err(&priv->ch->dev->dev,
+                                "channel submit out of sync\n");
+                        err = -EIO;
+                        break;
+                }
+                hdr = (struct nvhost_submit_hdr_ext *)buf;
+                if (hdr->submit_version > NVHOST_SUBMIT_VERSION_MAX_SUPPORTED) {
+                        dev_err(&priv->ch->dev->dev,
+                                "submit version %d > max supported %d\n",
+                                hdr->submit_version,
+                                NVHOST_SUBMIT_VERSION_MAX_SUPPORTED);
+                        err = -EINVAL;
+                        break;
+                }
+                memcpy(&priv->hdr, hdr, sizeof(struct nvhost_submit_hdr_ext));
+                err = set_submit(priv);
+                trace_nvhost_ioctl_channel_submit(priv->ch->dev->name,
+                        priv->hdr.submit_version,
+                        priv->hdr.num_cmdbufs, priv->hdr.num_relocs,
+                        priv->hdr.num_waitchks,
+                        priv->hdr.syncpt_id, priv->hdr.syncpt_incrs);
+                break;
+        }
+        case NVHOST_IOCTL_CHANNEL_GET_SYNCPOINTS:
+                /* host syncpt ID is used by the RM (and never be given out) */
+                BUG_ON(priv->ch->dev->syncpts & (1 << NVSYNCPT_GRAPHICS_HOST));
+                ((struct nvhost_get_param_args *)buf)->value =
+                        priv->ch->dev->syncpts;
+                break;
+        case NVHOST_IOCTL_CHANNEL_GET_WAITBASES:
+                ((struct nvhost_get_param_args *)buf)->value =
+                        priv->ch->dev->waitbases;
+                break;
+        case NVHOST_IOCTL_CHANNEL_GET_MODMUTEXES:
+                ((struct nvhost_get_param_args *)buf)->value =
+                        priv->ch->dev->modulemutexes;
+                break;
+        case NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD:
+        {
+                int fd = (int)((struct nvhost_set_nvmap_fd_args *)buf)->fd;
+                struct nvmap_client *new_client = nvmap_client_get_file(fd);
+                if (IS_ERR(new_client)) {
+                        err = PTR_ERR(new_client);
+                        break;
+                }
+                if (priv->nvmap)
+                        nvmap_client_put(priv->nvmap);
+                priv->nvmap = new_client;
+                break;
+        }
+        case NVHOST_IOCTL_CHANNEL_READ_3D_REG:
+                err = nvhost_ioctl_channel_read_3d_reg(priv, (void *)buf);
+                break;
+        case NVHOST_IOCTL_CHANNEL_GET_CLK_RATE:
+        {
+                unsigned long rate;
+                struct nvhost_clk_rate_args *arg =
+                                (struct nvhost_clk_rate_args *)buf;
+                err = nvhost_module_get_rate(priv->ch->dev, &rate, 0);
+                if (err == 0)
+                        arg->rate = rate;
+                break;
+        }
+        case NVHOST_IOCTL_CHANNEL_SET_CLK_RATE:
+        {
+                struct nvhost_clk_rate_args *arg =
+                                (struct nvhost_clk_rate_args *)buf;
+                unsigned long rate = (unsigned long)arg->rate;
+                err = nvhost_module_set_rate(priv->ch->dev, priv, rate, 0);
+                break;
+        }
+        case NVHOST_IOCTL_CHANNEL_SET_TIMEOUT:
+                priv->timeout =
+                        (u32)((struct nvhost_set_timeout_args *)buf)->timeout;
+                dev_dbg(&priv->ch->dev->dev,
+                        "%s: setting buffer timeout (%d ms) for userctx 0x%p\n",
+                        __func__, priv->timeout, priv);
+                break;
+        case NVHOST_IOCTL_CHANNEL_GET_TIMEDOUT:
+                ((struct nvhost_get_param_args *)buf)->value =
+                                priv->hwctx->has_timedout;
+                break;
+        case NVHOST_IOCTL_CHANNEL_SET_PRIORITY:
+                priv->priority =
+                        (u32)((struct nvhost_set_priority_args *)buf)->priority;
+                break;
+        default:
+                err = -ENOTTY;
+                break;
+        }
+        if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ))
+                err = copy_to_user((void __user *)arg, buf, _IOC_SIZE(cmd));
+        return err;
+}
+static const struct file_operations nvhost_channelops = {
+        .owner = THIS_MODULE,
+        .release = nvhost_channelrelease,
+        .open = nvhost_channelopen,
+        .write = nvhost_channelwrite,
+        .unlocked_ioctl = nvhost_channelctl
+};
+int nvhost_client_user_init(struct nvhost_device *dev)
+{
+        int err, devno;
+        struct nvhost_channel *ch = dev->channel;
+        cdev_init(&ch->cdev, &nvhost_channelops);
+        ch->cdev.owner = THIS_MODULE;
+        devno = MKDEV(nvhost_major, nvhost_minor + dev->index);
+        err = cdev_add(&ch->cdev, devno, 1);
+        if (err < 0) {
+                dev_err(&dev->dev,
+                        "failed to add chan %i cdev\n", dev->index);
+                goto fail;
+        }
+        ch->node = device_create(nvhost_get_host(dev)->nvhost_class, NULL, devno, NULL,
+                        IFACE_NAME "-%s", dev->name);
+        if (IS_ERR(ch->node)) {
+                err = PTR_ERR(ch->node);
+                dev_err(&dev->dev,
+                        "failed to create %s channel device\n", dev->name);
+                goto fail;
+        }
+        return 0;
+fail:
+        return err;
+}
+int nvhost_client_device_init(struct nvhost_device *dev)
+{
+        int err;
+        struct nvhost_master *nvhost_master = nvhost_get_host(dev);
+        struct nvhost_channel *ch = &nvhost_master->channels[dev->index];
+        /* store the pointer to this device for channel */
+        ch->dev = dev;
+        err = nvhost_channel_init(ch, nvhost_master, dev->index);
+        if (err)
+                goto fail;
+        err = nvhost_client_user_init(dev);
+        if (err)
+                goto fail;
+        err = nvhost_module_init(dev);
+        if (err)
+                goto fail;
+        dev_info(&dev->dev, "initialized\n");
+        return 0;
+fail:
+        /* Add clean-up */
+        return err;
+}
+int nvhost_client_device_suspend(struct nvhost_device *dev)
+{
+        int ret = 0;
+        dev_info(&dev->dev, "suspending\n");
+        ret = nvhost_channel_suspend(dev->channel);
+        if (ret)
+                return ret;
+        dev_info(&dev->dev, "suspend status: %d\n", ret);
+        return ret;
+}
diff --git a/drivers/video/tegra/host/bus_client.h b/drivers/video/tegra/host/bus_client.h
new file mode 100644
index 00000000000..4e47071fd14
--- /dev/null
+++ b/drivers/video/tegra/host/bus_client.h
@@ -0,0 +1,39 @@
+/*
+ * drivers/video/tegra/host/bus_client.h
+ *
+ * Tegra Graphics Host client
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_BUS_CLIENT_H
+#define __NVHOST_BUS_CLIENT_H
+#include <linux/types.h>
+struct nvhost_device;
+void nvhost_read_module_regs(struct nvhost_device *ndev,
+                        u32 offset, int count, u32 *values);
+void nvhost_write_module_regs(struct nvhost_device *ndev,
+                        u32 offset, int count, const u32 *values);
+int nvhost_client_user_init(struct nvhost_device *dev);
+int nvhost_client_device_init(struct nvhost_device *dev);
+int nvhost_client_device_suspend(struct nvhost_device *dev);
+#endif
diff --git a/drivers/video/tegra/host/chip_support.h b/drivers/video/tegra/host/chip_support.h
new file mode 100644
index 00000000000..6727e7a69fb
--- /dev/null
+++ b/drivers/video/tegra/host/chip_support.h
@@ -0,0 +1,141 @@
+/*
+ * drivers/video/tegra/host/chip_support.h
+ *
+ * Tegra Graphics Host Chip Support
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _NVHOST_CHIP_SUPPORT_H_
+#define _NVHOST_CHIP_SUPPORT_H_
+#include <linux/types.h>
+struct output;
+struct nvhost_waitchk;
+struct nvhost_userctx_timeout;
+struct nvhost_master;
+struct nvhost_channel;
+struct nvmap_handle;
+struct nvmap_client;
+struct nvhost_hwctx;
+struct nvhost_cdma;
+struct nvhost_intr;
+struct push_buffer;
+struct nvhost_syncpt;
+struct nvhost_master;
+struct dentry;
+struct nvhost_job;
+struct nvhost_chip_support {
+        struct {
+                int (*init)(struct nvhost_channel *,
+                            struct nvhost_master *,
+                            int chid);
+                int (*submit)(struct nvhost_job *job);
+                int (*read3dreg)(struct nvhost_channel *channel,
+                                struct nvhost_hwctx *hwctx,
+                                u32 offset,
+                                u32 *value);
+        } channel;
+        struct {
+                void (*start)(struct nvhost_cdma *);
+                void (*stop)(struct nvhost_cdma *);
+                void (*kick)(struct  nvhost_cdma *);
+                int (*timeout_init)(struct nvhost_cdma *,
+                                    u32 syncpt_id);
+                void (*timeout_destroy)(struct nvhost_cdma *);
+                void (*timeout_teardown_begin)(struct nvhost_cdma *);
+                void (*timeout_teardown_end)(struct nvhost_cdma *,
+                                             u32 getptr);
+                void (*timeout_cpu_incr)(struct nvhost_cdma *,
+                                         u32 getptr,
+                                         u32 syncpt_incrs,
+                                         u32 syncval,
+                                         u32 nr_slots);
+                void (*timeout_pb_incr)(struct nvhost_cdma *,
+                                        u32 getptr,
+                                        u32 syncpt_incrs,
+                                        u32 nr_slots,
+                                        bool exec_ctxsave);
+        } cdma;
+        struct {
+                void (*reset)(struct push_buffer *);
+                int (*init)(struct push_buffer *);
+                void (*destroy)(struct push_buffer *);
+                void (*push_to)(struct push_buffer *,
+                                struct nvmap_client *,
+                                struct nvmap_handle *,
+                                u32 op1, u32 op2);
+                void (*pop_from)(struct push_buffer *,
+                                 unsigned int slots);
+                u32 (*space)(struct push_buffer *);
+                u32 (*putptr)(struct push_buffer *);
+        } push_buffer;
+        struct {
+                void (*debug_init)(struct dentry *de);
+                void (*show_channel_cdma)(struct nvhost_master *,
+                                          struct nvhost_channel *,
+                                          struct output *,
+                                          int chid);
+                void (*show_channel_fifo)(struct nvhost_master *,
+                                          struct nvhost_channel *,
+                                          struct output *,
+                                          int chid);
+                void (*show_mlocks)(struct nvhost_master *m,
+                                    struct output *o);
+        } debug;
+        struct {
+                void (*reset)(struct nvhost_syncpt *, u32 id);
+                void (*reset_wait_base)(struct nvhost_syncpt *, u32 id);
+                void (*read_wait_base)(struct nvhost_syncpt *, u32 id);
+                u32 (*update_min)(struct nvhost_syncpt *, u32 id);
+                void (*cpu_incr)(struct nvhost_syncpt *, u32 id);
+                int (*wait_check)(struct nvhost_syncpt *sp,
+                                  struct nvmap_client *nvmap,
+                                  u32 waitchk_mask,
+                                  struct nvhost_waitchk *wait,
+                                  int num_waitchk);
+                void (*debug)(struct nvhost_syncpt *);
+                const char * (*name)(struct nvhost_syncpt *, u32 id);
+                int (*mutex_try_lock)(struct nvhost_syncpt *,
+                                      unsigned int idx);
+                void (*mutex_unlock)(struct nvhost_syncpt *,
+                                     unsigned int idx);
+        } syncpt;
+        struct {
+                void (*init_host_sync)(struct nvhost_intr *);
+                void (*set_host_clocks_per_usec)(
+                        struct nvhost_intr *, u32 clocks);
+                void (*set_syncpt_threshold)(
+                        struct nvhost_intr *, u32 id, u32 thresh);
+                void (*enable_syncpt_intr)(struct nvhost_intr *, u32 id);
+                void (*disable_all_syncpt_intrs)(struct nvhost_intr *);
+                int  (*request_host_general_irq)(struct nvhost_intr *);
+                void (*free_host_general_irq)(struct nvhost_intr *);
+                int (*request_syncpt_irq)(struct nvhost_intr_syncpt *syncpt);
+        } intr;
+        struct {
+                struct nvhost_device *(*get_nvhost_device)(struct nvhost_master *host,
+                        char *name);
+        } nvhost_dev;
+};
+#endif /* _NVHOST_CHIP_SUPPORT_H_ */
diff --git a/drivers/video/tegra/host/debug.c b/drivers/video/tegra/host/debug.c
new file mode 100644
index 00000000000..91436c903fc
--- /dev/null
+++ b/drivers/video/tegra/host/debug.c
@@ -0,0 +1,167 @@
+/*
+ * drivers/video/tegra/host/debug.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Erik Gilling <konkers@android.com>
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/io.h>
+#include "dev.h"
+#include "debug.h"
+pid_t nvhost_debug_null_kickoff_pid;
+unsigned int nvhost_debug_trace_cmdbuf;
+pid_t nvhost_debug_force_timeout_pid;
+u32 nvhost_debug_force_timeout_val;
+u32 nvhost_debug_force_timeout_channel;
+void nvhost_debug_output(struct output *o, const char* fmt, ...)
+{
+        va_list args;
+        int len;
+        va_start(args, fmt);
+        len = vsnprintf(o->buf, sizeof(o->buf), fmt, args);
+        va_end(args);
+        o->fn(o->ctx, o->buf, len);
+}
+static int show_channels(struct device *dev, void *data)
+{
+        struct nvhost_channel *ch;
+        struct nvhost_device *nvdev = to_nvhost_device(dev);
+        struct output *o = data;
+        struct nvhost_master *m;
+        if (nvdev == NULL)
+                return 0;
+        m = nvhost_get_host(nvdev);
+        ch = nvdev->channel;
+        if (ch) {
+                mutex_lock(&ch->reflock);
+                if (ch->refcount) {
+                        mutex_lock(&ch->cdma.lock);
+                        m->op.debug.show_channel_fifo(m, ch, o, nvdev->index);
+                        m->op.debug.show_channel_cdma(m, ch, o, nvdev->index);
+                        mutex_unlock(&ch->cdma.lock);
+                }
+                mutex_unlock(&ch->reflock);
+        }
+        return 0;
+}
+static void show_syncpts(struct nvhost_master *m, struct output *o)
+{
+        int i;
+        BUG_ON(!m->op.syncpt.name);
+        nvhost_debug_output(o, "---- syncpts ----\n");
+        for (i = 0; i < m->syncpt.nb_pts; i++) {
+                u32 max = nvhost_syncpt_read_max(&m->syncpt, i);
+                u32 min = nvhost_syncpt_update_min(&m->syncpt, i);
+                if (!min && !max)
+                        continue;
+                nvhost_debug_output(o, "id %d (%s) min %d max %d\n",
+                                i, m->op.syncpt.name(&m->syncpt, i),
+                                min, max);
+        }
+        for (i = 0; i < m->syncpt.nb_bases; i++) {
+                u32 base_val;
+                base_val = nvhost_syncpt_read_wait_base(&m->syncpt, i);
+                if (base_val)
+                        nvhost_debug_output(o, "waitbase id %d val %d\n",
+                                        i, base_val);
+        }
+        nvhost_debug_output(o, "\n");
+}
+static void show_all(struct nvhost_master *m, struct output *o)
+{
+        nvhost_module_busy(m->dev);
+        m->op.debug.show_mlocks(m, o);
+        show_syncpts(m, o);
+        nvhost_debug_output(o, "---- channels ----\n");
+        bus_for_each_dev(&nvhost_bus_type, NULL, o, show_channels);
+        nvhost_module_idle(m->dev);
+}
+#ifdef CONFIG_DEBUG_FS
+static int nvhost_debug_show(struct seq_file *s, void *unused)
+{
+        struct output o = {
+                .fn = write_to_seqfile,
+                .ctx = s
+        };
+        show_all(s->private, &o);
+        return 0;
+}
+static int nvhost_debug_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, nvhost_debug_show, inode->i_private);
+}
+static const struct file_operations nvhost_debug_fops = {
+        .open           = nvhost_debug_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+void nvhost_debug_init(struct nvhost_master *master)
+{
+        struct dentry *de = debugfs_create_dir("tegra_host", NULL);
+        debugfs_create_file("status", S_IRUGO, de,
+                        master, &nvhost_debug_fops);
+        debugfs_create_u32("null_kickoff_pid", S_IRUGO|S_IWUSR, de,
+                        &nvhost_debug_null_kickoff_pid);
+        debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, de,
+                        &nvhost_debug_trace_cmdbuf);
+        if (master->op.debug.debug_init)
+                master->op.debug.debug_init(de);
+        debugfs_create_u32("force_timeout_pid", S_IRUGO|S_IWUSR, de,
+                        &nvhost_debug_force_timeout_pid);
+        debugfs_create_u32("force_timeout_val", S_IRUGO|S_IWUSR, de,
+                        &nvhost_debug_force_timeout_val);
+        debugfs_create_u32("force_timeout_channel", S_IRUGO|S_IWUSR, de,
+                        &nvhost_debug_force_timeout_channel);
+}
+#else
+void nvhost_debug_init(struct nvhost_master *master)
+{
+}
+#endif
+void nvhost_debug_dump(struct nvhost_master *master)
+{
+        struct output o = {
+                .fn = write_to_printk
+        };
+        show_all(master, &o);
+}
diff --git a/drivers/video/tegra/host/debug.h b/drivers/video/tegra/host/debug.h
new file mode 100644
index 00000000000..3dc156ab474
--- /dev/null
+++ b/drivers/video/tegra/host/debug.h
@@ -0,0 +1,50 @@
+/*
+ * drivers/video/tegra/host/debug.h
+ *
+ * Tegra Graphics Host Debug
+ *
+ * Copyright (c) 2011-2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_DEBUG_H
+#define __NVHOST_DEBUG_H
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+struct output {
+        void (*fn)(void *ctx, const char* str, size_t len);
+        void *ctx;
+        char buf[256];
+};
+static inline void write_to_seqfile(void *ctx, const char* str, size_t len)
+{
+        seq_write((struct seq_file *)ctx, str, len);
+}
+static inline void write_to_printk(void *ctx, const char* str, size_t len)
+{
+        printk(KERN_INFO "%s", str);
+}
+void nvhost_debug_output(struct output *o, const char* fmt, ...);
+extern pid_t nvhost_debug_null_kickoff_pid;
+extern pid_t nvhost_debug_force_timeout_pid;
+extern u32 nvhost_debug_force_timeout_val;
+extern u32 nvhost_debug_force_timeout_channel;
+extern unsigned int nvhost_debug_trace_cmdbuf;
+#endif /*__NVHOST_DEBUG_H */
diff --git a/drivers/video/tegra/host/dev.c b/drivers/video/tegra/host/dev.c
new file mode 100644
index 00000000000..8f0c0393401
--- /dev/null
+++ b/drivers/video/tegra/host/dev.c
@@ -0,0 +1,635 @@
+/*
+ * drivers/video/tegra/host/dev.c
+ *
+ * Tegra Graphics Host Driver Entrypoint
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/spinlock.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#include <linux/file.h>
+#include <linux/clk.h>
+#include <linux/hrtimer.h>
+#include "dev.h"
+#define CREATE_TRACE_POINTS
+#include <trace/events/nvhost.h>
+#include <linux/io.h>
+#include <linux/nvhost.h>
+#include <linux/nvhost_ioctl.h>
+#include <mach/nvmap.h>
+#include <mach/gpufuse.h>
+#include <mach/hardware.h>
+#include <mach/iomap.h>
+#include "debug.h"
+#include "nvhost_job.h"
+#include "t20/t20.h"
+#include "t30/t30.h"
+#include "bus_client.h"
+#define DRIVER_NAME             "host1x"
+int nvhost_major;
+int nvhost_minor;
+static unsigned int register_sets;
+struct nvhost_ctrl_userctx {
+        struct nvhost_master *dev;
+        u32 *mod_locks;
+};
+static int nvhost_ctrlrelease(struct inode *inode, struct file *filp)
+{
+        struct nvhost_ctrl_userctx *priv = filp->private_data;
+        int i;
+        trace_nvhost_ctrlrelease(priv->dev->dev->name);
+        filp->private_data = NULL;
+        if (priv->mod_locks[0])
+                nvhost_module_idle(priv->dev->dev);
+        for (i = 1; i < priv->dev->syncpt.nb_mlocks; i++)
+                if (priv->mod_locks[i])
+                        nvhost_mutex_unlock(&priv->dev->syncpt, i);
+        kfree(priv->mod_locks);
+        kfree(priv);
+        return 0;
+}
+static int nvhost_ctrlopen(struct inode *inode, struct file *filp)
+{
+        struct nvhost_master *host = container_of(inode->i_cdev, struct nvhost_master, cdev);
+        struct nvhost_ctrl_userctx *priv;
+        u32 *mod_locks;
+        trace_nvhost_ctrlopen(host->dev->name);
+        priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+        mod_locks = kzalloc(sizeof(u32) * host->syncpt.nb_mlocks, GFP_KERNEL);
+        if (!(priv && mod_locks)) {
+                kfree(priv);
+                kfree(mod_locks);
+                return -ENOMEM;
+        }
+        priv->dev = host;
+        priv->mod_locks = mod_locks;
+        filp->private_data = priv;
+        return 0;
+}
+static int nvhost_ioctl_ctrl_syncpt_read(struct nvhost_ctrl_userctx *ctx,
+        struct nvhost_ctrl_syncpt_read_args *args)
+{
+        if (args->id >= ctx->dev->syncpt.nb_pts)
+                return -EINVAL;
+        args->value = nvhost_syncpt_read(&ctx->dev->syncpt, args->id);
+        trace_nvhost_ioctl_ctrl_syncpt_read(args->id, args->value);
+        return 0;
+}
+static int nvhost_ioctl_ctrl_syncpt_incr(struct nvhost_ctrl_userctx *ctx,
+        struct nvhost_ctrl_syncpt_incr_args *args)
+{
+        if (args->id >= ctx->dev->syncpt.nb_pts)
+                return -EINVAL;
+        trace_nvhost_ioctl_ctrl_syncpt_incr(args->id);
+        nvhost_syncpt_incr(&ctx->dev->syncpt, args->id);
+        return 0;
+}
+static int nvhost_ioctl_ctrl_syncpt_waitex(struct nvhost_ctrl_userctx *ctx,
+        struct nvhost_ctrl_syncpt_waitex_args *args)
+{
+        u32 timeout;
+        int err;
+        if (args->id >= ctx->dev->syncpt.nb_pts)
+                return -EINVAL;
+        if (args->timeout == NVHOST_NO_TIMEOUT)
+                timeout = MAX_SCHEDULE_TIMEOUT;
+        else
+                timeout = (u32)msecs_to_jiffies(args->timeout);
+        err = nvhost_syncpt_wait_timeout(&ctx->dev->syncpt, args->id,
+                                        args->thresh, timeout, &args->value);
+        trace_nvhost_ioctl_ctrl_syncpt_wait(args->id, args->thresh,
+          args->timeout, args->value, err);
+        return err;
+}
+static int nvhost_ioctl_ctrl_module_mutex(struct nvhost_ctrl_userctx *ctx,
+        struct nvhost_ctrl_module_mutex_args *args)
+{
+        int err = 0;
+        if (args->id >= ctx->dev->syncpt.nb_mlocks ||
+            args->lock > 1)
+                return -EINVAL;
+        trace_nvhost_ioctl_ctrl_module_mutex(args->lock, args->id);
+        if (args->lock && !ctx->mod_locks[args->id]) {
+                if (args->id == 0)
+                        nvhost_module_busy(ctx->dev->dev);
+                else
+                        err = nvhost_mutex_try_lock(&ctx->dev->syncpt,
+                                        args->id);
+                if (!err)
+                        ctx->mod_locks[args->id] = 1;
+        } else if (!args->lock && ctx->mod_locks[args->id]) {
+                if (args->id == 0)
+                        nvhost_module_idle(ctx->dev->dev);
+                else
+                        nvhost_mutex_unlock(&ctx->dev->syncpt, args->id);
+                ctx->mod_locks[args->id] = 0;
+        }
+        return err;
+}
+static struct nvhost_device *get_ndev_by_moduleid(struct nvhost_master *host,
+                u32 id)
+{
+        int i;
+        for (i = 0; i < host->nb_channels; i++) {
+                struct nvhost_device *ndev = host->channels[i].dev;
+                /* display and dsi do not use channel for register programming.
+                 * so their channels do not have device instance.
+                 * hence skip such channels from here. */
+                if (ndev == NULL)
+                        continue;
+                if (id == ndev->moduleid)
+                        return ndev;
+        }
+        return NULL;
+}
+static int nvhost_ioctl_ctrl_module_regrdwr(struct nvhost_ctrl_userctx *ctx,
+        struct nvhost_ctrl_module_regrdwr_args *args)
+{
+        u32 num_offsets = args->num_offsets;
+        u32 *offsets = args->offsets;
+        u32 *values = args->values;
+        u32 vals[64];
+        struct nvhost_device *ndev;
+        trace_nvhost_ioctl_ctrl_module_regrdwr(args->id,
+                        args->num_offsets, args->write);
+        /* Check that there is something to read and that block size is
+         * u32 aligned */
+        if (num_offsets == 0 || args->block_size & 3)
+                return -EINVAL;
+        ndev = get_ndev_by_moduleid(ctx->dev, args->id);
+        if (!ndev)
+                return -EINVAL;
+        while (num_offsets--) {
+                int remaining = args->block_size >> 2;
+                u32 offs;
+                if (get_user(offs, offsets))
+                        return -EFAULT;
+                offsets++;
+                while (remaining) {
+                        int batch = min(remaining, 64);
+                        if (args->write) {
+                                if (copy_from_user(vals, values,
+                                                        batch*sizeof(u32)))
+                                        return -EFAULT;
+                                nvhost_write_module_regs(ndev,
+                                                offs, batch, vals);
+                        } else {
+                                nvhost_read_module_regs(ndev,
+                                                offs, batch, vals);
+                                if (copy_to_user(values, vals,
+                                                        batch*sizeof(u32)))
+                                        return -EFAULT;
+                        }
+                        remaining -= batch;
+                        offs += batch;
+                        values += batch;
+                }
+        }
+        return 0;
+}
+static int nvhost_ioctl_ctrl_get_version(struct nvhost_ctrl_userctx *ctx,
+        struct nvhost_get_param_args *args)
+{
+        args->value = NVHOST_SUBMIT_VERSION_MAX_SUPPORTED;
+        return 0;
+}
+static long nvhost_ctrlctl(struct file *filp,
+        unsigned int cmd, unsigned long arg)
+{
+        struct nvhost_ctrl_userctx *priv = filp->private_data;
+        u8 buf[NVHOST_IOCTL_CTRL_MAX_ARG_SIZE];
+        int err = 0;
+        if ((_IOC_TYPE(cmd) != NVHOST_IOCTL_MAGIC) ||
+                (_IOC_NR(cmd) == 0) ||
+                (_IOC_NR(cmd) > NVHOST_IOCTL_CTRL_LAST))
+                return -EFAULT;
+        BUG_ON(_IOC_SIZE(cmd) > NVHOST_IOCTL_CTRL_MAX_ARG_SIZE);
+        if (_IOC_DIR(cmd) & _IOC_WRITE) {
+                if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd)))
+                        return -EFAULT;
+        }
+        switch (cmd) {
+        case NVHOST_IOCTL_CTRL_SYNCPT_READ:
+                err = nvhost_ioctl_ctrl_syncpt_read(priv, (void *)buf);
+                break;
+        case NVHOST_IOCTL_CTRL_SYNCPT_INCR:
+                err = nvhost_ioctl_ctrl_syncpt_incr(priv, (void *)buf);
+                break;
+        case NVHOST_IOCTL_CTRL_SYNCPT_WAIT:
+                err = nvhost_ioctl_ctrl_syncpt_waitex(priv, (void *)buf);
+                break;
+        case NVHOST_IOCTL_CTRL_MODULE_MUTEX:
+                err = nvhost_ioctl_ctrl_module_mutex(priv, (void *)buf);
+                break;
+        case NVHOST_IOCTL_CTRL_MODULE_REGRDWR:
+                err = nvhost_ioctl_ctrl_module_regrdwr(priv, (void *)buf);
+                break;
+        case NVHOST_IOCTL_CTRL_SYNCPT_WAITEX:
+                err = nvhost_ioctl_ctrl_syncpt_waitex(priv, (void *)buf);
+                break;
+        case NVHOST_IOCTL_CTRL_GET_VERSION:
+                err = nvhost_ioctl_ctrl_get_version(priv, (void *)buf);
+                break;
+        default:
+                err = -ENOTTY;
+                break;
+        }
+        if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ))
+                err = copy_to_user((void __user *)arg, buf, _IOC_SIZE(cmd));
+        return err;
+}
+static const struct file_operations nvhost_ctrlops = {
+        .owner = THIS_MODULE,
+        .release = nvhost_ctrlrelease,
+        .open = nvhost_ctrlopen,
+        .unlocked_ioctl = nvhost_ctrlctl
+};
+static void power_on_host(struct nvhost_device *dev)
+{
+        struct nvhost_master *host = nvhost_get_drvdata(dev);
+        nvhost_syncpt_reset(&host->syncpt);
+        nvhost_intr_start(&host->intr, clk_get_rate(dev->clk[0]));
+}
+static int power_off_host(struct nvhost_device *dev)
+{
+        struct nvhost_master *host = nvhost_get_drvdata(dev);
+        nvhost_syncpt_save(&host->syncpt);
+        nvhost_intr_stop(&host->intr);
+        return 0;
+}
+static int __devinit nvhost_user_init(struct nvhost_master *host)
+{
+        int err, devno;
+        host->nvhost_class = class_create(THIS_MODULE, IFACE_NAME);
+        if (IS_ERR(host->nvhost_class)) {
+                err = PTR_ERR(host->nvhost_class);
+                dev_err(&host->dev->dev, "failed to create class\n");
+                goto fail;
+        }
+        err = alloc_chrdev_region(&devno, nvhost_minor,
+                                host->nb_channels + 1, IFACE_NAME);
+        nvhost_major = MAJOR(devno);
+        if (err < 0) {
+                dev_err(&host->dev->dev, "failed to reserve chrdev region\n");
+                goto fail;
+        }
+        cdev_init(&host->cdev, &nvhost_ctrlops);
+        host->cdev.owner = THIS_MODULE;
+        devno = MKDEV(nvhost_major, nvhost_minor + host->nb_channels);
+        err = cdev_add(&host->cdev, devno, 1);
+        if (err < 0)
+                goto fail;
+        host->ctrl = device_create(host->nvhost_class, NULL, devno, NULL,
+                        IFACE_NAME "-ctrl");
+        if (IS_ERR(host->ctrl)) {
+                err = PTR_ERR(host->ctrl);
+                dev_err(&host->dev->dev, "failed to create ctrl device\n");
+                goto fail;
+        }
+        return 0;
+fail:
+        return err;
+}
+struct nvhost_device *nvhost_get_device(char *name)
+{
+        BUG_ON(!host_device_op(nvhost).get_nvhost_device);
+        return host_device_op(nvhost).get_nvhost_device(nvhost, name);
+}
+static void nvhost_remove_chip_support(struct nvhost_master *host)
+{
+        kfree(host->channels);
+        host->channels = 0;
+        kfree(host->syncpt.min_val);
+        host->syncpt.min_val = 0;
+        kfree(host->syncpt.max_val);
+        host->syncpt.max_val = 0;
+        kfree(host->syncpt.base_val);
+        host->syncpt.base_val = 0;
+        kfree(host->intr.syncpt);
+        host->intr.syncpt = 0;
+        kfree(host->syncpt.lock_counts);
+        host->syncpt.lock_counts = 0;
+}
+static int __devinit nvhost_init_chip_support(struct nvhost_master *host)
+{
+        int err;
+        switch (tegra_get_chipid()) {
+        case TEGRA_CHIPID_TEGRA2:
+                err = nvhost_init_t20_support(host);
+                break;
+        case TEGRA_CHIPID_TEGRA3:
+                err = nvhost_init_t30_support(host);
+                break;
+        default:
+                return -ENODEV;
+        }
+        if (err)
+                return err;
+        /* allocate items sized in chip specific support init */
+        host->channels = kzalloc(sizeof(struct nvhost_channel) *
+                                 host->nb_channels, GFP_KERNEL);
+        host->syncpt.min_val = kzalloc(sizeof(atomic_t) *
+                                       host->syncpt.nb_pts, GFP_KERNEL);
+        host->syncpt.max_val = kzalloc(sizeof(atomic_t) *
+                                       host->syncpt.nb_pts, GFP_KERNEL);
+        host->syncpt.base_val = kzalloc(sizeof(u32) *
+                                        host->syncpt.nb_bases, GFP_KERNEL);
+        host->intr.syncpt = kzalloc(sizeof(struct nvhost_intr_syncpt) *
+                                    host->syncpt.nb_pts, GFP_KERNEL);
+        host->syncpt.lock_counts = kzalloc(sizeof(atomic_t) *
+                                       host->syncpt.nb_mlocks, GFP_KERNEL);
+        if (!(host->channels && host->syncpt.min_val &&
+              host->syncpt.max_val && host->syncpt.base_val &&
+              host->intr.syncpt && host->syncpt.lock_counts)) {
+                /* frees happen in the support removal phase */
+                return -ENOMEM;
+        }
+        return 0;
+}
+static struct resource nvhost_resources[] = {
+        {
+                .start = TEGRA_HOST1X_BASE,
+                .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = TEGRA_DISPLAY_BASE,
+                .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = TEGRA_DISPLAY2_BASE,
+                .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = TEGRA_VI_BASE,
+                .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = TEGRA_ISP_BASE,
+                .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = TEGRA_MPE_BASE,
+                .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = INT_SYNCPT_THRESH_BASE,
+                .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = INT_HOST1X_MPCORE_GENERAL,
+                .end = INT_HOST1X_MPCORE_GENERAL,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct nvhost_device tegra_grhost_device = {
+        .name = DRIVER_NAME,
+        .id = -1,
+        .resource = nvhost_resources,
+        .num_resources = ARRAY_SIZE(nvhost_resources),
+        .finalize_poweron = power_on_host,
+        .prepare_poweroff = power_off_host,
+        .clocks = {{"host1x", UINT_MAX}, {} },
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+};
+static int __devinit nvhost_probe(struct nvhost_device *dev)
+{
+        struct nvhost_master *host;
+        struct resource *regs, *intr0, *intr1;
+        int i, err;
+        regs = nvhost_get_resource(dev, IORESOURCE_MEM, 0);
+        intr0 = nvhost_get_resource(dev, IORESOURCE_IRQ, 0);
+        intr1 = nvhost_get_resource(dev, IORESOURCE_IRQ, 1);
+        if (!regs || !intr0 || !intr1) {
+                dev_err(&dev->dev, "missing required platform resources\n");
+                return -ENXIO;
+        }
+        host = kzalloc(sizeof(*host), GFP_KERNEL);
+        if (!host)
+                return -ENOMEM;
+        host->nvmap = nvmap_create_client(nvmap_dev, "nvhost");
+        if (!host->nvmap) {
+                dev_err(&dev->dev, "unable to create nvmap client\n");
+                err = -EIO;
+                goto fail;
+        }
+        host->reg_mem = request_mem_region(regs->start,
+                                        resource_size(regs), dev->name);
+        if (!host->reg_mem) {
+                dev_err(&dev->dev, "failed to get host register memory\n");
+                err = -ENXIO;
+                goto fail;
+        }
+        host->aperture = ioremap(regs->start, resource_size(regs));
+        if (!host->aperture) {
+                dev_err(&dev->dev, "failed to remap host registers\n");
+                err = -ENXIO;
+                goto fail;
+        }
+        err = nvhost_init_chip_support(host);
+        if (err) {
+                dev_err(&dev->dev, "failed to init chip support\n");
+                goto fail;
+        }
+        /*  Register host1x device as bus master */
+        host->dev = dev;
+        /*  Give pointer to host1x via driver */
+        nvhost_set_drvdata(dev, host);
+        nvhost_bus_add_host(host);
+        err = nvhost_intr_init(&host->intr, intr1->start, intr0->start);
+        if (err)
+                goto fail;
+        err = nvhost_user_init(host);
+        if (err)
+                goto fail;
+        err = nvhost_module_init(&tegra_grhost_device);
+        if (err)
+                goto fail;
+        for (i = 0; i < host->dev->num_clks; i++)
+                clk_enable(host->dev->clk[i]);
+        nvhost_syncpt_reset(&host->syncpt);
+        for (i = 0; i < host->dev->num_clks; i++)
+                clk_disable(host->dev->clk[0]);
+        nvhost_debug_init(host);
+        dev_info(&dev->dev, "initialized\n");
+        return 0;
+fail:
+        nvhost_remove_chip_support(host);
+        if (host->nvmap)
+                nvmap_client_put(host->nvmap);
+        kfree(host);
+        return err;
+}
+static int __exit nvhost_remove(struct nvhost_device *dev)
+{
+        struct nvhost_master *host = nvhost_get_drvdata(dev);
+        nvhost_intr_deinit(&host->intr);
+        nvhost_remove_chip_support(host);
+        return 0;
+}
+static int nvhost_suspend(struct nvhost_device *dev, pm_message_t state)
+{
+        struct nvhost_master *host = nvhost_get_drvdata(dev);
+        int ret = 0;
+        dev_info(&dev->dev, "suspending\n");
+        ret = nvhost_module_suspend(host->dev, true);
+        dev_info(&dev->dev, "suspend status: %d\n", ret);
+        return ret;
+}
+static int nvhost_resume(struct nvhost_device *dev)
+{
+        dev_info(&dev->dev, "resuming\n");
+        return 0;
+}
+static struct nvhost_driver nvhost_driver = {
+        .probe = nvhost_probe,
+        .remove = __exit_p(nvhost_remove),
+        .suspend = nvhost_suspend,
+        .resume = nvhost_resume,
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = DRIVER_NAME
+        }
+};
+static int __init nvhost_mod_init(void)
+{
+        register_sets = tegra_gpu_register_sets();
+        return nvhost_driver_register(&nvhost_driver);
+}
+static void __exit nvhost_mod_exit(void)
+{
+        nvhost_driver_unregister(&nvhost_driver);
+}
+/* host1x master device needs nvmap to be instantiated first.
+ * nvmap is instantiated via fs_initcall.
+ * Hence instantiate host1x master device using rootfs_initcall
+ * which is one level after fs_initcall. */
+rootfs_initcall(nvhost_mod_init);
+module_exit(nvhost_mod_exit);
+module_param_call(register_sets, NULL, param_get_uint, &register_sets, 0444);
+MODULE_PARM_DESC(register_sets, "Number of register sets");
+MODULE_AUTHOR("NVIDIA");
+MODULE_DESCRIPTION("Graphics host driver for Tegra products");
+MODULE_VERSION("1.0");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform-nvhost");
diff --git a/drivers/video/tegra/host/dev.h b/drivers/video/tegra/host/dev.h
new file mode 100644
index 00000000000..74d7e16fc27
--- /dev/null
+++ b/drivers/video/tegra/host/dev.h
@@ -0,0 +1,68 @@
+/*
+ * drivers/video/tegra/host/dev.h
+ *
+ * Tegra Graphics Host Driver Entrypoint
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_DEV_H
+#define __NVHOST_DEV_H
+#include "nvhost_acm.h"
+#include "nvhost_syncpt.h"
+#include "nvhost_intr.h"
+#include "nvhost_channel.h"
+#include "chip_support.h"
+#define TRACE_MAX_LENGTH        128U
+#define IFACE_NAME              "nvhost"
+extern int nvhost_major;
+extern int nvhost_minor;
+struct nvhost_hwctx;
+struct nvhost_master {
+        void __iomem *aperture;
+        void __iomem *sync_aperture;
+        struct resource *reg_mem;
+        struct class *nvhost_class;
+        struct cdev cdev;
+        struct device *ctrl;
+        struct nvhost_syncpt syncpt;
+        struct nvmap_client *nvmap;
+        struct nvhost_intr intr;
+        struct nvhost_device *dev;
+        struct nvhost_channel *channels;
+        u32 nb_channels;
+        struct nvhost_chip_support op;
+        atomic_t clientid;
+};
+extern struct nvhost_master *nvhost;
+void nvhost_debug_init(struct nvhost_master *master);
+void nvhost_debug_dump(struct nvhost_master *master);
+#define host_device_op(host)    (host->op.nvhost_dev)
+struct nvhost_device *nvhost_get_device(char *name);
+extern pid_t nvhost_debug_null_kickoff_pid;
+#endif
diff --git a/drivers/video/tegra/host/dsi/Makefile b/drivers/video/tegra/host/dsi/Makefile
new file mode 100644
index 00000000000..eb94d3ec492
--- /dev/null
+++ b/drivers/video/tegra/host/dsi/Makefile
@@ -0,0 +1,7 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-dsi-objs  = \
+                dsi.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-dsi.o
diff --git a/drivers/video/tegra/host/dsi/dsi.c b/drivers/video/tegra/host/dsi/dsi.c
new file mode 100644
index 00000000000..0e49f591574
--- /dev/null
+++ b/drivers/video/tegra/host/dsi/dsi.c
@@ -0,0 +1,82 @@
+/*
+ * drivers/video/tegra/host/dsi/dsi.c
+ *
+ * Tegra Graphics DSI
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "dev.h"
+#include "bus_client.h"
+static int dsi_probe(struct nvhost_device *dev)
+{
+        return nvhost_client_device_init(dev);
+}
+static int __exit dsi_remove(struct nvhost_device *dev)
+{
+        /* Add clean-up */
+        return 0;
+}
+static int dsi_suspend(struct nvhost_device *dev, pm_message_t state)
+{
+        return nvhost_client_device_suspend(dev);
+}
+static int dsi_resume(struct nvhost_device *dev)
+{
+        dev_info(&dev->dev, "resuming\n");
+        return 0;
+}
+struct nvhost_device *dsi_device;
+static struct nvhost_driver dsi_driver = {
+        .probe = dsi_probe,
+        .remove = __exit_p(dsi_remove),
+#ifdef CONFIG_PM
+        .suspend = dsi_suspend,
+        .resume = dsi_resume,
+#endif
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "dsi",
+        }
+};
+static int __init dsi_init(void)
+{
+        int err;
+        dsi_device = nvhost_get_device("dsi");
+        if (!dsi_device)
+                return -ENXIO;
+        err = nvhost_device_register(dsi_device);
+        if (err)
+                return err;
+        return nvhost_driver_register(&dsi_driver);
+}
+static void __exit dsi_exit(void)
+{
+        nvhost_driver_unregister(&dsi_driver);
+}
+module_init(dsi_init);
+module_exit(dsi_exit);
diff --git a/drivers/video/tegra/host/gr2d/Makefile b/drivers/video/tegra/host/gr2d/Makefile
new file mode 100644
index 00000000000..a79a2101677
--- /dev/null
+++ b/drivers/video/tegra/host/gr2d/Makefile
@@ -0,0 +1,7 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-gr2d-objs  = \
+                gr2d.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-gr2d.o
diff --git a/drivers/video/tegra/host/gr2d/gr2d.c b/drivers/video/tegra/host/gr2d/gr2d.c
new file mode 100644
index 00000000000..f88eb72e0a4
--- /dev/null
+++ b/drivers/video/tegra/host/gr2d/gr2d.c
@@ -0,0 +1,82 @@
+/*
+ * drivers/video/tegra/host/gr2d/gr2d.c
+ *
+ * Tegra Graphics 2D
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "dev.h"
+#include "bus_client.h"
+static int __devinit gr2d_probe(struct nvhost_device *dev)
+{
+        return nvhost_client_device_init(dev);
+}
+static int __exit gr2d_remove(struct nvhost_device *dev)
+{
+        /* Add clean-up */
+        return 0;
+}
+static int gr2d_suspend(struct nvhost_device *dev, pm_message_t state)
+{
+        return nvhost_client_device_suspend(dev);
+}
+static int gr2d_resume(struct nvhost_device *dev)
+{
+        dev_info(&dev->dev, "resuming\n");
+        return 0;
+}
+struct nvhost_device *gr2d_device;
+static struct nvhost_driver gr2d_driver = {
+        .probe = gr2d_probe,
+        .remove = __exit_p(gr2d_remove),
+#ifdef CONFIG_PM
+        .suspend = gr2d_suspend,
+        .resume = gr2d_resume,
+#endif
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "gr2d",
+        }
+};
+static int __init gr2d_init(void)
+{
+        int err;
+        gr2d_device = nvhost_get_device("gr2d");
+        if (!gr2d_device)
+                return -ENXIO;
+        err = nvhost_device_register(gr2d_device);
+        if (err)
+                return err;
+        return nvhost_driver_register(&gr2d_driver);
+}
+static void __exit gr2d_exit(void)
+{
+        nvhost_driver_unregister(&gr2d_driver);
+}
+module_init(gr2d_init);
+module_exit(gr2d_exit);
diff --git a/drivers/video/tegra/host/gr3d/Makefile b/drivers/video/tegra/host/gr3d/Makefile
new file mode 100644
index 00000000000..dfbd078ab42
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/Makefile
@@ -0,0 +1,10 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-gr3d-objs  = \
+                gr3d.o \
+                gr3d_t20.o \
+                gr3d_t30.o \
+                scale3d.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-gr3d.o
diff --git a/drivers/video/tegra/host/gr3d/gr3d.c b/drivers/video/tegra/host/gr3d/gr3d.c
new file mode 100644
index 00000000000..f387d54e585
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/gr3d.c
@@ -0,0 +1,211 @@
+/*
+ * drivers/video/tegra/host/gr3d/gr3d.c
+ *
+ * Tegra Graphics Host 3D
+ *
+ * Copyright (c) 2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <mach/nvmap.h>
+#include <linux/slab.h>
+#include "t20/t20.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_syncpt.h"
+#include "nvhost_hwctx.h"
+#include "dev.h"
+#include "gr3d.h"
+#include "bus_client.h"
+#ifndef TEGRA_POWERGATE_3D1
+#define TEGRA_POWERGATE_3D1     -1
+#endif
+void nvhost_3dctx_restore_begin(struct host1x_hwctx_handler *p, u32 *ptr)
+{
+        /* set class to host */
+        ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+        /* increment sync point base */
+        ptr[1] = nvhost_class_host_incr_syncpt_base(p->waitbase,
+                        p->restore_incrs);
+        /* set class to 3D */
+        ptr[2] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
+        /* program PSEQ_QUAD_ID */
+        ptr[3] = nvhost_opcode_imm(AR3D_PSEQ_QUAD_ID, 0);
+}
+void nvhost_3dctx_restore_direct(u32 *ptr, u32 start_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_incr(start_reg, count);
+}
+void nvhost_3dctx_restore_indirect(u32 *ptr, u32 offset_reg, u32 offset,
+                        u32 data_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_imm(offset_reg, offset);
+        ptr[1] = nvhost_opcode_nonincr(data_reg, count);
+}
+void nvhost_3dctx_restore_end(struct host1x_hwctx_handler *p, u32 *ptr)
+{
+        /* syncpt increment to track restore gather. */
+        ptr[0] = nvhost_opcode_imm_incr_syncpt(
+                        NV_SYNCPT_OP_DONE, p->syncpt);
+}
+/*** ctx3d ***/
+struct host1x_hwctx *nvhost_3dctx_alloc_common(struct host1x_hwctx_handler *p,
+                struct nvhost_channel *ch, bool map_restore)
+{
+        struct nvmap_client *nvmap = nvhost_get_host(ch->dev)->nvmap;
+        struct host1x_hwctx *ctx;
+        ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+        if (!ctx)
+                return NULL;
+        ctx->restore = nvmap_alloc(nvmap, p->restore_size * 4, 32,
+                map_restore ? NVMAP_HANDLE_WRITE_COMBINE
+                            : NVMAP_HANDLE_UNCACHEABLE, 0);
+        if (IS_ERR_OR_NULL(ctx->restore))
+                goto fail;
+        if (map_restore) {
+                ctx->restore_virt = nvmap_mmap(ctx->restore);
+                if (!ctx->restore_virt)
+                        goto fail;
+        } else
+                ctx->restore_virt = NULL;
+        kref_init(&ctx->hwctx.ref);
+        ctx->hwctx.h = &p->h;
+        ctx->hwctx.channel = ch;
+        ctx->hwctx.valid = false;
+        ctx->save_incrs = p->save_incrs;
+        ctx->save_thresh = p->save_thresh;
+        ctx->save_slots = p->save_slots;
+        ctx->restore_phys = nvmap_pin(nvmap, ctx->restore);
+        if (IS_ERR_VALUE(ctx->restore_phys))
+                goto fail;
+        ctx->restore_size = p->restore_size;
+        ctx->restore_incrs = p->restore_incrs;
+        return ctx;
+fail:
+        if (map_restore && ctx->restore_virt) {
+                nvmap_munmap(ctx->restore, ctx->restore_virt);
+                ctx->restore_virt = NULL;
+        }
+        nvmap_free(nvmap, ctx->restore);
+        ctx->restore = NULL;
+        kfree(ctx);
+        return NULL;
+}
+void nvhost_3dctx_get(struct nvhost_hwctx *ctx)
+{
+        kref_get(&ctx->ref);
+}
+void nvhost_3dctx_free(struct kref *ref)
+{
+        struct nvhost_hwctx *nctx = container_of(ref, struct nvhost_hwctx, ref);
+        struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
+        struct nvmap_client *nvmap =
+                nvhost_get_host(nctx->channel->dev)->nvmap;
+        if (ctx->restore_virt) {
+                nvmap_munmap(ctx->restore, ctx->restore_virt);
+                ctx->restore_virt = NULL;
+        }
+        nvmap_unpin(nvmap, ctx->restore);
+        ctx->restore_phys = 0;
+        nvmap_free(nvmap, ctx->restore);
+        ctx->restore = NULL;
+        kfree(ctx);
+}
+void nvhost_3dctx_put(struct nvhost_hwctx *ctx)
+{
+        kref_put(&ctx->ref, nvhost_3dctx_free);
+}
+int nvhost_gr3d_prepare_power_off(struct nvhost_device *dev)
+{
+        return host1x_save_context(dev, NVSYNCPT_3D);
+}
+static int __devinit gr3d_probe(struct nvhost_device *dev)
+{
+        return nvhost_client_device_init(dev);
+}
+static int __exit gr3d_remove(struct nvhost_device *dev)
+{
+        /* Add clean-up */
+        return 0;
+}
+static int gr3d_suspend(struct nvhost_device *dev, pm_message_t state)
+{
+        return nvhost_client_device_suspend(dev);
+}
+static int gr3d_resume(struct nvhost_device *dev)
+{
+        dev_info(&dev->dev, "resuming\n");
+        return 0;
+}
+struct nvhost_device *gr3d_device;
+static struct nvhost_driver gr3d_driver = {
+        .probe = gr3d_probe,
+        .remove = __exit_p(gr3d_remove),
+#ifdef CONFIG_PM
+        .suspend = gr3d_suspend,
+        .resume = gr3d_resume,
+#endif
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "gr3d",
+        }
+};
+static int __init gr3d_init(void)
+{
+        int err;
+        gr3d_device = nvhost_get_device("gr3d");
+        if (!gr3d_device)
+                return -ENXIO;
+        err = nvhost_device_register(gr3d_device);
+        if (err)
+                return err;
+        return nvhost_driver_register(&gr3d_driver);
+}
+static void __exit gr3d_exit(void)
+{
+        nvhost_driver_unregister(&gr3d_driver);
+}
+module_init(gr3d_init);
+module_exit(gr3d_exit);
diff --git a/drivers/video/tegra/host/gr3d/gr3d.h b/drivers/video/tegra/host/gr3d/gr3d.h
new file mode 100644
index 00000000000..3855b237b70
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/gr3d.h
@@ -0,0 +1,54 @@
+/*
+ * drivers/video/tegra/host/gr3d/gr3d.h
+ *
+ * Tegra Graphics Host 3D
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_GR3D_GR3D_H
+#define __NVHOST_GR3D_GR3D_H
+#include "host1x/host1x_hwctx.h"
+#include <linux/types.h>
+/* Registers of 3D unit */
+#define AR3D_PSEQ_QUAD_ID 0x545
+#define AR3D_DW_MEMORY_OUTPUT_ADDRESS 0x904
+#define AR3D_DW_MEMORY_OUTPUT_DATA 0x905
+#define AR3D_GSHIM_WRITE_MASK 0xb00
+#define AR3D_GSHIM_READ_SELECT 0xb01
+#define AR3D_GLOBAL_MEMORY_OUTPUT_READS 0xe40
+struct nvhost_hwctx;
+struct nvhost_channel;
+struct kref;
+/* Functions used commonly by all 3D context switch modules */
+void nvhost_3dctx_restore_begin(struct host1x_hwctx_handler *h, u32 *ptr);
+void nvhost_3dctx_restore_direct(u32 *ptr, u32 start_reg, u32 count);
+void nvhost_3dctx_restore_indirect(u32 *ptr, u32 offset_reg,
+                u32 offset,     u32 data_reg, u32 count);
+void nvhost_3dctx_restore_end(struct host1x_hwctx_handler *h, u32 *ptr);
+struct host1x_hwctx *nvhost_3dctx_alloc_common(
+                struct host1x_hwctx_handler *p,
+                struct nvhost_channel *ch, bool map_restore);
+void nvhost_3dctx_get(struct nvhost_hwctx *ctx);
+void nvhost_3dctx_free(struct kref *ref);
+void nvhost_3dctx_put(struct nvhost_hwctx *ctx);
+int nvhost_gr3d_prepare_power_off(struct nvhost_device *dev);
+#endif
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t20.c b/drivers/video/tegra/host/gr3d/gr3d_t20.c
new file mode 100644
index 00000000000..3604142aaf2
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/gr3d_t20.c
@@ -0,0 +1,395 @@
+/*
+ * drivers/video/tegra/host/gr3d/gr3d_t20.c
+ *
+ * Tegra Graphics Host 3D for Tegra2
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_hwctx.h"
+#include "dev.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_syncpt.h"
+#include "gr3d.h"
+#include <linux/slab.h>
+static const struct hwctx_reginfo ctxsave_regs_3d_global[] = {
+        HWCTX_REGINFO(0xe00,    4, DIRECT),
+        HWCTX_REGINFO(0xe05,   30, DIRECT),
+        HWCTX_REGINFO(0xe25,    2, DIRECT),
+        HWCTX_REGINFO(0xe28,    2, DIRECT),
+        HWCTX_REGINFO(0x001,    2, DIRECT),
+        HWCTX_REGINFO(0x00c,   10, DIRECT),
+        HWCTX_REGINFO(0x100,   34, DIRECT),
+        HWCTX_REGINFO(0x124,    2, DIRECT),
+        HWCTX_REGINFO(0x200,    5, DIRECT),
+        HWCTX_REGINFO(0x205, 1024, INDIRECT),
+        HWCTX_REGINFO(0x207, 1024, INDIRECT),
+        HWCTX_REGINFO(0x209,    1, DIRECT),
+        HWCTX_REGINFO(0x300,   64, DIRECT),
+        HWCTX_REGINFO(0x343,   25, DIRECT),
+        HWCTX_REGINFO(0x363,    2, DIRECT),
+        HWCTX_REGINFO(0x400,   16, DIRECT),
+        HWCTX_REGINFO(0x411,    1, DIRECT),
+        HWCTX_REGINFO(0x500,    4, DIRECT),
+        HWCTX_REGINFO(0x520,   32, DIRECT),
+        HWCTX_REGINFO(0x540,   64, INDIRECT),
+        HWCTX_REGINFO(0x600,   16, INDIRECT_4X),
+        HWCTX_REGINFO(0x603,  128, INDIRECT),
+        HWCTX_REGINFO(0x608,    4, DIRECT),
+        HWCTX_REGINFO(0x60e,    1, DIRECT),
+        HWCTX_REGINFO(0x700,   64, INDIRECT),
+        HWCTX_REGINFO(0x710,   50, DIRECT),
+        HWCTX_REGINFO(0x800,   16, INDIRECT_4X),
+        HWCTX_REGINFO(0x803,  512, INDIRECT),
+        HWCTX_REGINFO(0x805,   64, INDIRECT),
+        HWCTX_REGINFO(0x820,   32, DIRECT),
+        HWCTX_REGINFO(0x900,   64, INDIRECT),
+        HWCTX_REGINFO(0x902,    2, DIRECT),
+        HWCTX_REGINFO(0xa02,   10, DIRECT),
+        HWCTX_REGINFO(0xe04,    1, DIRECT),
+        HWCTX_REGINFO(0xe2a,    1, DIRECT),
+};
+/* the same context save command sequence is used for all contexts. */
+#define SAVE_BEGIN_V0_SIZE 5
+#define SAVE_DIRECT_V0_SIZE 3
+#define SAVE_INDIRECT_V0_SIZE 5
+#define SAVE_END_V0_SIZE 5
+#define SAVE_INCRS 3
+#define SAVE_THRESH_OFFSET 1
+#define RESTORE_BEGIN_SIZE 4
+#define RESTORE_DIRECT_SIZE 1
+#define RESTORE_INDIRECT_SIZE 2
+#define RESTORE_END_SIZE 1
+struct save_info {
+        u32 *ptr;
+        unsigned int save_count;
+        unsigned int restore_count;
+        unsigned int save_incrs;
+        unsigned int restore_incrs;
+};
+static u32 *setup_restore_regs_v0(u32 *ptr,
+                        const struct hwctx_reginfo *regs,
+                        unsigned int nr_regs)
+{
+        const struct hwctx_reginfo *rend = regs + nr_regs;
+        for ( ; regs != rend; ++regs) {
+                u32 offset = regs->offset;
+                u32 count = regs->count;
+                u32 indoff = offset + 1;
+                switch (regs->type) {
+                case HWCTX_REGINFO_DIRECT:
+                        nvhost_3dctx_restore_direct(ptr, offset, count);
+                        ptr += RESTORE_DIRECT_SIZE;
+                        break;
+                case HWCTX_REGINFO_INDIRECT_4X:
+                        ++indoff;
+                        /* fall through */
+                case HWCTX_REGINFO_INDIRECT:
+                        nvhost_3dctx_restore_indirect(ptr,
+                                        offset, 0, indoff, count);
+                        ptr += RESTORE_INDIRECT_SIZE;
+                        break;
+                }
+                ptr += count;
+        }
+        return ptr;
+}
+static void setup_restore_v0(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        nvhost_3dctx_restore_begin(h, ptr);
+        ptr += RESTORE_BEGIN_SIZE;
+        ptr = setup_restore_regs_v0(ptr,
+                        ctxsave_regs_3d_global,
+                        ARRAY_SIZE(ctxsave_regs_3d_global));
+        nvhost_3dctx_restore_end(h, ptr);
+        wmb();
+}
+/*** v0 saver ***/
+static void save_push_v0(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
+{
+        struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
+        struct host1x_hwctx_handler *p = host1x_hwctx_handler(ctx);
+        nvhost_cdma_push_gather(cdma,
+                        (void *)NVHOST_CDMA_PUSH_GATHER_CTXSAVE,
+                        (void *)NVHOST_CDMA_PUSH_GATHER_CTXSAVE,
+                        nvhost_opcode_gather(p->save_size),
+                        p->save_phys);
+}
+static void __init save_begin_v0(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        /* 3d: when done, increment syncpt to base+1 */
+        ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
+        ptr[1] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+                        h->syncpt); /*  incr 1 */
+        /* host: wait for syncpt base+1 */
+        ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+        ptr[3] = nvhost_class_host_wait_syncpt_base(h->syncpt,
+                                                h->waitbase, 1);
+        /* host: signal context read thread to start reading */
+        ptr[4] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+                        h->syncpt); /* incr 2 */
+}
+static void __init save_direct_v0(u32 *ptr, u32 start_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDOFF, 1);
+        ptr[1] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
+                                                start_reg, true);
+        ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+}
+static void __init save_indirect_v0(u32 *ptr, u32 offset_reg, u32 offset,
+                        u32 data_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
+                                        offset_reg, 1);
+        ptr[1] = offset;
+        ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_INDOFF, 1);
+        ptr[3] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
+                                                data_reg, false);
+        ptr[4] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+}
+static void __init save_end_v0(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        /* Wait for context read service to finish (cpu incr 3) */
+        ptr[0] = nvhost_opcode_nonincr(NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+        ptr[1] = nvhost_class_host_wait_syncpt_base(h->syncpt,
+                        h->waitbase, h->save_incrs);
+        /* Advance syncpoint base */
+        ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+        ptr[3] = nvhost_class_host_incr_syncpt_base(NVWAITBASE_3D,
+                        h->save_incrs);
+        /* set class back to the unit */
+        ptr[4] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
+}
+static u32 *save_regs_v0(u32 *ptr, unsigned int *pending,
+                        void __iomem *chan_regs,
+                        const struct hwctx_reginfo *regs,
+                        unsigned int nr_regs)
+{
+        const struct hwctx_reginfo *rend = regs + nr_regs;
+        int drain_result = 0;
+        for ( ; regs != rend; ++regs) {
+                u32 count = regs->count;
+                switch (regs->type) {
+                case HWCTX_REGINFO_DIRECT:
+                        ptr += RESTORE_DIRECT_SIZE;
+                        break;
+                case HWCTX_REGINFO_INDIRECT:
+                case HWCTX_REGINFO_INDIRECT_4X:
+                        ptr += RESTORE_INDIRECT_SIZE;
+                        break;
+                }
+                drain_result = host1x_drain_read_fifo(chan_regs,
+                        ptr, count, pending);
+                BUG_ON(drain_result < 0);
+                ptr += count;
+        }
+        return ptr;
+}
+/*** save ***/
+static void __init setup_save_regs(struct save_info *info,
+                        const struct hwctx_reginfo *regs,
+                        unsigned int nr_regs)
+{
+        const struct hwctx_reginfo *rend = regs + nr_regs;
+        u32 *ptr = info->ptr;
+        unsigned int save_count = info->save_count;
+        unsigned int restore_count = info->restore_count;
+        for ( ; regs != rend; ++regs) {
+                u32 offset = regs->offset;
+                u32 count = regs->count;
+                u32 indoff = offset + 1;
+                switch (regs->type) {
+                case HWCTX_REGINFO_DIRECT:
+                        if (ptr) {
+                                save_direct_v0(ptr, offset, count);
+                                ptr += SAVE_DIRECT_V0_SIZE;
+                        }
+                        save_count += SAVE_DIRECT_V0_SIZE;
+                        restore_count += RESTORE_DIRECT_SIZE;
+                        break;
+                case HWCTX_REGINFO_INDIRECT_4X:
+                        ++indoff;
+                        /* fall through */
+                case HWCTX_REGINFO_INDIRECT:
+                        if (ptr) {
+                                save_indirect_v0(ptr, offset, 0,
+                                                indoff, count);
+                                ptr += SAVE_INDIRECT_V0_SIZE;
+                        }
+                        save_count += SAVE_INDIRECT_V0_SIZE;
+                        restore_count += RESTORE_INDIRECT_SIZE;
+                        break;
+                }
+                if (ptr) {
+                        /* SAVE cases only: reserve room for incoming data */
+                        u32 k = 0;
+                        /*
+                         * Create a signature pattern for indirect data (which
+                         * will be overwritten by true incoming data) for
+                         * better deducing where we are in a long command
+                         * sequence, when given only a FIFO snapshot for debug
+                         * purposes.
+                        */
+                        for (k = 0; k < count; k++)
+                                *(ptr + k) = 0xd000d000 | (offset << 16) | k;
+                        ptr += count;
+                }
+                save_count += count;
+                restore_count += count;
+        }
+        info->ptr = ptr;
+        info->save_count = save_count;
+        info->restore_count = restore_count;
+}
+static void __init setup_save(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        struct save_info info = {
+                ptr,
+                SAVE_BEGIN_V0_SIZE,
+                RESTORE_BEGIN_SIZE,
+                SAVE_INCRS,
+                1
+        };
+        if (info.ptr) {
+                save_begin_v0(h, info.ptr);
+                info.ptr += SAVE_BEGIN_V0_SIZE;
+        }
+        /* save regs */
+        setup_save_regs(&info,
+                        ctxsave_regs_3d_global,
+                        ARRAY_SIZE(ctxsave_regs_3d_global));
+        if (info.ptr) {
+                save_end_v0(h, info.ptr);
+                info.ptr += SAVE_END_V0_SIZE;
+        }
+        wmb();
+        h->save_size = info.save_count + SAVE_END_V0_SIZE;
+        h->restore_size = info.restore_count + RESTORE_END_SIZE;
+        h->save_incrs = info.save_incrs;
+        h->save_thresh = h->save_incrs - SAVE_THRESH_OFFSET;
+        h->restore_incrs = info.restore_incrs;
+}
+/*** ctx3d ***/
+static struct nvhost_hwctx *ctx3d_alloc_v0(struct nvhost_hwctx_handler *h,
+                struct nvhost_channel *ch)
+{
+        struct host1x_hwctx_handler *p = to_host1x_hwctx_handler(h);
+        struct host1x_hwctx *ctx =
+                nvhost_3dctx_alloc_common(p, ch, true);
+        if (ctx) {
+                setup_restore_v0(p, ctx->restore_virt);
+                return &ctx->hwctx;
+        } else
+                return NULL;
+}
+static void ctx3d_save_service(struct nvhost_hwctx *nctx)
+{
+        struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
+        u32 *ptr = (u32 *)ctx->restore_virt + RESTORE_BEGIN_SIZE;
+        unsigned int pending = 0;
+        ptr = save_regs_v0(ptr, &pending, nctx->channel->aperture,
+                        ctxsave_regs_3d_global,
+                        ARRAY_SIZE(ctxsave_regs_3d_global));
+        wmb();
+        nvhost_syncpt_cpu_incr(&nvhost_get_host(nctx->channel->dev)->syncpt,
+                        host1x_hwctx_handler(ctx)->syncpt);
+}
+struct nvhost_hwctx_handler * __init nvhost_gr3d_t20_ctxhandler_init(
+                u32 syncpt, u32 waitbase,
+                struct nvhost_channel *ch)
+{
+        struct nvmap_client *nvmap;
+        u32 *save_ptr;
+        struct host1x_hwctx_handler *p;
+        p = kmalloc(sizeof(*p), GFP_KERNEL);
+        if (!p)
+                return NULL;
+        nvmap = nvhost_get_host(ch->dev)->nvmap;
+        p->syncpt = syncpt;
+        p->waitbase = waitbase;
+        setup_save(p, NULL);
+        p->save_buf = nvmap_alloc(nvmap, p->save_size * sizeof(u32), 32,
+                                NVMAP_HANDLE_WRITE_COMBINE, 0);
+        if (IS_ERR(p->save_buf)) {
+                p->save_buf = NULL;
+                return NULL;
+        }
+        p->save_slots = 1;
+        save_ptr = nvmap_mmap(p->save_buf);
+        if (!save_ptr) {
+                nvmap_free(nvmap, p->save_buf);
+                p->save_buf = NULL;
+                return NULL;
+        }
+        p->save_phys = nvmap_pin(nvmap, p->save_buf);
+        setup_save(p, save_ptr);
+        p->h.alloc = ctx3d_alloc_v0;
+        p->h.save_push = save_push_v0;
+        p->h.save_service = ctx3d_save_service;
+        p->h.get = nvhost_3dctx_get;
+        p->h.put = nvhost_3dctx_put;
+        return &p->h;
+}
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t20.h b/drivers/video/tegra/host/gr3d/gr3d_t20.h
new file mode 100644
index 00000000000..5fe6d50d0c3
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/gr3d_t20.h
@@ -0,0 +1,30 @@
+/*
+ * drivers/video/tegra/host/gr3d/gr3d_t20.h
+ *
+ * Tegra Graphics Host 3D for Tegra2
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_GR3D_GR3D_T20_H
+#define __NVHOST_GR3D_GR3D_T20_H
+struct nvhost_hwctx_handler;
+struct nvhost_hwctx_handler *nvhost_gr3d_t20_ctxhandler_init(
+                u32 syncpt, u32 waitbase,
+                struct nvhost_channel *ch);
+#endif
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t30.c b/drivers/video/tegra/host/gr3d/gr3d_t30.c
new file mode 100644
index 00000000000..e7329e50e3d
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/gr3d_t30.c
@@ -0,0 +1,435 @@
+/*
+ * drivers/video/tegra/host/gr3d/gr3d_t30.c
+ *
+ * Tegra Graphics Host 3D for Tegra3
+ *
+ * Copyright (c) 2011-2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_hwctx.h"
+#include "dev.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_syncpt.h"
+#include "gr3d.h"
+#include <mach/gpufuse.h>
+#include <mach/hardware.h>
+#include <linux/slab.h>
+/*  99 > 2, which makes kernel panic if register set is incorrect */
+static int register_sets = 99;
+static const struct hwctx_reginfo ctxsave_regs_3d_global[] = {
+        HWCTX_REGINFO(0xe00,    4, DIRECT),
+        HWCTX_REGINFO(0xe05,   30, DIRECT),
+        HWCTX_REGINFO(0xe25,    2, DIRECT),
+        HWCTX_REGINFO(0xe28,    2, DIRECT),
+        HWCTX_REGINFO(0xe30,   16, DIRECT),
+        HWCTX_REGINFO(0x001,    2, DIRECT),
+        HWCTX_REGINFO(0x00c,   10, DIRECT),
+        HWCTX_REGINFO(0x100,   34, DIRECT),
+        HWCTX_REGINFO(0x124,    2, DIRECT),
+        HWCTX_REGINFO(0x200,    5, DIRECT),
+        HWCTX_REGINFO(0x205, 1024, INDIRECT),
+        HWCTX_REGINFO(0x207, 1024, INDIRECT),
+        HWCTX_REGINFO(0x209,    1, DIRECT),
+        HWCTX_REGINFO(0x300,   64, DIRECT),
+        HWCTX_REGINFO(0x343,   25, DIRECT),
+        HWCTX_REGINFO(0x363,    2, DIRECT),
+        HWCTX_REGINFO(0x400,   16, DIRECT),
+        HWCTX_REGINFO(0x411,    1, DIRECT),
+        HWCTX_REGINFO(0x412,    1, DIRECT),
+        HWCTX_REGINFO(0x500,    4, DIRECT),
+        HWCTX_REGINFO(0x520,   32, DIRECT),
+        HWCTX_REGINFO(0x540,   64, INDIRECT),
+        HWCTX_REGINFO(0x600,   16, INDIRECT_4X),
+        HWCTX_REGINFO(0x603,  128, INDIRECT),
+        HWCTX_REGINFO(0x608,    4, DIRECT),
+        HWCTX_REGINFO(0x60e,    1, DIRECT),
+        HWCTX_REGINFO(0x700,   64, INDIRECT),
+        HWCTX_REGINFO(0x710,   50, DIRECT),
+        HWCTX_REGINFO(0x750,   16, DIRECT),
+        HWCTX_REGINFO(0x800,   16, INDIRECT_4X),
+        HWCTX_REGINFO(0x803,  512, INDIRECT),
+        HWCTX_REGINFO(0x805,   64, INDIRECT),
+        HWCTX_REGINFO(0x820,   32, DIRECT),
+        HWCTX_REGINFO(0x900,   64, INDIRECT),
+        HWCTX_REGINFO(0x902,    2, DIRECT),
+        HWCTX_REGINFO(0x90a,    1, DIRECT),
+        HWCTX_REGINFO(0xa02,   10, DIRECT),
+        HWCTX_REGINFO(0xb04,    1, DIRECT),
+        HWCTX_REGINFO(0xb06,   13, DIRECT),
+        HWCTX_REGINFO(0xe42,    2, DIRECT), /* HW bug workaround */
+};
+static const struct hwctx_reginfo ctxsave_regs_3d_perset[] = {
+        HWCTX_REGINFO(0xe04,    1, DIRECT),
+        HWCTX_REGINFO(0xe2a,    1, DIRECT),
+        HWCTX_REGINFO(0x413,    1, DIRECT),
+        HWCTX_REGINFO(0x90b,    1, DIRECT),
+        HWCTX_REGINFO(0xe41,    1, DIRECT),
+};
+static unsigned int restore_set1_offset;
+#define SAVE_BEGIN_V1_SIZE (1 + RESTORE_BEGIN_SIZE)
+#define SAVE_DIRECT_V1_SIZE (4 + RESTORE_DIRECT_SIZE)
+#define SAVE_INDIRECT_V1_SIZE (6 + RESTORE_INDIRECT_SIZE)
+#define SAVE_END_V1_SIZE (9 + RESTORE_END_SIZE)
+#define SAVE_INCRS 3
+#define SAVE_THRESH_OFFSET 0
+#define RESTORE_BEGIN_SIZE 4
+#define RESTORE_DIRECT_SIZE 1
+#define RESTORE_INDIRECT_SIZE 2
+#define RESTORE_END_SIZE 1
+struct save_info {
+        u32 *ptr;
+        unsigned int save_count;
+        unsigned int restore_count;
+        unsigned int save_incrs;
+        unsigned int restore_incrs;
+};
+/*** v1 saver ***/
+static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
+{
+        struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
+        struct host1x_hwctx_handler *p = host1x_hwctx_handler(ctx);
+        /* wait for 3d idle */
+        nvhost_cdma_push(cdma,
+                        nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
+                        nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+                                        p->syncpt));
+        nvhost_cdma_push(cdma,
+                        nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
+                        nvhost_class_host_wait_syncpt_base(p->syncpt,
+                                                        p->waitbase, 1));
+        /* back to 3d */
+        nvhost_cdma_push(cdma,
+                        nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
+                        NVHOST_OPCODE_NOOP);
+        /* set register set 0 and 1 register read memory output addresses,
+           and send their reads to memory */
+        if (register_sets == 2) {
+                nvhost_cdma_push(cdma,
+                        nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 2),
+                        nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS,
+                                        1));
+                nvhost_cdma_push(cdma,
+                                nvhost_opcode_nonincr(0x904, 1),
+                                ctx->restore_phys + restore_set1_offset * 4);
+        }
+        nvhost_cdma_push(cdma,
+                nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 1),
+                nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1));
+        nvhost_cdma_push(cdma,
+                nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1),
+                ctx->restore_phys);
+        /* gather the save buffer */
+        nvhost_cdma_push_gather(cdma,
+                        (void *)NVHOST_CDMA_PUSH_GATHER_CTXSAVE,
+                        (void *)NVHOST_CDMA_PUSH_GATHER_CTXSAVE,
+                        nvhost_opcode_gather(p->save_size),
+                        p->save_phys);
+}
+static void __init save_begin_v1(struct host1x_hwctx_handler *p, u32 *ptr)
+{
+        ptr[0] = nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_DATA,
+                        RESTORE_BEGIN_SIZE);
+        nvhost_3dctx_restore_begin(p, ptr + 1);
+        ptr += RESTORE_BEGIN_SIZE;
+}
+static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
+                        AR3D_DW_MEMORY_OUTPUT_DATA, 1);
+        nvhost_3dctx_restore_direct(ptr + 1, start_reg, count);
+        ptr += RESTORE_DIRECT_SIZE;
+        ptr[1] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_INDOFF, 1);
+        ptr[2] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
+                                                start_reg, true);
+        /* TODO could do this in the setclass if count < 6 */
+        ptr[3] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+}
+static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
+                        u32 data_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
+        ptr[1] = nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_DATA,
+                        RESTORE_INDIRECT_SIZE);
+        nvhost_3dctx_restore_indirect(ptr + 2, offset_reg, offset, data_reg,
+                        count);
+        ptr += RESTORE_INDIRECT_SIZE;
+        ptr[2] = nvhost_opcode_imm(offset_reg, offset);
+        ptr[3] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_INDOFF, 1);
+        ptr[4] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
+                                                data_reg, false);
+        ptr[5] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+}
+static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
+{
+        /* write end of restore buffer */
+        ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
+                        AR3D_DW_MEMORY_OUTPUT_DATA, 1);
+        nvhost_3dctx_restore_end(p, ptr + 1);
+        ptr += RESTORE_END_SIZE;
+        /* reset to dual reg if necessary */
+        ptr[1] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
+                        (1 << register_sets) - 1);
+        /* op_done syncpt incr to flush FDC */
+        ptr[2] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, p->syncpt);
+        /* host wait for that syncpt incr, and advance the wait base */
+        ptr[3] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                        NV_CLASS_HOST_WAIT_SYNCPT_BASE,
+                        nvhost_mask2(
+                                        NV_CLASS_HOST_WAIT_SYNCPT_BASE,
+                                        NV_CLASS_HOST_INCR_SYNCPT_BASE));
+        ptr[4] = nvhost_class_host_wait_syncpt_base(p->syncpt,
+                                p->waitbase, p->save_incrs - 1);
+        ptr[5] = nvhost_class_host_incr_syncpt_base(p->waitbase,
+                        p->save_incrs);
+        /* set class back to 3d */
+        ptr[6] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
+        /* send reg reads back to host */
+        ptr[7] = nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 0);
+        /* final syncpt increment to release waiters */
+        ptr[8] = nvhost_opcode_imm(0, p->syncpt);
+}
+/*** save ***/
+static void __init setup_save_regs(struct save_info *info,
+                        const struct hwctx_reginfo *regs,
+                        unsigned int nr_regs)
+{
+        const struct hwctx_reginfo *rend = regs + nr_regs;
+        u32 *ptr = info->ptr;
+        unsigned int save_count = info->save_count;
+        unsigned int restore_count = info->restore_count;
+        for ( ; regs != rend; ++regs) {
+                u32 offset = regs->offset;
+                u32 count = regs->count;
+                u32 indoff = offset + 1;
+                switch (regs->type) {
+                case HWCTX_REGINFO_DIRECT:
+                        if (ptr) {
+                                save_direct_v1(ptr, offset, count);
+                                ptr += SAVE_DIRECT_V1_SIZE;
+                        }
+                        save_count += SAVE_DIRECT_V1_SIZE;
+                        restore_count += RESTORE_DIRECT_SIZE;
+                        break;
+                case HWCTX_REGINFO_INDIRECT_4X:
+                        ++indoff;
+                        /* fall through */
+                case HWCTX_REGINFO_INDIRECT:
+                        if (ptr) {
+                                save_indirect_v1(ptr, offset, 0,
+                                                indoff, count);
+                                ptr += SAVE_INDIRECT_V1_SIZE;
+                        }
+                        save_count += SAVE_INDIRECT_V1_SIZE;
+                        restore_count += RESTORE_INDIRECT_SIZE;
+                        break;
+                }
+                if (ptr) {
+                        /* SAVE cases only: reserve room for incoming data */
+                        u32 k = 0;
+                        /*
+                         * Create a signature pattern for indirect data (which
+                         * will be overwritten by true incoming data) for
+                         * better deducing where we are in a long command
+                         * sequence, when given only a FIFO snapshot for debug
+                         * purposes.
+                        */
+                        for (k = 0; k < count; k++)
+                                *(ptr + k) = 0xd000d000 | (offset << 16) | k;
+                        ptr += count;
+                }
+                save_count += count;
+                restore_count += count;
+        }
+        info->ptr = ptr;
+        info->save_count = save_count;
+        info->restore_count = restore_count;
+}
+static void __init switch_gpu(struct save_info *info,
+                        unsigned int save_src_set,
+                        u32 save_dest_sets,
+                        u32 restore_dest_sets)
+{
+        if (info->ptr) {
+                info->ptr[0] = nvhost_opcode_setclass(
+                                NV_GRAPHICS_3D_CLASS_ID,
+                                AR3D_DW_MEMORY_OUTPUT_DATA, 1);
+                info->ptr[1] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
+                                restore_dest_sets);
+                info->ptr[2] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
+                                save_dest_sets);
+                info->ptr[3] = nvhost_opcode_imm(AR3D_GSHIM_READ_SELECT,
+                                save_src_set);
+                info->ptr += 4;
+        }
+        info->save_count += 4;
+        info->restore_count += 1;
+}
+static void __init setup_save(struct host1x_hwctx_handler *p, u32 *ptr)
+{
+        struct save_info info = {
+                ptr,
+                SAVE_BEGIN_V1_SIZE,
+                RESTORE_BEGIN_SIZE,
+                SAVE_INCRS,
+                1
+        };
+        int save_end_size = SAVE_END_V1_SIZE;
+        BUG_ON(register_sets > 2);
+        if (info.ptr) {
+                save_begin_v1(p, info.ptr);
+                info.ptr += SAVE_BEGIN_V1_SIZE;
+        }
+        /* read from set0, write cmds through set0, restore to set0 and 1 */
+        if (register_sets == 2)
+                switch_gpu(&info, 0, 1, 3);
+        /* save regs that are common to both sets */
+        setup_save_regs(&info,
+                        ctxsave_regs_3d_global,
+                        ARRAY_SIZE(ctxsave_regs_3d_global));
+        /* read from set 0, write cmds through set0, restore to set0 */
+        if (register_sets == 2)
+                switch_gpu(&info, 0, 1, 1);
+        /* save set 0 specific regs */
+        setup_save_regs(&info,
+                        ctxsave_regs_3d_perset,
+                        ARRAY_SIZE(ctxsave_regs_3d_perset));
+        if (register_sets == 2) {
+                /* read from set1, write cmds through set1, restore to set1 */
+                switch_gpu(&info, 1, 2, 2);
+                /* note offset at which set 1 restore starts */
+                restore_set1_offset = info.restore_count;
+                /* save set 1 specific regs */
+                setup_save_regs(&info,
+                                ctxsave_regs_3d_perset,
+                                ARRAY_SIZE(ctxsave_regs_3d_perset));
+        }
+        /* read from set0, write cmds through set1, restore to set0 and 1 */
+        if (register_sets == 2)
+                switch_gpu(&info, 0, 2, 3);
+        if (info.ptr) {
+                save_end_v1(p, info.ptr);
+                info.ptr += SAVE_END_V1_SIZE;
+        }
+        wmb();
+        p->save_size = info.save_count + save_end_size;
+        p->restore_size = info.restore_count + RESTORE_END_SIZE;
+        p->save_incrs = info.save_incrs;
+        p->save_thresh = p->save_incrs - SAVE_THRESH_OFFSET;
+        p->restore_incrs = info.restore_incrs;
+}
+/*** ctx3d ***/
+static struct nvhost_hwctx *ctx3d_alloc_v1(struct nvhost_hwctx_handler *h,
+                struct nvhost_channel *ch)
+{
+        struct host1x_hwctx_handler *p = to_host1x_hwctx_handler(h);
+        struct host1x_hwctx *ctx = nvhost_3dctx_alloc_common(p, ch, false);
+        if (ctx)
+                return &ctx->hwctx;
+        else
+                return NULL;
+}
+struct nvhost_hwctx_handler *__init nvhost_gr3d_t30_ctxhandler_init(
+                u32 syncpt, u32 waitbase,
+                struct nvhost_channel *ch)
+{
+        struct nvmap_client *nvmap;
+        u32 *save_ptr;
+        struct host1x_hwctx_handler *p;
+        p = kmalloc(sizeof(*p), GFP_KERNEL);
+        if (!p)
+                return NULL;
+        nvmap = nvhost_get_host(ch->dev)->nvmap;
+        register_sets = tegra_gpu_register_sets();
+        BUG_ON(register_sets == 0 || register_sets > 2);
+        p->syncpt = syncpt;
+        p->waitbase = waitbase;
+        setup_save(p, NULL);
+        p->save_buf = nvmap_alloc(nvmap, p->save_size * 4, 32,
+                                NVMAP_HANDLE_WRITE_COMBINE, 0);
+        if (IS_ERR(p->save_buf)) {
+                p->save_buf = NULL;
+                return NULL;
+        }
+        p->save_slots = 6;
+        if (register_sets == 2)
+                p->save_slots += 2;
+        save_ptr = nvmap_mmap(p->save_buf);
+        if (!save_ptr) {
+                nvmap_free(nvmap, p->save_buf);
+                p->save_buf = NULL;
+                return NULL;
+        }
+        p->save_phys = nvmap_pin(nvmap, p->save_buf);
+        setup_save(p, save_ptr);
+        p->h.alloc = ctx3d_alloc_v1;
+        p->h.save_push = save_push_v1;
+        p->h.save_service = NULL;
+        p->h.get = nvhost_3dctx_get;
+        p->h.put = nvhost_3dctx_put;
+        return &p->h;
+}
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t30.h b/drivers/video/tegra/host/gr3d/gr3d_t30.h
new file mode 100644
index 00000000000..d1b787e14b4
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/gr3d_t30.h
@@ -0,0 +1,30 @@
+/*
+ * drivers/video/tegra/host/gr3d/gr3d_t30.h
+ *
+ * Tegra Graphics Host 3D for Tegra3
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_GR3D_GR3D_T30_H
+#define __NVHOST_GR3D_GR3D_T30_H
+struct nvhost_hwctx_handler;
+struct nvhost_hwctx_handler *nvhost_gr3d_t30_ctxhandler_init(
+                u32 syncpt, u32 waitbase,
+                struct nvhost_channel *ch);
+#endif
diff --git a/drivers/video/tegra/host/gr3d/scale3d.c b/drivers/video/tegra/host/gr3d/scale3d.c
new file mode 100644
index 00000000000..8a267a127ea
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/scale3d.c
@@ -0,0 +1,661 @@
+/*
+ * drivers/video/tegra/host/t20/scale3d.c
+ *
+ * Tegra Graphics Host 3D clock scaling
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * 3d clock scaling
+ *
+ * module3d_notify_busy() is called upon submit, module3d_notify_idle() is
+ * called when all outstanding submits are completed. Idle times are measured
+ * over a fixed time period (scale3d.p_period). If the 3d module idle time
+ * percentage goes over the limit (set in scale3d.p_idle_max), 3d clocks are
+ * scaled down. If the percentage goes under the minimum limit (set in
+ * scale3d.p_idle_min), 3d clocks are scaled up. An additional test is made
+ * over the time frame given in scale3d.p_fast_response for clocking up
+ * quickly in response to load peaks.
+ *
+ * 3d.emc clock is scaled proportionately to 3d clock, with a quadratic-
+ * bezier-like factor added to pull 3d.emc rate a bit lower.
+ */
+#include <linux/debugfs.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <mach/clk.h>
+#include <mach/hardware.h>
+#include "scale3d.h"
+#include "dev.h"
+static int scale3d_is_enabled(void);
+static void scale3d_enable(int enable);
+#define POW2(x) ((x) * (x))
+/*
+ * debugfs parameters to control 3d clock scaling test
+ *
+ * period        - time period for clock rate evaluation
+ * fast_response - time period for evaluation of 'busy' spikes
+ * idle_min      - if less than [idle_min] percent idle over [fast_response]
+ *                 microseconds, clock up.
+ * idle_max      - if over [idle_max] percent idle over [period] microseconds,
+ *                 clock down.
+ * max_scale     - limits rate changes to no less than (100 - max_scale)% or
+ *                 (100 + 2 * max_scale)% of current clock rate
+ * verbosity     - set above 5 for debug printouts
+ */
+struct scale3d_info_rec {
+        struct mutex lock; /* lock for timestamps etc */
+        int enable;
+        int init;
+        ktime_t idle_frame;
+        ktime_t fast_frame;
+        ktime_t last_idle;
+        ktime_t last_short_term_idle;
+        int is_idle;
+        ktime_t last_tweak;
+        ktime_t last_down;
+        int fast_up_count;
+        int slow_down_count;
+        int is_scaled;
+        int fast_responses;
+        unsigned long idle_total;
+        unsigned long idle_short_term_total;
+        unsigned long max_rate_3d;
+        long emc_slope;
+        long emc_offset;
+        long emc_dip_slope;
+        long emc_dip_offset;
+        long emc_xmid;
+        unsigned long min_rate_3d;
+        struct work_struct work;
+        struct delayed_work idle_timer;
+        unsigned int scale;
+        unsigned int p_period;
+        unsigned int period;
+        unsigned int p_idle_min;
+        unsigned int idle_min;
+        unsigned int p_idle_max;
+        unsigned int idle_max;
+        unsigned int p_fast_response;
+        unsigned int fast_response;
+        unsigned int p_adjust;
+        unsigned int p_scale_emc;
+        unsigned int p_emc_dip;
+        unsigned int p_verbosity;
+        struct clk *clk_3d;
+        struct clk *clk_3d2;
+        struct clk *clk_3d_emc;
+};
+static struct scale3d_info_rec scale3d;
+static void scale3d_clocks(unsigned long percent)
+{
+        unsigned long hz, curr;
+        if (!tegra_is_clk_enabled(scale3d.clk_3d))
+                return;
+        if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3)
+                if (!tegra_is_clk_enabled(scale3d.clk_3d2))
+                        return;
+        curr = clk_get_rate(scale3d.clk_3d);
+        hz = percent * (curr / 100);
+        if (!(hz >= scale3d.max_rate_3d && curr == scale3d.max_rate_3d)) {
+                if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3)
+                        clk_set_rate(scale3d.clk_3d2, 0);
+                clk_set_rate(scale3d.clk_3d, hz);
+                if (scale3d.p_scale_emc) {
+                        long after = (long) clk_get_rate(scale3d.clk_3d);
+                        hz = after * scale3d.emc_slope + scale3d.emc_offset;
+                        if (scale3d.p_emc_dip)
+                                hz -=
+                                        (scale3d.emc_dip_slope *
+                                        POW2(after / 1000 - scale3d.emc_xmid) +
+                                        scale3d.emc_dip_offset);
+                        clk_set_rate(scale3d.clk_3d_emc, hz);
+                }
+        }
+}
+static void scale3d_clocks_handler(struct work_struct *work)
+{
+        unsigned int scale;
+        mutex_lock(&scale3d.lock);
+        scale = scale3d.scale;
+        mutex_unlock(&scale3d.lock);
+        if (scale != 0)
+                scale3d_clocks(scale);
+}
+void nvhost_scale3d_suspend(struct nvhost_device *dev)
+{
+        if (!scale3d.enable)
+                return;
+        cancel_work_sync(&scale3d.work);
+        cancel_delayed_work(&scale3d.idle_timer);
+}
+/* set 3d clocks to max */
+static void reset_3d_clocks(void)
+{
+        if (clk_get_rate(scale3d.clk_3d) != scale3d.max_rate_3d) {
+                clk_set_rate(scale3d.clk_3d, scale3d.max_rate_3d);
+                if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3)
+                        clk_set_rate(scale3d.clk_3d2, scale3d.max_rate_3d);
+                if (scale3d.p_scale_emc)
+                        clk_set_rate(scale3d.clk_3d_emc,
+                                clk_round_rate(scale3d.clk_3d_emc, UINT_MAX));
+        }
+}
+static int scale3d_is_enabled(void)
+{
+        int enable;
+        if (!scale3d.enable)
+                return 0;
+        mutex_lock(&scale3d.lock);
+        enable = scale3d.enable;
+        mutex_unlock(&scale3d.lock);
+        return enable;
+}
+static void scale3d_enable(int enable)
+{
+        int disable = 0;
+        mutex_lock(&scale3d.lock);
+        if (enable) {
+                if (scale3d.max_rate_3d != scale3d.min_rate_3d)
+                        scale3d.enable = 1;
+        } else {
+                scale3d.enable = 0;
+                disable = 1;
+        }
+        mutex_unlock(&scale3d.lock);
+        if (disable)
+                reset_3d_clocks();
+}
+static void reset_scaling_counters(ktime_t time)
+{
+        scale3d.idle_total = 0;
+        scale3d.idle_short_term_total = 0;
+        scale3d.last_idle = time;
+        scale3d.last_short_term_idle = time;
+        scale3d.idle_frame = time;
+}
+/* scaling_adjust - use scale up / scale down hint counts to adjust scaling
+ * parameters.
+ *
+ * hint_ratio is 100 x the ratio of scale up to scale down hints. Three cases
+ * are distinguished:
+ *
+ * hint_ratio < HINT_RATIO_MIN - set parameters to maximize scaling effect
+ * hint_ratio > HINT_RATIO_MAX - set parameters to minimize scaling effect
+ * hint_ratio between limits - scale parameters linearly
+ *
+ * the parameters adjusted are
+ *
+ * * fast_response time
+ * * period - time for scaling down estimate
+ * * idle_min percentage
+ * * idle_max percentage
+ */
+#define SCALING_ADJUST_PERIOD 1000000
+#define HINT_RATIO_MAX 400
+#define HINT_RATIO_MIN 100
+#define HINT_RATIO_MID ((HINT_RATIO_MAX + HINT_RATIO_MIN) / 2)
+#define HINT_RATIO_DIFF (HINT_RATIO_MAX - HINT_RATIO_MIN)
+static void scaling_adjust(ktime_t time)
+{
+        long hint_ratio;
+        long fast_response_adjustment;
+        long period_adjustment;
+        int idle_min_adjustment;
+        int idle_max_adjustment;
+        unsigned long dt;
+        dt = (unsigned long) ktime_us_delta(time, scale3d.last_tweak);
+        if (dt < SCALING_ADJUST_PERIOD)
+                return;
+        hint_ratio = (100 * (scale3d.fast_up_count + 1)) /
+                                 (scale3d.slow_down_count + 1);
+        if (hint_ratio > HINT_RATIO_MAX) {
+                fast_response_adjustment = -((int) scale3d.p_fast_response) / 4;
+                period_adjustment = scale3d.p_period / 2;
+                idle_min_adjustment = scale3d.p_idle_min;
+                idle_max_adjustment = scale3d.p_idle_max;
+        } else if (hint_ratio < HINT_RATIO_MIN) {
+                fast_response_adjustment = scale3d.p_fast_response / 2;
+                period_adjustment = -((int) scale3d.p_period) / 4;
+                idle_min_adjustment = -((int) scale3d.p_idle_min) / 2;
+                idle_max_adjustment = -((int) scale3d.p_idle_max) / 2;
+        } else {
+                int diff;
+                int factor;
+                diff = HINT_RATIO_MID - hint_ratio;
+                if (diff < 0)
+                        factor = -diff * 2;
+                else {
+                        factor = -diff;
+                        diff *= 2;
+                }
+                fast_response_adjustment = diff *
+                        (scale3d.p_fast_response / (HINT_RATIO_DIFF * 2));
+                period_adjustment =
+                        diff * (scale3d.p_period / HINT_RATIO_DIFF);
+                idle_min_adjustment =
+                        (factor * (int) scale3d.p_idle_min) / HINT_RATIO_DIFF;
+                idle_max_adjustment =
+                        (factor * (int) scale3d.p_idle_max) / HINT_RATIO_DIFF;
+        }
+        scale3d.fast_response =
+                scale3d.p_fast_response + fast_response_adjustment;
+        scale3d.period = scale3d.p_period + period_adjustment;
+                scale3d.idle_min = scale3d.p_idle_min + idle_min_adjustment;
+        scale3d.idle_max = scale3d.p_idle_max + idle_max_adjustment;
+        if (scale3d.p_verbosity >= 10)
+                pr_info("scale3d stats: + %d - %d (/ %d) f %u p %u min %u max %u\n",
+                        scale3d.fast_up_count, scale3d.slow_down_count,
+                        scale3d.fast_responses, scale3d.fast_response,
+                        scale3d.period, scale3d.idle_min, scale3d.idle_max);
+        scale3d.fast_up_count = 0;
+        scale3d.slow_down_count = 0;
+        scale3d.fast_responses = 0;
+        scale3d.last_down = time;
+        scale3d.last_tweak = time;
+}
+#undef SCALING_ADJUST_PERIOD
+#undef HINT_RATIO_MAX
+#undef HINT_RATIO_MIN
+#undef HINT_RATIO_MID
+#undef HINT_RATIO_DIFF
+static void scaling_state_check(ktime_t time)
+{
+        unsigned long dt;
+        /* adjustment: set scale parameters (fast_response, period) +/- 25%
+         * based on ratio of scale up to scale down hints
+         */
+        if (scale3d.p_adjust)
+                scaling_adjust(time);
+        else {
+                scale3d.fast_response = scale3d.p_fast_response;
+                scale3d.period = scale3d.p_period;
+                scale3d.idle_min = scale3d.p_idle_min;
+                scale3d.idle_max = scale3d.p_idle_max;
+        }
+        /* check for load peaks */
+        dt = (unsigned long) ktime_us_delta(time, scale3d.fast_frame);
+        if (dt > scale3d.fast_response) {
+                unsigned long idleness =
+                        (scale3d.idle_short_term_total * 100) / dt;
+                scale3d.fast_responses++;
+                scale3d.fast_frame = time;
+                /* if too busy, scale up */
+                if (idleness < scale3d.idle_min) {
+                        scale3d.is_scaled = 0;
+                        scale3d.fast_up_count++;
+                        if (scale3d.p_verbosity >= 5)
+                                pr_info("scale3d: %ld%% busy\n",
+                                        100 - idleness);
+                        reset_3d_clocks();
+                        reset_scaling_counters(time);
+                        return;
+                }
+                scale3d.idle_short_term_total = 0;
+                scale3d.last_short_term_idle = time;
+        }
+        dt = (unsigned long) ktime_us_delta(time, scale3d.idle_frame);
+        if (dt > scale3d.period) {
+                unsigned long idleness = (scale3d.idle_total * 100) / dt;
+                if (scale3d.p_verbosity >= 5)
+                        pr_info("scale3d: idle %lu, ~%lu%%\n",
+                                scale3d.idle_total, idleness);
+                if (idleness > scale3d.idle_max) {
+                        if (!scale3d.is_scaled) {
+                                scale3d.is_scaled = 1;
+                                scale3d.last_down = time;
+                        }
+                        scale3d.slow_down_count++;
+                        /* if idle time is high, clock down */
+                        scale3d.scale = 100 - (idleness - scale3d.idle_min);
+                        schedule_work(&scale3d.work);
+                }
+                reset_scaling_counters(time);
+        }
+}
+void nvhost_scale3d_notify_idle(struct nvhost_device *dev)
+{
+        ktime_t t;
+        unsigned long dt;
+        if (!scale3d.enable)
+                return;
+        mutex_lock(&scale3d.lock);
+        t = ktime_get();
+        if (scale3d.is_idle) {
+                dt = ktime_us_delta(t, scale3d.last_idle);
+                scale3d.idle_total += dt;
+                dt = ktime_us_delta(t, scale3d.last_short_term_idle);
+                scale3d.idle_short_term_total += dt;
+        } else
+                scale3d.is_idle = 1;
+        scale3d.last_idle = t;
+        scale3d.last_short_term_idle = t;
+        scaling_state_check(scale3d.last_idle);
+        /* delay idle_max % of 2 * fast_response time (given in microseconds) */
+        schedule_delayed_work(&scale3d.idle_timer,
+                msecs_to_jiffies((scale3d.idle_max * scale3d.fast_response)
+                        / 50000));
+        mutex_unlock(&scale3d.lock);
+}
+void nvhost_scale3d_notify_busy(struct nvhost_device *dev)
+{
+        unsigned long idle;
+        unsigned long short_term_idle;
+        ktime_t t;
+        if (!scale3d.enable)
+                return;
+        mutex_lock(&scale3d.lock);
+        cancel_delayed_work(&scale3d.idle_timer);
+        t = ktime_get();
+        if (scale3d.is_idle) {
+                idle = (unsigned long)
+                        ktime_us_delta(t, scale3d.last_idle);
+                scale3d.idle_total += idle;
+                short_term_idle =
+                        ktime_us_delta(t, scale3d.last_short_term_idle);
+                scale3d.idle_short_term_total += short_term_idle;
+                scale3d.is_idle = 0;
+        }
+        scaling_state_check(t);
+        mutex_unlock(&scale3d.lock);
+}
+static void scale3d_idle_handler(struct work_struct *work)
+{
+        int notify_idle = 0;
+        if (!scale3d.enable)
+                return;
+        mutex_lock(&scale3d.lock);
+        if (scale3d.is_idle && tegra_is_clk_enabled(scale3d.clk_3d)) {
+                unsigned long curr = clk_get_rate(scale3d.clk_3d);
+                if (curr > scale3d.min_rate_3d)
+                        notify_idle = 1;
+        }
+        mutex_unlock(&scale3d.lock);
+        if (notify_idle)
+                nvhost_scale3d_notify_idle(NULL);
+}
+void nvhost_scale3d_reset()
+{
+        ktime_t t;
+        if (!scale3d.enable)
+                return;
+        t = ktime_get();
+        mutex_lock(&scale3d.lock);
+        reset_scaling_counters(t);
+        mutex_unlock(&scale3d.lock);
+}
+/*
+ * debugfs parameters to control 3d clock scaling
+ */
+void nvhost_scale3d_debug_init(struct dentry *de)
+{
+        struct dentry *d, *f;
+        d = debugfs_create_dir("scaling", de);
+        if (!d) {
+                pr_err("scale3d: can\'t create debugfs directory\n");
+                return;
+        }
+#define CREATE_SCALE3D_FILE(fname) \
+        do {\
+                f = debugfs_create_u32(#fname, S_IRUGO | S_IWUSR, d,\
+                        &scale3d.p_##fname);\
+                if (NULL == f) {\
+                        pr_err("scale3d: can\'t create file " #fname "\n");\
+                        return;\
+                } \
+        } while (0)
+        CREATE_SCALE3D_FILE(fast_response);
+        CREATE_SCALE3D_FILE(idle_min);
+        CREATE_SCALE3D_FILE(idle_max);
+        CREATE_SCALE3D_FILE(period);
+        CREATE_SCALE3D_FILE(adjust);
+        CREATE_SCALE3D_FILE(scale_emc);
+        CREATE_SCALE3D_FILE(emc_dip);
+        CREATE_SCALE3D_FILE(verbosity);
+#undef CREATE_SCALE3D_FILE
+}
+static ssize_t enable_3d_scaling_show(struct device *device,
+        struct device_attribute *attr, char *buf)
+{
+        ssize_t res;
+        res = snprintf(buf, PAGE_SIZE, "%d\n", scale3d_is_enabled());
+        return res;
+}
+static ssize_t enable_3d_scaling_store(struct device *dev,
+        struct device_attribute *attr, const char *buf, size_t count)
+{
+        unsigned long val = 0;
+        if (strict_strtoul(buf, 10, &val) < 0)
+                return -EINVAL;
+        scale3d_enable(val);
+        return count;
+}
+static DEVICE_ATTR(enable_3d_scaling, S_IRUGO | S_IWUSR,
+        enable_3d_scaling_show, enable_3d_scaling_store);
+void nvhost_scale3d_init(struct nvhost_device *d)
+{
+        if (!scale3d.init) {
+                int error;
+                unsigned long max_emc, min_emc;
+                long correction;
+                mutex_init(&scale3d.lock);
+                scale3d.clk_3d = d->clk[0];
+                if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) {
+                        scale3d.clk_3d2 = d->clk[1];
+                        scale3d.clk_3d_emc = d->clk[2];
+                } else
+                        scale3d.clk_3d_emc = d->clk[1];
+                scale3d.max_rate_3d = clk_round_rate(scale3d.clk_3d, UINT_MAX);
+                scale3d.min_rate_3d = clk_round_rate(scale3d.clk_3d, 0);
+                if (scale3d.max_rate_3d == scale3d.min_rate_3d) {
+                        pr_warn("scale3d: 3d max rate = min rate (%lu), "
+                                "disabling\n", scale3d.max_rate_3d);
+                        scale3d.enable = 0;
+                        return;
+                }
+                /* emc scaling:
+                 *
+                 * Remc = S * R3d + O - (Sd * (R3d - Rm)^2 + Od)
+                 *
+                 * Remc - 3d.emc rate
+                 * R3d  - 3d.cbus rate
+                 * Rm   - 3d.cbus 'middle' rate = (max + min)/2
+                 * S    - emc_slope
+                 * O    - emc_offset
+                 * Sd   - emc_dip_slope
+                 * Od   - emc_dip_offset
+                 *
+                 * this superposes a quadratic dip centered around the middle 3d
+                 * frequency over a linear correlation of 3d.emc to 3d clock
+                 * rates.
+                 *
+                 * S, O are chosen so that the maximum 3d rate produces the
+                 * maximum 3d.emc rate exactly, and the minimum 3d rate produces
+                 * at least the minimum 3d.emc rate.
+                 *
+                 * Sd and Od are chosen to produce the largest dip that will
+                 * keep 3d.emc frequencies monotonously decreasing with 3d
+                 * frequencies. To achieve this, the first derivative of Remc
+                 * with respect to R3d should be zero for the minimal 3d rate:
+                 *
+                 *   R'emc = S - 2 * Sd * (R3d - Rm)
+                 *   R'emc(R3d-min) = 0
+                 *   S = 2 * Sd * (R3d-min - Rm)
+                 *     = 2 * Sd * (R3d-min - R3d-max) / 2
+                 *   Sd = S / (R3d-min - R3d-max)
+                 *
+                 *   +---------------------------------------------------+
+                 *   | Sd = -(emc-max - emc-min) / (R3d-min - R3d-max)^2 |
+                 *   +---------------------------------------------------+
+                 *
+                 *   dip = Sd * (R3d - Rm)^2 + Od
+                 *
+                 * requiring dip(R3d-min) = 0 and dip(R3d-max) = 0 gives
+                 *
+                 *   Sd * (R3d-min - Rm)^2 + Od = 0
+                 *   Od = -Sd * ((R3d-min - R3d-max) / 2)^2
+                 *      = -Sd * ((R3d-min - R3d-max)^2) / 4
+                 *
+                 *   +------------------------------+
+                 *   | Od = (emc-max - emc-min) / 4 |
+                 *   +------------------------------+
+                 */
+                max_emc = clk_round_rate(scale3d.clk_3d_emc, UINT_MAX);
+                min_emc = clk_round_rate(scale3d.clk_3d_emc, 0);
+                scale3d.emc_slope = (max_emc - min_emc) /
+                         (scale3d.max_rate_3d - scale3d.min_rate_3d);
+                scale3d.emc_offset = max_emc -
+                        scale3d.emc_slope * scale3d.max_rate_3d;
+                /* guarantee max 3d rate maps to max emc rate */
+                scale3d.emc_offset += max_emc -
+                        (scale3d.emc_slope * scale3d.max_rate_3d +
+                        scale3d.emc_offset);
+                scale3d.emc_dip_offset = (max_emc - min_emc) / 4;
+                scale3d.emc_dip_slope =
+                        -4 * (scale3d.emc_dip_offset /
+                        (POW2(scale3d.max_rate_3d - scale3d.min_rate_3d)));
+                scale3d.emc_xmid =
+                        (scale3d.max_rate_3d + scale3d.min_rate_3d) / 2;
+                correction =
+                        scale3d.emc_dip_offset +
+                                scale3d.emc_dip_slope *
+                                POW2(scale3d.max_rate_3d - scale3d.emc_xmid);
+                scale3d.emc_dip_offset -= correction;
+                INIT_WORK(&scale3d.work, scale3d_clocks_handler);
+                INIT_DELAYED_WORK(&scale3d.idle_timer, scale3d_idle_handler);
+                /* set scaling parameter defaults */
+                scale3d.enable = 1;
+                scale3d.period = scale3d.p_period = 100000;
+                scale3d.idle_min = scale3d.p_idle_min = 10;
+                scale3d.idle_max = scale3d.p_idle_max = 15;
+                scale3d.fast_response = scale3d.p_fast_response = 7000;
+                scale3d.p_scale_emc = 1;
+                scale3d.p_emc_dip = 1;
+                scale3d.p_verbosity = 0;
+                scale3d.p_adjust = 1;
+                error = device_create_file(&d->dev,
+                                &dev_attr_enable_3d_scaling);
+                if (error)
+                        dev_err(&d->dev, "failed to create sysfs attributes");
+                scale3d.init = 1;
+        }
+        nvhost_scale3d_reset();
+}
+void nvhost_scale3d_deinit(struct nvhost_device *dev)
+{
+        device_remove_file(&dev->dev, &dev_attr_enable_3d_scaling);
+        scale3d.init = 0;
+}
diff --git a/drivers/video/tegra/host/gr3d/scale3d.h b/drivers/video/tegra/host/gr3d/scale3d.h
new file mode 100644
index 00000000000..f8aae1d591a
--- /dev/null
+++ b/drivers/video/tegra/host/gr3d/scale3d.h
@@ -0,0 +1,47 @@
+/*
+ * drivers/video/tegra/host/t30/scale3d.h
+ *
+ * Tegra Graphics Host 3D Clock Scaling
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef NVHOST_T30_SCALE3D_H
+#define NVHOST_T30_SCALE3D_H
+struct nvhost_device;
+struct device;
+struct dentry;
+/* Initialization and de-initialization for module */
+void nvhost_scale3d_init(struct nvhost_device *);
+void nvhost_scale3d_deinit(struct nvhost_device *);
+/* Suspend is called when powering down module */
+void nvhost_scale3d_suspend(struct nvhost_device *);
+/* reset 3d module load counters, called on resume */
+void nvhost_scale3d_reset(void);
+/*
+ * call when performing submit to notify scaling mechanism that 3d module is
+ * in use
+ */
+void nvhost_scale3d_notify_busy(struct nvhost_device *);
+void nvhost_scale3d_notify_idle(struct nvhost_device *);
+void nvhost_scale3d_debug_init(struct dentry *de);
+#endif
diff --git a/drivers/video/tegra/host/host1x/Makefile b/drivers/video/tegra/host/host1x/Makefile
new file mode 100644
index 00000000000..c3214ffe147
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/Makefile
@@ -0,0 +1,12 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-host1x-objs  = \
+        host1x_syncpt.o \
+        host1x_channel.o \
+        host1x_intr.o \
+        host1x_cdma.o \
+        host1x_debug.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-host1x.o
diff --git a/drivers/video/tegra/host/host1x/host1x_cdma.c b/drivers/video/tegra/host/host1x/host1x_cdma.c
new file mode 100644
index 00000000000..cdd6026718b
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_cdma.c
@@ -0,0 +1,665 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_cdma.c
+ *
+ * Tegra Graphics Host Command DMA
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/slab.h>
+#include "nvhost_cdma.h"
+#include "dev.h"
+#include "host1x_hardware.h"
+#include "host1x_syncpt.h"
+#include "host1x_cdma.h"
+#include "host1x_hwctx.h"
+static inline u32 host1x_channel_dmactrl(int stop, int get_rst, int init_get)
+{
+        return HOST1X_CREATE(CHANNEL_DMACTRL, DMASTOP, stop)
+                        | HOST1X_CREATE(CHANNEL_DMACTRL, DMAGETRST, get_rst)
+                        | HOST1X_CREATE(CHANNEL_DMACTRL, DMAINITGET, init_get);
+}
+static void cdma_timeout_handler(struct work_struct *work);
+/*
+ * push_buffer
+ *
+ * The push buffer is a circular array of words to be fetched by command DMA.
+ * Note that it works slightly differently to the sync queue; fence == cur
+ * means that the push buffer is full, not empty.
+ */
+/**
+ * Reset to empty push buffer
+ */
+static void push_buffer_reset(struct push_buffer *pb)
+{
+        pb->fence = PUSH_BUFFER_SIZE - 8;
+        pb->cur = 0;
+}
+/**
+ * Init push buffer resources
+ */
+static int push_buffer_init(struct push_buffer *pb)
+{
+        struct nvhost_cdma *cdma = pb_to_cdma(pb);
+        struct nvmap_client *nvmap = cdma_to_nvmap(cdma);
+        pb->mem = NULL;
+        pb->mapped = NULL;
+        pb->phys = 0;
+        pb->nvmap = NULL;
+        BUG_ON(!cdma_pb_op(cdma).reset);
+        cdma_pb_op(cdma).reset(pb);
+        /* allocate and map pushbuffer memory */
+        pb->mem = nvmap_alloc(nvmap, PUSH_BUFFER_SIZE + 4, 32,
+                              NVMAP_HANDLE_WRITE_COMBINE, 0);
+        if (IS_ERR_OR_NULL(pb->mem)) {
+                pb->mem = NULL;
+                goto fail;
+        }
+        pb->mapped = nvmap_mmap(pb->mem);
+        if (pb->mapped == NULL)
+                goto fail;
+        /* pin pushbuffer and get physical address */
+        pb->phys = nvmap_pin(nvmap, pb->mem);
+        if (pb->phys >= 0xfffff000) {
+                pb->phys = 0;
+                goto fail;
+        }
+        /* memory for storing nvmap client and handles for each opcode pair */
+        pb->nvmap = kzalloc(NVHOST_GATHER_QUEUE_SIZE *
+                                sizeof(struct nvmap_client_handle),
+                        GFP_KERNEL);
+        if (!pb->nvmap)
+                goto fail;
+        /* put the restart at the end of pushbuffer memory */
+        *(pb->mapped + (PUSH_BUFFER_SIZE >> 2)) =
+                nvhost_opcode_restart(pb->phys);
+        return 0;
+fail:
+        cdma_pb_op(cdma).destroy(pb);
+        return -ENOMEM;
+}
+/**
+ * Clean up push buffer resources
+ */
+static void push_buffer_destroy(struct push_buffer *pb)
+{
+        struct nvhost_cdma *cdma = pb_to_cdma(pb);
+        struct nvmap_client *nvmap = cdma_to_nvmap(cdma);
+        if (pb->mapped)
+                nvmap_munmap(pb->mem, pb->mapped);
+        if (pb->phys != 0)
+                nvmap_unpin(nvmap, pb->mem);
+        if (pb->mem)
+                nvmap_free(nvmap, pb->mem);
+        kfree(pb->nvmap);
+        pb->mem = NULL;
+        pb->mapped = NULL;
+        pb->phys = 0;
+        pb->nvmap = 0;
+}
+/**
+ * Push two words to the push buffer
+ * Caller must ensure push buffer is not full
+ */
+static void push_buffer_push_to(struct push_buffer *pb,
+                struct nvmap_client *client,
+                struct nvmap_handle *handle, u32 op1, u32 op2)
+{
+        u32 cur = pb->cur;
+        u32 *p = (u32 *)((u32)pb->mapped + cur);
+        u32 cur_nvmap = (cur/8) & (NVHOST_GATHER_QUEUE_SIZE - 1);
+        BUG_ON(cur == pb->fence);
+        *(p++) = op1;
+        *(p++) = op2;
+        pb->nvmap[cur_nvmap].client = client;
+        pb->nvmap[cur_nvmap].handle = handle;
+        pb->cur = (cur + 8) & (PUSH_BUFFER_SIZE - 1);
+}
+/**
+ * Pop a number of two word slots from the push buffer
+ * Caller must ensure push buffer is not empty
+ */
+static void push_buffer_pop_from(struct push_buffer *pb,
+                unsigned int slots)
+{
+        /* Clear the nvmap references for old items from pb */
+        unsigned int i;
+        u32 fence_nvmap = pb->fence/8;
+        for (i = 0; i < slots; i++) {
+                int cur_fence_nvmap = (fence_nvmap+i)
+                                & (NVHOST_GATHER_QUEUE_SIZE - 1);
+                struct nvmap_client_handle *h =
+                                &pb->nvmap[cur_fence_nvmap];
+                h->client = NULL;
+                h->handle = NULL;
+        }
+        /* Advance the next write position */
+        pb->fence = (pb->fence + slots * 8) & (PUSH_BUFFER_SIZE - 1);
+}
+/**
+ * Return the number of two word slots free in the push buffer
+ */
+static u32 push_buffer_space(struct push_buffer *pb)
+{
+        return ((pb->fence - pb->cur) & (PUSH_BUFFER_SIZE - 1)) / 8;
+}
+static u32 push_buffer_putptr(struct push_buffer *pb)
+{
+        return pb->phys + pb->cur;
+}
+/*
+ * The syncpt incr buffer is filled with methods to increment syncpts, which
+ * is later GATHER-ed into the mainline PB. It's used when a timed out context
+ * is interleaved with other work, so needs to inline the syncpt increments
+ * to maintain the count (but otherwise does no work).
+ */
+/**
+ * Init timeout and syncpt incr buffer resources
+ */
+static int cdma_timeout_init(struct nvhost_cdma *cdma,
+                                 u32 syncpt_id)
+{
+        struct nvhost_master *dev = cdma_to_dev(cdma);
+        struct nvmap_client *nvmap = cdma_to_nvmap(cdma);
+        struct syncpt_buffer *sb = &cdma->syncpt_buffer;
+        struct nvhost_channel *ch = cdma_to_channel(cdma);
+        u32 i = 0;
+        if (syncpt_id == NVSYNCPT_INVALID)
+                return -EINVAL;
+        /* allocate and map syncpt incr memory */
+        sb->mem = nvmap_alloc(nvmap,
+                        (SYNCPT_INCR_BUFFER_SIZE_WORDS * sizeof(u32)), 32,
+                        NVMAP_HANDLE_WRITE_COMBINE, 0);
+        if (IS_ERR_OR_NULL(sb->mem)) {
+                sb->mem = NULL;
+                goto fail;
+        }
+        sb->mapped = nvmap_mmap(sb->mem);
+        if (sb->mapped == NULL)
+                goto fail;
+        /* pin syncpt buffer and get physical address */
+        sb->phys = nvmap_pin(nvmap, sb->mem);
+        if (sb->phys >= 0xfffff000) {
+                sb->phys = 0;
+                goto fail;
+        }
+        dev_dbg(&dev->dev->dev, "%s: SYNCPT_INCR buffer at 0x%x\n",
+                 __func__, sb->phys);
+        sb->words_per_incr = (syncpt_id == NVSYNCPT_3D) ? 5 : 3;
+        sb->incr_per_buffer = (SYNCPT_INCR_BUFFER_SIZE_WORDS /
+                                sb->words_per_incr);
+        /* init buffer with SETCL and INCR_SYNCPT methods */
+        while (i < sb->incr_per_buffer) {
+                sb->mapped[i++] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                                0, 0);
+                sb->mapped[i++] = nvhost_opcode_imm_incr_syncpt(
+                                                NV_SYNCPT_IMMEDIATE,
+                                                syncpt_id);
+                if (syncpt_id == NVSYNCPT_3D) {
+                        /* also contains base increments */
+                        sb->mapped[i++] = nvhost_opcode_nonincr(
+                                                NV_CLASS_HOST_INCR_SYNCPT_BASE,
+                                                1);
+                        sb->mapped[i++] = nvhost_class_host_incr_syncpt_base(
+                                                NVWAITBASE_3D, 1);
+                }
+                sb->mapped[i++] = nvhost_opcode_setclass(ch->dev->class,
+                                                0, 0);
+        }
+        wmb();
+        INIT_DELAYED_WORK(&cdma->timeout.wq, cdma_timeout_handler);
+        cdma->timeout.initialized = true;
+        return 0;
+fail:
+        cdma_op(cdma).timeout_destroy(cdma);
+        return -ENOMEM;
+}
+/**
+ * Clean up timeout syncpt buffer resources
+ */
+static void cdma_timeout_destroy(struct nvhost_cdma *cdma)
+{
+        struct nvmap_client *nvmap = cdma_to_nvmap(cdma);
+        struct syncpt_buffer *sb = &cdma->syncpt_buffer;
+        if (sb->mapped)
+                nvmap_munmap(sb->mem, sb->mapped);
+        if (sb->phys != 0)
+                nvmap_unpin(nvmap, sb->mem);
+        if (sb->mem)
+                nvmap_free(nvmap, sb->mem);
+        sb->mem = NULL;
+        sb->mapped = NULL;
+        sb->phys = 0;
+        if (cdma->timeout.initialized)
+                cancel_delayed_work(&cdma->timeout.wq);
+        cdma->timeout.initialized = false;
+}
+/**
+ * Increment timedout buffer's syncpt via CPU.
+ */
+static void cdma_timeout_cpu_incr(struct nvhost_cdma *cdma, u32 getptr,
+                                u32 syncpt_incrs, u32 syncval, u32 nr_slots)
+{
+        struct nvhost_master *dev = cdma_to_dev(cdma);
+        struct push_buffer *pb = &cdma->push_buffer;
+        u32 i, getidx;
+        for (i = 0; i < syncpt_incrs; i++)
+                nvhost_syncpt_cpu_incr(&dev->syncpt, cdma->timeout.syncpt_id);
+        /* after CPU incr, ensure shadow is up to date */
+        nvhost_syncpt_update_min(&dev->syncpt, cdma->timeout.syncpt_id);
+        /* update WAITBASE_3D by same number of incrs */
+        if (cdma->timeout.syncpt_id == NVSYNCPT_3D) {
+                void __iomem *p;
+                p = dev->sync_aperture + HOST1X_SYNC_SYNCPT_BASE_0 +
+                                (NVWAITBASE_3D * sizeof(u32));
+                writel(syncval, p);
+        }
+        /* NOP all the PB slots */
+        getidx = getptr - pb->phys;
+        while (nr_slots--) {
+                u32 *p = (u32 *)((u32)pb->mapped + getidx);
+                *(p++) = NVHOST_OPCODE_NOOP;
+                *(p++) = NVHOST_OPCODE_NOOP;
+                dev_dbg(&dev->dev->dev, "%s: NOP at 0x%x\n",
+                        __func__, pb->phys + getidx);
+                getidx = (getidx + 8) & (PUSH_BUFFER_SIZE - 1);
+        }
+        wmb();
+}
+/**
+ * This routine is called at the point we transition back into a timed
+ * ctx. The syncpts are incremented via pushbuffer with a flag indicating
+ * whether there's a CTXSAVE that should be still executed (for the
+ * preceding HW ctx).
+ */
+static void cdma_timeout_pb_incr(struct nvhost_cdma *cdma, u32 getptr,
+                                u32 syncpt_incrs, u32 nr_slots,
+                                bool exec_ctxsave)
+{
+        struct nvhost_master *dev = cdma_to_dev(cdma);
+        struct syncpt_buffer *sb = &cdma->syncpt_buffer;
+        struct push_buffer *pb = &cdma->push_buffer;
+        struct host1x_hwctx *hwctx = to_host1x_hwctx(cdma->timeout.ctx);
+        u32 getidx, *p;
+        /* should have enough slots to incr to desired count */
+        BUG_ON(syncpt_incrs > (nr_slots * sb->incr_per_buffer));
+        getidx = getptr - pb->phys;
+        if (exec_ctxsave) {
+                /* don't disrupt the CTXSAVE of a good/non-timed out ctx */
+                nr_slots -= hwctx->save_slots;
+                syncpt_incrs -= hwctx->save_incrs;
+                getidx += (hwctx->save_slots * 8);
+                getidx &= (PUSH_BUFFER_SIZE - 1);
+                dev_dbg(&dev->dev->dev,
+                        "%s: exec CTXSAVE of prev ctx (slots %d, incrs %d)\n",
+                        __func__, nr_slots, syncpt_incrs);
+        }
+        while (syncpt_incrs) {
+                u32 incrs, count;
+                /* GATHER count are incrs * number of DWORDs per incr */
+                incrs = min(syncpt_incrs, sb->incr_per_buffer);
+                count = incrs * sb->words_per_incr;
+                p = (u32 *)((u32)pb->mapped + getidx);
+                *(p++) = nvhost_opcode_gather(count);
+                *(p++) = sb->phys;
+                dev_dbg(&dev->dev->dev,
+                        "%s: GATHER at 0x%x, from 0x%x, dcount = %d\n",
+                        __func__,
+                        pb->phys + getidx, sb->phys,
+                        (incrs * sb->words_per_incr));
+                syncpt_incrs -= incrs;
+                getidx = (getidx + 8) & (PUSH_BUFFER_SIZE - 1);
+                nr_slots--;
+        }
+        /* NOP remaining slots */
+        while (nr_slots--) {
+                p = (u32 *)((u32)pb->mapped + getidx);
+                *(p++) = NVHOST_OPCODE_NOOP;
+                *(p++) = NVHOST_OPCODE_NOOP;
+                dev_dbg(&dev->dev->dev, "%s: NOP at 0x%x\n",
+                        __func__, pb->phys + getidx);
+                getidx = (getidx + 8) & (PUSH_BUFFER_SIZE - 1);
+        }
+        wmb();
+}
+/**
+ * Start channel DMA
+ */
+static void cdma_start(struct nvhost_cdma *cdma)
+{
+        void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
+        if (cdma->running)
+                return;
+        BUG_ON(!cdma_pb_op(cdma).putptr);
+        cdma->last_put = cdma_pb_op(cdma).putptr(&cdma->push_buffer);
+        writel(host1x_channel_dmactrl(true, false, false),
+                chan_regs + HOST1X_CHANNEL_DMACTRL);
+        /* set base, put, end pointer (all of memory) */
+        writel(0, chan_regs + HOST1X_CHANNEL_DMASTART);
+        writel(cdma->last_put, chan_regs + HOST1X_CHANNEL_DMAPUT);
+        writel(0xFFFFFFFF, chan_regs + HOST1X_CHANNEL_DMAEND);
+        /* reset GET */
+        writel(host1x_channel_dmactrl(true, true, true),
+                chan_regs + HOST1X_CHANNEL_DMACTRL);
+        /* start the command DMA */
+        writel(host1x_channel_dmactrl(false, false, false),
+                chan_regs + HOST1X_CHANNEL_DMACTRL);
+        cdma->running = true;
+}
+/**
+ * Similar to cdma_start(), but rather than starting from an idle
+ * state (where DMA GET is set to DMA PUT), on a timeout we restore
+ * DMA GET from an explicit value (so DMA may again be pending).
+ */
+static void cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
+{
+        struct nvhost_master *dev = cdma_to_dev(cdma);
+        void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
+        if (cdma->running)
+                return;
+        BUG_ON(!cdma_pb_op(cdma).putptr);
+        cdma->last_put = cdma_pb_op(cdma).putptr(&cdma->push_buffer);
+        writel(host1x_channel_dmactrl(true, false, false),
+                chan_regs + HOST1X_CHANNEL_DMACTRL);
+        /* set base, end pointer (all of memory) */
+        writel(0, chan_regs + HOST1X_CHANNEL_DMASTART);
+        writel(0xFFFFFFFF, chan_regs + HOST1X_CHANNEL_DMAEND);
+        /* set GET, by loading the value in PUT (then reset GET) */
+        writel(getptr, chan_regs + HOST1X_CHANNEL_DMAPUT);
+        writel(host1x_channel_dmactrl(true, true, true),
+                chan_regs + HOST1X_CHANNEL_DMACTRL);
+        dev_dbg(&dev->dev->dev,
+                "%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\n",
+                __func__,
+                readl(chan_regs + HOST1X_CHANNEL_DMAGET),
+                readl(chan_regs + HOST1X_CHANNEL_DMAPUT),
+                cdma->last_put);
+        /* deassert GET reset and set PUT */
+        writel(host1x_channel_dmactrl(true, false, false),
+                chan_regs + HOST1X_CHANNEL_DMACTRL);
+        writel(cdma->last_put, chan_regs + HOST1X_CHANNEL_DMAPUT);
+        /* start the command DMA */
+        writel(host1x_channel_dmactrl(false, false, false),
+                chan_regs + HOST1X_CHANNEL_DMACTRL);
+        cdma->running = true;
+}
+/**
+ * Kick channel DMA into action by writing its PUT offset (if it has changed)
+ */
+static void cdma_kick(struct nvhost_cdma *cdma)
+{
+        u32 put;
+        BUG_ON(!cdma_pb_op(cdma).putptr);
+        put = cdma_pb_op(cdma).putptr(&cdma->push_buffer);
+        if (put != cdma->last_put) {
+                void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
+                wmb();
+                writel(put, chan_regs + HOST1X_CHANNEL_DMAPUT);
+                cdma->last_put = put;
+        }
+}
+static void cdma_stop(struct nvhost_cdma *cdma)
+{
+        void __iomem *chan_regs = cdma_to_channel(cdma)->aperture;
+        mutex_lock(&cdma->lock);
+        if (cdma->running) {
+                nvhost_cdma_wait_locked(cdma, CDMA_EVENT_SYNC_QUEUE_EMPTY);
+                writel(host1x_channel_dmactrl(true, false, false),
+                        chan_regs + HOST1X_CHANNEL_DMACTRL);
+                cdma->running = false;
+        }
+        mutex_unlock(&cdma->lock);
+}
+/**
+ * Retrieve the op pair at a slot offset from a DMA address
+ */
+void cdma_peek(struct nvhost_cdma *cdma,
+                          u32 dmaget, int slot, u32 *out)
+{
+        u32 offset = dmaget - cdma->push_buffer.phys;
+        u32 *p = cdma->push_buffer.mapped;
+        offset = ((offset + slot * 8) & (PUSH_BUFFER_SIZE - 1)) >> 2;
+        out[0] = p[offset];
+        out[1] = p[offset + 1];
+}
+/**
+ * Stops both channel's command processor and CDMA immediately.
+ * Also, tears down the channel and resets corresponding module.
+ */
+void cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
+{
+        struct nvhost_master *dev = cdma_to_dev(cdma);
+        struct nvhost_channel *ch = cdma_to_channel(cdma);
+        u32 cmdproc_stop;
+        BUG_ON(cdma->torndown);
+        dev_dbg(&dev->dev->dev,
+                "begin channel teardown (channel id %d)\n", ch->chid);
+        cmdproc_stop = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+        cmdproc_stop |= BIT(ch->chid);
+        writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+        dev_dbg(&dev->dev->dev,
+                "%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\n",
+                __func__,
+                readl(ch->aperture + HOST1X_CHANNEL_DMAGET),
+                readl(ch->aperture + HOST1X_CHANNEL_DMAPUT),
+                cdma->last_put);
+        writel(host1x_channel_dmactrl(true, false, false),
+                ch->aperture + HOST1X_CHANNEL_DMACTRL);
+        writel(BIT(ch->chid), dev->sync_aperture + HOST1X_SYNC_CH_TEARDOWN);
+        nvhost_module_reset(ch->dev);
+        cdma->running = false;
+        cdma->torndown = true;
+}
+void cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr)
+{
+        struct nvhost_master *dev = cdma_to_dev(cdma);
+        struct nvhost_channel *ch = cdma_to_channel(cdma);
+        u32 cmdproc_stop;
+        BUG_ON(!cdma->torndown || cdma->running);
+        dev_dbg(&dev->dev->dev,
+                "end channel teardown (id %d, DMAGET restart = 0x%x)\n",
+                ch->chid, getptr);
+        cmdproc_stop = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+        cmdproc_stop &= ~(BIT(ch->chid));
+        writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+        cdma->torndown = false;
+        cdma_timeout_restart(cdma, getptr);
+}
+/**
+ * If this timeout fires, it indicates the current sync_queue entry has
+ * exceeded its TTL and the userctx should be timed out and remaining
+ * submits already issued cleaned up (future submits return an error).
+ */
+static void cdma_timeout_handler(struct work_struct *work)
+{
+        struct nvhost_cdma *cdma;
+        struct nvhost_master *dev;
+        struct nvhost_syncpt *sp;
+        struct nvhost_channel *ch;
+        u32 syncpt_val;
+        u32 prev_cmdproc, cmdproc_stop;
+        cdma = container_of(to_delayed_work(work), struct nvhost_cdma,
+                            timeout.wq);
+        dev = cdma_to_dev(cdma);
+        sp = &dev->syncpt;
+        ch = cdma_to_channel(cdma);
+        mutex_lock(&cdma->lock);
+        if (!cdma->timeout.clientid) {
+                dev_dbg(&dev->dev->dev,
+                         "cdma_timeout: expired, but has no clientid\n");
+                mutex_unlock(&cdma->lock);
+                return;
+        }
+        /* stop processing to get a clean snapshot */
+        prev_cmdproc = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+        cmdproc_stop = prev_cmdproc | BIT(ch->chid);
+        writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+        dev_dbg(&dev->dev->dev, "cdma_timeout: cmdproc was 0x%x is 0x%x\n",
+                prev_cmdproc, cmdproc_stop);
+        syncpt_val = nvhost_syncpt_update_min(&dev->syncpt,
+                        cdma->timeout.syncpt_id);
+        /* has buffer actually completed? */
+        if ((s32)(syncpt_val - cdma->timeout.syncpt_val) >= 0) {
+                dev_dbg(&dev->dev->dev,
+                         "cdma_timeout: expired, but buffer had completed\n");
+                /* restore */
+                cmdproc_stop = prev_cmdproc & ~(BIT(ch->chid));
+                writel(cmdproc_stop,
+                        dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
+                mutex_unlock(&cdma->lock);
+                return;
+        }
+        dev_warn(&dev->dev->dev,
+                "%s: timeout: %d (%s) ctx 0x%p, HW thresh %d, done %d\n",
+                __func__,
+                cdma->timeout.syncpt_id,
+                syncpt_op(sp).name(sp, cdma->timeout.syncpt_id),
+                cdma->timeout.ctx,
+                syncpt_val, cdma->timeout.syncpt_val);
+        /* stop HW, resetting channel/module */
+        cdma_op(cdma).timeout_teardown_begin(cdma);
+        nvhost_cdma_update_sync_queue(cdma, sp, &dev->dev->dev);
+        mutex_unlock(&cdma->lock);
+}
+int host1x_init_cdma_support(struct nvhost_master *host)
+{
+        host->op.cdma.start = cdma_start;
+        host->op.cdma.stop = cdma_stop;
+        host->op.cdma.kick = cdma_kick;
+        host->op.cdma.timeout_init = cdma_timeout_init;
+        host->op.cdma.timeout_destroy = cdma_timeout_destroy;
+        host->op.cdma.timeout_teardown_begin = cdma_timeout_teardown_begin;
+        host->op.cdma.timeout_teardown_end = cdma_timeout_teardown_end;
+        host->op.cdma.timeout_cpu_incr = cdma_timeout_cpu_incr;
+        host->op.cdma.timeout_pb_incr = cdma_timeout_pb_incr;
+        host->op.push_buffer.reset = push_buffer_reset;
+        host->op.push_buffer.init = push_buffer_init;
+        host->op.push_buffer.destroy = push_buffer_destroy;
+        host->op.push_buffer.push_to = push_buffer_push_to;
+        host->op.push_buffer.pop_from = push_buffer_pop_from;
+        host->op.push_buffer.space = push_buffer_space;
+        host->op.push_buffer.putptr = push_buffer_putptr;
+        return 0;
+}
diff --git a/drivers/video/tegra/host/host1x/host1x_cdma.h b/drivers/video/tegra/host/host1x/host1x_cdma.h
new file mode 100644
index 00000000000..60909236a7c
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_cdma.h
@@ -0,0 +1,41 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_cdma.h
+ *
+ * Tegra Graphics Host Channel
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_HOST1X_HOST1X_CDMA_H
+#define __NVHOST_HOST1X_HOST1X_CDMA_H
+/* Size of the sync queue. If it is too small, we won't be able to queue up
+ * many command buffers. If it is too large, we waste memory. */
+#define NVHOST_SYNC_QUEUE_SIZE 512
+/* Number of gathers we allow to be queued up per channel. Must be a
+ * power of two. Currently sized such that pushbuffer is 4KB (512*8B). */
+#define NVHOST_GATHER_QUEUE_SIZE 512
+/* 8 bytes per slot. (This number does not include the final RESTART.) */
+#define PUSH_BUFFER_SIZE (NVHOST_GATHER_QUEUE_SIZE * 8)
+/* 4K page containing GATHERed methods to increment channel syncpts
+ * and replaces the original timed out contexts GATHER slots */
+#define SYNCPT_INCR_BUFFER_SIZE_WORDS   (4096 / sizeof(u32))
+int host1x_init_cdma_support(struct nvhost_master *);
+#endif
diff --git a/drivers/video/tegra/host/host1x/host1x_channel.c b/drivers/video/tegra/host/host1x/host1x_channel.c
new file mode 100644
index 00000000000..b16a34f416a
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_channel.c
@@ -0,0 +1,627 @@
+/*
+ * drivers/video/tegra/host/host1x/channel_host1x.c
+ *
+ * Tegra Graphics Host Channel
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_channel.h"
+#include "dev.h"
+#include "nvhost_hwctx.h"
+#include <trace/events/nvhost.h>
+#include <linux/slab.h>
+#include "host1x_syncpt.h"
+#include "host1x_channel.h"
+#include "host1x_hardware.h"
+#include "host1x_hwctx.h"
+#include "nvhost_intr.h"
+#define NV_FIFO_READ_TIMEOUT 200000
+static void sync_waitbases(struct nvhost_channel *ch, u32 syncpt_val)
+{
+        unsigned long waitbase;
+        unsigned long int waitbase_mask = ch->dev->waitbases;
+        if (ch->dev->waitbasesync) {
+                waitbase = find_first_bit(&waitbase_mask, BITS_PER_LONG);
+                nvhost_cdma_push(&ch->cdma,
+                        nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                NV_CLASS_HOST_LOAD_SYNCPT_BASE,
+                                1),
+                                nvhost_class_host_load_syncpt_base(waitbase,
+                                                syncpt_val));
+        }
+}
+static void *pre_submit_ctxsave(struct nvhost_job *job,
+                struct nvhost_hwctx *cur_ctx)
+{
+        struct nvhost_channel *ch = job->ch;
+        void *ctxsave_waiter = NULL;
+        /* Is a save needed? */
+        if (!cur_ctx || ch->cur_ctx == job->hwctx)
+                return NULL;
+        if (cur_ctx->has_timedout) {
+                dev_dbg(&ch->dev->dev,
+                        "%s: skip save of timed out context (0x%p)\n",
+                        __func__, ch->cur_ctx);
+                return NULL;
+        }
+        /* Allocate save waiter if needed */
+        if (ch->ctxhandler->save_service) {
+                ctxsave_waiter = nvhost_intr_alloc_waiter();
+                if (!ctxsave_waiter)
+                        return ERR_PTR(-ENOMEM);
+        }
+        return ctxsave_waiter;
+}
+static void submit_ctxsave(struct nvhost_job *job, void *ctxsave_waiter,
+                struct nvhost_hwctx *cur_ctx)
+{
+        struct nvhost_master *host = nvhost_get_host(job->ch->dev);
+        struct nvhost_channel *ch = job->ch;
+        u32 syncval;
+        int err;
+        u32 save_thresh = 0;
+        /* Is a save needed? */
+        if (!cur_ctx || cur_ctx == job->hwctx || cur_ctx->has_timedout)
+                return;
+        /* Retrieve save threshold if we have a waiter */
+        if (ctxsave_waiter)
+                save_thresh =
+                        nvhost_syncpt_read_max(&host->syncpt, job->syncpt_id)
+                        + to_host1x_hwctx(cur_ctx)->save_thresh;
+        /* Adjust the syncpoint max */
+        job->syncpt_incrs += to_host1x_hwctx(cur_ctx)->save_incrs;
+        syncval = nvhost_syncpt_incr_max(&host->syncpt,
+                        job->syncpt_id,
+                        to_host1x_hwctx(cur_ctx)->save_incrs);
+        /* Send the save to channel */
+        cur_ctx->valid = true;
+        ch->ctxhandler->save_push(cur_ctx, &ch->cdma);
+        nvhost_job_get_hwctx(job, cur_ctx);
+        /* Notify save service */
+        if (ctxsave_waiter) {
+                err = nvhost_intr_add_action(&host->intr,
+                        job->syncpt_id,
+                        save_thresh,
+                        NVHOST_INTR_ACTION_CTXSAVE, cur_ctx,
+                        ctxsave_waiter,
+                        NULL);
+                ctxsave_waiter = NULL;
+                WARN(err, "Failed to set ctx save interrupt");
+        }
+        trace_nvhost_channel_context_save(ch->dev->name, cur_ctx);
+}
+static void submit_ctxrestore(struct nvhost_job *job)
+{
+        struct nvhost_master *host = nvhost_get_host(job->ch->dev);
+        struct nvhost_channel *ch = job->ch;
+        u32 syncval;
+        struct host1x_hwctx *ctx =
+                job->hwctx ? to_host1x_hwctx(job->hwctx) : NULL;
+        /* First check if we have a valid context to restore */
+        if(ch->cur_ctx == job->hwctx || !job->hwctx || !job->hwctx->valid)
+                return;
+        /* Increment syncpt max */
+        job->syncpt_incrs += ctx->restore_incrs;
+        syncval = nvhost_syncpt_incr_max(&host->syncpt,
+                        job->syncpt_id,
+                        ctx->restore_incrs);
+        /* Send restore buffer to channel */
+        nvhost_cdma_push_gather(&ch->cdma,
+                host->nvmap,
+                nvmap_ref_to_handle(ctx->restore),
+                nvhost_opcode_gather(ctx->restore_size),
+                ctx->restore_phys);
+        trace_nvhost_channel_context_restore(ch->dev->name, &ctx->hwctx);
+}
+void submit_nullkickoff(struct nvhost_job *job, int user_syncpt_incrs)
+{
+        struct nvhost_channel *ch = job->ch;
+        int incr;
+        u32 op_incr;
+        /* push increments that correspond to nulled out commands */
+        op_incr = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+                        job->syncpt_id);
+        for (incr = 0; incr < (user_syncpt_incrs >> 1); incr++)
+                nvhost_cdma_push(&ch->cdma, op_incr, op_incr);
+        if (user_syncpt_incrs & 1)
+                nvhost_cdma_push(&ch->cdma, op_incr, NVHOST_OPCODE_NOOP);
+        /* for 3d, waitbase needs to be incremented after each submit */
+        if (ch->dev->class == NV_GRAPHICS_3D_CLASS_ID) {
+                u32 waitbase = to_host1x_hwctx_handler(job->hwctx->h)->waitbase;
+                nvhost_cdma_push(&ch->cdma,
+                        nvhost_opcode_setclass(
+                                NV_HOST1X_CLASS_ID,
+                                NV_CLASS_HOST_INCR_SYNCPT_BASE,
+                                1),
+                        nvhost_class_host_incr_syncpt_base(
+                                waitbase,
+                                user_syncpt_incrs));
+        }
+}
+void submit_gathers(struct nvhost_job *job)
+{
+        /* push user gathers */
+        int i = 0;
+        for ( ; i < job->num_gathers; i++) {
+                u32 op1 = nvhost_opcode_gather(job->gathers[i].words);
+                u32 op2 = job->gathers[i].mem;
+                nvhost_cdma_push_gather(&job->ch->cdma,
+                                job->nvmap, job->unpins[i/2],
+                                op1, op2);
+        }
+}
+int host1x_channel_submit(struct nvhost_job *job)
+{
+        struct nvhost_channel *ch = job->ch;
+        struct nvhost_syncpt *sp = &nvhost_get_host(job->ch->dev)->syncpt;
+        u32 user_syncpt_incrs = job->syncpt_incrs;
+        u32 prev_max = 0;
+        u32 syncval;
+        int err;
+        void *completed_waiter = NULL, *ctxsave_waiter = NULL;
+        /* Bail out on timed out contexts */
+        if (job->hwctx && job->hwctx->has_timedout)
+                return -ETIMEDOUT;
+        /* Turn on the client module and host1x */
+        nvhost_module_busy(ch->dev);
+        if (ch->dev->busy)
+                ch->dev->busy(ch->dev);
+        /* before error checks, return current max */
+        prev_max = job->syncpt_end =
+                nvhost_syncpt_read_max(sp, job->syncpt_id);
+        /* get submit lock */
+        err = mutex_lock_interruptible(&ch->submitlock);
+        if (err) {
+                nvhost_module_idle(ch->dev);
+                goto error;
+        }
+        /* Do the needed allocations */
+        ctxsave_waiter = pre_submit_ctxsave(job, ch->cur_ctx);
+        if (IS_ERR(ctxsave_waiter)) {
+                err = PTR_ERR(ctxsave_waiter);
+                nvhost_module_idle(ch->dev);
+                mutex_unlock(&ch->submitlock);
+                goto error;
+        }
+        completed_waiter = nvhost_intr_alloc_waiter();
+        if (!completed_waiter) {
+                nvhost_module_idle(ch->dev);
+                mutex_unlock(&ch->submitlock);
+                err = -ENOMEM;
+                goto error;
+        }
+        /* remove stale waits */
+        if (job->num_waitchk) {
+                err = nvhost_syncpt_wait_check(sp,
+                                               job->nvmap,
+                                               job->waitchk_mask,
+                                               job->waitchk,
+                                               job->num_waitchk);
+                if (err) {
+                        dev_warn(&ch->dev->dev,
+                                 "nvhost_syncpt_wait_check failed: %d\n", err);
+                        mutex_unlock(&ch->submitlock);
+                        nvhost_module_idle(ch->dev);
+                        goto error;
+                }
+        }
+        /* begin a CDMA submit */
+        err = nvhost_cdma_begin(&ch->cdma, job);
+        if (err) {
+                mutex_unlock(&ch->submitlock);
+                nvhost_module_idle(ch->dev);
+                goto error;
+        }
+        submit_ctxsave(job, ctxsave_waiter, ch->cur_ctx);
+        submit_ctxrestore(job);
+        ch->cur_ctx = job->hwctx;
+        syncval = nvhost_syncpt_incr_max(sp,
+                        job->syncpt_id, user_syncpt_incrs);
+        job->syncpt_end = syncval;
+        /* add a setclass for modules that require it */
+        if (ch->dev->class)
+                nvhost_cdma_push(&ch->cdma,
+                        nvhost_opcode_setclass(ch->dev->class, 0, 0),
+                        NVHOST_OPCODE_NOOP);
+        if (job->null_kickoff)
+                submit_nullkickoff(job, user_syncpt_incrs);
+        else
+                submit_gathers(job);
+        sync_waitbases(ch, job->syncpt_end);
+        /* end CDMA submit & stash pinned hMems into sync queue */
+        nvhost_cdma_end(&ch->cdma, job);
+        trace_nvhost_channel_submitted(ch->dev->name,
+                        prev_max, syncval);
+        /* schedule a submit complete interrupt */
+        err = nvhost_intr_add_action(&nvhost_get_host(ch->dev)->intr,
+                        job->syncpt_id, syncval,
+                        NVHOST_INTR_ACTION_SUBMIT_COMPLETE, ch,
+                        completed_waiter,
+                        NULL);
+        completed_waiter = NULL;
+        WARN(err, "Failed to set submit complete interrupt");
+        mutex_unlock(&ch->submitlock);
+        return 0;
+error:
+        kfree(ctxsave_waiter);
+        kfree(completed_waiter);
+        return err;
+}
+int host1x_channel_read_3d_reg(
+        struct nvhost_channel *channel,
+        struct nvhost_hwctx *hwctx,
+        u32 offset,
+        u32 *value)
+{
+        struct host1x_hwctx *hwctx_to_save = NULL;
+        struct nvhost_hwctx_handler *h = hwctx->h;
+        struct host1x_hwctx_handler *p = to_host1x_hwctx_handler(h);
+        bool need_restore = false;
+        u32 syncpt_incrs = 4;
+        unsigned int pending = 0;
+        DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
+        void *ref;
+        void *ctx_waiter, *read_waiter, *completed_waiter;
+        struct nvhost_job *job;
+        u32 syncval;
+        int err;
+        if (hwctx && hwctx->has_timedout)
+                return -ETIMEDOUT;
+        ctx_waiter = nvhost_intr_alloc_waiter();
+        read_waiter = nvhost_intr_alloc_waiter();
+        completed_waiter = nvhost_intr_alloc_waiter();
+        if (!ctx_waiter || !read_waiter || !completed_waiter) {
+                err = -ENOMEM;
+                goto done;
+        }
+        job = nvhost_job_alloc(channel, hwctx,
+                        NULL,
+                        nvhost_get_host(channel->dev)->nvmap, 0, 0);
+        if (!job) {
+                err = -ENOMEM;
+                goto done;
+        }
+        /* keep module powered */
+        nvhost_module_busy(channel->dev);
+        /* get submit lock */
+        err = mutex_lock_interruptible(&channel->submitlock);
+        if (err) {
+                nvhost_module_idle(channel->dev);
+                return err;
+        }
+        /* context switch */
+        if (channel->cur_ctx != hwctx) {
+                hwctx_to_save = channel->cur_ctx ?
+                        to_host1x_hwctx(channel->cur_ctx) : NULL;
+                if (hwctx_to_save) {
+                        syncpt_incrs += hwctx_to_save->save_incrs;
+                        hwctx_to_save->hwctx.valid = true;
+                        channel->ctxhandler->get(&hwctx_to_save->hwctx);
+                }
+                channel->cur_ctx = hwctx;
+                if (channel->cur_ctx && channel->cur_ctx->valid) {
+                        need_restore = true;
+                        syncpt_incrs += to_host1x_hwctx(channel->cur_ctx)
+                                ->restore_incrs;
+                }
+        }
+        syncval = nvhost_syncpt_incr_max(&nvhost_get_host(channel->dev)->syncpt,
+                p->syncpt, syncpt_incrs);
+        job->syncpt_id = p->syncpt;
+        job->syncpt_incrs = syncpt_incrs;
+        job->syncpt_end = syncval;
+        /* begin a CDMA submit */
+        nvhost_cdma_begin(&channel->cdma, job);
+        /* push save buffer (pre-gather setup depends on unit) */
+        if (hwctx_to_save)
+                h->save_push(&hwctx_to_save->hwctx, &channel->cdma);
+        /* gather restore buffer */
+        if (need_restore)
+                nvhost_cdma_push(&channel->cdma,
+                        nvhost_opcode_gather(to_host1x_hwctx(channel->cur_ctx)
+                                ->restore_size),
+                        to_host1x_hwctx(channel->cur_ctx)->restore_phys);
+        /* Switch to 3D - wait for it to complete what it was doing */
+        nvhost_cdma_push(&channel->cdma,
+                nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
+                nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+                        p->syncpt));
+        nvhost_cdma_push(&channel->cdma,
+                nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                        NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
+                nvhost_class_host_wait_syncpt_base(p->syncpt,
+                        p->waitbase, 1));
+        /*  Tell 3D to send register value to FIFO */
+        nvhost_cdma_push(&channel->cdma,
+                nvhost_opcode_nonincr(NV_CLASS_HOST_INDOFF, 1),
+                nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
+                        offset, false));
+        nvhost_cdma_push(&channel->cdma,
+                nvhost_opcode_imm(NV_CLASS_HOST_INDDATA, 0),
+                NVHOST_OPCODE_NOOP);
+        /*  Increment syncpt to indicate that FIFO can be read */
+        nvhost_cdma_push(&channel->cdma,
+                nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+                        p->syncpt),
+                NVHOST_OPCODE_NOOP);
+        /*  Wait for value to be read from FIFO */
+        nvhost_cdma_push(&channel->cdma,
+                nvhost_opcode_nonincr(NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
+                nvhost_class_host_wait_syncpt_base(p->syncpt,
+                        p->waitbase, 3));
+        /*  Indicate submit complete */
+        nvhost_cdma_push(&channel->cdma,
+                nvhost_opcode_nonincr(NV_CLASS_HOST_INCR_SYNCPT_BASE, 1),
+                nvhost_class_host_incr_syncpt_base(p->waitbase, 4));
+        nvhost_cdma_push(&channel->cdma,
+                NVHOST_OPCODE_NOOP,
+                nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+                        p->syncpt));
+        /* end CDMA submit  */
+        nvhost_cdma_end(&channel->cdma, job);
+        nvhost_job_put(job);
+        job = NULL;
+        /*
+         * schedule a context save interrupt (to drain the host FIFO
+         * if necessary, and to release the restore buffer)
+         */
+        if (hwctx_to_save) {
+                err = nvhost_intr_add_action(
+                        &nvhost_get_host(channel->dev)->intr,
+                        p->syncpt,
+                        syncval - syncpt_incrs
+                                + hwctx_to_save->save_incrs
+                                - 1,
+                        NVHOST_INTR_ACTION_CTXSAVE, hwctx_to_save,
+                        ctx_waiter,
+                        NULL);
+                ctx_waiter = NULL;
+                WARN(err, "Failed to set context save interrupt");
+        }
+        /* Wait for FIFO to be ready */
+        err = nvhost_intr_add_action(&nvhost_get_host(channel->dev)->intr,
+                        p->syncpt, syncval - 2,
+                        NVHOST_INTR_ACTION_WAKEUP, &wq,
+                        read_waiter,
+                        &ref);
+        read_waiter = NULL;
+        WARN(err, "Failed to set wakeup interrupt");
+        wait_event(wq,
+                nvhost_syncpt_is_expired(&nvhost_get_host(channel->dev)->syncpt,
+                                p->syncpt, syncval - 2));
+        nvhost_intr_put_ref(&nvhost_get_host(channel->dev)->intr, ref);
+        /* Read the register value from FIFO */
+        err = host1x_drain_read_fifo(channel->aperture,
+                value, 1, &pending);
+        /* Indicate we've read the value */
+        nvhost_syncpt_cpu_incr(&nvhost_get_host(channel->dev)->syncpt,
+                        p->syncpt);
+        /* Schedule a submit complete interrupt */
+        err = nvhost_intr_add_action(&nvhost_get_host(channel->dev)->intr,
+                        p->syncpt, syncval,
+                        NVHOST_INTR_ACTION_SUBMIT_COMPLETE, channel,
+                        completed_waiter, NULL);
+        completed_waiter = NULL;
+        WARN(err, "Failed to set submit complete interrupt");
+        mutex_unlock(&channel->submitlock);
+done:
+        kfree(ctx_waiter);
+        kfree(read_waiter);
+        kfree(completed_waiter);
+        return err;
+}
+int host1x_drain_read_fifo(void __iomem *chan_regs,
+        u32 *ptr, unsigned int count, unsigned int *pending)
+{
+        unsigned int entries = *pending;
+        unsigned long timeout = jiffies + NV_FIFO_READ_TIMEOUT;
+        while (count) {
+                unsigned int num;
+                while (!entries && time_before(jiffies, timeout)) {
+                        /* query host for number of entries in fifo */
+                        entries = HOST1X_VAL(CHANNEL_FIFOSTAT, OUTFENTRIES,
+                                readl(chan_regs + HOST1X_CHANNEL_FIFOSTAT));
+                        if (!entries)
+                                cpu_relax();
+                }
+                /*  timeout -> return error */
+                if (!entries)
+                        return -EIO;
+                num = min(entries, count);
+                entries -= num;
+                count -= num;
+                while (num & ~0x3) {
+                        u32 arr[4];
+                        arr[0] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
+                        arr[1] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
+                        arr[2] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
+                        arr[3] = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
+                        memcpy(ptr, arr, 4*sizeof(u32));
+                        ptr += 4;
+                        num -= 4;
+                }
+                while (num--)
+                        *ptr++ = readl(chan_regs + HOST1X_CHANNEL_INDDATA);
+        }
+        *pending = entries;
+        return 0;
+}
+int host1x_save_context(struct nvhost_device *dev, u32 syncpt_id)
+{
+        struct nvhost_channel *ch = dev->channel;
+        struct nvhost_hwctx *hwctx_to_save;
+        DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
+        u32 syncpt_incrs, syncpt_val;
+        int err = 0;
+        void *ref;
+        void *ctx_waiter = NULL, *wakeup_waiter = NULL;
+        struct nvhost_job *job;
+        ctx_waiter = nvhost_intr_alloc_waiter();
+        wakeup_waiter = nvhost_intr_alloc_waiter();
+        if (!ctx_waiter || !wakeup_waiter) {
+                err = -ENOMEM;
+                goto done;
+        }
+        if (dev->busy)
+                dev->busy(dev);
+        mutex_lock(&ch->submitlock);
+        hwctx_to_save = ch->cur_ctx;
+        if (!hwctx_to_save) {
+                mutex_unlock(&ch->submitlock);
+                goto done;
+        }
+        job = nvhost_job_alloc(ch, hwctx_to_save,
+                        NULL,
+                        nvhost_get_host(ch->dev)->nvmap, 0, 0);
+        if (IS_ERR_OR_NULL(job)) {
+                err = PTR_ERR(job);
+                mutex_unlock(&ch->submitlock);
+                goto done;
+        }
+        hwctx_to_save->valid = true;
+        ch->ctxhandler->get(hwctx_to_save);
+        ch->cur_ctx = NULL;
+        syncpt_incrs = to_host1x_hwctx(hwctx_to_save)->save_incrs;
+        syncpt_val = nvhost_syncpt_incr_max(&nvhost_get_host(ch->dev)->syncpt,
+                                        syncpt_id, syncpt_incrs);
+        job->syncpt_id = syncpt_id;
+        job->syncpt_incrs = syncpt_incrs;
+        job->syncpt_end = syncpt_val;
+        err = nvhost_cdma_begin(&ch->cdma, job);
+        if (err) {
+                mutex_unlock(&ch->submitlock);
+                goto done;
+        }
+        ch->ctxhandler->save_push(hwctx_to_save, &ch->cdma);
+        nvhost_cdma_end(&ch->cdma, job);
+        nvhost_job_put(job);
+        job = NULL;
+        err = nvhost_intr_add_action(&nvhost_get_host(ch->dev)->intr, syncpt_id,
+                        syncpt_val - syncpt_incrs +
+                                to_host1x_hwctx(hwctx_to_save)->save_thresh,
+                        NVHOST_INTR_ACTION_CTXSAVE, hwctx_to_save,
+                        ctx_waiter,
+                        NULL);
+        ctx_waiter = NULL;
+        WARN(err, "Failed to set context save interrupt");
+        err = nvhost_intr_add_action(&nvhost_get_host(ch->dev)->intr,
+                        syncpt_id, syncpt_val,
+                        NVHOST_INTR_ACTION_WAKEUP, &wq,
+                        wakeup_waiter,
+                        &ref);
+        wakeup_waiter = NULL;
+        WARN(err, "Failed to set wakeup interrupt");
+        wait_event(wq,
+                nvhost_syncpt_is_expired(&nvhost_get_host(ch->dev)->syncpt,
+                                syncpt_id, syncpt_val));
+        nvhost_intr_put_ref(&nvhost_get_host(ch->dev)->intr, ref);
+        nvhost_cdma_update(&ch->cdma);
+        mutex_unlock(&ch->submitlock);
+done:
+        kfree(ctx_waiter);
+        kfree(wakeup_waiter);
+        return err;
+}
diff --git a/drivers/video/tegra/host/host1x/host1x_channel.h b/drivers/video/tegra/host/host1x/host1x_channel.h
new file mode 100644
index 00000000000..4113dbcada2
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_channel.h
@@ -0,0 +1,45 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_channel.h
+ *
+ * Tegra Graphics Host Channel
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_HOST1X_CHANNEL_H
+#define __NVHOST_HOST1X_CHANNEL_H
+struct nvhost_job;
+struct nvhost_channel;
+struct nvhost_hwctx;
+struct nvhost_device;
+/*  Submit job to a host1x client */
+int host1x_channel_submit(struct nvhost_job *job);
+/*  Read 3d register via FIFO */
+int host1x_channel_read_3d_reg(
+        struct nvhost_channel *channel,
+        struct nvhost_hwctx *hwctx,
+        u32 offset,
+        u32 *value);
+/* Reads words from FIFO */
+int host1x_drain_read_fifo(void __iomem *chan_regs,
+                u32 *ptr, unsigned int count, unsigned int *pending);
+int host1x_save_context(struct nvhost_device *dev, u32 syncpt_id);
+#endif
diff --git a/drivers/video/tegra/host/host1x/host1x_debug.c b/drivers/video/tegra/host/host1x/host1x_debug.c
new file mode 100644
index 00000000000..1a1d764bbd6
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_debug.c
@@ -0,0 +1,404 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_debug.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Erik Gilling <konkers@android.com>
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include "dev.h"
+#include "debug.h"
+#include "nvhost_cdma.h"
+#include "../../nvmap/nvmap.h"
+#include "host1x_hardware.h"
+#include "host1x_cdma.h"
+#define NVHOST_DEBUG_MAX_PAGE_OFFSET 102400
+enum {
+        NVHOST_DBG_STATE_CMD = 0,
+        NVHOST_DBG_STATE_DATA = 1,
+        NVHOST_DBG_STATE_GATHER = 2
+};
+static int show_channel_command(struct output *o, u32 addr, u32 val, int *count)
+{
+        unsigned mask;
+        unsigned subop;
+        switch (val >> 28) {
+        case 0x0:
+                mask = val & 0x3f;
+                if (mask) {
+                        nvhost_debug_output(o,
+                                "SETCL(class=%03x, offset=%03x, mask=%02x, [",
+                                val >> 6 & 0x3ff, val >> 16 & 0xfff, mask);
+                        *count = hweight8(mask);
+                        return NVHOST_DBG_STATE_DATA;
+                } else {
+                        nvhost_debug_output(o, "SETCL(class=%03x)\n",
+                                val >> 6 & 0x3ff);
+                        return NVHOST_DBG_STATE_CMD;
+                }
+        case 0x1:
+                nvhost_debug_output(o, "INCR(offset=%03x, [",
+                        val >> 16 & 0xfff);
+                *count = val & 0xffff;
+                return NVHOST_DBG_STATE_DATA;
+        case 0x2:
+                nvhost_debug_output(o, "NONINCR(offset=%03x, [",
+                        val >> 16 & 0xfff);
+                *count = val & 0xffff;
+                return NVHOST_DBG_STATE_DATA;
+        case 0x3:
+                mask = val & 0xffff;
+                nvhost_debug_output(o, "MASK(offset=%03x, mask=%03x, [",
+                           val >> 16 & 0xfff, mask);
+                *count = hweight16(mask);
+                return NVHOST_DBG_STATE_DATA;
+        case 0x4:
+                nvhost_debug_output(o, "IMM(offset=%03x, data=%03x)\n",
+                           val >> 16 & 0xfff, val & 0xffff);
+                return NVHOST_DBG_STATE_CMD;
+        case 0x5:
+                nvhost_debug_output(o, "RESTART(offset=%08x)\n", val << 4);
+                return NVHOST_DBG_STATE_CMD;
+        case 0x6:
+                nvhost_debug_output(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
+                        val >> 16 & 0xfff, val >> 15 & 0x1, val >> 14 & 0x1,
+                        val & 0x3fff);
+                *count = val & 0x3fff; /* TODO: insert */
+                return NVHOST_DBG_STATE_GATHER;
+        case 0xe:
+                subop = val >> 24 & 0xf;
+                if (subop == 0)
+                        nvhost_debug_output(o, "ACQUIRE_MLOCK(index=%d)\n",
+                                val & 0xff);
+                else if (subop == 1)
+                        nvhost_debug_output(o, "RELEASE_MLOCK(index=%d)\n",
+                                val & 0xff);
+                else
+                        nvhost_debug_output(o, "EXTEND_UNKNOWN(%08x)\n", val);
+                return NVHOST_DBG_STATE_CMD;
+        default:
+                return NVHOST_DBG_STATE_CMD;
+        }
+}
+static void show_channel_gather(struct output *o, u32 addr,
+                phys_addr_t phys_addr, u32 words, struct nvhost_cdma *cdma);
+static void show_channel_word(struct output *o, int *state, int *count,
+                u32 addr, u32 val, struct nvhost_cdma *cdma)
+{
+        static int start_count, dont_print;
+        switch (*state) {
+        case NVHOST_DBG_STATE_CMD:
+                if (addr)
+                        nvhost_debug_output(o, "%08x: %08x:", addr, val);
+                else
+                        nvhost_debug_output(o, "%08x:", val);
+                *state = show_channel_command(o, addr, val, count);
+                dont_print = 0;
+                start_count = *count;
+                if (*state == NVHOST_DBG_STATE_DATA && *count == 0) {
+                        *state = NVHOST_DBG_STATE_CMD;
+                        nvhost_debug_output(o, "])\n");
+                }
+                break;
+        case NVHOST_DBG_STATE_DATA:
+                (*count)--;
+                if (start_count - *count < 64)
+                        nvhost_debug_output(o, "%08x%s",
+                                val, *count > 0 ? ", " : "])\n");
+                else if (!dont_print && (*count > 0)) {
+                        nvhost_debug_output(o, "[truncated; %d more words]\n",
+                                *count);
+                        dont_print = 1;
+                }
+                if (*count == 0)
+                        *state = NVHOST_DBG_STATE_CMD;
+                break;
+        case NVHOST_DBG_STATE_GATHER:
+                *state = NVHOST_DBG_STATE_CMD;
+                nvhost_debug_output(o, "%08x]):\n", val);
+                if (cdma) {
+                        show_channel_gather(o, addr, val,
+                                        *count, cdma);
+                }
+                break;
+        }
+}
+static void show_channel_gather(struct output *o, u32 addr,
+                phys_addr_t phys_addr,
+                u32 words, struct nvhost_cdma *cdma)
+{
+#if defined(CONFIG_TEGRA_NVMAP)
+        /* Map dmaget cursor to corresponding nvmap_handle */
+        struct push_buffer *pb = &cdma->push_buffer;
+        u32 cur = addr - pb->phys;
+        struct nvmap_client_handle *nvmap = &pb->nvmap[cur/8];
+        struct nvmap_handle_ref ref;
+        u32 *map_addr, offset;
+        phys_addr_t pin_addr;
+        int state, count, i;
+        if ((u32)nvmap->handle == NVHOST_CDMA_PUSH_GATHER_CTXSAVE) {
+                nvhost_debug_output(o, "[context save]\n");
+                return;
+        }
+        if (!nvmap->handle || !nvmap->client
+                        || atomic_read(&nvmap->handle->ref) < 1) {
+                nvhost_debug_output(o, "[already deallocated]\n");
+                return;
+        }
+        /* Create a fake nvmap_handle_ref - nvmap requires it
+         * but accesses only the first field - nvmap_handle */
+        ref.handle = nvmap->handle;
+        map_addr = nvmap_mmap(&ref);
+        if (!map_addr) {
+                nvhost_debug_output(o, "[could not mmap]\n");
+                return;
+        }
+        /* Get base address from nvmap */
+        pin_addr = nvmap_pin(nvmap->client, &ref);
+        if (IS_ERR_VALUE(pin_addr)) {
+                nvhost_debug_output(o, "[couldn't pin]\n");
+                nvmap_munmap(&ref, map_addr);
+                return;
+        }
+        offset = phys_addr - pin_addr;
+        /*
+         * Sometimes we're given different hardware address to the same
+         * page - in these cases the offset will get an invalid number and
+         * we just have to bail out.
+         */
+        if (offset > NVHOST_DEBUG_MAX_PAGE_OFFSET) {
+                nvhost_debug_output(o, "[address mismatch]\n");
+        } else {
+                /* GATHER buffer starts always with commands */
+                state = NVHOST_DBG_STATE_CMD;
+                for (i = 0; i < words; i++)
+                        show_channel_word(o, &state, &count,
+                                        phys_addr + i * 4,
+                                        *(map_addr + offset/4 + i),
+                                        cdma);
+        }
+        nvmap_unpin(nvmap->client, &ref);
+        nvmap_munmap(&ref, map_addr);
+#endif
+}
+static void show_channel_pair(struct output *o, u32 addr,
+                u32 w0, u32 w1, struct nvhost_cdma *cdma)
+{
+        int state = NVHOST_DBG_STATE_CMD;
+        int count;
+        show_channel_word(o, &state, &count, addr, w0, cdma);
+        show_channel_word(o, &state, &count, addr+4, w1, cdma);
+}
+/**
+ * Retrieve the op pair at a slot offset from a DMA address
+ */
+static void cdma_peek(struct nvhost_cdma *cdma,
+                      u32 dmaget, int slot, u32 *out)
+{
+        u32 offset = dmaget - cdma->push_buffer.phys;
+        u32 *p = cdma->push_buffer.mapped;
+        offset = ((offset + slot * 8) & (PUSH_BUFFER_SIZE - 1)) >> 2;
+        out[0] = p[offset];
+        out[1] = p[offset + 1];
+}
+u32 previous_oppair(struct nvhost_cdma *cdma, u32 cur)
+{
+        u32 pb = cdma->push_buffer.phys;
+        u32 prev = cur-8;
+        if (prev < pb)
+                prev += PUSH_BUFFER_SIZE;
+        return prev;
+}
+static void t20_debug_show_channel_cdma(struct nvhost_master *m,
+        struct nvhost_channel *ch, struct output *o, int chid)
+{
+        struct nvhost_channel *channel = ch;
+        struct nvhost_cdma *cdma = &channel->cdma;
+        u32 dmaput, dmaget, dmactrl;
+        u32 cbstat, cbread;
+        u32 val, base, baseval;
+        u32 pbw[2];
+        dmaput = readl(channel->aperture + HOST1X_CHANNEL_DMAPUT);
+        dmaget = readl(channel->aperture + HOST1X_CHANNEL_DMAGET);
+        dmactrl = readl(channel->aperture + HOST1X_CHANNEL_DMACTRL);
+        cbread = readl(m->sync_aperture + HOST1X_SYNC_CBREAD_x(chid));
+        cbstat = readl(m->sync_aperture + HOST1X_SYNC_CBSTAT_x(chid));
+        nvhost_debug_output(o, "%d-%s (%d): ", chid,
+                            channel->dev->name,
+                            channel->dev->refcount);
+        if (HOST1X_VAL(CHANNEL_DMACTRL, DMASTOP, dmactrl)
+                || !channel->cdma.push_buffer.mapped) {
+                nvhost_debug_output(o, "inactive\n\n");
+                return;
+        }
+        switch (cbstat) {
+        case 0x00010008:
+                nvhost_debug_output(o, "waiting on syncpt %d val %d\n",
+                        cbread >> 24, cbread & 0xffffff);
+                break;
+        case 0x00010009:
+                base = (cbread >> 16) & 0xff;
+                val = readl(m->sync_aperture +
+                                HOST1X_SYNC_SYNCPT_BASE_x(base));
+                baseval = HOST1X_VAL(SYNC_SYNCPT_BASE_0, BASE, val);
+                val = cbread & 0xffff;
+                nvhost_debug_output(o, "waiting on syncpt %d val %d "
+                          "(base %d = %d; offset = %d)\n",
+                        cbread >> 24, baseval + val,
+                        base, baseval, val);
+                break;
+        default:
+                nvhost_debug_output(o,
+                                "active class %02x, offset %04x, val %08x\n",
+                                HOST1X_VAL(SYNC_CBSTAT_0, CBCLASS0, cbstat),
+                                HOST1X_VAL(SYNC_CBSTAT_0, CBOFFSET0, cbstat),
+                                cbread);
+                break;
+        }
+        nvhost_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
+                dmaput, dmaget, dmactrl);
+        nvhost_debug_output(o, "CBREAD %08x, CBSTAT %08x\n", cbread, cbstat);
+        cdma_peek(cdma, dmaget, -1, pbw);
+        show_channel_pair(o, previous_oppair(cdma, dmaget),
+                pbw[0], pbw[1], &channel->cdma);
+        nvhost_debug_output(o, "\n");
+}
+void t20_debug_show_channel_fifo(struct nvhost_master *m,
+        struct nvhost_channel *ch, struct output *o, int chid)
+{
+        u32 val, rd_ptr, wr_ptr, start, end;
+        struct nvhost_channel *channel = ch;
+        int state, count;
+        nvhost_debug_output(o, "%d: fifo:\n", chid);
+        val = readl(channel->aperture + HOST1X_CHANNEL_FIFOSTAT);
+        nvhost_debug_output(o, "FIFOSTAT %08x\n", val);
+        if (HOST1X_VAL(CHANNEL_FIFOSTAT, CFEMPTY, val)) {
+                nvhost_debug_output(o, "[empty]\n");
+                return;
+        }
+        writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+        writel(HOST1X_CREATE(SYNC_CFPEEK_CTRL, ENA, 1)
+                        | HOST1X_CREATE(SYNC_CFPEEK_CTRL, CHANNR, chid),
+                m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+        val = readl(m->sync_aperture + HOST1X_SYNC_CFPEEK_PTRS);
+        rd_ptr = HOST1X_VAL(SYNC_CFPEEK_PTRS, CF_RD_PTR, val);
+        wr_ptr = HOST1X_VAL(SYNC_CFPEEK_PTRS, CF_WR_PTR, val);
+        val = readl(m->sync_aperture + HOST1X_SYNC_CFx_SETUP(chid));
+        start = HOST1X_VAL(SYNC_CF0_SETUP, BASE, val);
+        end = HOST1X_VAL(SYNC_CF0_SETUP, LIMIT, val);
+        state = NVHOST_DBG_STATE_CMD;
+        do {
+                writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+                writel(HOST1X_CREATE(SYNC_CFPEEK_CTRL, ENA, 1)
+                                | HOST1X_CREATE(SYNC_CFPEEK_CTRL, CHANNR, chid)
+                                | HOST1X_CREATE(SYNC_CFPEEK_CTRL, ADDR, rd_ptr),
+                        m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+                val = readl(m->sync_aperture + HOST1X_SYNC_CFPEEK_READ);
+                show_channel_word(o, &state, &count, 0, val, NULL);
+                if (rd_ptr == end)
+                        rd_ptr = start;
+                else
+                        rd_ptr++;
+        } while (rd_ptr != wr_ptr);
+        if (state == NVHOST_DBG_STATE_DATA)
+                nvhost_debug_output(o, ", ...])\n");
+        nvhost_debug_output(o, "\n");
+        writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+}
+static void t20_debug_show_mlocks(struct nvhost_master *m, struct output *o)
+{
+        u32 __iomem *mlo_regs = m->sync_aperture + HOST1X_SYNC_MLOCK_OWNER_0;
+        int i;
+        nvhost_debug_output(o, "---- mlocks ----\n");
+        for (i = 0; i < NV_HOST1X_NB_MLOCKS; i++) {
+                u32 owner = readl(mlo_regs + i);
+                if (HOST1X_VAL(SYNC_MLOCK_OWNER_0, CH_OWNS, owner))
+                        nvhost_debug_output(o, "%d: locked by channel %d\n",
+                                i, HOST1X_VAL(SYNC_MLOCK_OWNER_0, CHID, owner));
+                else if (HOST1X_VAL(SYNC_MLOCK_OWNER_0, CPU_OWNS, owner))
+                        nvhost_debug_output(o, "%d: locked by cpu\n", i);
+                else
+                        nvhost_debug_output(o, "%d: unlocked\n", i);
+        }
+        nvhost_debug_output(o, "\n");
+}
+int nvhost_init_t20_debug_support(struct nvhost_master *host)
+{
+        host->op.debug.show_channel_cdma = t20_debug_show_channel_cdma;
+        host->op.debug.show_channel_fifo = t20_debug_show_channel_fifo;
+        host->op.debug.show_mlocks = t20_debug_show_mlocks;
+        return 0;
+}
diff --git a/drivers/video/tegra/host/host1x/host1x_hardware.h b/drivers/video/tegra/host/host1x/host1x_hardware.h
new file mode 100644
index 00000000000..d13d5752364
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_hardware.h
@@ -0,0 +1,274 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_hardware.h
+ *
+ * Tegra Graphics Host Register Offsets
+ *
+ * Copyright (c) 2010-2012 NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_HOST1X_HOST1X_HARDWARE_H
+#define __NVHOST_HOST1X_HOST1X_HARDWARE_H
+#include <linux/types.h>
+#include <linux/bitops.h>
+/* class ids */
+enum {
+        NV_HOST1X_CLASS_ID = 0x1,
+        NV_VIDEO_ENCODE_MPEG_CLASS_ID = 0x20,
+        NV_GRAPHICS_3D_CLASS_ID = 0x60
+};
+/* channel registers */
+#define NV_HOST1X_CHANNELS 8
+#define NV_HOST1X_CHANNEL0_BASE 0
+#define NV_HOST1X_CHANNEL_MAP_SIZE_BYTES 16384
+#define NV_HOST1X_SYNC_MLOCK_NUM 16
+#define HOST1X_VAL(reg, field, regdata) \
+        ((regdata >> HOST1X_##reg##_##field##_SHIFT) \
+                        & HOST1X_##reg##_##field##_MASK)
+#define HOST1X_CREATE(reg, field, data) \
+        ((data & HOST1X_##reg##_##field##_MASK) \
+                        << HOST1X_##reg##_##field##_SHIFT) \
+#define HOST1X_CHANNEL_FIFOSTAT         0x00
+#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_SHIFT 10
+#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_MASK 0x1
+#define HOST1X_CHANNEL_FIFOSTAT_OUTFENTRIES_SHIFT 24
+#define HOST1X_CHANNEL_FIFOSTAT_OUTFENTRIES_MASK 0x1f
+#define HOST1X_CHANNEL_INDDATA          0x0c
+#define HOST1X_CHANNEL_DMASTART         0x14
+#define HOST1X_CHANNEL_DMAPUT           0x18
+#define HOST1X_CHANNEL_DMAGET           0x1c
+#define HOST1X_CHANNEL_DMAEND           0x20
+#define HOST1X_CHANNEL_DMACTRL          0x24
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP_SHIFT 0
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP_MASK 0x1
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST_SHIFT 1
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST_MASK 0x1
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET_SHIFT 2
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET_MASK 0x1
+#define HOST1X_CHANNEL_SYNC_REG_BASE    0x3000
+#define HOST1X_SYNC_INTMASK             0x4
+#define HOST1X_SYNC_INTC0MASK           0x8
+#define HOST1X_SYNC_HINTSTATUS          0x20
+#define HOST1X_SYNC_HINTMASK            0x24
+#define HOST1X_SYNC_HINTSTATUS_EXT      0x28
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_READ_INT_SHIFT 30
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_READ_INT_MASK 0x1
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_WRITE_INT_SHIFT 31
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_WRITE_INT_MASK 0x1
+#define HOST1X_SYNC_HINTMASK_EXT        0x2c
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS 0x40
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU1_INT_STATUS 0x48
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE 0x60
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0 0x68
+#define HOST1X_SYNC_CF0_SETUP           0x80
+#define HOST1X_SYNC_CF0_SETUP_BASE_SHIFT 0
+#define HOST1X_SYNC_CF0_SETUP_BASE_MASK 0x1ff
+#define HOST1X_SYNC_CF0_SETUP_LIMIT_SHIFT 16
+#define HOST1X_SYNC_CF0_SETUP_LIMIT_MASK 0x1ff
+#define HOST1X_SYNC_CFx_SETUP(x)        (HOST1X_SYNC_CF0_SETUP + (4 * (x)))
+#define HOST1X_SYNC_CMDPROC_STOP        0xac
+#define HOST1X_SYNC_CH_TEARDOWN         0xb0
+#define HOST1X_SYNC_USEC_CLK            0x1a4
+#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG   0x1a8
+#define HOST1X_SYNC_IP_BUSY_TIMEOUT     0x1bc
+#define HOST1X_SYNC_IP_READ_TIMEOUT_ADDR 0x1c0
+#define HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR 0x1c4
+#define HOST1X_SYNC_MLOCK_0             0x2c0
+#define HOST1X_SYNC_MLOCK_OWNER_0       0x340
+#define HOST1X_SYNC_MLOCK_OWNER_0_CHID_SHIFT 8
+#define HOST1X_SYNC_MLOCK_OWNER_0_CHID_MASK 0xf
+#define HOST1X_SYNC_MLOCK_OWNER_0_CPU_OWNS_SHIFT 1
+#define HOST1X_SYNC_MLOCK_OWNER_0_CPU_OWNS_MASK 0x1
+#define HOST1X_SYNC_MLOCK_OWNER_0_CH_OWNS_SHIFT 0
+#define HOST1X_SYNC_MLOCK_OWNER_0_CH_OWNS_MASK 0x1
+#define HOST1X_SYNC_SYNCPT_0            0x400
+#define HOST1X_SYNC_SYNCPT_INT_THRESH_0 0x500
+#define HOST1X_SYNC_SYNCPT_BASE_0       0x600
+#define HOST1X_SYNC_SYNCPT_BASE_0_BASE_SHIFT 0
+#define HOST1X_SYNC_SYNCPT_BASE_0_BASE_MASK 0xffff
+#define HOST1X_SYNC_SYNCPT_BASE_x(x)    (HOST1X_SYNC_SYNCPT_BASE_0 + (4 * (x)))
+#define HOST1X_SYNC_SYNCPT_CPU_INCR     0x700
+#define HOST1X_SYNC_CBREAD_0            0x720
+#define HOST1X_SYNC_CBREAD_x(x)         (HOST1X_SYNC_CBREAD_0 + (4 * (x)))
+#define HOST1X_SYNC_CFPEEK_CTRL         0x74c
+#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_SHIFT 0
+#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_MASK 0x1ff
+#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_SHIFT 16
+#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_MASK 0x7
+#define HOST1X_SYNC_CFPEEK_CTRL_ENA_SHIFT 31
+#define HOST1X_SYNC_CFPEEK_CTRL_ENA_MASK 0x1
+#define HOST1X_SYNC_CFPEEK_READ         0x750
+#define HOST1X_SYNC_CFPEEK_PTRS         0x754
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_SHIFT 0
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_MASK 0x1ff
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_SHIFT 16
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_MASK 0x1ff
+#define HOST1X_SYNC_CBSTAT_0            0x758
+#define HOST1X_SYNC_CBSTAT_0_CBOFFSET0_SHIFT 0
+#define HOST1X_SYNC_CBSTAT_0_CBOFFSET0_MASK 0xffff
+#define HOST1X_SYNC_CBSTAT_0_CBCLASS0_SHIFT 16
+#define HOST1X_SYNC_CBSTAT_0_CBCLASS0_MASK 0xffff
+#define HOST1X_SYNC_CBSTAT_x(x)         (HOST1X_SYNC_CBSTAT_0 + (4 * (x)))
+/* sync registers */
+#define NV_HOST1X_SYNCPT_NB_PTS 32
+#define NV_HOST1X_SYNCPT_NB_BASES 8
+#define NV_HOST1X_NB_MLOCKS 16
+/* host class methods */
+enum {
+        NV_CLASS_HOST_INCR_SYNCPT = 0x0,
+        NV_CLASS_HOST_WAIT_SYNCPT = 0x8,
+        NV_CLASS_HOST_WAIT_SYNCPT_BASE = 0x9,
+        NV_CLASS_HOST_LOAD_SYNCPT_BASE = 0xb,
+        NV_CLASS_HOST_INCR_SYNCPT_BASE = 0xc,
+        NV_CLASS_HOST_INDOFF = 0x2d,
+        NV_CLASS_HOST_INDDATA = 0x2e
+};
+/*  sync point conditionals */
+enum {
+        NV_SYNCPT_IMMEDIATE = 0x0,
+        NV_SYNCPT_OP_DONE = 0x1,
+        NV_SYNCPT_RD_DONE = 0x2,
+        NV_SYNCPT_REG_WR_SAFE = 0x3,
+};
+static inline u32 nvhost_class_host_wait_syncpt(
+        unsigned indx, unsigned threshold)
+{
+        return (indx << 24) | (threshold & 0xffffff);
+}
+static inline u32 nvhost_class_host_load_syncpt_base(
+        unsigned indx, unsigned threshold)
+{
+        return (indx << 24) | (threshold & 0xffffff);
+}
+static inline u32 nvhost_class_host_wait_syncpt_base(
+        unsigned indx, unsigned base_indx, unsigned offset)
+{
+        return (indx << 24) | (base_indx << 16) | offset;
+}
+static inline u32 nvhost_class_host_incr_syncpt_base(
+        unsigned base_indx, unsigned offset)
+{
+        return (base_indx << 24) | offset;
+}
+static inline u32 nvhost_class_host_incr_syncpt(
+        unsigned cond, unsigned indx)
+{
+        return (cond << 8) | indx;
+}
+enum {
+        NV_HOST_MODULE_HOST1X = 0,
+        NV_HOST_MODULE_MPE = 1,
+        NV_HOST_MODULE_GR3D = 6
+};
+static inline u32 nvhost_class_host_indoff_reg_write(
+        unsigned mod_id, unsigned offset, bool auto_inc)
+{
+        u32 v = (0xf << 28) | (mod_id << 18) | (offset << 2);
+        if (auto_inc)
+                v |= BIT(27);
+        return v;
+}
+static inline u32 nvhost_class_host_indoff_reg_read(
+        unsigned mod_id, unsigned offset, bool auto_inc)
+{
+        u32 v = (mod_id << 18) | (offset << 2) | 1;
+        if (auto_inc)
+                v |= BIT(27);
+        return v;
+}
+/* cdma opcodes */
+static inline u32 nvhost_opcode_setclass(
+        unsigned class_id, unsigned offset, unsigned mask)
+{
+        return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
+}
+static inline u32 nvhost_opcode_incr(unsigned offset, unsigned count)
+{
+        return (1 << 28) | (offset << 16) | count;
+}
+static inline u32 nvhost_opcode_nonincr(unsigned offset, unsigned count)
+{
+        return (2 << 28) | (offset << 16) | count;
+}
+static inline u32 nvhost_opcode_mask(unsigned offset, unsigned mask)
+{
+        return (3 << 28) | (offset << 16) | mask;
+}
+static inline u32 nvhost_opcode_imm(unsigned offset, unsigned value)
+{
+        return (4 << 28) | (offset << 16) | value;
+}
+static inline u32 nvhost_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
+{
+        return nvhost_opcode_imm(NV_CLASS_HOST_INCR_SYNCPT,
+                nvhost_class_host_incr_syncpt(cond, indx));
+}
+static inline u32 nvhost_opcode_restart(unsigned address)
+{
+        return (5 << 28) | (address >> 4);
+}
+static inline u32 nvhost_opcode_gather(unsigned count)
+{
+        return (6 << 28) | count;
+}
+static inline u32 nvhost_opcode_gather_nonincr(unsigned offset, unsigned count)
+{
+        return (6 << 28) | (offset << 16) | BIT(15) | count;
+}
+static inline u32 nvhost_opcode_gather_incr(unsigned offset, unsigned count)
+{
+        return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
+}
+#define NVHOST_OPCODE_NOOP nvhost_opcode_nonincr(0, 0)
+static inline u32 nvhost_mask2(unsigned x, unsigned y)
+{
+        return 1 | (1 << (y - x));
+}
+#endif
diff --git a/drivers/video/tegra/host/host1x/host1x_hwctx.h b/drivers/video/tegra/host/host1x/host1x_hwctx.h
new file mode 100644
index 00000000000..7587642d0e1
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_hwctx.h
@@ -0,0 +1,65 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_hwctx.h
+ *
+ * Tegra Graphics Host HOST1X Hardware Context Interface
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#ifndef __NVHOST_HOST1X_HWCTX_H
+#define __NVHOST_HOST1X_HWCTX_H
+#include <linux/kref.h>
+struct nvhost_hwctx_handler;
+struct nvhost_channel;
+#define to_host1x_hwctx_handler(handler) \
+        container_of((handler), struct host1x_hwctx_handler, h)
+#define to_host1x_hwctx(h) container_of((h), struct host1x_hwctx, hwctx)
+#define host1x_hwctx_handler(_hwctx) to_host1x_hwctx_handler((_hwctx)->hwctx.h)
+struct host1x_hwctx {
+        struct nvhost_hwctx hwctx;
+        u32 save_incrs;
+        u32 save_thresh;
+        u32 save_slots;
+        struct nvmap_handle_ref *restore;
+        u32 *restore_virt;
+        phys_addr_t restore_phys;
+        u32 restore_size;
+        u32 restore_incrs;
+};
+struct host1x_hwctx_handler {
+        struct nvhost_hwctx_handler h;
+        u32 syncpt;
+        u32 waitbase;
+        u32 restore_size;
+        u32 restore_incrs;
+        struct nvmap_handle_ref *save_buf;
+        u32 save_incrs;
+        u32 save_thresh;
+        u32 save_slots;
+        phys_addr_t save_phys;
+        u32 save_size;
+};
+#endif
diff --git a/drivers/video/tegra/host/host1x/host1x_intr.c b/drivers/video/tegra/host/host1x/host1x_intr.c
new file mode 100644
index 00000000000..47e984e2943
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_intr.c
@@ -0,0 +1,218 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_intr.c
+ *
+ * Tegra Graphics Host Interrupt Management
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include "nvhost_intr.h"
+#include "dev.h"
+#include "host1x_hardware.h"
+/*** HW host sync management ***/
+static void t20_intr_init_host_sync(struct nvhost_intr *intr)
+{
+        struct nvhost_master *dev = intr_to_dev(intr);
+        void __iomem *sync_regs = dev->sync_aperture;
+        /* disable the ip_busy_timeout. this prevents write drops, etc.
+         * there's no real way to recover from a hung client anyway.
+         */
+        writel(0, sync_regs + HOST1X_SYNC_IP_BUSY_TIMEOUT);
+        /* increase the auto-ack timout to the maximum value. 2d will hang
+         * otherwise on ap20.
+         */
+        writel(0xff, sync_regs + HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
+}
+static void t20_intr_set_host_clocks_per_usec(struct nvhost_intr *intr, u32 cpm)
+{
+        struct nvhost_master *dev = intr_to_dev(intr);
+        void __iomem *sync_regs = dev->sync_aperture;
+        /* write microsecond clock register */
+        writel(cpm, sync_regs + HOST1X_SYNC_USEC_CLK);
+}
+static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
+        u32 id, u32 thresh)
+{
+        struct nvhost_master *dev = intr_to_dev(intr);
+        void __iomem *sync_regs = dev->sync_aperture;
+        thresh &= 0xffff;
+        writel(thresh, sync_regs + (HOST1X_SYNC_SYNCPT_INT_THRESH_0 + id * 4));
+}
+static void t20_intr_enable_syncpt_intr(struct nvhost_intr *intr, u32 id)
+{
+        struct nvhost_master *dev = intr_to_dev(intr);
+        void __iomem *sync_regs = dev->sync_aperture;
+        writel(BIT(id), sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0);
+}
+static void t20_intr_disable_all_syncpt_intrs(struct nvhost_intr *intr)
+{
+        struct nvhost_master *dev = intr_to_dev(intr);
+        void __iomem *sync_regs = dev->sync_aperture;
+        /* disable interrupts for both cpu's */
+        writel(0, sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
+        /* clear status for both cpu's */
+        writel(0xffffffffu, sync_regs +
+                HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
+        writel(0xffffffffu, sync_regs +
+                HOST1X_SYNC_SYNCPT_THRESH_CPU1_INT_STATUS);
+}
+/**
+ * Sync point threshold interrupt service function
+ * Handles sync point threshold triggers, in interrupt context
+ */
+irqreturn_t t20_intr_syncpt_thresh_isr(int irq, void *dev_id)
+{
+        struct nvhost_intr_syncpt *syncpt = dev_id;
+        unsigned int id = syncpt->id;
+        struct nvhost_intr *intr = intr_syncpt_to_intr(syncpt);
+        void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
+        writel(BIT(id),
+                sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
+        writel(BIT(id),
+                sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
+        return IRQ_WAKE_THREAD;
+}
+/**
+ * Host general interrupt service function
+ * Handles read / write failures
+ */
+static irqreturn_t t20_intr_host1x_isr(int irq, void *dev_id)
+{
+        struct nvhost_intr *intr = dev_id;
+        void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
+        u32 stat;
+        u32 ext_stat;
+        u32 addr;
+        stat = readl(sync_regs + HOST1X_SYNC_HINTSTATUS);
+        ext_stat = readl(sync_regs + HOST1X_SYNC_HINTSTATUS_EXT);
+        if (HOST1X_VAL(SYNC_HINTSTATUS_EXT, IP_READ_INT, ext_stat)) {
+                addr = readl(sync_regs + HOST1X_SYNC_IP_READ_TIMEOUT_ADDR);
+                pr_err("Host read timeout at address %x\n", addr);
+        }
+        if (HOST1X_VAL(SYNC_HINTSTATUS_EXT, IP_WRITE_INT, ext_stat)) {
+                addr = readl(sync_regs + HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR);
+                pr_err("Host write timeout at address %x\n", addr);
+        }
+        writel(ext_stat, sync_regs + HOST1X_SYNC_HINTSTATUS_EXT);
+        writel(stat, sync_regs + HOST1X_SYNC_HINTSTATUS);
+        return IRQ_HANDLED;
+}
+static int t20_intr_request_host_general_irq(struct nvhost_intr *intr)
+{
+        void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
+        int err;
+        if (intr->host_general_irq_requested)
+                return 0;
+        /* master disable for general (not syncpt) host interrupts */
+        writel(0, sync_regs + HOST1X_SYNC_INTMASK);
+        /* clear status & extstatus */
+        writel(0xfffffffful, sync_regs + HOST1X_SYNC_HINTSTATUS_EXT);
+        writel(0xfffffffful, sync_regs + HOST1X_SYNC_HINTSTATUS);
+        err = request_irq(intr->host_general_irq, t20_intr_host1x_isr, 0,
+                        "host_status", intr);
+        if (err)
+                return err;
+        /* enable extra interrupt sources IP_READ_INT and IP_WRITE_INT */
+        writel(BIT(30) | BIT(31), sync_regs + HOST1X_SYNC_HINTMASK_EXT);
+        /* enable extra interrupt sources */
+        writel(BIT(31), sync_regs + HOST1X_SYNC_HINTMASK);
+        /* enable host module interrupt to CPU0 */
+        writel(BIT(0), sync_regs + HOST1X_SYNC_INTC0MASK);
+        /* master enable for general (not syncpt) host interrupts */
+        writel(BIT(0), sync_regs + HOST1X_SYNC_INTMASK);
+        intr->host_general_irq_requested = true;
+        return err;
+}
+static void t20_intr_free_host_general_irq(struct nvhost_intr *intr)
+{
+        if (intr->host_general_irq_requested) {
+                void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
+                /* master disable for general (not syncpt) host interrupts */
+                writel(0, sync_regs + HOST1X_SYNC_INTMASK);
+                free_irq(intr->host_general_irq, intr);
+                intr->host_general_irq_requested = false;
+        }
+}
+static int t20_request_syncpt_irq(struct nvhost_intr_syncpt *syncpt)
+{
+        int err;
+        if (syncpt->irq_requested)
+                return 0;
+        err = request_threaded_irq(syncpt->irq,
+                                   t20_intr_syncpt_thresh_isr,
+                                   nvhost_syncpt_thresh_fn,
+                                   0, syncpt->thresh_irq_name, syncpt);
+        if (err)
+                return err;
+        syncpt->irq_requested = 1;
+        return 0;
+}
+int nvhost_init_t20_intr_support(struct nvhost_master *host)
+{
+        host->op.intr.init_host_sync = t20_intr_init_host_sync;
+        host->op.intr.set_host_clocks_per_usec =
+                t20_intr_set_host_clocks_per_usec;
+        host->op.intr.set_syncpt_threshold = t20_intr_set_syncpt_threshold;
+        host->op.intr.enable_syncpt_intr = t20_intr_enable_syncpt_intr;
+        host->op.intr.disable_all_syncpt_intrs =
+                t20_intr_disable_all_syncpt_intrs;
+        host->op.intr.request_host_general_irq =
+                t20_intr_request_host_general_irq;
+        host->op.intr.free_host_general_irq =
+                t20_intr_free_host_general_irq;
+        host->op.intr.request_syncpt_irq =
+                t20_request_syncpt_irq;
+        return 0;
+}
diff --git a/drivers/video/tegra/host/host1x/host1x_syncpt.c b/drivers/video/tegra/host/host1x/host1x_syncpt.c
new file mode 100644
index 00000000000..b0fd9970aaa
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_syncpt.c
@@ -0,0 +1,248 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_syncpt.c
+ *
+ * Tegra Graphics Host Syncpoints for HOST1X
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/nvhost_ioctl.h>
+#include "nvhost_syncpt.h"
+#include "dev.h"
+#include "host1x_syncpt.h"
+#include "host1x_hardware.h"
+/**
+ * Write the current syncpoint value back to hw.
+ */
+static void t20_syncpt_reset(struct nvhost_syncpt *sp, u32 id)
+{
+        struct nvhost_master *dev = syncpt_to_dev(sp);
+        int min = nvhost_syncpt_read_min(sp, id);
+        writel(min, dev->sync_aperture + (HOST1X_SYNC_SYNCPT_0 + id * 4));
+}
+/**
+ * Write the current waitbase value back to hw.
+ */
+static void t20_syncpt_reset_wait_base(struct nvhost_syncpt *sp, u32 id)
+{
+        struct nvhost_master *dev = syncpt_to_dev(sp);
+        writel(sp->base_val[id],
+                dev->sync_aperture + (HOST1X_SYNC_SYNCPT_BASE_0 + id * 4));
+}
+/**
+ * Read waitbase value from hw.
+ */
+static void t20_syncpt_read_wait_base(struct nvhost_syncpt *sp, u32 id)
+{
+        struct nvhost_master *dev = syncpt_to_dev(sp);
+        sp->base_val[id] = readl(dev->sync_aperture +
+                                (HOST1X_SYNC_SYNCPT_BASE_0 + id * 4));
+}
+/**
+ * Updates the last value read from hardware.
+ * (was nvhost_syncpt_update_min)
+ */
+static u32 t20_syncpt_update_min(struct nvhost_syncpt *sp, u32 id)
+{
+        struct nvhost_master *dev = syncpt_to_dev(sp);
+        void __iomem *sync_regs = dev->sync_aperture;
+        u32 old, live;
+        do {
+                old = nvhost_syncpt_read_min(sp, id);
+                live = readl(sync_regs + (HOST1X_SYNC_SYNCPT_0 + id * 4));
+        } while ((u32)atomic_cmpxchg(&sp->min_val[id], old, live) != old);
+        if (!nvhost_syncpt_check_max(sp, id, live))
+                dev_err(&syncpt_to_dev(sp)->dev->dev,
+                                "%s failed: id=%u\n",
+                                __func__,
+                                id);
+        return live;
+}
+/**
+ * Write a cpu syncpoint increment to the hardware, without touching
+ * the cache. Caller is responsible for host being powered.
+ */
+static void t20_syncpt_cpu_incr(struct nvhost_syncpt *sp, u32 id)
+{
+        struct nvhost_master *dev = syncpt_to_dev(sp);
+        BUG_ON(!nvhost_module_powered(dev->dev));
+        if (!client_managed(id) && nvhost_syncpt_min_eq_max(sp, id)) {
+                dev_err(&syncpt_to_dev(sp)->dev->dev,
+                        "Trying to increment syncpoint id %d beyond max\n",
+                        id);
+                nvhost_debug_dump(syncpt_to_dev(sp));
+                return;
+        }
+        writel(BIT(id), dev->sync_aperture + HOST1X_SYNC_SYNCPT_CPU_INCR);
+        wmb();
+}
+/* check for old WAITs to be removed (avoiding a wrap) */
+static int t20_syncpt_wait_check(struct nvhost_syncpt *sp,
+                                 struct nvmap_client *nvmap,
+                                 u32 waitchk_mask,
+                                 struct nvhost_waitchk *wait,
+                                 int num_waitchk)
+{
+        u32 idx;
+        int err = 0;
+        /* get current syncpt values */
+        for (idx = 0; idx < NV_HOST1X_SYNCPT_NB_PTS; idx++) {
+                if (BIT(idx) & waitchk_mask)
+                        nvhost_syncpt_update_min(sp, idx);
+        }
+        BUG_ON(!wait && !num_waitchk);
+        /* compare syncpt vs wait threshold */
+        while (num_waitchk) {
+                u32 override;
+                BUG_ON(wait->syncpt_id >= NV_HOST1X_SYNCPT_NB_PTS);
+                if (nvhost_syncpt_is_expired(sp,
+                                        wait->syncpt_id, wait->thresh)) {
+                        /*
+                         * NULL an already satisfied WAIT_SYNCPT host method,
+                         * by patching its args in the command stream. The
+                         * method data is changed to reference a reserved
+                         * (never given out or incr) NVSYNCPT_GRAPHICS_HOST
+                         * syncpt with a matching threshold value of 0, so
+                         * is guaranteed to be popped by the host HW.
+                         */
+                        dev_dbg(&syncpt_to_dev(sp)->dev->dev,
+                            "drop WAIT id %d (%s) thresh 0x%x, min 0x%x\n",
+                            wait->syncpt_id,
+                            syncpt_op(sp).name(sp, wait->syncpt_id),
+                            wait->thresh,
+                            nvhost_syncpt_read_min(sp, wait->syncpt_id));
+                        /* patch the wait */
+                        override = nvhost_class_host_wait_syncpt(
+                                        NVSYNCPT_GRAPHICS_HOST, 0);
+                        err = nvmap_patch_word(nvmap,
+                                        (struct nvmap_handle *)wait->mem,
+                                        wait->offset, override);
+                        if (err)
+                                break;
+                }
+                wait++;
+                num_waitchk--;
+        }
+        return err;
+}
+static const char *s_syncpt_names[32] = {
+        "gfx_host",
+        "", "", "", "", "", "", "",
+        "disp0_a", "disp1_a", "avp_0",
+        "csi_vi_0", "csi_vi_1",
+        "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
+        "2d_0", "2d_1",
+        "disp0_b", "disp1_b",
+        "3d",
+        "mpe",
+        "disp0_c", "disp1_c",
+        "vblank0", "vblank1",
+        "mpe_ebm_eof", "mpe_wr_safe",
+        "2d_tinyblt",
+        "dsi"
+};
+static const char *t20_syncpt_name(struct nvhost_syncpt *s, u32 id)
+{
+        BUG_ON(id >= ARRAY_SIZE(s_syncpt_names));
+        return s_syncpt_names[id];
+}
+static void t20_syncpt_debug(struct nvhost_syncpt *sp)
+{
+        u32 i;
+        for (i = 0; i < NV_HOST1X_SYNCPT_NB_PTS; i++) {
+                u32 max = nvhost_syncpt_read_max(sp, i);
+                u32 min = nvhost_syncpt_update_min(sp, i);
+                if (!max && !min)
+                        continue;
+                dev_info(&syncpt_to_dev(sp)->dev->dev,
+                        "id %d (%s) min %d max %d\n",
+                        i, syncpt_op(sp).name(sp, i),
+                        min, max);
+        }
+        for (i = 0; i < NV_HOST1X_SYNCPT_NB_BASES; i++) {
+                u32 base_val;
+                t20_syncpt_read_wait_base(sp, i);
+                base_val = sp->base_val[i];
+                if (base_val)
+                        dev_info(&syncpt_to_dev(sp)->dev->dev,
+                                        "waitbase id %d val %d\n",
+                                        i, base_val);
+        }
+}
+static int syncpt_mutex_try_lock(struct nvhost_syncpt *sp,
+                unsigned int idx)
+{
+        void __iomem *sync_regs = syncpt_to_dev(sp)->sync_aperture;
+        /* mlock registers returns 0 when the lock is aquired.
+         * writing 0 clears the lock. */
+        return !!readl(sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
+}
+static void syncpt_mutex_unlock(struct nvhost_syncpt *sp,
+               unsigned int idx)
+{
+        void __iomem *sync_regs = syncpt_to_dev(sp)->sync_aperture;
+        writel(0, sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
+}
+int host1x_init_syncpt_support(struct nvhost_master *host)
+{
+        host->sync_aperture = host->aperture +
+                (NV_HOST1X_CHANNEL0_BASE +
+                        HOST1X_CHANNEL_SYNC_REG_BASE);
+        host->op.syncpt.reset = t20_syncpt_reset;
+        host->op.syncpt.reset_wait_base = t20_syncpt_reset_wait_base;
+        host->op.syncpt.read_wait_base = t20_syncpt_read_wait_base;
+        host->op.syncpt.update_min = t20_syncpt_update_min;
+        host->op.syncpt.cpu_incr = t20_syncpt_cpu_incr;
+        host->op.syncpt.wait_check = t20_syncpt_wait_check;
+        host->op.syncpt.debug = t20_syncpt_debug;
+        host->op.syncpt.name = t20_syncpt_name;
+        host->op.syncpt.mutex_try_lock = syncpt_mutex_try_lock;
+        host->op.syncpt.mutex_unlock = syncpt_mutex_unlock;
+        host->syncpt.nb_pts = NV_HOST1X_SYNCPT_NB_PTS;
+        host->syncpt.nb_bases = NV_HOST1X_SYNCPT_NB_BASES;
+        host->syncpt.client_managed = NVSYNCPTS_CLIENT_MANAGED;
+        host->syncpt.nb_mlocks =  NV_HOST1X_SYNC_MLOCK_NUM;
+        return 0;
+}
diff --git a/drivers/video/tegra/host/host1x/host1x_syncpt.h b/drivers/video/tegra/host/host1x/host1x_syncpt.h
new file mode 100644
index 00000000000..0d263dc92ed
--- /dev/null
+++ b/drivers/video/tegra/host/host1x/host1x_syncpt.h
@@ -0,0 +1,77 @@
+/*
+ * drivers/video/tegra/host/host1x/host1x_syncpt.h
+ *
+ * Tegra Graphics Host Syncpoints for HOST1X
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_HOST1X_HOST1X_SYNCPT_H
+#define __NVHOST_HOST1X_HOST1X_SYNCPT_H
+#define NVSYNCPT_DISP0_A                     (8)
+#define NVSYNCPT_DISP1_A                     (9)
+#define NVSYNCPT_AVP_0                       (10)
+#define NVSYNCPT_CSI_VI_0                    (11)
+#define NVSYNCPT_CSI_VI_1                    (12)
+#define NVSYNCPT_VI_ISP_0                    (13)
+#define NVSYNCPT_VI_ISP_1                    (14)
+#define NVSYNCPT_VI_ISP_2                    (15)
+#define NVSYNCPT_VI_ISP_3                    (16)
+#define NVSYNCPT_VI_ISP_4                    (17)
+#define NVSYNCPT_2D_0                        (18)
+#define NVSYNCPT_2D_1                        (19)
+#define NVSYNCPT_DISP0_B                     (20)
+#define NVSYNCPT_DISP1_B                     (21)
+#define NVSYNCPT_3D                          (22)
+#define NVSYNCPT_MPE                         (23)
+#define NVSYNCPT_DISP0_C                     (24)
+#define NVSYNCPT_DISP1_C                     (25)
+#define NVSYNCPT_VBLANK0                     (26)
+#define NVSYNCPT_VBLANK1                     (27)
+#define NVSYNCPT_MPE_EBM_EOF                 (28)
+#define NVSYNCPT_MPE_WR_SAFE                 (29)
+#define NVSYNCPT_DSI                         (31)
+/*#define NVSYNCPT_2D_CHANNEL2_0    (20) */
+/*#define NVSYNCPT_2D_CHANNEL2_1    (21) */
+/*#define NVSYNCPT_2D_TINYBLT_WAR                    (30)*/
+/*#define NVSYNCPT_2D_TINYBLT_RESTORE_CLASS_ID (30)*/
+/* sync points that are wholly managed by the client */
+#define NVSYNCPTS_CLIENT_MANAGED ( \
+        BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) | \
+        BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) | \
+        BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) | \
+        BIT(NVSYNCPT_DSI) | \
+        BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1) | \
+        BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) | \
+        BIT(NVSYNCPT_VI_ISP_1) | BIT(NVSYNCPT_VI_ISP_2) | \
+        BIT(NVSYNCPT_VI_ISP_3) | BIT(NVSYNCPT_VI_ISP_4) | \
+        BIT(NVSYNCPT_MPE_EBM_EOF) | BIT(NVSYNCPT_MPE_WR_SAFE) | \
+        BIT(NVSYNCPT_2D_1) | BIT(NVSYNCPT_AVP_0))
+#define NVWAITBASE_2D_0 (1)
+#define NVWAITBASE_2D_1 (2)
+#define NVWAITBASE_3D   (3)
+#define NVWAITBASE_MPE  (4)
+struct nvhost_master;
+int host1x_init_syncpt(struct nvhost_master *host);
+int host1x_init_syncpt_support(struct nvhost_master *host);
+#endif
diff --git a/drivers/video/tegra/host/isp/Makefile b/drivers/video/tegra/host/isp/Makefile
new file mode 100644
index 00000000000..7bcdc33c83d
--- /dev/null
+++ b/drivers/video/tegra/host/isp/Makefile
@@ -0,0 +1,7 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-isp-objs  = \
+                isp.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-isp.o
diff --git a/drivers/video/tegra/host/isp/isp.c b/drivers/video/tegra/host/isp/isp.c
new file mode 100644
index 00000000000..f39dc644b27
--- /dev/null
+++ b/drivers/video/tegra/host/isp/isp.c
@@ -0,0 +1,82 @@
+/*
+ * drivers/video/tegra/host/isp/isp.c
+ *
+ * Tegra Graphics ISP
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "dev.h"
+#include "bus_client.h"
+static int __devinit isp_probe(struct nvhost_device *dev)
+{
+        return nvhost_client_device_init(dev);
+}
+static int __exit isp_remove(struct nvhost_device *dev)
+{
+        /* Add clean-up */
+        return 0;
+}
+static int isp_suspend(struct nvhost_device *dev, pm_message_t state)
+{
+        return nvhost_client_device_suspend(dev);
+}
+static int isp_resume(struct nvhost_device *dev)
+{
+        dev_info(&dev->dev, "resuming\n");
+        return 0;
+}
+struct nvhost_device *isp_device;
+static struct nvhost_driver isp_driver = {
+        .probe = isp_probe,
+        .remove = __exit_p(isp_remove),
+#ifdef CONFIG_PM
+        .suspend = isp_suspend,
+        .resume = isp_resume,
+#endif
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "isp",
+        }
+};
+static int __init isp_init(void)
+{
+        int err;
+        isp_device = nvhost_get_device("isp");
+        if (!isp_device)
+                return -ENXIO;
+        err = nvhost_device_register(isp_device);
+        if (err)
+                return err;
+        return nvhost_driver_register(&isp_driver);
+}
+static void __exit isp_exit(void)
+{
+        nvhost_driver_unregister(&isp_driver);
+}
+module_init(isp_init);
+module_exit(isp_exit);
diff --git a/drivers/video/tegra/host/mpe/Makefile b/drivers/video/tegra/host/mpe/Makefile
new file mode 100644
index 00000000000..efd77bb88fe
--- /dev/null
+++ b/drivers/video/tegra/host/mpe/Makefile
@@ -0,0 +1,7 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-mpe-objs  = \
+                mpe.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-mpe.o
diff --git a/drivers/video/tegra/host/mpe/mpe.c b/drivers/video/tegra/host/mpe/mpe.c
new file mode 100644
index 00000000000..28002aa637a
--- /dev/null
+++ b/drivers/video/tegra/host/mpe/mpe.c
@@ -0,0 +1,638 @@
+/*
+ * drivers/video/tegra/host/mpe/mpe.c
+ *
+ * Tegra Graphics Host MPE
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_hwctx.h"
+#include "dev.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_syncpt.h"
+#include "host1x/host1x_hwctx.h"
+#include "t20/t20.h"
+#include <linux/slab.h>
+#include "bus_client.h"
+enum {
+        HWCTX_REGINFO_NORMAL = 0,
+        HWCTX_REGINFO_STASH,
+        HWCTX_REGINFO_CALCULATE,
+        HWCTX_REGINFO_WRITEBACK
+};
+const struct hwctx_reginfo ctxsave_regs_mpe[] = {
+        HWCTX_REGINFO(0x124,  1, STASH),
+        HWCTX_REGINFO(0x123,  1, STASH),
+        HWCTX_REGINFO(0x103,  1, STASH),
+        HWCTX_REGINFO(0x074,  1, STASH),
+        HWCTX_REGINFO(0x021,  1, NORMAL),
+        HWCTX_REGINFO(0x020,  1, STASH),
+        HWCTX_REGINFO(0x024,  2, NORMAL),
+        HWCTX_REGINFO(0x0e6,  1, NORMAL),
+        HWCTX_REGINFO(0x3fc,  1, NORMAL),
+        HWCTX_REGINFO(0x3d0,  1, NORMAL),
+        HWCTX_REGINFO(0x3d4,  1, NORMAL),
+        HWCTX_REGINFO(0x013,  1, NORMAL),
+        HWCTX_REGINFO(0x022,  1, NORMAL),
+        HWCTX_REGINFO(0x030,  4, NORMAL),
+        HWCTX_REGINFO(0x023,  1, NORMAL),
+        HWCTX_REGINFO(0x070,  1, NORMAL),
+        HWCTX_REGINFO(0x0a0,  9, NORMAL),
+        HWCTX_REGINFO(0x071,  1, NORMAL),
+        HWCTX_REGINFO(0x100,  4, NORMAL),
+        HWCTX_REGINFO(0x104,  2, NORMAL),
+        HWCTX_REGINFO(0x108,  9, NORMAL),
+        HWCTX_REGINFO(0x112,  2, NORMAL),
+        HWCTX_REGINFO(0x114,  1, STASH),
+        HWCTX_REGINFO(0x014,  1, NORMAL),
+        HWCTX_REGINFO(0x072,  1, NORMAL),
+        HWCTX_REGINFO(0x200,  1, NORMAL),
+        HWCTX_REGINFO(0x0d1,  1, NORMAL),
+        HWCTX_REGINFO(0x0d0,  1, NORMAL),
+        HWCTX_REGINFO(0x0c0,  1, NORMAL),
+        HWCTX_REGINFO(0x0c3,  2, NORMAL),
+        HWCTX_REGINFO(0x0d2,  1, NORMAL),
+        HWCTX_REGINFO(0x0d8,  1, NORMAL),
+        HWCTX_REGINFO(0x0e0,  2, NORMAL),
+        HWCTX_REGINFO(0x07f,  2, NORMAL),
+        HWCTX_REGINFO(0x084,  8, NORMAL),
+        HWCTX_REGINFO(0x0d3,  1, NORMAL),
+        HWCTX_REGINFO(0x040, 13, NORMAL),
+        HWCTX_REGINFO(0x050,  6, NORMAL),
+        HWCTX_REGINFO(0x058,  1, NORMAL),
+        HWCTX_REGINFO(0x057,  1, NORMAL),
+        HWCTX_REGINFO(0x111,  1, NORMAL),
+        HWCTX_REGINFO(0x130,  3, NORMAL),
+        HWCTX_REGINFO(0x201,  1, NORMAL),
+        HWCTX_REGINFO(0x068,  2, NORMAL),
+        HWCTX_REGINFO(0x08c,  1, NORMAL),
+        HWCTX_REGINFO(0x0cf,  1, NORMAL),
+        HWCTX_REGINFO(0x082,  2, NORMAL),
+        HWCTX_REGINFO(0x075,  1, NORMAL),
+        HWCTX_REGINFO(0x0e8,  1, NORMAL),
+        HWCTX_REGINFO(0x056,  1, NORMAL),
+        HWCTX_REGINFO(0x057,  1, NORMAL),
+        HWCTX_REGINFO(0x073,  1, CALCULATE),
+        HWCTX_REGINFO(0x074,  1, NORMAL),
+        HWCTX_REGINFO(0x075,  1, NORMAL),
+        HWCTX_REGINFO(0x076,  1, STASH),
+        HWCTX_REGINFO(0x11a,  9, NORMAL),
+        HWCTX_REGINFO(0x123,  1, NORMAL),
+        HWCTX_REGINFO(0x124,  1, NORMAL),
+        HWCTX_REGINFO(0x12a,  5, NORMAL),
+        HWCTX_REGINFO(0x12f,  1, STASH),
+        HWCTX_REGINFO(0x125,  2, NORMAL),
+        HWCTX_REGINFO(0x034,  1, NORMAL),
+        HWCTX_REGINFO(0x133,  2, NORMAL),
+        HWCTX_REGINFO(0x127,  1, NORMAL),
+        HWCTX_REGINFO(0x106,  1, WRITEBACK),
+        HWCTX_REGINFO(0x107,  1, WRITEBACK)
+};
+#define NR_STASHES 8
+#define NR_WRITEBACKS 2
+#define RC_RAM_LOAD_CMD 0x115
+#define RC_RAM_LOAD_DATA 0x116
+#define RC_RAM_READ_CMD 0x128
+#define RC_RAM_READ_DATA 0x129
+#define RC_RAM_SIZE 692
+#define IRFR_RAM_LOAD_CMD 0xc5
+#define IRFR_RAM_LOAD_DATA 0xc6
+#define IRFR_RAM_READ_CMD 0xcd
+#define IRFR_RAM_READ_DATA 0xce
+#define IRFR_RAM_SIZE 408
+struct mpe_save_info {
+        u32 in[NR_STASHES];
+        u32 out[NR_WRITEBACKS];
+        unsigned in_pos;
+        unsigned out_pos;
+        u32 h264_mode;
+};
+/*** restore ***/
+static unsigned int restore_size;
+static void restore_begin(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        /* set class to host */
+        ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+        /* increment sync point base */
+        ptr[1] = nvhost_class_host_incr_syncpt_base(h->waitbase, 1);
+        /* set class to MPE */
+        ptr[2] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID, 0, 0);
+}
+#define RESTORE_BEGIN_SIZE 3
+static void restore_ram(u32 *ptr, unsigned words,
+                        unsigned cmd_reg, unsigned data_reg)
+{
+        ptr[0] = nvhost_opcode_imm(cmd_reg, words);
+        ptr[1] = nvhost_opcode_nonincr(data_reg, words);
+}
+#define RESTORE_RAM_SIZE 2
+static void restore_end(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        /* syncpt increment to track restore gather. */
+        ptr[0] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
+                        h->syncpt);
+}
+#define RESTORE_END_SIZE 1
+static u32 *setup_restore_regs(u32 *ptr,
+                        const struct hwctx_reginfo *regs,
+                        unsigned int nr_regs)
+{
+        const struct hwctx_reginfo *rend = regs + nr_regs;
+        for ( ; regs != rend; ++regs) {
+                u32 offset = regs->offset;
+                u32 count = regs->count;
+                *ptr++ = nvhost_opcode_incr(offset, count);
+                ptr += count;
+        }
+        return ptr;
+}
+static u32 *setup_restore_ram(u32 *ptr, unsigned words,
+                        unsigned cmd_reg, unsigned data_reg)
+{
+        restore_ram(ptr, words, cmd_reg, data_reg);
+        return ptr + (RESTORE_RAM_SIZE + words);
+}
+static void setup_restore(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        restore_begin(h, ptr);
+        ptr += RESTORE_BEGIN_SIZE;
+        ptr = setup_restore_regs(ptr, ctxsave_regs_mpe,
+                                ARRAY_SIZE(ctxsave_regs_mpe));
+        ptr = setup_restore_ram(ptr, RC_RAM_SIZE,
+                        RC_RAM_LOAD_CMD, RC_RAM_LOAD_DATA);
+        ptr = setup_restore_ram(ptr, IRFR_RAM_SIZE,
+                        IRFR_RAM_LOAD_CMD, IRFR_RAM_LOAD_DATA);
+        restore_end(h, ptr);
+        wmb();
+}
+/*** save ***/
+struct save_info {
+        u32 *ptr;
+        unsigned int save_count;
+        unsigned int restore_count;
+};
+static void __init save_begin(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        /* MPE: when done, increment syncpt to base+1 */
+        ptr[0] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID, 0, 0);
+        ptr[1] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, h->syncpt);
+        /* host: wait for syncpt base+1 */
+        ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+        ptr[3] = nvhost_class_host_wait_syncpt_base(h->syncpt, h->waitbase, 1);
+        /* host: signal context read thread to start reading */
+        ptr[4] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE, h->syncpt);
+}
+#define SAVE_BEGIN_SIZE 5
+static void __init save_direct(u32 *ptr, u32 start_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_INDOFF, 1);
+        ptr[1] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_MPE,
+                                                start_reg, true);
+        ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+}
+#define SAVE_DIRECT_SIZE 3
+static void __init save_set_ram_cmd(u32 *ptr, u32 cmd_reg, u32 count)
+{
+        ptr[0] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID,
+                                        cmd_reg, 1);
+        ptr[1] = count;
+}
+#define SAVE_SET_RAM_CMD_SIZE 2
+static void __init save_read_ram_data_nasty(u32 *ptr, u32 data_reg)
+{
+        ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_INDOFF, 1);
+        ptr[1] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_MPE,
+                                                data_reg, false);
+        ptr[2] = nvhost_opcode_imm(NV_CLASS_HOST_INDDATA, 0);
+        /* write junk data to avoid 'cached problem with register memory' */
+        ptr[3] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID,
+                                        data_reg, 1);
+        ptr[4] = 0x99;
+}
+#define SAVE_READ_RAM_DATA_NASTY_SIZE 5
+static void __init save_end(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        /* Wait for context read service to finish (cpu incr 3) */
+        ptr[0] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+                                        NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1);
+        ptr[1] = nvhost_class_host_wait_syncpt_base(h->syncpt, h->waitbase, 3);
+        /* Advance syncpoint base */
+        ptr[2] = nvhost_opcode_nonincr(NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+        ptr[3] = nvhost_class_host_incr_syncpt_base(h->waitbase, 3);
+        /* set class back to the unit */
+        ptr[4] = nvhost_opcode_setclass(NV_VIDEO_ENCODE_MPEG_CLASS_ID, 0, 0);
+}
+#define SAVE_END_SIZE 5
+static void __init setup_save_regs(struct save_info *info,
+                        const struct hwctx_reginfo *regs,
+                        unsigned int nr_regs)
+{
+        const struct hwctx_reginfo *rend = regs + nr_regs;
+        u32 *ptr = info->ptr;
+        unsigned int save_count = info->save_count;
+        unsigned int restore_count = info->restore_count;
+        for ( ; regs != rend; ++regs) {
+                u32 offset = regs->offset;
+                u32 count = regs->count;
+                if (regs->type != HWCTX_REGINFO_WRITEBACK) {
+                        if (ptr) {
+                                save_direct(ptr, offset, count);
+                                ptr += SAVE_DIRECT_SIZE;
+                                memset(ptr, 0, count * 4);
+                                ptr += count;
+                        }
+                        save_count += (SAVE_DIRECT_SIZE + count);
+                }
+                restore_count += (1 + count);
+        }
+        info->ptr = ptr;
+        info->save_count = save_count;
+        info->restore_count = restore_count;
+}
+static void __init setup_save_ram_nasty(struct save_info *info, unsigned words,
+                                        unsigned cmd_reg, unsigned data_reg)
+{
+        u32 *ptr = info->ptr;
+        unsigned int save_count = info->save_count;
+        unsigned int restore_count = info->restore_count;
+        unsigned i;
+        if (ptr) {
+                save_set_ram_cmd(ptr, cmd_reg, words);
+                ptr += SAVE_SET_RAM_CMD_SIZE;
+                for (i = words; i; --i) {
+                        save_read_ram_data_nasty(ptr, data_reg);
+                        ptr += SAVE_READ_RAM_DATA_NASTY_SIZE;
+                }
+        }
+        save_count += SAVE_SET_RAM_CMD_SIZE;
+        save_count += words * SAVE_READ_RAM_DATA_NASTY_SIZE;
+        restore_count += (RESTORE_RAM_SIZE + words);
+        info->ptr = ptr;
+        info->save_count = save_count;
+        info->restore_count = restore_count;
+}
+static void __init setup_save(struct host1x_hwctx_handler *h, u32 *ptr)
+{
+        struct save_info info = {
+                ptr,
+                SAVE_BEGIN_SIZE,
+                RESTORE_BEGIN_SIZE
+        };
+        if (info.ptr) {
+                save_begin(h, info.ptr);
+                info.ptr += SAVE_BEGIN_SIZE;
+        }
+        setup_save_regs(&info, ctxsave_regs_mpe,
+                        ARRAY_SIZE(ctxsave_regs_mpe));
+        setup_save_ram_nasty(&info, RC_RAM_SIZE,
+                        RC_RAM_READ_CMD, RC_RAM_READ_DATA);
+        setup_save_ram_nasty(&info, IRFR_RAM_SIZE,
+                        IRFR_RAM_READ_CMD, IRFR_RAM_READ_DATA);
+        if (info.ptr) {
+                save_end(h, info.ptr);
+                info.ptr += SAVE_END_SIZE;
+        }
+        wmb();
+        h->save_size = info.save_count + SAVE_END_SIZE;
+        restore_size = info.restore_count + RESTORE_END_SIZE;
+}
+static u32 calculate_mpe(u32 word, struct mpe_save_info *msi)
+{
+        u32 buffer_full_read = msi->in[0] & 0x01ffffff;
+        u32 byte_len = msi->in[1];
+        u32 drain = (msi->in[2] >> 2) & 0x007fffff;
+        u32 rep_frame = msi->in[3] & 0x0000ffff;
+        u32 h264_mode = (msi->in[4] >> 11) & 1;
+        int new_buffer_full;
+        if (h264_mode)
+                byte_len >>= 3;
+        new_buffer_full = buffer_full_read + byte_len - (drain * 4);
+        msi->out[0] = max(0, new_buffer_full);
+        msi->out[1] = rep_frame;
+        if (rep_frame == 0)
+                word &= 0xffff0000;
+        return word;
+}
+static u32 *save_regs(u32 *ptr, unsigned int *pending,
+                struct nvhost_channel *channel,
+                const struct hwctx_reginfo *regs,
+                unsigned int nr_regs,
+                struct mpe_save_info *msi)
+{
+        const struct hwctx_reginfo *rend = regs + nr_regs;
+        for ( ; regs != rend; ++regs) {
+                u32 count = regs->count;
+                ++ptr; /* restore incr */
+                if (regs->type == HWCTX_REGINFO_NORMAL) {
+                        host1x_drain_read_fifo(channel->aperture,
+                                                ptr, count, pending);
+                        ptr += count;
+                } else {
+                        u32 word;
+                        if (regs->type == HWCTX_REGINFO_WRITEBACK) {
+                                BUG_ON(msi->out_pos >= NR_WRITEBACKS);
+                                word = msi->out[msi->out_pos++];
+                        } else {
+                                host1x_drain_read_fifo(channel->aperture,
+                                                        &word, 1, pending);
+                                if (regs->type == HWCTX_REGINFO_STASH) {
+                                        BUG_ON(msi->in_pos >= NR_STASHES);
+                                        msi->in[msi->in_pos++] = word;
+                                } else {
+                                        word = calculate_mpe(word, msi);
+                                }
+                        }
+                        *ptr++ = word;
+                }
+        }
+        return ptr;
+}
+static u32 *save_ram(u32 *ptr, unsigned int *pending,
+                struct nvhost_channel *channel,
+                unsigned words, unsigned cmd_reg, unsigned data_reg)
+{
+        int err = 0;
+        ptr += RESTORE_RAM_SIZE;
+        err = host1x_drain_read_fifo(channel->aperture, ptr, words, pending);
+        WARN_ON(err);
+        return ptr + words;
+}
+/*** ctxmpe ***/
+static struct nvhost_hwctx *ctxmpe_alloc(struct nvhost_hwctx_handler *h,
+                struct nvhost_channel *ch)
+{
+        struct nvmap_client *nvmap = nvhost_get_host(ch->dev)->nvmap;
+        struct host1x_hwctx_handler *p = to_host1x_hwctx_handler(h);
+        struct host1x_hwctx *ctx;
+        ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+        if (!ctx)
+                return NULL;
+        ctx->restore = nvmap_alloc(nvmap, restore_size * 4, 32,
+                                NVMAP_HANDLE_WRITE_COMBINE, 0);
+        if (IS_ERR_OR_NULL(ctx->restore)) {
+                kfree(ctx);
+                return NULL;
+        }
+        ctx->restore_virt = nvmap_mmap(ctx->restore);
+        if (!ctx->restore_virt) {
+                nvmap_free(nvmap, ctx->restore);
+                kfree(ctx);
+                return NULL;
+        }
+        kref_init(&ctx->hwctx.ref);
+        ctx->hwctx.h = &p->h;
+        ctx->hwctx.channel = ch;
+        ctx->hwctx.valid = false;
+        ctx->save_incrs = 3;
+        ctx->save_thresh = 2;
+        ctx->restore_phys = nvmap_pin(nvmap, ctx->restore);
+        ctx->restore_size = restore_size;
+        ctx->restore_incrs = 1;
+        setup_restore(p, ctx->restore_virt);
+        return &ctx->hwctx;
+}
+static void ctxmpe_get(struct nvhost_hwctx *ctx)
+{
+        kref_get(&ctx->ref);
+}
+static void ctxmpe_free(struct kref *ref)
+{
+        struct nvhost_hwctx *nctx = container_of(ref, struct nvhost_hwctx, ref);
+        struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
+        struct nvmap_client *nvmap =
+                nvhost_get_host(nctx->channel->dev)->nvmap;
+        if (ctx->restore_virt)
+                nvmap_munmap(ctx->restore, ctx->restore_virt);
+        nvmap_unpin(nvmap, ctx->restore);
+        nvmap_free(nvmap, ctx->restore);
+        kfree(ctx);
+}
+static void ctxmpe_put(struct nvhost_hwctx *ctx)
+{
+        kref_put(&ctx->ref, ctxmpe_free);
+}
+static void ctxmpe_save_push(struct nvhost_hwctx *nctx,
+                struct nvhost_cdma *cdma)
+{
+        struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
+        struct host1x_hwctx_handler *h = host1x_hwctx_handler(ctx);
+        nvhost_cdma_push(cdma,
+                        nvhost_opcode_gather(h->save_size),
+                        h->save_phys);
+}
+static void ctxmpe_save_service(struct nvhost_hwctx *nctx)
+{
+        struct host1x_hwctx *ctx = to_host1x_hwctx(nctx);
+        struct host1x_hwctx_handler *h = host1x_hwctx_handler(ctx);
+        u32 *ptr = (u32 *)ctx->restore_virt + RESTORE_BEGIN_SIZE;
+        unsigned int pending = 0;
+        struct mpe_save_info msi;
+        msi.in_pos = 0;
+        msi.out_pos = 0;
+        ptr = save_regs(ptr, &pending, nctx->channel,
+                        ctxsave_regs_mpe, ARRAY_SIZE(ctxsave_regs_mpe), &msi);
+        ptr = save_ram(ptr, &pending, nctx->channel,
+                RC_RAM_SIZE, RC_RAM_READ_CMD, RC_RAM_READ_DATA);
+        ptr = save_ram(ptr, &pending, nctx->channel,
+                IRFR_RAM_SIZE, IRFR_RAM_READ_CMD, IRFR_RAM_READ_DATA);
+        wmb();
+        nvhost_syncpt_cpu_incr(&nvhost_get_host(nctx->channel->dev)->syncpt,
+                        h->syncpt);
+}
+struct nvhost_hwctx_handler * __init nvhost_mpe_ctxhandler_init(
+                u32 syncpt, u32 waitbase,
+                struct nvhost_channel *ch)
+{
+        struct nvmap_client *nvmap;
+        u32 *save_ptr;
+        struct host1x_hwctx_handler *p;
+        p = kmalloc(sizeof(*p), GFP_KERNEL);
+        if (!p)
+                return NULL;
+        nvmap = nvhost_get_host(ch->dev)->nvmap;
+        p->syncpt = syncpt;
+        p->waitbase = waitbase;
+        setup_save(p, NULL);
+        p->save_buf = nvmap_alloc(nvmap, p->save_size * 4, 32,
+                                NVMAP_HANDLE_WRITE_COMBINE, 0);
+        if (IS_ERR(p->save_buf)) {
+                p->save_buf = NULL;
+                return NULL;
+        }
+        save_ptr = nvmap_mmap(p->save_buf);
+        if (!save_ptr) {
+                nvmap_free(nvmap, p->save_buf);
+                p->save_buf = NULL;
+                return NULL;
+        }
+        p->save_phys = nvmap_pin(nvmap, p->save_buf);
+        setup_save(p, save_ptr);
+        p->h.alloc = ctxmpe_alloc;
+        p->h.save_push = ctxmpe_save_push;
+        p->h.save_service = ctxmpe_save_service;
+        p->h.get = ctxmpe_get;
+        p->h.put = ctxmpe_put;
+        return &p->h;
+}
+int nvhost_mpe_prepare_power_off(struct nvhost_device *dev)
+{
+        return host1x_save_context(dev, NVSYNCPT_MPE);
+}
+static int __devinit mpe_probe(struct nvhost_device *dev)
+{
+        return nvhost_client_device_init(dev);
+}
+static int __exit mpe_remove(struct nvhost_device *dev)
+{
+        /* Add clean-up */
+        return 0;
+}
+static int mpe_suspend(struct nvhost_device *dev, pm_message_t state)
+{
+        return nvhost_client_device_suspend(dev);
+}
+static int mpe_resume(struct nvhost_device *dev)
+{
+        dev_info(&dev->dev, "resuming\n");
+        return 0;
+}
+struct nvhost_device *mpe_device;
+static struct nvhost_driver mpe_driver = {
+        .probe = mpe_probe,
+        .remove = __exit_p(mpe_remove),
+#ifdef CONFIG_PM
+        .suspend = mpe_suspend,
+        .resume = mpe_resume,
+#endif
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "mpe",
+        }
+};
+static int __init mpe_init(void)
+{
+        int err;
+        mpe_device = nvhost_get_device("mpe");
+        if (!mpe_device)
+                return -ENXIO;
+        err = nvhost_device_register(mpe_device);
+        if (err)
+                return err;
+        return nvhost_driver_register(&mpe_driver);
+}
+static void __exit mpe_exit(void)
+{
+        nvhost_driver_unregister(&mpe_driver);
+}
+module_init(mpe_init);
+module_exit(mpe_exit);
diff --git a/drivers/video/tegra/host/mpe/mpe.h b/drivers/video/tegra/host/mpe/mpe.h
new file mode 100644
index 00000000000..1bc2a8a04c1
--- /dev/null
+++ b/drivers/video/tegra/host/mpe/mpe.h
@@ -0,0 +1,32 @@
+/*
+ * drivers/video/tegra/host/mpe/mpe.h
+ *
+ * Tegra Graphics Host MPE
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_MPE_MPE_H
+#define __NVHOST_MPE_MPE_H
+struct nvhost_hwctx_handler;
+struct nvhost_device;
+struct nvhost_hwctx_handler *nvhost_mpe_ctxhandler_init(
+                u32 syncpt, u32 waitbase,
+                struct nvhost_channel *ch);
+int nvhost_mpe_prepare_power_off(struct nvhost_device *dev);
+#endif
diff --git a/drivers/video/tegra/host/nvhost_acm.c b/drivers/video/tegra/host/nvhost_acm.c
new file mode 100644
index 00000000000..318f209651a
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_acm.c
@@ -0,0 +1,467 @@
+/*
+ * drivers/video/tegra/host/nvhost_acm.c
+ *
+ * Tegra Graphics Host Automatic Clock Management
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_acm.h"
+#include "dev.h"
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sched.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <mach/powergate.h>
+#include <mach/clk.h>
+#include <mach/hardware.h>
+#define ACM_SUSPEND_WAIT_FOR_IDLE_TIMEOUT (2 * HZ)
+#define POWERGATE_DELAY 10
+#define MAX_DEVID_LENGTH 16
+DEFINE_MUTEX(client_list_lock);
+struct nvhost_module_client {
+        struct list_head node;
+        unsigned long rate[NVHOST_MODULE_MAX_CLOCKS];
+        void *priv;
+};
+static void do_powergate_locked(int id)
+{
+        if (id != -1 && tegra_powergate_is_powered(id))
+                tegra_powergate_partition(id);
+}
+static void do_unpowergate_locked(int id)
+{
+        if (id != -1)
+                tegra_unpowergate_partition(id);
+}
+void nvhost_module_reset(struct nvhost_device *dev)
+{
+        dev_dbg(&dev->dev,
+                "%s: asserting %s module reset (id %d, id2 %d)\n",
+                __func__, dev->name,
+                dev->powergate_ids[0], dev->powergate_ids[1]);
+        mutex_lock(&dev->lock);
+        /* assert module and mc client reset */
+        if (dev->powergate_ids[0] != -1) {
+                tegra_powergate_mc_disable(dev->powergate_ids[0]);
+                tegra_periph_reset_assert(dev->clk[0]);
+                tegra_powergate_mc_flush(dev->powergate_ids[0]);
+        }
+        if (dev->powergate_ids[1] != -1) {
+                tegra_powergate_mc_disable(dev->powergate_ids[1]);
+                tegra_periph_reset_assert(dev->clk[1]);
+                tegra_powergate_mc_flush(dev->powergate_ids[1]);
+        }
+        udelay(POWERGATE_DELAY);
+        /* deassert reset */
+        if (dev->powergate_ids[0] != -1) {
+                tegra_powergate_mc_flush_done(dev->powergate_ids[0]);
+                tegra_periph_reset_deassert(dev->clk[0]);
+                tegra_powergate_mc_enable(dev->powergate_ids[0]);
+        }
+        if (dev->powergate_ids[1] != -1) {
+                tegra_powergate_mc_flush_done(dev->powergate_ids[1]);
+                tegra_periph_reset_deassert(dev->clk[1]);
+                tegra_powergate_mc_enable(dev->powergate_ids[1]);
+        }
+        mutex_unlock(&dev->lock);
+        dev_dbg(&dev->dev, "%s: module %s out of reset\n",
+                __func__, dev->name);
+}
+static void to_state_clockgated_locked(struct nvhost_device *dev)
+{
+        if (dev->powerstate == NVHOST_POWER_STATE_RUNNING) {
+                int i;
+                for (i = 0; i < dev->num_clks; i++)
+                        clk_disable(dev->clk[i]);
+                if (dev->dev.parent)
+                        nvhost_module_idle(to_nvhost_device(dev->dev.parent));
+        } else if (dev->powerstate == NVHOST_POWER_STATE_POWERGATED
+                        && dev->can_powergate) {
+                do_unpowergate_locked(dev->powergate_ids[0]);
+                do_unpowergate_locked(dev->powergate_ids[1]);
+        }
+        dev->powerstate = NVHOST_POWER_STATE_CLOCKGATED;
+}
+static void to_state_running_locked(struct nvhost_device *dev)
+{
+        int prev_state = dev->powerstate;
+        if (dev->powerstate == NVHOST_POWER_STATE_POWERGATED)
+                to_state_clockgated_locked(dev);
+        if (dev->powerstate == NVHOST_POWER_STATE_CLOCKGATED) {
+                int i;
+                if (dev->dev.parent)
+                        nvhost_module_busy(to_nvhost_device(dev->dev.parent));
+                for (i = 0; i < dev->num_clks; i++) {
+                        int err = clk_enable(dev->clk[i]);
+                        BUG_ON(err);
+                }
+                if (prev_state == NVHOST_POWER_STATE_POWERGATED
+                                && dev->finalize_poweron)
+                        dev->finalize_poweron(dev);
+        }
+        dev->powerstate = NVHOST_POWER_STATE_RUNNING;
+}
+/* This gets called from powergate_handler() and from module suspend.
+ * Module suspend is done for all modules, runtime power gating only
+ * for modules with can_powergate set.
+ */
+static int to_state_powergated_locked(struct nvhost_device *dev)
+{
+        int err = 0;
+        if (dev->prepare_poweroff
+                        && dev->powerstate != NVHOST_POWER_STATE_POWERGATED) {
+                /* Clock needs to be on in prepare_poweroff */
+                to_state_running_locked(dev);
+                err = dev->prepare_poweroff(dev);
+                if (err)
+                        return err;
+        }
+        if (dev->powerstate == NVHOST_POWER_STATE_RUNNING)
+                to_state_clockgated_locked(dev);
+        if (dev->can_powergate) {
+                do_powergate_locked(dev->powergate_ids[0]);
+                do_powergate_locked(dev->powergate_ids[1]);
+        }
+        dev->powerstate = NVHOST_POWER_STATE_POWERGATED;
+        return 0;
+}
+static void schedule_powergating_locked(struct nvhost_device *dev)
+{
+        if (dev->can_powergate)
+                schedule_delayed_work(&dev->powerstate_down,
+                                msecs_to_jiffies(dev->powergate_delay));
+}
+static void schedule_clockgating_locked(struct nvhost_device *dev)
+{
+        schedule_delayed_work(&dev->powerstate_down,
+                        msecs_to_jiffies(dev->clockgate_delay));
+}
+void nvhost_module_busy(struct nvhost_device *dev)
+{
+        if (dev->busy)
+                dev->busy(dev);
+        mutex_lock(&dev->lock);
+        cancel_delayed_work(&dev->powerstate_down);
+        dev->refcount++;
+        if (dev->refcount > 0 && !nvhost_module_powered(dev))
+                to_state_running_locked(dev);
+        mutex_unlock(&dev->lock);
+}
+static void powerstate_down_handler(struct work_struct *work)
+{
+        struct nvhost_device *dev;
+        dev = container_of(to_delayed_work(work),
+                        struct nvhost_device,
+                        powerstate_down);
+        mutex_lock(&dev->lock);
+        if (dev->refcount == 0) {
+                switch (dev->powerstate) {
+                case NVHOST_POWER_STATE_RUNNING:
+                        to_state_clockgated_locked(dev);
+                        schedule_powergating_locked(dev);
+                        break;
+                case NVHOST_POWER_STATE_CLOCKGATED:
+                        if (to_state_powergated_locked(dev))
+                                schedule_powergating_locked(dev);
+                        break;
+                default:
+                        break;
+                }
+        }
+        mutex_unlock(&dev->lock);
+}
+void nvhost_module_idle_mult(struct nvhost_device *dev, int refs)
+{
+        bool kick = false;
+        mutex_lock(&dev->lock);
+        dev->refcount -= refs;
+        if (dev->refcount == 0) {
+                if (nvhost_module_powered(dev))
+                        schedule_clockgating_locked(dev);
+                kick = true;
+        }
+        mutex_unlock(&dev->lock);
+        if (kick) {
+                wake_up(&dev->idle_wq);
+                if (dev->idle)
+                        dev->idle(dev);
+        }
+}
+int nvhost_module_get_rate(struct nvhost_device *dev, unsigned long *rate,
+                int index)
+{
+        struct clk *c;
+        c = dev->clk[index];
+        if (IS_ERR_OR_NULL(c))
+                return -EINVAL;
+        /* Need to enable client to get correct rate */
+        nvhost_module_busy(dev);
+        *rate = clk_get_rate(c);
+        nvhost_module_idle(dev);
+        return 0;
+}
+static int nvhost_module_update_rate(struct nvhost_device *dev, int index)
+{
+        unsigned long rate = 0;
+        struct nvhost_module_client *m;
+        if (!dev->clk[index])
+                return -EINVAL;
+        list_for_each_entry(m, &dev->client_list, node) {
+                rate = max(m->rate[index], rate);
+        }
+        if (!rate)
+                rate = clk_round_rate(dev->clk[index],
+                                dev->clocks[index].default_rate);
+        return clk_set_rate(dev->clk[index], rate);
+}
+int nvhost_module_set_rate(struct nvhost_device *dev, void *priv,
+                unsigned long rate, int index)
+{
+        struct nvhost_module_client *m;
+        int i, ret = 0;
+        mutex_lock(&client_list_lock);
+        list_for_each_entry(m, &dev->client_list, node) {
+                if (m->priv == priv) {
+                        for (i = 0; i < dev->num_clks; i++)
+                                m->rate[i] = clk_round_rate(dev->clk[i], rate);
+                        break;
+                }
+        }
+        for (i = 0; i < dev->num_clks; i++) {
+                ret = nvhost_module_update_rate(dev, i);
+                if (ret < 0)
+                        break;
+        }
+        mutex_unlock(&client_list_lock);
+        return ret;
+}
+int nvhost_module_add_client(struct nvhost_device *dev, void *priv)
+{
+        int i;
+        unsigned long rate;
+        struct nvhost_module_client *client;
+        client = kzalloc(sizeof(*client), GFP_KERNEL);
+        if (!client)
+                return -ENOMEM;
+        INIT_LIST_HEAD(&client->node);
+        client->priv = priv;
+        for (i = 0; i < dev->num_clks; i++) {
+                rate = clk_round_rate(dev->clk[i],
+                                dev->clocks[i].default_rate);
+                client->rate[i] = rate;
+        }
+        mutex_lock(&client_list_lock);
+        list_add_tail(&client->node, &dev->client_list);
+        mutex_unlock(&client_list_lock);
+        return 0;
+}
+void nvhost_module_remove_client(struct nvhost_device *dev, void *priv)
+{
+        int i;
+        struct nvhost_module_client *m;
+        mutex_lock(&client_list_lock);
+        list_for_each_entry(m, &dev->client_list, node) {
+                if (priv == m->priv) {
+                        list_del(&m->node);
+                        break;
+                }
+        }
+        if (m) {
+                kfree(m);
+                for (i = 0; i < dev->num_clks; i++)
+                        nvhost_module_update_rate(dev, i);
+        }
+        mutex_unlock(&client_list_lock);
+}
+int nvhost_module_init(struct nvhost_device *dev)
+{
+        int i = 0;
+        /* initialize clocks to known state */
+        INIT_LIST_HEAD(&dev->client_list);
+        while (dev->clocks[i].name && i < NVHOST_MODULE_MAX_CLOCKS) {
+                char devname[MAX_DEVID_LENGTH];
+                long rate = dev->clocks[i].default_rate;
+                struct clk *c;
+                snprintf(devname, MAX_DEVID_LENGTH, "tegra_%s", dev->name);
+                c = clk_get_sys(devname, dev->clocks[i].name);
+                BUG_ON(IS_ERR_OR_NULL(c));
+                rate = clk_round_rate(c, rate);
+                clk_enable(c);
+                clk_set_rate(c, rate);
+                clk_disable(c);
+                dev->clk[i] = c;
+                i++;
+        }
+        dev->num_clks = i;
+        mutex_init(&dev->lock);
+        init_waitqueue_head(&dev->idle_wq);
+        INIT_DELAYED_WORK(&dev->powerstate_down, powerstate_down_handler);
+        /* power gate units that we can power gate */
+        if (dev->can_powergate) {
+                do_powergate_locked(dev->powergate_ids[0]);
+                do_powergate_locked(dev->powergate_ids[1]);
+                dev->powerstate = NVHOST_POWER_STATE_POWERGATED;
+        } else {
+                do_unpowergate_locked(dev->powergate_ids[0]);
+                do_unpowergate_locked(dev->powergate_ids[1]);
+                dev->powerstate = NVHOST_POWER_STATE_CLOCKGATED;
+        }
+        return 0;
+}
+static int is_module_idle(struct nvhost_device *dev)
+{
+        int count;
+        mutex_lock(&dev->lock);
+        count = dev->refcount;
+        mutex_unlock(&dev->lock);
+        return (count == 0);
+}
+static void debug_not_idle(struct nvhost_master *host)
+{
+        int i;
+        bool lock_released = true;
+        for (i = 0; i < host->nb_channels; i++) {
+                struct nvhost_device *dev = host->channels[i].dev;
+                mutex_lock(&dev->lock);
+                if (dev->name)
+                        dev_warn(&host->dev->dev,
+                                "tegra_grhost: %s: refcnt %d\n", dev->name,
+                                dev->refcount);
+                mutex_unlock(&dev->lock);
+        }
+        for (i = 0; i < host->syncpt.nb_mlocks; i++) {
+                int c = atomic_read(&host->syncpt.lock_counts[i]);
+                if (c) {
+                        dev_warn(&host->dev->dev,
+                                "tegra_grhost: lock id %d: refcnt %d\n",
+                                i, c);
+                        lock_released = false;
+                }
+        }
+        if (lock_released)
+                dev_dbg(&host->dev->dev, "tegra_grhost: all locks released\n");
+}
+int nvhost_module_suspend(struct nvhost_device *dev, bool system_suspend)
+{
+        int ret;
+        struct nvhost_master *host = nvhost_get_host(dev);
+        if (system_suspend && !is_module_idle(dev))
+                debug_not_idle(host);
+        ret = wait_event_timeout(dev->idle_wq, is_module_idle(dev),
+                        ACM_SUSPEND_WAIT_FOR_IDLE_TIMEOUT);
+        if (ret == 0) {
+                dev_info(&dev->dev, "%s prevented suspend\n",
+                                dev->name);
+                return -EBUSY;
+        }
+        if (system_suspend)
+                dev_dbg(&dev->dev, "tegra_grhost: entered idle\n");
+        mutex_lock(&dev->lock);
+        cancel_delayed_work(&dev->powerstate_down);
+        to_state_powergated_locked(dev);
+        mutex_unlock(&dev->lock);
+        if (dev->suspend)
+                dev->suspend(dev);
+        return 0;
+}
+void nvhost_module_deinit(struct nvhost_device *dev)
+{
+        int i;
+        if (dev->deinit)
+                dev->deinit(dev);
+        nvhost_module_suspend(dev, false);
+        for (i = 0; i < dev->num_clks; i++)
+                clk_put(dev->clk[i]);
+        dev->powerstate = NVHOST_POWER_STATE_DEINIT;
+}
diff --git a/drivers/video/tegra/host/nvhost_acm.h b/drivers/video/tegra/host/nvhost_acm.h
new file mode 100644
index 00000000000..a12c0c3fa32
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_acm.h
@@ -0,0 +1,60 @@
+/*
+ * drivers/video/tegra/host/nvhost_acm.h
+ *
+ * Tegra Graphics Host Automatic Clock Management
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_ACM_H
+#define __NVHOST_ACM_H
+#include <linux/workqueue.h>
+#include <linux/wait.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/nvhost.h>
+/* Sets clocks and powergating state for a module */
+int nvhost_module_init(struct nvhost_device *ndev);
+void nvhost_module_deinit(struct nvhost_device *dev);
+int nvhost_module_suspend(struct nvhost_device *dev, bool system_suspend);
+void nvhost_module_reset(struct nvhost_device *dev);
+void nvhost_module_busy(struct nvhost_device *dev);
+void nvhost_module_idle_mult(struct nvhost_device *dev, int refs);
+int nvhost_module_add_client(struct nvhost_device *dev,
+                void *priv);
+void nvhost_module_remove_client(struct nvhost_device *dev,
+                void *priv);
+int nvhost_module_get_rate(struct nvhost_device *dev,
+                unsigned long *rate,
+                int index);
+int nvhost_module_set_rate(struct nvhost_device *dev, void *priv,
+                unsigned long rate, int index);
+static inline bool nvhost_module_powered(struct nvhost_device *dev)
+{
+        return dev->powerstate == NVHOST_POWER_STATE_RUNNING;
+}
+static inline void nvhost_module_idle(struct nvhost_device *dev)
+{
+        nvhost_module_idle_mult(dev, 1);
+}
+#endif
diff --git a/drivers/video/tegra/host/nvhost_cdma.c b/drivers/video/tegra/host/nvhost_cdma.c
new file mode 100644
index 00000000000..775d761e65c
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_cdma.c
@@ -0,0 +1,508 @@
+/*
+ * drivers/video/tegra/host/nvhost_cdma.c
+ *
+ * Tegra Graphics Host Command DMA
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_cdma.h"
+#include "dev.h"
+#include <asm/cacheflush.h>
+#include <linux/slab.h>
+#include <linux/kfifo.h>
+#include <trace/events/nvhost.h>
+#include <linux/interrupt.h>
+/*
+ * TODO:
+ *   stats
+ *     - for figuring out what to optimize further
+ *   resizable push buffer
+ *     - some channels hardly need any, some channels (3d) could use more
+ */
+/**
+ * Add an entry to the sync queue.
+ */
+static void add_to_sync_queue(struct nvhost_cdma *cdma,
+                              struct nvhost_job *job,
+                              u32 nr_slots,
+                              u32 first_get)
+{
+        BUG_ON(job->syncpt_id == NVSYNCPT_INVALID);
+        job->first_get = first_get;
+        job->num_slots = nr_slots;
+        nvhost_job_get(job);
+        list_add_tail(&job->list, &cdma->sync_queue);
+}
+/**
+ * Return the status of the cdma's sync queue or push buffer for the given event
+ *  - sq empty: returns 1 for empty, 0 for not empty (as in "1 empty queue" :-)
+ *  - pb space: returns the number of free slots in the channel's push buffer
+ * Must be called with the cdma lock held.
+ */
+static unsigned int cdma_status_locked(struct nvhost_cdma *cdma,
+                enum cdma_event event)
+{
+        switch (event) {
+        case CDMA_EVENT_SYNC_QUEUE_EMPTY:
+                return list_empty(&cdma->sync_queue) ? 1 : 0;
+        case CDMA_EVENT_PUSH_BUFFER_SPACE: {
+                struct push_buffer *pb = &cdma->push_buffer;
+                BUG_ON(!cdma_pb_op(cdma).space);
+                return cdma_pb_op(cdma).space(pb);
+        }
+        default:
+                return 0;
+        }
+}
+/**
+ * Sleep (if necessary) until the requested event happens
+ *   - CDMA_EVENT_SYNC_QUEUE_EMPTY : sync queue is completely empty.
+ *     - Returns 1
+ *   - CDMA_EVENT_PUSH_BUFFER_SPACE : there is space in the push buffer
+ *     - Return the amount of space (> 0)
+ * Must be called with the cdma lock held.
+ */
+unsigned int nvhost_cdma_wait_locked(struct nvhost_cdma *cdma,
+                enum cdma_event event)
+{
+        for (;;) {
+                unsigned int space = cdma_status_locked(cdma, event);
+                if (space)
+                        return space;
+                trace_nvhost_wait_cdma(cdma_to_channel(cdma)->dev->name,
+                                event);
+                BUG_ON(cdma->event != CDMA_EVENT_NONE);
+                cdma->event = event;
+                mutex_unlock(&cdma->lock);
+                down(&cdma->sem);
+                mutex_lock(&cdma->lock);
+        }
+        return 0;
+}
+/**
+ * Start timer for a buffer submition that has completed yet.
+ * Must be called with the cdma lock held.
+ */
+static void cdma_start_timer_locked(struct nvhost_cdma *cdma,
+                struct nvhost_job *job)
+{
+        BUG_ON(!job);
+        if (cdma->timeout.clientid) {
+                /* timer already started */
+                return;
+        }
+        cdma->timeout.ctx = job->hwctx;
+        cdma->timeout.clientid = job->clientid;
+        cdma->timeout.syncpt_id = job->syncpt_id;
+        cdma->timeout.syncpt_val = job->syncpt_end;
+        cdma->timeout.start_ktime = ktime_get();
+        schedule_delayed_work(&cdma->timeout.wq,
+                        msecs_to_jiffies(job->timeout));
+}
+/**
+ * Stop timer when a buffer submition completes.
+ * Must be called with the cdma lock held.
+ */
+static void stop_cdma_timer_locked(struct nvhost_cdma *cdma)
+{
+        cancel_delayed_work(&cdma->timeout.wq);
+        cdma->timeout.ctx = NULL;
+        cdma->timeout.clientid = 0;
+}
+/**
+ * For all sync queue entries that have already finished according to the
+ * current sync point registers:
+ *  - unpin & unref their mems
+ *  - pop their push buffer slots
+ *  - remove them from the sync queue
+ * This is normally called from the host code's worker thread, but can be
+ * called manually if necessary.
+ * Must be called with the cdma lock held.
+ */
+static void update_cdma_locked(struct nvhost_cdma *cdma)
+{
+        bool signal = false;
+        struct nvhost_master *dev = cdma_to_dev(cdma);
+        struct nvhost_syncpt *sp = &dev->syncpt;
+        struct nvhost_job *job, *n;
+        BUG_ON(!cdma->running);
+        /*
+         * Walk the sync queue, reading the sync point registers as necessary,
+         * to consume as many sync queue entries as possible without blocking
+         */
+        list_for_each_entry_safe(job, n, &cdma->sync_queue, list) {
+                BUG_ON(job->syncpt_id == NVSYNCPT_INVALID);
+                /* Check whether this syncpt has completed, and bail if not */
+                if (!nvhost_syncpt_is_expired(sp,
+                                job->syncpt_id, job->syncpt_end)) {
+                        /* Start timer on next pending syncpt */
+                        if (job->timeout)
+                                cdma_start_timer_locked(cdma, job);
+                        break;
+                }
+                /* Cancel timeout, when a buffer completes */
+                if (cdma->timeout.clientid)
+                        stop_cdma_timer_locked(cdma);
+                /* Unpin the memory */
+                nvhost_job_unpin(job);
+                /* Pop push buffer slots */
+                if (job->num_slots) {
+                        struct push_buffer *pb = &cdma->push_buffer;
+                        BUG_ON(!cdma_pb_op(cdma).pop_from);
+                        cdma_pb_op(cdma).pop_from(pb, job->num_slots);
+                        if (cdma->event == CDMA_EVENT_PUSH_BUFFER_SPACE)
+                                signal = true;
+                }
+                list_del(&job->list);
+                nvhost_job_put(job);
+        }
+        if (list_empty(&cdma->sync_queue) &&
+                                cdma->event == CDMA_EVENT_SYNC_QUEUE_EMPTY)
+                        signal = true;
+        /* Wake up CdmaWait() if the requested event happened */
+        if (signal) {
+                cdma->event = CDMA_EVENT_NONE;
+                up(&cdma->sem);
+        }
+}
+void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
+                struct nvhost_syncpt *syncpt, struct device *dev)
+{
+        u32 get_restart;
+        u32 syncpt_incrs;
+        bool exec_ctxsave;
+        struct nvhost_job *job = NULL;
+        u32 syncpt_val;
+        syncpt_val = nvhost_syncpt_update_min(syncpt, cdma->timeout.syncpt_id);
+        dev_dbg(dev,
+                "%s: starting cleanup (thresh %d)\n",
+                __func__, syncpt_val);
+        /*
+         * Move the sync_queue read pointer to the first entry that hasn't
+         * completed based on the current HW syncpt value. It's likely there
+         * won't be any (i.e. we're still at the head), but covers the case
+         * where a syncpt incr happens just prior/during the teardown.
+         */
+        dev_dbg(dev,
+                "%s: skip completed buffers still in sync_queue\n",
+                __func__);
+        list_for_each_entry(job, &cdma->sync_queue, list) {
+                if (syncpt_val < job->syncpt_end)
+                        break;
+                nvhost_job_dump(dev, job);
+        }
+        /*
+         * Walk the sync_queue, first incrementing with the CPU syncpts that
+         * are partially executed (the first buffer) or fully skipped while
+         * still in the current context (slots are also NOP-ed).
+         *
+         * At the point contexts are interleaved, syncpt increments must be
+         * done inline with the pushbuffer from a GATHER buffer to maintain
+         * the order (slots are modified to be a GATHER of syncpt incrs).
+         *
+         * Note: save in get_restart the location where the timed out buffer
+         * started in the PB, so we can start the refetch from there (with the
+         * modified NOP-ed PB slots). This lets things appear to have completed
+         * properly for this buffer and resources are freed.
+         */
+        dev_dbg(dev,
+                "%s: perform CPU incr on pending same ctx buffers\n",
+                __func__);
+        get_restart = cdma->last_put;
+        if (!list_empty(&cdma->sync_queue))
+                get_restart = job->first_get;
+        /* do CPU increments as long as this context continues */
+        list_for_each_entry_from(job, &cdma->sync_queue, list) {
+                /* different context, gets us out of this loop */
+                if (job->clientid != cdma->timeout.clientid)
+                        break;
+                /* won't need a timeout when replayed */
+                job->timeout = 0;
+                syncpt_incrs = job->syncpt_end - syncpt_val;
+                dev_dbg(dev,
+                        "%s: CPU incr (%d)\n", __func__, syncpt_incrs);
+                nvhost_job_dump(dev, job);
+                /* safe to use CPU to incr syncpts */
+                cdma_op(cdma).timeout_cpu_incr(cdma,
+                                job->first_get,
+                                syncpt_incrs,
+                                job->syncpt_end,
+                                job->num_slots);
+                syncpt_val += syncpt_incrs;
+        }
+        dev_dbg(dev,
+                "%s: GPU incr blocked interleaved ctx buffers\n",
+                __func__);
+        exec_ctxsave = false;
+        /* setup GPU increments */
+        list_for_each_entry_from(job, &cdma->sync_queue, list) {
+                /* same context, increment in the pushbuffer */
+                if (job->clientid == cdma->timeout.clientid) {
+                        /* won't need a timeout when replayed */
+                        job->timeout = 0;
+                        /* update buffer's syncpts in the pushbuffer */
+                        cdma_op(cdma).timeout_pb_incr(cdma,
+                                        job->first_get,
+                                        job->syncpt_incrs,
+                                        job->num_slots,
+                                        exec_ctxsave);
+                        exec_ctxsave = false;
+                } else {
+                        dev_dbg(dev,
+                                "%s: switch to a different userctx\n",
+                                __func__);
+                        /*
+                         * If previous context was the timed out context
+                         * then clear its CTXSAVE in this slot.
+                         */
+                        exec_ctxsave = true;
+                }
+                nvhost_job_dump(dev, job);
+        }
+        dev_dbg(dev,
+                "%s: finished sync_queue modification\n", __func__);
+        /* roll back DMAGET and start up channel again */
+        cdma_op(cdma).timeout_teardown_end(cdma, get_restart);
+        if (cdma->timeout.ctx)
+                cdma->timeout.ctx->has_timedout = true;
+}
+/**
+ * Create a cdma
+ */
+int nvhost_cdma_init(struct nvhost_cdma *cdma)
+{
+        int err;
+        struct push_buffer *pb = &cdma->push_buffer;
+        BUG_ON(!cdma_pb_op(cdma).init);
+        mutex_init(&cdma->lock);
+        sema_init(&cdma->sem, 0);
+        INIT_LIST_HEAD(&cdma->sync_queue);
+        cdma->event = CDMA_EVENT_NONE;
+        cdma->running = false;
+        cdma->torndown = false;
+        err = cdma_pb_op(cdma).init(pb);
+        if (err)
+                return err;
+        return 0;
+}
+/**
+ * Destroy a cdma
+ */
+void nvhost_cdma_deinit(struct nvhost_cdma *cdma)
+{
+        struct push_buffer *pb = &cdma->push_buffer;
+        BUG_ON(!cdma_pb_op(cdma).destroy);
+        BUG_ON(cdma->running);
+        cdma_pb_op(cdma).destroy(pb);
+        cdma_op(cdma).timeout_destroy(cdma);
+}
+/**
+ * Begin a cdma submit
+ */
+int nvhost_cdma_begin(struct nvhost_cdma *cdma, struct nvhost_job *job)
+{
+        mutex_lock(&cdma->lock);
+        if (job->timeout) {
+                /* init state on first submit with timeout value */
+                if (!cdma->timeout.initialized) {
+                        int err;
+                        BUG_ON(!cdma_op(cdma).timeout_init);
+                        err = cdma_op(cdma).timeout_init(cdma,
+                                job->syncpt_id);
+                        if (err) {
+                                mutex_unlock(&cdma->lock);
+                                return err;
+                        }
+                }
+        }
+        if (!cdma->running) {
+                BUG_ON(!cdma_op(cdma).start);
+                cdma_op(cdma).start(cdma);
+        }
+        cdma->slots_free = 0;
+        cdma->slots_used = 0;
+        cdma->first_get = cdma_pb_op(cdma).putptr(&cdma->push_buffer);
+        return 0;
+}
+/**
+ * Push two words into a push buffer slot
+ * Blocks as necessary if the push buffer is full.
+ */
+void nvhost_cdma_push(struct nvhost_cdma *cdma, u32 op1, u32 op2)
+{
+        nvhost_cdma_push_gather(cdma, NULL, NULL, op1, op2);
+}
+/**
+ * Push two words into a push buffer slot
+ * Blocks as necessary if the push buffer is full.
+ */
+void nvhost_cdma_push_gather(struct nvhost_cdma *cdma,
+                struct nvmap_client *client,
+                struct nvmap_handle *handle, u32 op1, u32 op2)
+{
+        u32 slots_free = cdma->slots_free;
+        struct push_buffer *pb = &cdma->push_buffer;
+        BUG_ON(!cdma_pb_op(cdma).push_to);
+        BUG_ON(!cdma_op(cdma).kick);
+        if (slots_free == 0) {
+                cdma_op(cdma).kick(cdma);
+                slots_free = nvhost_cdma_wait_locked(cdma,
+                                CDMA_EVENT_PUSH_BUFFER_SPACE);
+        }
+        cdma->slots_free = slots_free - 1;
+        cdma->slots_used++;
+        cdma_pb_op(cdma).push_to(pb, client, handle, op1, op2);
+}
+/**
+ * End a cdma submit
+ * Kick off DMA, add job to the sync queue, and a number of slots to be freed
+ * from the pushbuffer. The handles for a submit must all be pinned at the same
+ * time, but they can be unpinned in smaller chunks.
+ */
+void nvhost_cdma_end(struct nvhost_cdma *cdma,
+                struct nvhost_job *job)
+{
+        bool was_idle = list_empty(&cdma->sync_queue);
+        BUG_ON(!cdma_op(cdma).kick);
+        cdma_op(cdma).kick(cdma);
+        BUG_ON(job->syncpt_id == NVSYNCPT_INVALID);
+        add_to_sync_queue(cdma,
+                        job,
+                        cdma->slots_used,
+                        cdma->first_get);
+        /* start timer on idle -> active transitions */
+        if (job->timeout && was_idle)
+                cdma_start_timer_locked(cdma, job);
+        mutex_unlock(&cdma->lock);
+}
+/**
+ * Update cdma state according to current sync point values
+ */
+void nvhost_cdma_update(struct nvhost_cdma *cdma)
+{
+        mutex_lock(&cdma->lock);
+        update_cdma_locked(cdma);
+        mutex_unlock(&cdma->lock);
+}
+/**
+ * Wait for push buffer to be empty.
+ * @cdma pointer to channel cdma
+ * @timeout timeout in ms
+ * Returns -ETIME if timeout was reached, zero if push buffer is empty.
+ */
+int nvhost_cdma_flush(struct nvhost_cdma *cdma, int timeout)
+{
+        unsigned int space, err = 0;
+        unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+        /*
+         * Wait for at most timeout ms. Recalculate timeout at each iteration
+         * to better keep within given timeout.
+         */
+        while(!err && time_before(jiffies, end_jiffies)) {
+                int timeout_jiffies = end_jiffies - jiffies;
+                mutex_lock(&cdma->lock);
+                space = cdma_status_locked(cdma,
+                                CDMA_EVENT_SYNC_QUEUE_EMPTY);
+                if (space) {
+                        mutex_unlock(&cdma->lock);
+                        return 0;
+                }
+                /*
+                 * Wait for sync queue to become empty. If there is already
+                 * an event pending, we need to poll.
+                 */
+                if (cdma->event != CDMA_EVENT_NONE) {
+                        mutex_unlock(&cdma->lock);
+                        schedule();
+                } else {
+                        cdma->event = CDMA_EVENT_SYNC_QUEUE_EMPTY;
+                        mutex_unlock(&cdma->lock);
+                        err = down_timeout(&cdma->sem,
+                                        jiffies_to_msecs(timeout_jiffies));
+                }
+        }
+        return err;
+}
diff --git a/drivers/video/tegra/host/nvhost_cdma.h b/drivers/video/tegra/host/nvhost_cdma.h
new file mode 100644
index 00000000000..9cb9b827725
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_cdma.h
@@ -0,0 +1,133 @@
+/*
+ * drivers/video/tegra/host/nvhost_cdma.h
+ *
+ * Tegra Graphics Host Command DMA
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_CDMA_H
+#define __NVHOST_CDMA_H
+#include <linux/sched.h>
+#include <linux/semaphore.h>
+#include <linux/nvhost.h>
+#include <mach/nvmap.h>
+#include <linux/list.h>
+#include "nvhost_acm.h"
+struct nvhost_syncpt;
+struct nvhost_userctx_timeout;
+struct nvhost_job;
+/*
+ * cdma
+ *
+ * This is in charge of a host command DMA channel.
+ * Sends ops to a push buffer, and takes responsibility for unpinning
+ * (& possibly freeing) of memory after those ops have completed.
+ * Producer:
+ *      begin
+ *              push - send ops to the push buffer
+ *      end - start command DMA and enqueue handles to be unpinned
+ * Consumer:
+ *      update - call to update sync queue and push buffer, unpin memory
+ */
+struct nvmap_client_handle {
+        struct nvmap_client *client;
+        struct nvmap_handle *handle;
+};
+struct push_buffer {
+        struct nvmap_handle_ref *mem;   /* handle to pushbuffer memory */
+        u32 *mapped;                    /* mapped pushbuffer memory */
+        u32 phys;                       /* physical address of pushbuffer */
+        u32 fence;                      /* index we've written */
+        u32 cur;                        /* index to write to */
+        struct nvmap_client_handle *nvmap;
+                                        /* nvmap handle for each opcode pair */
+};
+struct syncpt_buffer {
+        struct nvmap_handle_ref *mem; /* handle to pushbuffer memory */
+        u32 *mapped;            /* mapped gather buffer (at channel offset */
+        u32 phys;               /* physical address (at channel offset) */
+        u32 incr_per_buffer;    /* max # of incrs per GATHER */
+        u32 words_per_incr;     /* # of DWORDS in buffer to incr a syncpt */
+};
+struct buffer_timeout {
+        struct delayed_work wq;         /* work queue */
+        bool initialized;               /* timer one-time setup flag */
+        u32 syncpt_id;                  /* buffer completion syncpt id */
+        u32 syncpt_val;                 /* syncpt value when completed */
+        ktime_t start_ktime;            /* starting time */
+        /* context timeout information */
+        struct nvhost_hwctx *ctx;
+        int clientid;
+};
+enum cdma_event {
+        CDMA_EVENT_NONE,                /* not waiting for any event */
+        CDMA_EVENT_SYNC_QUEUE_EMPTY,    /* wait for empty sync queue */
+        CDMA_EVENT_PUSH_BUFFER_SPACE    /* wait for space in push buffer */
+};
+struct nvhost_cdma {
+        struct mutex lock;              /* controls access to shared state */
+        struct semaphore sem;           /* signalled when event occurs */
+        enum cdma_event event;          /* event that sem is waiting for */
+        unsigned int slots_used;        /* pb slots used in current submit */
+        unsigned int slots_free;        /* pb slots free in current submit */
+        unsigned int first_get;         /* DMAGET value, where submit begins */
+        unsigned int last_put;          /* last value written to DMAPUT */
+        struct push_buffer push_buffer; /* channel's push buffer */
+        struct syncpt_buffer syncpt_buffer; /* syncpt incr buffer */
+        struct list_head sync_queue;    /* job queue */
+        struct buffer_timeout timeout;  /* channel's timeout state/wq */
+        bool running;
+        bool torndown;
+};
+#define cdma_to_channel(cdma) container_of(cdma, struct nvhost_channel, cdma)
+#define cdma_to_dev(cdma) nvhost_get_host(cdma_to_channel(cdma)->dev)
+#define cdma_op(cdma) (cdma_to_dev(cdma)->op.cdma)
+#define cdma_to_nvmap(cdma) ((cdma_to_dev(cdma))->nvmap)
+#define pb_to_cdma(pb) container_of(pb, struct nvhost_cdma, push_buffer)
+#define cdma_pb_op(cdma) (cdma_to_dev(cdma)->op.push_buffer)
+int     nvhost_cdma_init(struct nvhost_cdma *cdma);
+void    nvhost_cdma_deinit(struct nvhost_cdma *cdma);
+void    nvhost_cdma_stop(struct nvhost_cdma *cdma);
+int     nvhost_cdma_begin(struct nvhost_cdma *cdma, struct nvhost_job *job);
+void    nvhost_cdma_push(struct nvhost_cdma *cdma, u32 op1, u32 op2);
+#define NVHOST_CDMA_PUSH_GATHER_CTXSAVE 0xffffffff
+void    nvhost_cdma_push_gather(struct nvhost_cdma *cdma,
+                struct nvmap_client *client,
+                struct nvmap_handle *handle, u32 op1, u32 op2);
+void    nvhost_cdma_end(struct nvhost_cdma *cdma,
+                struct nvhost_job *job);
+void    nvhost_cdma_update(struct nvhost_cdma *cdma);
+int     nvhost_cdma_flush(struct nvhost_cdma *cdma, int timeout);
+void    nvhost_cdma_peek(struct nvhost_cdma *cdma,
+                u32 dmaget, int slot, u32 *out);
+unsigned int nvhost_cdma_wait_locked(struct nvhost_cdma *cdma,
+                enum cdma_event event);
+void nvhost_cdma_update_sync_queue(struct nvhost_cdma *cdma,
+                struct nvhost_syncpt *syncpt, struct device *dev);
+#endif
diff --git a/drivers/video/tegra/host/nvhost_channel.c b/drivers/video/tegra/host/nvhost_channel.c
new file mode 100644
index 00000000000..a7c03308134
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_channel.c
@@ -0,0 +1,158 @@
+/*
+ * drivers/video/tegra/host/nvhost_channel.c
+ *
+ * Tegra Graphics Host Channel
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_channel.h"
+#include "dev.h"
+#include "nvhost_job.h"
+#include <trace/events/nvhost.h>
+#include <linux/nvhost_ioctl.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#define NVHOST_CHANNEL_LOW_PRIO_MAX_WAIT 50
+int nvhost_channel_init(struct nvhost_channel *ch,
+                struct nvhost_master *dev, int index)
+{
+        int err;
+        struct nvhost_device *ndev;
+        struct resource *r = NULL;
+        void __iomem *regs = NULL;
+        struct resource *reg_mem = NULL;
+        /* Link nvhost_device to nvhost_channel */
+        err = host_channel_op(dev).init(ch, dev, index);
+        if (err < 0) {
+                dev_err(&dev->dev->dev, "failed to init channel %d\n",
+                                index);
+                return err;
+        }
+        ndev = ch->dev;
+        ndev->channel = ch;
+        /* Map IO memory related to nvhost_device */
+        if (ndev->moduleid != NVHOST_MODULE_NONE) {
+                /* First one is host1x - skip that */
+                r = nvhost_get_resource(dev->dev,
+                                IORESOURCE_MEM, ndev->moduleid + 1);
+                if (!r)
+                        goto fail;
+                reg_mem = request_mem_region(r->start,
+                                resource_size(r), ndev->name);
+                if (!reg_mem)
+                        goto fail;
+                regs = ioremap(r->start, resource_size(r));
+                if (!regs)
+                        goto fail;
+                ndev->reg_mem = reg_mem;
+                ndev->aperture = regs;
+        }
+        return 0;
+fail:
+        if (reg_mem)
+                release_mem_region(r->start, resource_size(r));
+        if (regs)
+                iounmap(regs);
+        dev_err(&ndev->dev, "failed to get register memory\n");
+        return -ENXIO;
+}
+int nvhost_channel_submit(struct nvhost_job *job)
+{
+        /* Low priority submits wait until sync queue is empty. Ignores result
+         * from nvhost_cdma_flush, as we submit either when push buffer is
+         * empty or when we reach the timeout. */
+        if (job->priority < NVHOST_PRIORITY_MEDIUM)
+                (void)nvhost_cdma_flush(&job->ch->cdma,
+                                NVHOST_CHANNEL_LOW_PRIO_MAX_WAIT);
+        return channel_op(job->ch).submit(job);
+}
+struct nvhost_channel *nvhost_getchannel(struct nvhost_channel *ch)
+{
+        int err = 0;
+        mutex_lock(&ch->reflock);
+        if (ch->refcount == 0) {
+                if (ch->dev->init)
+                        ch->dev->init(ch->dev);
+                err = nvhost_cdma_init(&ch->cdma);
+        } else if (ch->dev->exclusive) {
+                err = -EBUSY;
+        }
+        if (!err)
+                ch->refcount++;
+        mutex_unlock(&ch->reflock);
+        /* Keep alive modules that needs to be when a channel is open */
+        if (!err && ch->dev->keepalive)
+                nvhost_module_busy(ch->dev);
+        return err ? NULL : ch;
+}
+void nvhost_putchannel(struct nvhost_channel *ch, struct nvhost_hwctx *ctx)
+{
+        BUG_ON(!channel_cdma_op(ch).stop);
+        if (ctx) {
+                mutex_lock(&ch->submitlock);
+                if (ch->cur_ctx == ctx)
+                        ch->cur_ctx = NULL;
+                mutex_unlock(&ch->submitlock);
+        }
+        /* Allow keep-alive'd module to be turned off */
+        if (ch->dev->keepalive)
+                nvhost_module_idle(ch->dev);
+        mutex_lock(&ch->reflock);
+        if (ch->refcount == 1) {
+                channel_cdma_op(ch).stop(&ch->cdma);
+                nvhost_cdma_deinit(&ch->cdma);
+                nvhost_module_suspend(ch->dev, false);
+        }
+        ch->refcount--;
+        mutex_unlock(&ch->reflock);
+}
+int nvhost_channel_suspend(struct nvhost_channel *ch)
+{
+        int ret = 0;
+        mutex_lock(&ch->reflock);
+        BUG_ON(!channel_cdma_op(ch).stop);
+        if (ch->refcount) {
+                ret = nvhost_module_suspend(ch->dev, false);
+                if (!ret)
+                        channel_cdma_op(ch).stop(&ch->cdma);
+        }
+        mutex_unlock(&ch->reflock);
+        return ret;
+}
diff --git a/drivers/video/tegra/host/nvhost_channel.h b/drivers/video/tegra/host/nvhost_channel.h
new file mode 100644
index 00000000000..7b946c8ee85
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_channel.h
@@ -0,0 +1,86 @@
+/*
+ * drivers/video/tegra/host/nvhost_channel.h
+ *
+ * Tegra Graphics Host Channel
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_CHANNEL_H
+#define __NVHOST_CHANNEL_H
+#include "nvhost_cdma.h"
+#include "nvhost_acm.h"
+#include "nvhost_hwctx.h"
+#include "nvhost_job.h"
+#include <linux/cdev.h>
+#include <linux/io.h>
+#define NVHOST_MAX_WAIT_CHECKS 256
+#define NVHOST_MAX_GATHERS 512
+#define NVHOST_MAX_HANDLES 1280
+#define NVHOST_MAX_POWERGATE_IDS 2
+struct nvhost_master;
+struct nvhost_waitchk;
+struct nvhost_device;
+struct nvhost_channel_gather {
+        u32 words;
+        phys_addr_t mem;
+        u32 mem_id;
+        int offset;
+};
+struct nvhost_channel {
+        int refcount;
+        int chid;
+        u32 syncpt_id;
+        struct mutex reflock;
+        struct mutex submitlock;
+        void __iomem *aperture;
+        struct nvhost_hwctx *cur_ctx;
+        struct device *node;
+        struct nvhost_device *dev;
+        struct cdev cdev;
+        struct nvhost_hwctx_handler *ctxhandler;
+        struct nvhost_cdma cdma;
+};
+int nvhost_channel_init(
+        struct nvhost_channel *ch,
+        struct nvhost_master *dev, int index);
+int nvhost_channel_submit(struct nvhost_job *job);
+struct nvhost_channel *nvhost_getchannel(struct nvhost_channel *ch);
+void nvhost_putchannel(struct nvhost_channel *ch, struct nvhost_hwctx *ctx);
+int nvhost_channel_suspend(struct nvhost_channel *ch);
+#define channel_cdma_op(ch) (nvhost_get_host(ch->dev)->op.cdma)
+#define channel_op(ch) (nvhost_get_host(ch->dev)->op.channel)
+#define host_channel_op(host) (host->op.channel)
+int nvhost_channel_drain_read_fifo(void __iomem *chan_regs,
+                        u32 *ptr, unsigned int count, unsigned int *pending);
+int nvhost_channel_read_3d_reg(
+        struct nvhost_channel *channel,
+        struct nvhost_hwctx *hwctx,
+        u32 offset,
+        u32 *value);
+#endif
diff --git a/drivers/video/tegra/host/nvhost_hwctx.h b/drivers/video/tegra/host/nvhost_hwctx.h
new file mode 100644
index 00000000000..02a3976f01c
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_hwctx.h
@@ -0,0 +1,67 @@
+/*
+ * drivers/video/tegra/host/nvhost_hwctx.h
+ *
+ * Tegra Graphics Host Hardware Context Interface
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_HWCTX_H
+#define __NVHOST_HWCTX_H
+#include <linux/string.h>
+#include <linux/kref.h>
+#include <linux/nvhost.h>
+#include <mach/nvmap.h>
+struct nvhost_channel;
+struct nvhost_cdma;
+struct nvhost_hwctx {
+        struct kref ref;
+        struct nvhost_hwctx_handler *h;
+        struct nvhost_channel *channel;
+        bool valid;
+        bool has_timedout;
+};
+struct nvhost_hwctx_handler {
+        struct nvhost_hwctx * (*alloc) (struct nvhost_hwctx_handler *h,
+                        struct nvhost_channel *ch);
+        void (*get) (struct nvhost_hwctx *ctx);
+        void (*put) (struct nvhost_hwctx *ctx);
+        void (*save_push) (struct nvhost_hwctx *ctx,
+                        struct nvhost_cdma *cdma);
+        void (*save_service) (struct nvhost_hwctx *ctx);
+        void *priv;
+};
+struct hwctx_reginfo {
+        unsigned int offset:12;
+        unsigned int count:16;
+        unsigned int type:2;
+};
+enum {
+        HWCTX_REGINFO_DIRECT = 0,
+        HWCTX_REGINFO_INDIRECT,
+        HWCTX_REGINFO_INDIRECT_4X
+};
+#define HWCTX_REGINFO(offset, count, type) {offset, count, HWCTX_REGINFO_##type}
+#endif
diff --git a/drivers/video/tegra/host/nvhost_intr.c b/drivers/video/tegra/host/nvhost_intr.c
new file mode 100644
index 00000000000..7c4bdc7bafb
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_intr.c
@@ -0,0 +1,428 @@
+/*
+ * drivers/video/tegra/host/nvhost_intr.c
+ *
+ * Tegra Graphics Host Interrupt Management
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "nvhost_intr.h"
+#include "dev.h"
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+#include <trace/events/nvhost.h>
+/*** Wait list management ***/
+struct nvhost_waitlist {
+        struct list_head list;
+        struct kref refcount;
+        u32 thresh;
+        enum nvhost_intr_action action;
+        atomic_t state;
+        void *data;
+        int count;
+};
+enum waitlist_state {
+        WLS_PENDING,
+        WLS_REMOVED,
+        WLS_CANCELLED,
+        WLS_HANDLED
+};
+static void waiter_release(struct kref *kref)
+{
+        kfree(container_of(kref, struct nvhost_waitlist, refcount));
+}
+/**
+ * add a waiter to a waiter queue, sorted by threshold
+ * returns true if it was added at the head of the queue
+ */
+static bool add_waiter_to_queue(struct nvhost_waitlist *waiter,
+                                struct list_head *queue)
+{
+        struct nvhost_waitlist *pos;
+        u32 thresh = waiter->thresh;
+        list_for_each_entry_reverse(pos, queue, list)
+                if ((s32)(pos->thresh - thresh) <= 0) {
+                        list_add(&waiter->list, &pos->list);
+                        return false;
+                }
+        list_add(&waiter->list, queue);
+        return true;
+}
+/**
+ * run through a waiter queue for a single sync point ID
+ * and gather all completed waiters into lists by actions
+ */
+static void remove_completed_waiters(struct list_head *head, u32 sync,
+                        struct list_head completed[NVHOST_INTR_ACTION_COUNT])
+{
+        struct list_head *dest;
+        struct nvhost_waitlist *waiter, *next, *prev;
+        list_for_each_entry_safe(waiter, next, head, list) {
+                if ((s32)(waiter->thresh - sync) > 0)
+                        break;
+                dest = completed + waiter->action;
+                /* consolidate submit cleanups */
+                if (waiter->action == NVHOST_INTR_ACTION_SUBMIT_COMPLETE
+                        && !list_empty(dest)) {
+                        prev = list_entry(dest->prev,
+                                        struct nvhost_waitlist, list);
+                        if (prev->data == waiter->data) {
+                                prev->count++;
+                                dest = NULL;
+                        }
+                }
+                /* PENDING->REMOVED or CANCELLED->HANDLED */
+                if (atomic_inc_return(&waiter->state) == WLS_HANDLED || !dest) {
+                        list_del(&waiter->list);
+                        kref_put(&waiter->refcount, waiter_release);
+                } else {
+                        list_move_tail(&waiter->list, dest);
+                }
+        }
+}
+void reset_threshold_interrupt(struct nvhost_intr *intr,
+                               struct list_head *head,
+                               unsigned int id)
+{
+        u32 thresh = list_first_entry(head,
+                                struct nvhost_waitlist, list)->thresh;
+        BUG_ON(!(intr_op(intr).set_syncpt_threshold &&
+                 intr_op(intr).enable_syncpt_intr));
+        intr_op(intr).set_syncpt_threshold(intr, id, thresh);
+        intr_op(intr).enable_syncpt_intr(intr, id);
+}
+static void action_submit_complete(struct nvhost_waitlist *waiter)
+{
+        struct nvhost_channel *channel = waiter->data;
+        int nr_completed = waiter->count;
+        /*  Add nr_completed to trace */
+        trace_nvhost_channel_submit_complete(channel->dev->name,
+                        nr_completed, waiter->thresh);
+        nvhost_cdma_update(&channel->cdma);
+        nvhost_module_idle_mult(channel->dev, nr_completed);
+}
+static void action_ctxsave(struct nvhost_waitlist *waiter)
+{
+        struct nvhost_hwctx *hwctx = waiter->data;
+        struct nvhost_channel *channel = hwctx->channel;
+        if (channel->ctxhandler->save_service)
+                channel->ctxhandler->save_service(hwctx);
+}
+static void action_wakeup(struct nvhost_waitlist *waiter)
+{
+        wait_queue_head_t *wq = waiter->data;
+        wake_up(wq);
+}
+static void action_wakeup_interruptible(struct nvhost_waitlist *waiter)
+{
+        wait_queue_head_t *wq = waiter->data;
+        wake_up_interruptible(wq);
+}
+typedef void (*action_handler)(struct nvhost_waitlist *waiter);
+static action_handler action_handlers[NVHOST_INTR_ACTION_COUNT] = {
+        action_submit_complete,
+        action_ctxsave,
+        action_wakeup,
+        action_wakeup_interruptible,
+};
+static void run_handlers(struct list_head completed[NVHOST_INTR_ACTION_COUNT])
+{
+        struct list_head *head = completed;
+        int i;
+        for (i = 0; i < NVHOST_INTR_ACTION_COUNT; ++i, ++head) {
+                action_handler handler = action_handlers[i];
+                struct nvhost_waitlist *waiter, *next;
+                list_for_each_entry_safe(waiter, next, head, list) {
+                        list_del(&waiter->list);
+                        handler(waiter);
+                        WARN_ON(atomic_xchg(&waiter->state, WLS_HANDLED) != WLS_REMOVED);
+                        kref_put(&waiter->refcount, waiter_release);
+                }
+        }
+}
+/**
+ * Remove & handle all waiters that have completed for the given syncpt
+ */
+static int process_wait_list(struct nvhost_intr *intr,
+                             struct nvhost_intr_syncpt *syncpt,
+                             u32 threshold)
+{
+        struct list_head completed[NVHOST_INTR_ACTION_COUNT];
+        unsigned int i;
+        int empty;
+        for (i = 0; i < NVHOST_INTR_ACTION_COUNT; ++i)
+                INIT_LIST_HEAD(completed + i);
+        spin_lock(&syncpt->lock);
+        remove_completed_waiters(&syncpt->wait_head, threshold, completed);
+        empty = list_empty(&syncpt->wait_head);
+        if (!empty)
+                reset_threshold_interrupt(intr, &syncpt->wait_head,
+                                          syncpt->id);
+        spin_unlock(&syncpt->lock);
+        run_handlers(completed);
+        return empty;
+}
+/*** host syncpt interrupt service functions ***/
+/**
+ * Sync point threshold interrupt service thread function
+ * Handles sync point threshold triggers, in thread context
+ */
+irqreturn_t nvhost_syncpt_thresh_fn(int irq, void *dev_id)
+{
+        struct nvhost_intr_syncpt *syncpt = dev_id;
+        unsigned int id = syncpt->id;
+        struct nvhost_intr *intr = intr_syncpt_to_intr(syncpt);
+        struct nvhost_master *dev = intr_to_dev(intr);
+        (void)process_wait_list(intr, syncpt,
+                                nvhost_syncpt_update_min(&dev->syncpt, id));
+        return IRQ_HANDLED;
+}
+/**
+ * free a syncpt's irq. syncpt interrupt should be disabled first.
+ */
+static void free_syncpt_irq(struct nvhost_intr_syncpt *syncpt)
+{
+        if (syncpt->irq_requested) {
+                free_irq(syncpt->irq, syncpt);
+                syncpt->irq_requested = 0;
+        }
+}
+/*** host general interrupt service functions ***/
+/*** Main API ***/
+int nvhost_intr_add_action(struct nvhost_intr *intr, u32 id, u32 thresh,
+                        enum nvhost_intr_action action, void *data,
+                        void *_waiter,
+                        void **ref)
+{
+        struct nvhost_waitlist *waiter = _waiter;
+        struct nvhost_intr_syncpt *syncpt;
+        int queue_was_empty;
+        int err;
+        BUG_ON(waiter == NULL);
+        BUG_ON(!(intr_op(intr).set_syncpt_threshold &&
+                 intr_op(intr).enable_syncpt_intr));
+        /* initialize a new waiter */
+        INIT_LIST_HEAD(&waiter->list);
+        kref_init(&waiter->refcount);
+        if (ref)
+                kref_get(&waiter->refcount);
+        waiter->thresh = thresh;
+        waiter->action = action;
+        atomic_set(&waiter->state, WLS_PENDING);
+        waiter->data = data;
+        waiter->count = 1;
+        BUG_ON(id >= intr_to_dev(intr)->syncpt.nb_pts);
+        syncpt = intr->syncpt + id;
+        spin_lock(&syncpt->lock);
+        /* lazily request irq for this sync point */
+        if (!syncpt->irq_requested) {
+                spin_unlock(&syncpt->lock);
+                mutex_lock(&intr->mutex);
+                BUG_ON(!(intr_op(intr).request_syncpt_irq));
+                err = intr_op(intr).request_syncpt_irq(syncpt);
+                mutex_unlock(&intr->mutex);
+                if (err) {
+                        kfree(waiter);
+                        return err;
+                }
+                spin_lock(&syncpt->lock);
+        }
+        queue_was_empty = list_empty(&syncpt->wait_head);
+        if (add_waiter_to_queue(waiter, &syncpt->wait_head)) {
+                /* added at head of list - new threshold value */
+                intr_op(intr).set_syncpt_threshold(intr, id, thresh);
+                /* added as first waiter - enable interrupt */
+                if (queue_was_empty)
+                        intr_op(intr).enable_syncpt_intr(intr, id);
+        }
+        spin_unlock(&syncpt->lock);
+        if (ref)
+                *ref = waiter;
+        return 0;
+}
+void *nvhost_intr_alloc_waiter()
+{
+        return kzalloc(sizeof(struct nvhost_waitlist),
+                        GFP_KERNEL|__GFP_REPEAT);
+}
+void nvhost_intr_put_ref(struct nvhost_intr *intr, void *ref)
+{
+        struct nvhost_waitlist *waiter = ref;
+        while (atomic_cmpxchg(&waiter->state,
+                                WLS_PENDING, WLS_CANCELLED) == WLS_REMOVED)
+                schedule();
+        kref_put(&waiter->refcount, waiter_release);
+}
+/*** Init & shutdown ***/
+int nvhost_intr_init(struct nvhost_intr *intr, u32 irq_gen, u32 irq_sync)
+{
+        unsigned int id;
+        struct nvhost_intr_syncpt *syncpt;
+        struct nvhost_master *host =
+                container_of(intr, struct nvhost_master, intr);
+        u32 nb_pts = host->syncpt.nb_pts;
+        mutex_init(&intr->mutex);
+        intr->host_general_irq = irq_gen;
+        intr->host_general_irq_requested = false;
+        for (id = 0, syncpt = intr->syncpt;
+             id < nb_pts;
+             ++id, ++syncpt) {
+                syncpt->intr = &host->intr;
+                syncpt->id = id;
+                syncpt->irq = irq_sync + id;
+                syncpt->irq_requested = 0;
+                spin_lock_init(&syncpt->lock);
+                INIT_LIST_HEAD(&syncpt->wait_head);
+                snprintf(syncpt->thresh_irq_name,
+                        sizeof(syncpt->thresh_irq_name),
+                        "host_sp_%02d", id);
+        }
+        return 0;
+}
+void nvhost_intr_deinit(struct nvhost_intr *intr)
+{
+        nvhost_intr_stop(intr);
+}
+void nvhost_intr_start(struct nvhost_intr *intr, u32 hz)
+{
+        BUG_ON(!(intr_op(intr).init_host_sync &&
+                 intr_op(intr).set_host_clocks_per_usec &&
+                 intr_op(intr).request_host_general_irq));
+        mutex_lock(&intr->mutex);
+        intr_op(intr).init_host_sync(intr);
+        intr_op(intr).set_host_clocks_per_usec(intr,
+                                               (hz + 1000000 - 1)/1000000);
+        intr_op(intr).request_host_general_irq(intr);
+        mutex_unlock(&intr->mutex);
+}
+void nvhost_intr_stop(struct nvhost_intr *intr)
+{
+        unsigned int id;
+        struct nvhost_intr_syncpt *syncpt;
+        u32 nb_pts = intr_to_dev(intr)->syncpt.nb_pts;
+        BUG_ON(!(intr_op(intr).disable_all_syncpt_intrs &&
+                 intr_op(intr).free_host_general_irq));
+        mutex_lock(&intr->mutex);
+        intr_op(intr).disable_all_syncpt_intrs(intr);
+        for (id = 0, syncpt = intr->syncpt;
+             id < nb_pts;
+             ++id, ++syncpt) {
+                struct nvhost_waitlist *waiter, *next;
+                list_for_each_entry_safe(waiter, next, &syncpt->wait_head, list) {
+                        if (atomic_cmpxchg(&waiter->state, WLS_CANCELLED, WLS_HANDLED)
+                                == WLS_CANCELLED) {
+                                list_del(&waiter->list);
+                                kref_put(&waiter->refcount, waiter_release);
+                        }
+                }
+                if (!list_empty(&syncpt->wait_head)) {  /* output diagnostics */
+                        printk(KERN_DEBUG "%s id=%d\n", __func__, id);
+                        BUG_ON(1);
+                }
+                free_syncpt_irq(syncpt);
+        }
+        intr_op(intr).free_host_general_irq(intr);
+        mutex_unlock(&intr->mutex);
+}
diff --git a/drivers/video/tegra/host/nvhost_intr.h b/drivers/video/tegra/host/nvhost_intr.h
new file mode 100644
index 00000000000..26ab04ebd4a
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_intr.h
@@ -0,0 +1,115 @@
+/*
+ * drivers/video/tegra/host/nvhost_intr.h
+ *
+ * Tegra Graphics Host Interrupt Management
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_INTR_H
+#define __NVHOST_INTR_H
+#include <linux/kthread.h>
+#include <linux/semaphore.h>
+#include <linux/interrupt.h>
+struct nvhost_channel;
+enum nvhost_intr_action {
+        /**
+         * Perform cleanup after a submit has completed.
+         * 'data' points to a channel
+         */
+        NVHOST_INTR_ACTION_SUBMIT_COMPLETE = 0,
+        /**
+         * Save a HW context.
+         * 'data' points to a context
+         */
+        NVHOST_INTR_ACTION_CTXSAVE,
+        /**
+         * Wake up a  task.
+         * 'data' points to a wait_queue_head_t
+         */
+        NVHOST_INTR_ACTION_WAKEUP,
+        /**
+         * Wake up a interruptible task.
+         * 'data' points to a wait_queue_head_t
+         */
+        NVHOST_INTR_ACTION_WAKEUP_INTERRUPTIBLE,
+        NVHOST_INTR_ACTION_COUNT
+};
+struct nvhost_intr;
+struct nvhost_intr_syncpt {
+        struct  nvhost_intr *intr;
+        u8 id;
+        u8 irq_requested;
+        u16 irq;
+        spinlock_t lock;
+        struct list_head wait_head;
+        char thresh_irq_name[12];
+};
+struct nvhost_intr {
+        struct nvhost_intr_syncpt *syncpt;
+        struct mutex mutex;
+        int host_general_irq;
+        bool host_general_irq_requested;
+};
+#define intr_to_dev(x) container_of(x, struct nvhost_master, intr)
+#define intr_op(intr) (intr_to_dev(intr)->op.intr)
+#define intr_syncpt_to_intr(is) (is->intr)
+/**
+ * Schedule an action to be taken when a sync point reaches the given threshold.
+ *
+ * @id the sync point
+ * @thresh the threshold
+ * @action the action to take
+ * @data a pointer to extra data depending on action, see above
+ * @waiter waiter allocated with nvhost_intr_alloc_waiter - assumes ownership
+ * @ref must be passed if cancellation is possible, else NULL
+ *
+ * This is a non-blocking api.
+ */
+int nvhost_intr_add_action(struct nvhost_intr *intr, u32 id, u32 thresh,
+                        enum nvhost_intr_action action, void *data,
+                        void *waiter,
+                        void **ref);
+/**
+ * Allocate a waiter.
+ */
+void *nvhost_intr_alloc_waiter(void);
+/**
+ * Unreference an action submitted to nvhost_intr_add_action().
+ * You must call this if you passed non-NULL as ref.
+ * @ref the ref returned from nvhost_intr_add_action()
+ */
+void nvhost_intr_put_ref(struct nvhost_intr *intr, void *ref);
+int nvhost_intr_init(struct nvhost_intr *intr, u32 irq_gen, u32 irq_sync);
+void nvhost_intr_deinit(struct nvhost_intr *intr);
+void nvhost_intr_start(struct nvhost_intr *intr, u32 hz);
+void nvhost_intr_stop(struct nvhost_intr *intr);
+irqreturn_t nvhost_syncpt_thresh_fn(int irq, void *dev_id);
+#endif
diff --git a/drivers/video/tegra/host/nvhost_job.c b/drivers/video/tegra/host/nvhost_job.c
new file mode 100644
index 00000000000..df7a62d689b
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_job.c
@@ -0,0 +1,339 @@
+/*
+ * drivers/video/tegra/host/nvhost_job.c
+ *
+ * Tegra Graphics Host Job
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/slab.h>
+#include <linux/kref.h>
+#include <linux/err.h>
+#include <linux/vmalloc.h>
+#include <mach/nvmap.h>
+#include "nvhost_channel.h"
+#include "nvhost_job.h"
+#include "dev.h"
+/* Magic to use to fill freed handle slots */
+#define BAD_MAGIC 0xdeadbeef
+static int job_size(struct nvhost_submit_hdr_ext *hdr)
+{
+        int num_pins = hdr ? (hdr->num_relocs + hdr->num_cmdbufs)*2 : 0;
+        int num_waitchks = hdr ? hdr->num_waitchks : 0;
+        return sizeof(struct nvhost_job)
+                        + num_pins * sizeof(struct nvmap_pinarray_elem)
+                        + num_pins * sizeof(struct nvmap_handle *)
+                        + num_waitchks * sizeof(struct nvhost_waitchk);
+}
+static int gather_size(int num_cmdbufs)
+{
+        return num_cmdbufs * sizeof(struct nvhost_channel_gather);
+}
+static void free_gathers(struct nvhost_job *job)
+{
+        if (job->gathers) {
+                nvmap_munmap(job->gather_mem, job->gathers);
+                job->gathers = NULL;
+        }
+        if (job->gather_mem) {
+                nvmap_free(job->nvmap, job->gather_mem);
+                job->gather_mem = NULL;
+        }
+}
+static int alloc_gathers(struct nvhost_job *job,
+                int num_cmdbufs)
+{
+        int err = 0;
+        job->gather_mem = NULL;
+        job->gathers = NULL;
+        job->gather_mem_size = 0;
+        if (num_cmdbufs) {
+                /* Allocate memory */
+                job->gather_mem = nvmap_alloc(job->nvmap,
+                                gather_size(num_cmdbufs),
+                                32, NVMAP_HANDLE_CACHEABLE, 0);
+                if (IS_ERR_OR_NULL(job->gather_mem)) {
+                        err = PTR_ERR(job->gather_mem);
+                        job->gather_mem = NULL;
+                        goto error;
+                }
+                job->gather_mem_size = gather_size(num_cmdbufs);
+                /* Map memory to kernel */
+                job->gathers = nvmap_mmap(job->gather_mem);
+                if (IS_ERR_OR_NULL(job->gathers)) {
+                        err = PTR_ERR(job->gathers);
+                        job->gathers = NULL;
+                        goto error;
+                }
+        }
+        return 0;
+error:
+        free_gathers(job);
+        return err;
+}
+static int realloc_gathers(struct nvhost_job *oldjob,
+                struct nvhost_job *newjob,
+                int num_cmdbufs)
+{
+        int err = 0;
+        /* Check if we can reuse gather buffer */
+        if (oldjob->gather_mem_size < gather_size(num_cmdbufs)
+                        || oldjob->nvmap != newjob->nvmap) {
+                free_gathers(oldjob);
+                err = alloc_gathers(newjob, num_cmdbufs);
+        } else {
+                newjob->gather_mem = oldjob->gather_mem;
+                newjob->gathers = oldjob->gathers;
+                newjob->gather_mem_size = oldjob->gather_mem_size;
+                oldjob->gather_mem = NULL;
+                oldjob->gathers = NULL;
+                oldjob->gather_mem_size = 0;
+        }
+        return err;
+}
+static void init_fields(struct nvhost_job *job,
+                struct nvhost_submit_hdr_ext *hdr,
+                int priority, int clientid)
+{
+        int num_pins = hdr ? (hdr->num_relocs + hdr->num_cmdbufs)*2 : 0;
+        int num_waitchks = hdr ? hdr->num_waitchks : 0;
+        void *mem = job;
+        /* First init state to zero */
+        job->num_gathers = 0;
+        job->num_pins = 0;
+        job->num_unpins = 0;
+        job->num_waitchk = 0;
+        job->waitchk_mask = 0;
+        job->syncpt_id = 0;
+        job->syncpt_incrs = 0;
+        job->syncpt_end = 0;
+        job->priority = priority;
+        job->clientid = clientid;
+        job->null_kickoff = false;
+        job->first_get = 0;
+        job->num_slots = 0;
+        /* Redistribute memory to the structs */
+        mem += sizeof(struct nvhost_job);
+        if (num_pins) {
+                job->pinarray = mem;
+                mem += num_pins * sizeof(struct nvmap_pinarray_elem);
+                job->unpins = mem;
+                mem += num_pins * sizeof(struct nvmap_handle *);
+        } else {
+                job->pinarray = NULL;
+                job->unpins = NULL;
+        }
+        job->waitchk = num_waitchks ? mem : NULL;
+        /* Copy information from header */
+        if (hdr) {
+                job->waitchk_mask = hdr->waitchk_mask;
+                job->syncpt_id = hdr->syncpt_id;
+                job->syncpt_incrs = hdr->syncpt_incrs;
+        }
+}
+struct nvhost_job *nvhost_job_alloc(struct nvhost_channel *ch,
+                struct nvhost_hwctx *hwctx,
+                struct nvhost_submit_hdr_ext *hdr,
+                struct nvmap_client *nvmap,
+                int priority,
+                int clientid)
+{
+        struct nvhost_job *job = NULL;
+        int num_cmdbufs = hdr ? hdr->num_cmdbufs : 0;
+        int err = 0;
+        job = vzalloc(job_size(hdr));
+        if (!job)
+                goto error;
+        kref_init(&job->ref);
+        job->ch = ch;
+        job->hwctx = hwctx;
+        if (hwctx)
+                hwctx->h->get(hwctx);
+        job->nvmap = nvmap ? nvmap_client_get(nvmap) : NULL;
+        err = alloc_gathers(job, num_cmdbufs);
+        if (err)
+                goto error;
+        init_fields(job, hdr, priority, clientid);
+        return job;
+error:
+        if (job)
+                nvhost_job_put(job);
+        return NULL;
+}
+struct nvhost_job *nvhost_job_realloc(
+                struct nvhost_job *oldjob,
+                struct nvhost_hwctx *hwctx,
+                struct nvhost_submit_hdr_ext *hdr,
+                struct nvmap_client *nvmap,
+                int priority, int clientid)
+{
+        struct nvhost_job *newjob = NULL;
+        int num_cmdbufs = hdr ? hdr->num_cmdbufs : 0;
+        int err = 0;
+        newjob = vzalloc(job_size(hdr));
+        if (!newjob)
+                goto error;
+        kref_init(&newjob->ref);
+        newjob->ch = oldjob->ch;
+        newjob->hwctx = hwctx;
+        if (hwctx)
+                newjob->hwctx->h->get(newjob->hwctx);
+        newjob->timeout = oldjob->timeout;
+        newjob->nvmap = nvmap ? nvmap_client_get(nvmap) : NULL;
+        err = realloc_gathers(oldjob, newjob, num_cmdbufs);
+        if (err)
+                goto error;
+        nvhost_job_put(oldjob);
+        init_fields(newjob, hdr, priority, clientid);
+        return newjob;
+error:
+        if (newjob)
+                nvhost_job_put(newjob);
+        if (oldjob)
+                nvhost_job_put(oldjob);
+        return NULL;
+}
+void nvhost_job_get(struct nvhost_job *job)
+{
+        kref_get(&job->ref);
+}
+static void job_free(struct kref *ref)
+{
+        struct nvhost_job *job = container_of(ref, struct nvhost_job, ref);
+        if (job->hwctxref)
+                job->hwctxref->h->put(job->hwctxref);
+        if (job->hwctx)
+                job->hwctx->h->put(job->hwctx);
+        if (job->gathers)
+                nvmap_munmap(job->gather_mem, job->gathers);
+        if (job->gather_mem)
+                nvmap_free(job->nvmap, job->gather_mem);
+        if (job->nvmap)
+                nvmap_client_put(job->nvmap);
+        vfree(job);
+}
+/* Acquire reference to a hardware context. Used for keeping saved contexts in
+ * memory. */
+void nvhost_job_get_hwctx(struct nvhost_job *job, struct nvhost_hwctx *hwctx)
+{
+        BUG_ON(job->hwctxref);
+        job->hwctxref = hwctx;
+        hwctx->h->get(hwctx);
+}
+void nvhost_job_put(struct nvhost_job *job)
+{
+        kref_put(&job->ref, job_free);
+}
+void nvhost_job_add_gather(struct nvhost_job *job,
+                u32 mem_id, u32 words, u32 offset)
+{
+        struct nvmap_pinarray_elem *pin;
+        struct nvhost_channel_gather *cur_gather =
+                        &job->gathers[job->num_gathers];
+        pin = &job->pinarray[job->num_pins++];
+        pin->patch_mem = (u32)nvmap_ref_to_handle(job->gather_mem);
+        pin->patch_offset = (void *)&(cur_gather->mem) - (void *)job->gathers;
+        pin->pin_mem = nvmap_convert_handle_u2k(mem_id);
+        pin->pin_offset = offset;
+        cur_gather->words = words;
+        cur_gather->mem_id = mem_id;
+        cur_gather->offset = offset;
+        job->num_gathers += 1;
+}
+int nvhost_job_pin(struct nvhost_job *job)
+{
+        int err = 0;
+        /* pin mem handles and patch physical addresses */
+        job->num_unpins = nvmap_pin_array(job->nvmap,
+                                nvmap_ref_to_handle(job->gather_mem),
+                                job->pinarray, job->num_pins,
+                                job->unpins);
+        if (job->num_unpins < 0)
+                err = job->num_unpins;
+        return err;
+}
+void nvhost_job_unpin(struct nvhost_job *job)
+{
+        nvmap_unpin_handles(job->nvmap, job->unpins,
+                        job->num_unpins);
+        memset(job->unpins, BAD_MAGIC,
+                        job->num_unpins * sizeof(struct nvmap_handle *));
+}
+/**
+ * Debug routine used to dump job entries
+ */
+void nvhost_job_dump(struct device *dev, struct nvhost_job *job)
+{
+        dev_dbg(dev, "    SYNCPT_ID   %d\n",
+                job->syncpt_id);
+        dev_dbg(dev, "    SYNCPT_VAL  %d\n",
+                job->syncpt_end);
+        dev_dbg(dev, "    FIRST_GET   0x%x\n",
+                job->first_get);
+        dev_dbg(dev, "    TIMEOUT     %d\n",
+                job->timeout);
+        dev_dbg(dev, "    CTX 0x%p\n",
+                job->hwctx);
+        dev_dbg(dev, "    NUM_SLOTS   %d\n",
+                job->num_slots);
+        dev_dbg(dev, "    NUM_HANDLES %d\n",
+                job->num_unpins);
+}
diff --git a/drivers/video/tegra/host/nvhost_job.h b/drivers/video/tegra/host/nvhost_job.h
new file mode 100644
index 00000000000..ad9d1af60da
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_job.h
@@ -0,0 +1,150 @@
+/*
+ * drivers/video/tegra/host/nvhost_job.h
+ *
+ * Tegra Graphics Host Interrupt Management
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_JOB_H
+#define __NVHOST_JOB_H
+#include <linux/nvhost_ioctl.h>
+struct nvhost_channel;
+struct nvhost_hwctx;
+struct nvmap_client;
+struct nvhost_waitchk;
+struct nvmap_handle;
+/*
+ * Each submit is tracked as a nvhost_job.
+ */
+struct nvhost_job {
+        /* When refcount goes to zero, job can be freed */
+        struct kref ref;
+        /* List entry */
+        struct list_head list;
+        /* Channel where job is submitted to */
+        struct nvhost_channel *ch;
+        /* Hardware context valid for this client */
+        struct nvhost_hwctx *hwctx;
+        int clientid;
+        /* Nvmap to be used for pinning & unpinning memory */
+        struct nvmap_client *nvmap;
+        /* Gathers and their memory */
+        struct nvmap_handle_ref *gather_mem;
+        struct nvhost_channel_gather *gathers;
+        int num_gathers;
+        int gather_mem_size;
+        /* Wait checks to be processed at submit time */
+        struct nvhost_waitchk *waitchk;
+        int num_waitchk;
+        u32 waitchk_mask;
+        /* Array of handles to be pinned & unpinned */
+        struct nvmap_pinarray_elem *pinarray;
+        int num_pins;
+        struct nvmap_handle **unpins;
+        int num_unpins;
+        /* Sync point id, number of increments and end related to the submit */
+        u32 syncpt_id;
+        u32 syncpt_incrs;
+        u32 syncpt_end;
+        /* Priority of this submit. */
+        int priority;
+        /* Maximum time to wait for this job */
+        int timeout;
+        /* Null kickoff prevents submit from being sent to hardware */
+        bool null_kickoff;
+        /* Index and number of slots used in the push buffer */
+        int first_get;
+        int num_slots;
+        /* Context to be freed */
+        struct nvhost_hwctx *hwctxref;
+};
+/*
+ * Allocate memory for a job. Just enough memory will be allocated to
+ * accomodate the submit announced in submit header.
+ */
+struct nvhost_job *nvhost_job_alloc(struct nvhost_channel *ch,
+                struct nvhost_hwctx *hwctx,
+                struct nvhost_submit_hdr_ext *hdr,
+                struct nvmap_client *nvmap,
+                int priority, int clientid);
+/*
+ * Allocate memory for a job. Just enough memory will be allocated to
+ * accomodate the submit announced in submit header. Gather memory from
+ * oldjob will be reused, and nvhost_job_put() will be called to it.
+ */
+struct nvhost_job *nvhost_job_realloc(struct nvhost_job *oldjob,
+                struct nvhost_hwctx *hwctx,
+                struct nvhost_submit_hdr_ext *hdr,
+                struct nvmap_client *nvmap,
+                int priority, int clientid);
+/*
+ * Add a gather to a job.
+ */
+void nvhost_job_add_gather(struct nvhost_job *job,
+                u32 mem_id, u32 words, u32 offset);
+/*
+ * Increment reference going to nvhost_job.
+ */
+void nvhost_job_get(struct nvhost_job *job);
+/*
+ * Increment reference for a hardware context.
+ */
+void nvhost_job_get_hwctx(struct nvhost_job *job, struct nvhost_hwctx *hwctx);
+/*
+ * Decrement reference job, free if goes to zero.
+ */
+void nvhost_job_put(struct nvhost_job *job);
+/*
+ * Pin memory related to job. This handles relocation of addresses to the
+ * host1x address space. Handles both the gather memory and any other memory
+ * referred to from the gather buffers.
+ */
+int nvhost_job_pin(struct nvhost_job *job);
+/*
+ * Unpin memory related to job.
+ */
+void nvhost_job_unpin(struct nvhost_job *job);
+/*
+ * Dump contents of job to debug output.
+ */
+void nvhost_job_dump(struct device *dev, struct nvhost_job *job);
+#endif
diff --git a/drivers/video/tegra/host/nvhost_syncpt.c b/drivers/video/tegra/host/nvhost_syncpt.c
new file mode 100644
index 00000000000..eb5176ea1bf
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_syncpt.c
@@ -0,0 +1,319 @@
+/*
+ * drivers/video/tegra/host/nvhost_syncpt.c
+ *
+ * Tegra Graphics Host Syncpoints
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/nvhost_ioctl.h>
+#include <linux/platform_device.h>
+#include "nvhost_syncpt.h"
+#include "dev.h"
+#define MAX_STUCK_CHECK_COUNT 15
+/**
+ * Resets syncpoint and waitbase values to sw shadows
+ */
+void nvhost_syncpt_reset(struct nvhost_syncpt *sp)
+{
+        u32 i;
+        BUG_ON(!(syncpt_op(sp).reset && syncpt_op(sp).reset_wait_base));
+        for (i = 0; i < sp->nb_pts; i++)
+                syncpt_op(sp).reset(sp, i);
+        for (i = 0; i < sp->nb_bases; i++)
+                syncpt_op(sp).reset_wait_base(sp, i);
+        wmb();
+}
+/**
+ * Updates sw shadow state for client managed registers
+ */
+void nvhost_syncpt_save(struct nvhost_syncpt *sp)
+{
+        u32 i;
+        BUG_ON(!(syncpt_op(sp).update_min && syncpt_op(sp).read_wait_base));
+        for (i = 0; i < sp->nb_pts; i++) {
+                if (client_managed(i))
+                        syncpt_op(sp).update_min(sp, i);
+                else
+                        BUG_ON(!nvhost_syncpt_min_eq_max(sp, i));
+        }
+        for (i = 0; i < sp->nb_bases; i++)
+                syncpt_op(sp).read_wait_base(sp, i);
+}
+/**
+ * Updates the last value read from hardware.
+ */
+u32 nvhost_syncpt_update_min(struct nvhost_syncpt *sp, u32 id)
+{
+        BUG_ON(!syncpt_op(sp).update_min);
+        return syncpt_op(sp).update_min(sp, id);
+}
+/**
+ * Get the current syncpoint value
+ */
+u32 nvhost_syncpt_read(struct nvhost_syncpt *sp, u32 id)
+{
+        u32 val;
+        BUG_ON(!syncpt_op(sp).update_min);
+        nvhost_module_busy(syncpt_to_dev(sp)->dev);
+        val = syncpt_op(sp).update_min(sp, id);
+        nvhost_module_idle(syncpt_to_dev(sp)->dev);
+        return val;
+}
+/**
+ * Get the current syncpoint base
+ */
+u32 nvhost_syncpt_read_wait_base(struct nvhost_syncpt *sp, u32 id)
+{
+        u32 val;
+        BUG_ON(!syncpt_op(sp).read_wait_base);
+        nvhost_module_busy(syncpt_to_dev(sp)->dev);
+        syncpt_op(sp).read_wait_base(sp, id);
+        val = sp->base_val[id];
+        nvhost_module_idle(syncpt_to_dev(sp)->dev);
+        return val;
+}
+/**
+ * Write a cpu syncpoint increment to the hardware, without touching
+ * the cache. Caller is responsible for host being powered.
+ */
+void nvhost_syncpt_cpu_incr(struct nvhost_syncpt *sp, u32 id)
+{
+        BUG_ON(!syncpt_op(sp).cpu_incr);
+        syncpt_op(sp).cpu_incr(sp, id);
+}
+/**
+ * Increment syncpoint value from cpu, updating cache
+ */
+void nvhost_syncpt_incr(struct nvhost_syncpt *sp, u32 id)
+{
+        if (client_managed(id))
+                nvhost_syncpt_incr_max(sp, id, 1);
+        nvhost_module_busy(syncpt_to_dev(sp)->dev);
+        nvhost_syncpt_cpu_incr(sp, id);
+        nvhost_module_idle(syncpt_to_dev(sp)->dev);
+}
+/**
+ * Main entrypoint for syncpoint value waits.
+ */
+int nvhost_syncpt_wait_timeout(struct nvhost_syncpt *sp, u32 id,
+                        u32 thresh, u32 timeout, u32 *value)
+{
+        DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
+        void *ref;
+        void *waiter;
+        int err = 0, check_count = 0, low_timeout = 0;
+        u32 val;
+        if (value)
+                *value = 0;
+        /* first check cache */
+        if (nvhost_syncpt_is_expired(sp, id, thresh)) {
+                if (value)
+                        *value = nvhost_syncpt_read_min(sp, id);
+                return 0;
+        }
+        /* keep host alive */
+        nvhost_module_busy(syncpt_to_dev(sp)->dev);
+        /* try to read from register */
+        val = syncpt_op(sp).update_min(sp, id);
+        if (nvhost_syncpt_is_expired(sp, id, thresh)) {
+                if (value)
+                        *value = val;
+                goto done;
+        }
+        if (!timeout) {
+                err = -EAGAIN;
+                goto done;
+        }
+        /* schedule a wakeup when the syncpoint value is reached */
+        waiter = nvhost_intr_alloc_waiter();
+        if (!waiter) {
+                err = -ENOMEM;
+                goto done;
+        }
+        err = nvhost_intr_add_action(&(syncpt_to_dev(sp)->intr), id, thresh,
+                                NVHOST_INTR_ACTION_WAKEUP_INTERRUPTIBLE, &wq,
+                                waiter,
+                                &ref);
+        if (err)
+                goto done;
+        err = -EAGAIN;
+        /* Caller-specified timeout may be impractically low */
+        if (timeout < SYNCPT_CHECK_PERIOD)
+                low_timeout = timeout;
+        /* wait for the syncpoint, or timeout, or signal */
+        while (timeout) {
+                u32 check = min_t(u32, SYNCPT_CHECK_PERIOD, timeout);
+                int remain = wait_event_interruptible_timeout(wq,
+                                nvhost_syncpt_is_expired(sp, id, thresh),
+                                check);
+                if (remain > 0) {
+                        if (value)
+                                *value = nvhost_syncpt_read_min(sp, id);
+                        err = 0;
+                        break;
+                }
+                if (remain < 0) {
+                        err = remain;
+                        break;
+                }
+                if (timeout != NVHOST_NO_TIMEOUT)
+                        timeout -= check;
+                if (timeout) {
+                        dev_warn(&syncpt_to_dev(sp)->dev->dev,
+                                "%s: syncpoint id %d (%s) stuck waiting %d, timeout=%d\n",
+                                 current->comm, id, syncpt_op(sp).name(sp, id),
+                                 thresh, timeout);
+                        syncpt_op(sp).debug(sp);
+                        if (check_count > MAX_STUCK_CHECK_COUNT) {
+                                if (low_timeout) {
+                                        dev_warn(&syncpt_to_dev(sp)->dev->dev,
+                                                "is timeout %d too low?\n",
+                                                low_timeout);
+                                }
+                                nvhost_debug_dump(syncpt_to_dev(sp));
+                                BUG();
+                        }
+                        check_count++;
+                }
+        }
+        nvhost_intr_put_ref(&(syncpt_to_dev(sp)->intr), ref);
+done:
+        nvhost_module_idle(syncpt_to_dev(sp)->dev);
+        return err;
+}
+/**
+ * Returns true if syncpoint is expired, false if we may need to wait
+ */
+bool nvhost_syncpt_is_expired(
+        struct nvhost_syncpt *sp,
+        u32 id,
+        u32 thresh)
+{
+        u32 current_val;
+        u32 future_val;
+        smp_rmb();
+        current_val = (u32)atomic_read(&sp->min_val[id]);
+        future_val = (u32)atomic_read(&sp->max_val[id]);
+        /* Note the use of unsigned arithmetic here (mod 1<<32).
+         *
+         * c = current_val = min_val    = the current value of the syncpoint.
+         * t = thresh                   = the value we are checking
+         * f = future_val  = max_val    = the value c will reach when all
+         *                                outstanding increments have completed.
+         *
+         * Note that c always chases f until it reaches f.
+         *
+         * Dtf = (f - t)
+         * Dtc = (c - t)
+         *
+         *  Consider all cases:
+         *
+         *      A) .....c..t..f.....    Dtf < Dtc       need to wait
+         *      B) .....c.....f..t..    Dtf > Dtc       expired
+         *      C) ..t..c.....f.....    Dtf > Dtc       expired    (Dct very large)
+         *
+         *  Any case where f==c: always expired (for any t).    Dtf == Dcf
+         *  Any case where t==c: always expired (for any f).    Dtf >= Dtc (because Dtc==0)
+         *  Any case where t==f!=c: always wait.                Dtf <  Dtc (because Dtf==0,
+         *                                                      Dtc!=0)
+         *
+         *  Other cases:
+         *
+         *      A) .....t..f..c.....    Dtf < Dtc       need to wait
+         *      A) .....f..c..t.....    Dtf < Dtc       need to wait
+         *      A) .....f..t..c.....    Dtf > Dtc       expired
+         *
+         *   So:
+         *         Dtf >= Dtc implies EXPIRED   (return true)
+         *         Dtf <  Dtc implies WAIT      (return false)
+         *
+         * Note: If t is expired then we *cannot* wait on it. We would wait
+         * forever (hang the system).
+         *
+         * Note: do NOT get clever and remove the -thresh from both sides. It
+         * is NOT the same.
+         *
+         * If future valueis zero, we have a client managed sync point. In that
+         * case we do a direct comparison.
+         */
+        if (!client_managed(id))
+                return future_val - thresh >= current_val - thresh;
+        else
+                return (s32)(current_val - thresh) >= 0;
+}
+void nvhost_syncpt_debug(struct nvhost_syncpt *sp)
+{
+        syncpt_op(sp).debug(sp);
+}
+int nvhost_mutex_try_lock(struct nvhost_syncpt *sp, int idx)
+{
+        struct nvhost_master *host = syncpt_to_dev(sp);
+        u32 reg;
+        nvhost_module_busy(host->dev);
+        reg = syncpt_op(sp).mutex_try_lock(sp, idx);
+        if (reg) {
+                nvhost_module_idle(host->dev);
+                return -EBUSY;
+        }
+        atomic_inc(&sp->lock_counts[idx]);
+        return 0;
+}
+void nvhost_mutex_unlock(struct nvhost_syncpt *sp, int idx)
+{
+        syncpt_op(sp).mutex_unlock(sp, idx);
+        nvhost_module_idle(syncpt_to_dev(sp)->dev);
+        atomic_dec(&sp->lock_counts[idx]);
+}
+/* check for old WAITs to be removed (avoiding a wrap) */
+int nvhost_syncpt_wait_check(struct nvhost_syncpt *sp,
+                             struct nvmap_client *nvmap,
+                             u32 waitchk_mask,
+                             struct nvhost_waitchk *wait,
+                             int num_waitchk)
+{
+        return syncpt_op(sp).wait_check(sp, nvmap,
+                        waitchk_mask, wait, num_waitchk);
+}
diff --git a/drivers/video/tegra/host/nvhost_syncpt.h b/drivers/video/tegra/host/nvhost_syncpt.h
new file mode 100644
index 00000000000..5b339178d1e
--- /dev/null
+++ b/drivers/video/tegra/host/nvhost_syncpt.h
@@ -0,0 +1,155 @@
+/*
+ * drivers/video/tegra/host/nvhost_syncpt.h
+ *
+ * Tegra Graphics Host Syncpoints
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __NVHOST_SYNCPT_H
+#define __NVHOST_SYNCPT_H
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/nvhost.h>
+#include <mach/nvmap.h>
+#include <linux/atomic.h>
+struct nvhost_syncpt;
+struct nvhost_waitchk;
+/* host managed and invalid syncpt id */
+#define NVSYNCPT_GRAPHICS_HOST               (0)
+#define NVSYNCPT_INVALID                     (-1)
+struct nvhost_syncpt {
+        atomic_t *min_val;
+        atomic_t *max_val;
+        u32 *base_val;
+        u32 nb_pts;
+        u32 nb_bases;
+        u32 client_managed;
+        atomic_t *lock_counts;
+        u32 nb_mlocks;
+};
+int nvhost_syncpt_init(struct nvhost_syncpt *);
+#define client_managed(id) (BIT(id) & sp->client_managed)
+#define syncpt_to_dev(sp) container_of(sp, struct nvhost_master, syncpt)
+#define syncpt_op(sp) (syncpt_to_dev(sp)->op.syncpt)
+#define SYNCPT_CHECK_PERIOD (2*HZ)
+/**
+ * Updates the value sent to hardware.
+ */
+static inline u32 nvhost_syncpt_incr_max(struct nvhost_syncpt *sp,
+                                        u32 id, u32 incrs)
+{
+        return (u32)atomic_add_return(incrs, &sp->max_val[id]);
+}
+/**
+ * Updated the value sent to hardware.
+ */
+static inline u32 nvhost_syncpt_set_max(struct nvhost_syncpt *sp,
+                                        u32 id, u32 val)
+{
+        atomic_set(&sp->max_val[id], val);
+        smp_wmb();
+        return val;
+}
+static inline u32 nvhost_syncpt_read_max(struct nvhost_syncpt *sp, u32 id)
+{
+        smp_rmb();
+        return (u32)atomic_read(&sp->max_val[id]);
+}
+static inline u32 nvhost_syncpt_read_min(struct nvhost_syncpt *sp, u32 id)
+{
+        smp_rmb();
+        return (u32)atomic_read(&sp->min_val[id]);
+}
+static inline bool nvhost_syncpt_check_max(struct nvhost_syncpt *sp,
+                u32 id, u32 real)
+{
+        u32 max;
+        if (client_managed(id))
+                return true;
+        max = nvhost_syncpt_read_max(sp, id);
+        return (s32)(max - real) >= 0;
+}
+/**
+ * Returns true if syncpoint min == max
+ */
+static inline bool nvhost_syncpt_min_eq_max(struct nvhost_syncpt *sp, u32 id)
+{
+        int min, max;
+        smp_rmb();
+        min = atomic_read(&sp->min_val[id]);
+        max = atomic_read(&sp->max_val[id]);
+        return (min == max);
+}
+void nvhost_syncpt_cpu_incr(struct nvhost_syncpt *sp, u32 id);
+u32 nvhost_syncpt_update_min(struct nvhost_syncpt *sp, u32 id);
+bool nvhost_syncpt_is_expired(struct nvhost_syncpt *sp, u32 id, u32 thresh);
+void nvhost_syncpt_save(struct nvhost_syncpt *sp);
+void nvhost_syncpt_reset(struct nvhost_syncpt *sp);
+u32 nvhost_syncpt_read(struct nvhost_syncpt *sp, u32 id);
+u32 nvhost_syncpt_read_wait_base(struct nvhost_syncpt *sp, u32 id);
+void nvhost_syncpt_incr(struct nvhost_syncpt *sp, u32 id);
+int nvhost_syncpt_wait_timeout(struct nvhost_syncpt *sp, u32 id, u32 thresh,
+                        u32 timeout, u32 *value);
+static inline int nvhost_syncpt_wait(struct nvhost_syncpt *sp, u32 id, u32 thresh)
+{
+        return nvhost_syncpt_wait_timeout(sp, id, thresh,
+                                          MAX_SCHEDULE_TIMEOUT, NULL);
+}
+/*
+ * Check driver supplied waitchk structs for syncpt thresholds
+ * that have already been satisfied and NULL the comparison (to
+ * avoid a wrap condition in the HW).
+ *
+ * @param: sp - global shadowed syncpt struct
+ * @param: nvmap - needed to access command buffer
+ * @param: mask - bit mask of syncpt IDs referenced in WAITs
+ * @param: wait - start of filled in array of waitchk structs
+ * @param: waitend - end ptr (one beyond last valid waitchk)
+ */
+int nvhost_syncpt_wait_check(struct nvhost_syncpt *sp,
+                        struct nvmap_client *nvmap,
+                        u32 mask,
+                        struct nvhost_waitchk *wait,
+                        int num_waitchk);
+void nvhost_syncpt_debug(struct nvhost_syncpt *sp);
+int nvhost_mutex_try_lock(struct nvhost_syncpt *sp, int idx);
+void nvhost_mutex_unlock(struct nvhost_syncpt *sp, int idx);
+#endif
diff --git a/drivers/video/tegra/host/t20/Makefile b/drivers/video/tegra/host/t20/Makefile
new file mode 100644
index 00000000000..c2ade9bf925
--- /dev/null
+++ b/drivers/video/tegra/host/t20/Makefile
@@ -0,0 +1,8 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-t20-objs  = \
+        t20.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-t20.o
diff --git a/drivers/video/tegra/host/t20/t20.c b/drivers/video/tegra/host/t20/t20.c
new file mode 100644
index 00000000000..24ddedc842e
--- /dev/null
+++ b/drivers/video/tegra/host/t20/t20.c
@@ -0,0 +1,233 @@
+/*
+ * drivers/video/tegra/host/t20/t20.c
+ *
+ * Tegra Graphics Init for T20 Architecture Chips
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/slab.h>
+#include <mach/powergate.h>
+#include "dev.h"
+#include "t20.h"
+#include "host1x/host1x_channel.h"
+#include "host1x/host1x_syncpt.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_cdma.h"
+#include "gr3d/gr3d.h"
+#include "gr3d/gr3d_t20.h"
+#include "mpe/mpe.h"
+#include "nvhost_hwctx.h"
+#define NVMODMUTEX_2D_FULL      (1)
+#define NVMODMUTEX_2D_SIMPLE    (2)
+#define NVMODMUTEX_2D_SB_A      (3)
+#define NVMODMUTEX_2D_SB_B      (4)
+#define NVMODMUTEX_3D           (5)
+#define NVMODMUTEX_DISPLAYA     (6)
+#define NVMODMUTEX_DISPLAYB     (7)
+#define NVMODMUTEX_VI           (8)
+#define NVMODMUTEX_DSI          (9)
+#define NVHOST_NUMCHANNELS      (NV_HOST1X_CHANNELS - 1)
+struct nvhost_device t20_devices[] = {
+{
+        /* channel 0 */
+        .name           = "display",
+        .id             = -1,
+        .index          = 0,
+        .syncpts        = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
+                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
+                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
+                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
+        .modulemutexes  = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_NONE,
+},
+{
+        /* channel 1 */
+        .name           = "gr3d",
+        .id             = -1,
+        .index          = 1,
+        .syncpts        = BIT(NVSYNCPT_3D),
+        .waitbases      = BIT(NVWAITBASE_3D),
+        .modulemutexes  = BIT(NVMODMUTEX_3D),
+        .class          = NV_GRAPHICS_3D_CLASS_ID,
+        .prepare_poweroff = nvhost_gr3d_prepare_power_off,
+        .alloc_hwctx_handler = nvhost_gr3d_t20_ctxhandler_init,
+        .clocks         = {{"gr3d", UINT_MAX}, {"emc", UINT_MAX}, {} },
+        .powergate_ids  = {TEGRA_POWERGATE_3D, -1},
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_NONE,
+},
+{
+        /* channel 2 */
+        .name           = "gr2d",
+        .id             = -1,
+        .index          = 2,
+        .syncpts        = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
+        .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
+        .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
+                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+        .clocks         = { {"gr2d", UINT_MAX},
+                            {"epp", UINT_MAX},
+                            {"emc", UINT_MAX} },
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        .clockgate_delay = 0,
+        .moduleid       = NVHOST_MODULE_NONE,
+},
+{
+        /* channel 3 */
+        .name           = "isp",
+        .id             = -1,
+        .index          = 3,
+        .syncpts        = 0,
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_ISP,
+},
+{
+        /* channel 4 */
+        .name           = "vi",
+        .id             = -1,
+        .index          = 4,
+        .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
+                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
+                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
+                          BIT(NVSYNCPT_VI_ISP_4),
+        .modulemutexes  = BIT(NVMODMUTEX_VI),
+        .exclusive      = true,
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_VI,
+},
+{
+        /* channel 5 */
+        .name           = "mpe",
+        .id             = -1,
+        .index          = 5,
+        .syncpts        = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
+                          BIT(NVSYNCPT_MPE_WR_SAFE),
+        .waitbases      = BIT(NVWAITBASE_MPE),
+        .class          = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
+        .waitbasesync   = true,
+        .keepalive      = true,
+        .prepare_poweroff = nvhost_mpe_prepare_power_off,
+        .alloc_hwctx_handler = nvhost_mpe_ctxhandler_init,
+        .clocks         = { {"mpe", UINT_MAX},
+                            {"emc", UINT_MAX} },
+        .powergate_ids  = {TEGRA_POWERGATE_MPE, -1},
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_MPE,
+},
+{
+        /* channel 6 */
+        .name           = "dsi",
+        .id             = -1,
+        .index          = 6,
+        .syncpts        = BIT(NVSYNCPT_DSI),
+        .modulemutexes  = BIT(NVMODMUTEX_DSI),
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_NONE,
+} };
+static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
+{
+        p += NV_HOST1X_CHANNEL0_BASE;
+        p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
+        return p;
+}
+static inline int t20_nvhost_hwctx_handler_init(struct nvhost_channel *ch)
+{
+        int err = 0;
+        unsigned long syncpts = ch->dev->syncpts;
+        unsigned long waitbases = ch->dev->waitbases;
+        u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG);
+        u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG);
+        if (ch->dev->alloc_hwctx_handler) {
+                ch->ctxhandler = ch->dev->alloc_hwctx_handler(syncpt,
+                                waitbase, ch);
+                if (!ch->ctxhandler)
+                        err = -ENOMEM;
+        }
+        return err;
+}
+static int t20_channel_init(struct nvhost_channel *ch,
+        struct nvhost_master *dev, int index)
+{
+        ch->chid = index;
+        mutex_init(&ch->reflock);
+        mutex_init(&ch->submitlock);
+        ch->aperture = t20_channel_aperture(dev->aperture, index);
+        return t20_nvhost_hwctx_handler_init(ch);
+}
+int nvhost_init_t20_channel_support(struct nvhost_master *host)
+{
+        host->nb_channels =  NVHOST_NUMCHANNELS;
+        host->op.channel.init = t20_channel_init;
+        host->op.channel.submit = host1x_channel_submit;
+        host->op.channel.read3dreg = host1x_channel_read_3d_reg;
+        return 0;
+}
+struct nvhost_device *t20_get_nvhost_device(struct nvhost_master *host,
+        char *name)
+{
+        int i;
+        for (i = 0; i < host->nb_channels; i++) {
+                if (strcmp(t20_devices[i].name, name) == 0)
+                        return &t20_devices[i];
+        }
+        return NULL;
+}
+int nvhost_init_t20_support(struct nvhost_master *host)
+{
+        int err;
+        /* don't worry about cleaning up on failure... "remove" does it. */
+        err = nvhost_init_t20_channel_support(host);
+        if (err)
+                return err;
+        err = host1x_init_cdma_support(host);
+        if (err)
+                return err;
+        err = nvhost_init_t20_debug_support(host);
+        if (err)
+                return err;
+        err = host1x_init_syncpt_support(host);
+        if (err)
+                return err;
+        err = nvhost_init_t20_intr_support(host);
+        if (err)
+                return err;
+        host->op.nvhost_dev.get_nvhost_device = t20_get_nvhost_device;
+        return 0;
+}
diff --git a/drivers/video/tegra/host/t20/t20.h b/drivers/video/tegra/host/t20/t20.h
new file mode 100644
index 00000000000..93555a55b58
--- /dev/null
+++ b/drivers/video/tegra/host/t20/t20.h
@@ -0,0 +1,33 @@
+/*
+ * drivers/video/tegra/host/t20/t20.h
+ *
+ * Tegra Graphics Chip support for T20
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _NVHOST_T20_H_
+#define _NVHOST_T20_H_
+struct nvhost_master;
+struct nvhost_module;
+int nvhost_init_t20_channel_support(struct nvhost_master *);
+int nvhost_init_t20_debug_support(struct nvhost_master *);
+int nvhost_init_t20_syncpt_support(struct nvhost_master *);
+int nvhost_init_t20_intr_support(struct nvhost_master *);
+int nvhost_init_t20_support(struct nvhost_master *host);
+int nvhost_t20_save_context(struct nvhost_module *mod, u32 syncpt_id);
+#endif /* _NVHOST_T20_H_ */
diff --git a/drivers/video/tegra/host/t30/Makefile b/drivers/video/tegra/host/t30/Makefile
new file mode 100644
index 00000000000..b343eb4fc7c
--- /dev/null
+++ b/drivers/video/tegra/host/t30/Makefile
@@ -0,0 +1,8 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-t30-objs  = \
+        t30.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-t30.o
diff --git a/drivers/video/tegra/host/t30/t30.c b/drivers/video/tegra/host/t30/t30.c
new file mode 100644
index 00000000000..8a8b1f4d924
--- /dev/null
+++ b/drivers/video/tegra/host/t30/t30.c
@@ -0,0 +1,251 @@
+/*
+ * drivers/video/tegra/host/t30/t30.c
+ *
+ * Tegra Graphics Init for T30 Architecture Chips
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/mutex.h>
+#include <mach/powergate.h>
+#include <mach/iomap.h>
+#include "dev.h"
+#include "t20/t20.h"
+#include "t30.h"
+#include "gr3d/gr3d.h"
+#include "mpe/mpe.h"
+#include "gr3d/gr3d_t30.h"
+#include "gr3d/scale3d.h"
+#include "host1x/host1x_hardware.h"
+#include "host1x/host1x_cdma.h"
+#include "host1x/host1x_syncpt.h"
+#include "chip_support.h"
+#define NVMODMUTEX_2D_FULL      (1)
+#define NVMODMUTEX_2D_SIMPLE    (2)
+#define NVMODMUTEX_2D_SB_A      (3)
+#define NVMODMUTEX_2D_SB_B      (4)
+#define NVMODMUTEX_3D           (5)
+#define NVMODMUTEX_DISPLAYA     (6)
+#define NVMODMUTEX_DISPLAYB     (7)
+#define NVMODMUTEX_VI           (8)
+#define NVMODMUTEX_DSI          (9)
+#define NVHOST_CHANNEL_BASE     0
+struct nvhost_device t30_devices[] = {
+{
+        /* channel 0 */
+        .name           = "display",
+        .id             = -1,
+        .index          = 0,
+        .syncpts        = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
+                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
+                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
+                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
+        .modulemutexes  = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_NONE,
+},
+{
+        /* channel 1 */
+        .name           = "gr3d",
+        .id             = -1,
+        .index          = 1,
+        .syncpts        = BIT(NVSYNCPT_3D),
+        .waitbases      = BIT(NVWAITBASE_3D),
+        .modulemutexes  = BIT(NVMODMUTEX_3D),
+        .class          = NV_GRAPHICS_3D_CLASS_ID,
+        .prepare_poweroff = nvhost_gr3d_prepare_power_off,
+        .busy           = nvhost_scale3d_notify_busy,
+        .idle           = nvhost_scale3d_notify_idle,
+        .init           = nvhost_scale3d_init,
+        .deinit         = nvhost_scale3d_deinit,
+        .suspend        = nvhost_scale3d_suspend,
+        .alloc_hwctx_handler = nvhost_gr3d_t30_ctxhandler_init,
+        .clocks         = { {"gr3d", UINT_MAX},
+                            {"gr3d2", UINT_MAX},
+                            {"emc", UINT_MAX} },
+        .powergate_ids = { TEGRA_POWERGATE_3D,
+                           TEGRA_POWERGATE_3D1 },
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .can_powergate = false,
+        .powergate_delay = 250,
+        .moduleid       = NVHOST_MODULE_NONE,
+},
+{
+        /* channel 2 */
+        .name           = "gr2d",
+        .id             = -1,
+        .index          = 2,
+        .syncpts        = BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
+        .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
+        .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
+                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+        .clocks         = { {"gr2d", 0},
+                            {"epp", 0},
+                            {"emc", 300000000} },
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        .clockgate_delay = 0,
+        .moduleid       = NVHOST_MODULE_NONE,
+},
+{
+        /* channel 3 */
+        .name           = "isp",
+        .id             = -1,
+        .index          = 3,
+        .syncpts        = 0,
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_ISP,
+},
+{
+        /* channel 4 */
+        .name           = "vi",
+        .id             = -1,
+        .index          = 4,
+        .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
+                          BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
+                          BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
+                          BIT(NVSYNCPT_VI_ISP_4),
+        .modulemutexes  = BIT(NVMODMUTEX_VI),
+        .exclusive      = true,
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_VI,
+},
+{
+        /* channel 5 */
+        .name           = "mpe",
+        .id             = -1,
+        .index          = 5,
+        .syncpts        = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
+                          BIT(NVSYNCPT_MPE_WR_SAFE),
+        .waitbases      = BIT(NVWAITBASE_MPE),
+        .class          = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
+        .waitbasesync   = true,
+        .keepalive      = true,
+        .prepare_poweroff = nvhost_mpe_prepare_power_off,
+        .alloc_hwctx_handler = nvhost_mpe_ctxhandler_init,
+        .clocks         = { {"mpe", UINT_MAX},
+                            {"emc", UINT_MAX} },
+        .powergate_ids  = {TEGRA_POWERGATE_MPE, -1},
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .can_powergate  = true,
+        .powergate_delay = 100,
+        .moduleid       = NVHOST_MODULE_MPE,
+},
+{
+        /* channel 6 */
+        .name           = "dsi",
+        .id             = -1,
+        .index          = 6,
+        .syncpts        = BIT(NVSYNCPT_DSI),
+        .modulemutexes  = BIT(NVMODMUTEX_DSI),
+        NVHOST_MODULE_NO_POWERGATE_IDS,
+        NVHOST_DEFAULT_CLOCKGATE_DELAY,
+        .moduleid       = NVHOST_MODULE_NONE,
+} };
+static inline int t30_nvhost_hwctx_handler_init(struct nvhost_channel *ch)
+{
+        int err = 0;
+        unsigned long syncpts = ch->dev->syncpts;
+        unsigned long waitbases = ch->dev->waitbases;
+        u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG);
+        u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG);
+        if (ch->dev->alloc_hwctx_handler) {
+                ch->ctxhandler = ch->dev->alloc_hwctx_handler(syncpt,
+                                waitbase, ch);
+                if (!ch->ctxhandler)
+                        err = -ENOMEM;
+        }
+        return err;
+}
+static inline void __iomem *t30_channel_aperture(void __iomem *p, int ndx)
+{
+        ndx += NVHOST_CHANNEL_BASE;
+        p += NV_HOST1X_CHANNEL0_BASE;
+        p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
+        return p;
+}
+static int t30_channel_init(struct nvhost_channel *ch,
+                            struct nvhost_master *dev, int index)
+{
+        ch->chid = index;
+        mutex_init(&ch->reflock);
+        mutex_init(&ch->submitlock);
+        ch->aperture = t30_channel_aperture(dev->aperture, index);
+        return t30_nvhost_hwctx_handler_init(ch);
+}
+int nvhost_init_t30_channel_support(struct nvhost_master *host)
+{
+        int result = nvhost_init_t20_channel_support(host);
+        host->op.channel.init = t30_channel_init;
+        return result;
+}
+int nvhost_init_t30_debug_support(struct nvhost_master *host)
+{
+        nvhost_init_t20_debug_support(host);
+        host->op.debug.debug_init = nvhost_scale3d_debug_init;
+        return 0;
+}
+struct nvhost_device *t30_get_nvhost_device(struct nvhost_master *host,
+        char *name)
+{
+        int i;
+        for (i = 0; i < host->nb_channels; i++) {
+                if (strcmp(t30_devices[i].name, name) == 0)
+                        return &t30_devices[i];
+        }
+        return NULL;
+}
+int nvhost_init_t30_support(struct nvhost_master *host)
+{
+        int err;
+        /* don't worry about cleaning up on failure... "remove" does it. */
+        err = nvhost_init_t30_channel_support(host);
+        if (err)
+                return err;
+        err = host1x_init_cdma_support(host);
+        if (err)
+                return err;
+        err = nvhost_init_t30_debug_support(host);
+        if (err)
+                return err;
+        err = host1x_init_syncpt_support(host);
+        if (err)
+                return err;
+        err = nvhost_init_t20_intr_support(host);
+        if (err)
+                return err;
+        host->op.nvhost_dev.get_nvhost_device = t30_get_nvhost_device;
+        return 0;
+}
diff --git a/drivers/video/tegra/host/t30/t30.h b/drivers/video/tegra/host/t30/t30.h
new file mode 100644
index 00000000000..0446dbd19b3
--- /dev/null
+++ b/drivers/video/tegra/host/t30/t30.h
@@ -0,0 +1,29 @@
+/*
+ * drivers/video/tegra/host/t30/t30.h
+ *
+ * Tegra Graphics Chip support for Tegra3
+ *
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _NVHOST_T30_H_
+#define _NVHOST_T30_H_
+struct nvhost_master;
+int nvhost_init_t30_channel_support(struct nvhost_master *);
+int nvhost_init_t30_debug_support(struct nvhost_master *);
+int nvhost_init_t30_support(struct nvhost_master *host);
+#endif /* _NVHOST_T30_H_ */
diff --git a/drivers/video/tegra/host/vi/Makefile b/drivers/video/tegra/host/vi/Makefile
new file mode 100644
index 00000000000..8c130e49814
--- /dev/null
+++ b/drivers/video/tegra/host/vi/Makefile
@@ -0,0 +1,7 @@
+GCOV_PROFILE := y
+EXTRA_CFLAGS += -Idrivers/video/tegra/host
+nvhost-vi-objs  = \
+                vi.o
+obj-$(CONFIG_TEGRA_GRHOST) += nvhost-vi.o
diff --git a/drivers/video/tegra/host/vi/vi.c b/drivers/video/tegra/host/vi/vi.c
new file mode 100644
index 00000000000..71d517152ad
--- /dev/null
+++ b/drivers/video/tegra/host/vi/vi.c
@@ -0,0 +1,82 @@
+/*
+ * drivers/video/tegra/host/vi/vi.c
+ *
+ * Tegra Graphics Host VI
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "dev.h"
+#include "bus_client.h"
+static int __devinit vi_probe(struct nvhost_device *dev)
+{
+        return nvhost_client_device_init(dev);
+}
+static int __exit vi_remove(struct nvhost_device *dev)
+{
+        /* Add clean-up */
+        return 0;
+}
+static int vi_suspend(struct nvhost_device *dev, pm_message_t state)
+{
+        return nvhost_client_device_suspend(dev);
+}
+static int vi_resume(struct nvhost_device *dev)
+{
+        dev_info(&dev->dev, "resuming\n");
+        return 0;
+}
+struct nvhost_device *vi_device;
+static struct nvhost_driver vi_driver = {
+        .probe = vi_probe,
+        .remove = __exit_p(vi_remove),
+#ifdef CONFIG_PM
+        .suspend = vi_suspend,
+        .resume = vi_resume,
+#endif
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "vi",
+        }
+};
+static int __init vi_init(void)
+{
+        int err;
+        vi_device = nvhost_get_device("vi");
+        if (!vi_device)
+                return -ENXIO;
+        err = nvhost_device_register(vi_device);
+        if (err)
+                return err;
+        return nvhost_driver_register(&vi_driver);
+}
+static void __exit vi_exit(void)
+{
+        nvhost_driver_unregister(&vi_driver);
+}
+module_init(vi_init);
+module_exit(vi_exit);