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path: root/drivers/video/tegra/dc/hdmi_reg.h
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-rw-r--r--drivers/video/tegra/dc/hdmi_reg.h478
1 files changed, 478 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/hdmi_reg.h b/drivers/video/tegra/dc/hdmi_reg.h
new file mode 100644
index 00000000000..0bdda43199e
--- /dev/null
+++ b/drivers/video/tegra/dc/hdmi_reg.h
@@ -0,0 +1,478 @@
1/*
2 * drivers/video/tegra/dc/hdmi_reg.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __DRIVERS_VIDEO_TEGRA_DC_HDMI_REG_H
19#define __DRIVERS_VIDEO_TEGRA_DC_HDMI_REG_H
20
21#define HDMI_CTXSW 0x00
22#define HDMI_NV_PDISP_SOR_STATE0 0x01
23#define SOR_STATE_UPDATE (1 << 0)
24
25#define HDMI_NV_PDISP_SOR_STATE1 0x02
26#define SOR_STATE_ASY_HEAD_OPMODE_SLEEP (0 << 0)
27#define SOR_STATE_ASY_HEAD_OPMODE_SNOOSE (1 << 0)
28#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
29#define SOR_STATE_ASY_ORMODE_SAFE (0 << 2)
30#define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
31#define SOR_STATE_ATTACHED (1 << 3)
32#define SOR_STATE_ARM_SHOW_VGA (1 << 4)
33
34#define HDMI_NV_PDISP_SOR_STATE2 0x03
35#define SOR_STATE_ASY_OWNER_NONE (0 << 0)
36#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
37#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
38#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
39#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
40#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
41#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
42#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
43#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
44#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
45#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
46#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
47#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
48#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
49#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
50#define SOR_STATE_ASY_DEPOL_POS (0 << 14)
51#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
52
53#define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
54#define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
55#define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
56#define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
57#define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
58#define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
59#define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
60#define REPEATER (1 << 31)
61#define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
62#define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
63#define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
64#define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
65#define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
66#define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
67#define HDCP_RUN_YES (1 << 0)
68#define CRYPT_ENABLED (1 << 1)
69#define ONEONE_ENABLED (1 << 3)
70#define AN_VALID (1 << 8)
71#define R0_VALID (1 << 9)
72#define SPRIME_VALID (1 << 10)
73#define MPRIME_VALID (1 << 11)
74#define SROM_ERR (1 << 13)
75#define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
76#define TMDS0_LINK0 (1 << 4)
77#define READ_S (1 << 0)
78#define READ_M (2 << 0)
79#define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
80#define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
81#define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
82#define STATUS_CS (1 << 6)
83#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
84#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
85#define HDMI_NV_PDISP_RG_HDCP_RI 0x17
86#define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
87#define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
88#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
89#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
90#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
91#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
92#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
93#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
94#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
95#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
96#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
97#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
98#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
99#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
100#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
101#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
102#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
103#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
104#define INFOFRAME_CTRL_ENABLE (1 << 0)
105#define INFOFRAME_CTRL_OTHER (1 << 4)
106#define INFOFRAME_CTRL_SINGLE (1 << 8)
107
108#define INFOFRAME_HEADER_TYPE(x) ((x) & 0xff)
109#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
110#define INFOFRAME_HEADER_LEN(x) (((x) & 0xf) << 16)
111
112#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
113#define GENERIC_CTRL_ENABLE (1 << 0)
114#define GENERIC_CTRL_OTHER (1 << 4)
115#define GENERIC_CTRL_SINGLE (1 << 8)
116#define GENERIC_CTRL_HBLANK (1 << 12)
117#define GENERIC_CTRL_AUDIO (1 << 16)
118
119#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
120#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
121#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
122#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
123#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f
124#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30
125#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31
126#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32
127#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33
128#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34
129#define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35
130#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36
131#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37
132#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38
133#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39
134#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a
135#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b
136#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c
137#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d
138#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e
139#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f
140#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40
141#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41
142#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42
143#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43
144#define ACR_SB3(x) (((x) & 0xff) << 8)
145#define ACR_SB2(x) (((x) & 0xff) << 16)
146#define ACR_SB1(x) (((x) & 0xff) << 24)
147#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
148
149#define ACR_SB6(x) (((x) & 0xff) << 0)
150#define ACR_SB5(x) (((x) & 0xff) << 8)
151#define ACR_SB4(x) (((x) & 0xff) << 16)
152#define ACR_ENABLE (1 << 31)
153#define ACR_SUBPACK_N(x) ((x) & 0xffffff)
154
155#define HDMI_NV_PDISP_HDMI_CTRL 0x44
156#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
157#define HDMI_CTRL_AUDIO_LAYOUT (1 << 8)
158#define HDMI_CTRL_SAMPLE_FLAT (1 << 12)
159#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
160#define HDMI_CTRL_ENABLE (1 << 30)
161
162#define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45
163#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46
164#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
165#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
166#define VSYNC_WINDOW_ENABLE (1 << 31)
167
168#define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47
169#define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48
170#define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49
171#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a
172#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b
173#define HDMI_NV_PDISP_HDMI_EMU0 0x4c
174#define HDMI_NV_PDISP_HDMI_EMU1 0x4d
175#define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e
176#define HDMI_NV_PDISP_HDMI_SPARE 0x4f
177#define SPARE_HW_CTS (1 << 0)
178#define SPARE_FORCE_SW_CTS (1 << 1)
179#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
180#define SPARE_ACR_PRIORITY_HIGH (0 << 31)
181#define SPARE_ACR_PRIORITY_LOW (1 << 31)
182
183#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50
184#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51
185#define HDMI_NV_PDISP_HDCPRIF_ROM_CTRL 0x53
186#define HDMI_NV_PDISP_SOR_CAP 0x54
187#define HDMI_NV_PDISP_SOR_PWR 0x55
188#define SOR_PWR_NORMAL_STATE_PD (0 << 0)
189#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
190#define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
191#define SOR_PWR_NORMAL_START_ALT (1 << 1)
192#define SOR_PWR_SAFE_STATE_PD (0 << 16)
193#define SOR_PWR_SAFE_STATE_PU (1 << 16)
194#define SOR_PWR_SAFE_START_NORMAL (0 << 17)
195#define SOR_PWR_SAFE_START_ALT (1 << 17)
196#define SOR_PWR_HALT_DELAY (1 << 24)
197#define SOR_PWR_MODE (1 << 28)
198#define SOR_PWR_SETTING_NEW_DONE (0 << 31)
199#define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
200#define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
201
202#define HDMI_NV_PDISP_SOR_TEST 0x56
203#define HDMI_NV_PDISP_SOR_PLL0 0x57
204#define SOR_PLL_PWR (1 << 0)
205#define SOR_PLL_PDBG (1 << 1)
206#define SOR_PLL_VCOPD (1 << 2)
207#define SOR_PLL_PDPORT (1 << 3)
208#define SOR_PLL_RESISTORSEL (1 << 4)
209#define SOR_PLL_PULLDOWN (1 << 5)
210#define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
211#define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
212#define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
213#define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
214#define SOR_PLL_TX_REG_LOAD(x) (((x) & 0x3) << 28)
215
216#define HDMI_NV_PDISP_SOR_PLL1 0x58
217#define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
218#define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
219#define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
220#define SOR_PLL_PE_EN (1 << 28)
221#define SOR_PLL_HALF_FULL_PE (1 << 29)
222#define SOR_PLL_S_D_PIN_PE (1 << 30)
223
224#define HDMI_NV_PDISP_SOR_PLL2 0x59
225#define HDMI_NV_PDISP_SOR_CSTM 0x5a
226#define SOR_CSTM_PD_TXDA_0 (1 << 0)
227#define SOR_CSTM_PD_TXDA_1 (1 << 1)
228#define SOR_CSTM_PD_TXDA_2 (1 << 2)
229#define SOR_CSTM_PD_TXDA_3 (1 << 3)
230#define SOR_CSTM_PD_TXDB_0 (1 << 4)
231#define SOR_CSTM_PD_TXDB_1 (1 << 5)
232#define SOR_CSTM_PD_TXDB_2 (1 << 6)
233#define SOR_CSTM_PD_TXDB_3 (1 << 7)
234#define SOR_CSTM_PD_TXCA (1 << 8)
235#define SOR_CSTM_PD_TXCB (1 << 9)
236#define SOR_CSTM_UPPER (1 << 11)
237#define SOR_CSTM_MODE(x) (((x) & 0x3) << 12)
238#define SOR_CSTM_LINKACTA (1 << 14)
239#define SOR_CSTM_LINKACTB (1 << 15)
240#define SOR_CSTM_LVDS_EN (1 << 16)
241#define SOR_CSTM_DUP_SYNC (1 << 17)
242#define SOR_CSTM_NEW_MODE (1 << 18)
243#define SOR_CSTM_BALANCED (1 << 19)
244#define SOR_CSTM_PLLDIV (1 << 21)
245#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
246#define SOR_CSTM_ROTDAT(x) (((x) & 0x7) << 28)
247
248#define HDMI_NV_PDISP_SOR_LVDS 0x5b
249#define HDMI_NV_PDISP_SOR_CRCA 0x5c
250#define HDMI_NV_PDISP_SOR_CRCB 0x5d
251#define HDMI_NV_PDISP_SOR_BLANK 0x5e
252#define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f
253#define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0)
254#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
255#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
256#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
257#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
258#define SOR_SEQ_STATUS (1 << 28)
259#define SOR_SEQ_SWITCH (1 << 30)
260
261#define HDMI_NV_PDISP_SOR_SEQ_INST0 0x60
262#define HDMI_NV_PDISP_SOR_SEQ_INST1 0x61
263#define HDMI_NV_PDISP_SOR_SEQ_INST2 0x62
264#define HDMI_NV_PDISP_SOR_SEQ_INST3 0x63
265#define HDMI_NV_PDISP_SOR_SEQ_INST4 0x64
266#define HDMI_NV_PDISP_SOR_SEQ_INST5 0x65
267#define HDMI_NV_PDISP_SOR_SEQ_INST6 0x66
268#define HDMI_NV_PDISP_SOR_SEQ_INST7 0x67
269#define HDMI_NV_PDISP_SOR_SEQ_INST8 0x68
270#define HDMI_NV_PDISP_SOR_SEQ_INST9 0x69
271#define HDMI_NV_PDISP_SOR_SEQ_INSTA 0x6a
272#define HDMI_NV_PDISP_SOR_SEQ_INSTB 0x6b
273#define HDMI_NV_PDISP_SOR_SEQ_INSTC 0x6c
274#define HDMI_NV_PDISP_SOR_SEQ_INSTD 0x6d
275#define HDMI_NV_PDISP_SOR_SEQ_INSTE 0x6e
276#define HDMI_NV_PDISP_SOR_SEQ_INSTF 0x6f
277#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
278#define SOR_SEQ_INST_WAIT_UNITS_US (0 << 12)
279#define SOR_SEQ_INST_WAIT_UNITS_MS (1 << 12)
280#define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
281#define SOR_SEQ_INST_HALT (1 << 15)
282#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
283#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
284#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
285#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
286#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
287#define SOR_SEQ_INST_TRISTATE_IOS (1 << 24)
288#define SOR_SEQ_INST_SOR_SEQ_INST_BLACK_DATA (1 << 25)
289#define SOR_SEQ_INST_BLANK_DE (1 << 26)
290#define SOR_SEQ_INST_BLANK_H (1 << 27)
291#define SOR_SEQ_INST_BLANK_V (1 << 28)
292#define SOR_SEQ_INST_ASSERT_PLL_RESETV (1 << 29)
293#define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)
294#define SOR_SEQ_INST_PLL_PULLDOWN (1 << 31)
295
296#define HDMI_NV_PDISP_SOR_VCRCA0 0x72
297#define HDMI_NV_PDISP_SOR_VCRCA1 0x73
298#define HDMI_NV_PDISP_SOR_CCRCA0 0x74
299#define HDMI_NV_PDISP_SOR_CCRCA1 0x75
300#define HDMI_NV_PDISP_SOR_EDATAA0 0x76
301#define HDMI_NV_PDISP_SOR_EDATAA1 0x77
302#define HDMI_NV_PDISP_SOR_COUNTA0 0x78
303#define HDMI_NV_PDISP_SOR_COUNTA1 0x79
304#define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a
305#define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b
306#define HDMI_NV_PDISP_SOR_TRIG 0x7c
307#define HDMI_NV_PDISP_SOR_MSCHECK 0x7d
308#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e
309#define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
310#define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
311#define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
312#define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
313#define DRIVE_CURRENT_FUSE_OVERRIDE (1 << 31)
314#define DRIVE_CURRENT_1_500_mA 0x00
315#define DRIVE_CURRENT_1_875_mA 0x01
316#define DRIVE_CURRENT_2_250_mA 0x02
317#define DRIVE_CURRENT_2_625_mA 0x03
318#define DRIVE_CURRENT_3_000_mA 0x04
319#define DRIVE_CURRENT_3_375_mA 0x05
320#define DRIVE_CURRENT_3_750_mA 0x06
321#define DRIVE_CURRENT_4_125_mA 0x07
322#define DRIVE_CURRENT_4_500_mA 0x08
323#define DRIVE_CURRENT_4_875_mA 0x09
324#define DRIVE_CURRENT_5_250_mA 0x0a
325#define DRIVE_CURRENT_5_625_mA 0x0b
326#define DRIVE_CURRENT_6_000_mA 0x0c
327#define DRIVE_CURRENT_6_375_mA 0x0d
328#define DRIVE_CURRENT_6_750_mA 0x0e
329#define DRIVE_CURRENT_7_125_mA 0x0f
330#define DRIVE_CURRENT_7_500_mA 0x10
331#define DRIVE_CURRENT_7_875_mA 0x11
332#define DRIVE_CURRENT_8_250_mA 0x12
333#define DRIVE_CURRENT_8_625_mA 0x13
334#define DRIVE_CURRENT_9_000_mA 0x14
335#define DRIVE_CURRENT_9_375_mA 0x15
336#define DRIVE_CURRENT_9_750_mA 0x16
337#define DRIVE_CURRENT_10_125_mA 0x17
338#define DRIVE_CURRENT_10_500_mA 0x18
339#define DRIVE_CURRENT_10_875_mA 0x19
340#define DRIVE_CURRENT_11_250_mA 0x1a
341#define DRIVE_CURRENT_11_625_mA 0x1b
342#define DRIVE_CURRENT_12_000_mA 0x1c
343#define DRIVE_CURRENT_12_375_mA 0x1d
344#define DRIVE_CURRENT_12_750_mA 0x1e
345#define DRIVE_CURRENT_13_125_mA 0x1f
346#define DRIVE_CURRENT_13_500_mA 0x20
347#define DRIVE_CURRENT_13_875_mA 0x21
348#define DRIVE_CURRENT_14_250_mA 0x22
349#define DRIVE_CURRENT_14_625_mA 0x23
350#define DRIVE_CURRENT_15_000_mA 0x24
351#define DRIVE_CURRENT_15_375_mA 0x25
352#define DRIVE_CURRENT_15_750_mA 0x26
353#define DRIVE_CURRENT_16_125_mA 0x27
354#define DRIVE_CURRENT_16_500_mA 0x28
355#define DRIVE_CURRENT_16_875_mA 0x29
356#define DRIVE_CURRENT_17_250_mA 0x2a
357#define DRIVE_CURRENT_17_625_mA 0x2b
358#define DRIVE_CURRENT_18_000_mA 0x2c
359#define DRIVE_CURRENT_18_375_mA 0x2d
360#define DRIVE_CURRENT_18_750_mA 0x2e
361#define DRIVE_CURRENT_19_125_mA 0x2f
362#define DRIVE_CURRENT_19_500_mA 0x30
363#define DRIVE_CURRENT_19_875_mA 0x31
364#define DRIVE_CURRENT_20_250_mA 0x32
365#define DRIVE_CURRENT_20_625_mA 0x33
366#define DRIVE_CURRENT_21_000_mA 0x34
367#define DRIVE_CURRENT_21_375_mA 0x35
368#define DRIVE_CURRENT_21_750_mA 0x36
369#define DRIVE_CURRENT_22_125_mA 0x37
370#define DRIVE_CURRENT_22_500_mA 0x38
371#define DRIVE_CURRENT_22_875_mA 0x39
372#define DRIVE_CURRENT_23_250_mA 0x3a
373#define DRIVE_CURRENT_23_625_mA 0x3b
374#define DRIVE_CURRENT_24_000_mA 0x3c
375#define DRIVE_CURRENT_24_375_mA 0x3d
376#define DRIVE_CURRENT_24_750_mA 0x3e
377
378#define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
379#define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
380#define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
381/* note: datasheet defines FS1..FS7. we have FS(0)..FS(6) */
382#define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))
383#define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
384#define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
385
386
387#define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89
388#define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a
389#define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b
390#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
391#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0 0xac
392#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0 0xbc
393#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0 0xbd
394#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0 0xbf
395#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_0 0xc0
396#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_0 0xc1
397#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_0 0xc2
398#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_0 0xc3
399#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_0 0xc4
400#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_0 0xc5
401#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0 0xc6
402#endif
403#define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
404#define AUDIO_CNTRL0_SOFT_RESET (1 << 8)
405#define AUDIO_CNTRL0_SOFT_RESET_ALL (1 << 12)
406#define AUDIO_CNTRL0_SAMPLING_FREQ_UNKNOWN (1 << 16)
407#define AUDIO_CNTRL0_SAMPLING_FREQ_32K (2 << 16)
408#define AUDIO_CNTRL0_SAMPLING_FREQ_44_1K (0 << 16)
409#define AUDIO_CNTRL0_SAMPLING_FREQ_48K (2 << 16)
410#define AUDIO_CNTRL0_SAMPLING_FREQ_88_2K (8 << 16)
411#define AUDIO_CNTRL0_SAMPLING_FREQ_96K (10 << 16)
412#define AUDIO_CNTRL0_SAMPLING_FREQ_176_4K (12 << 16)
413#define AUDIO_CNTRL0_SAMPLING_FREQ_192K (14 << 16)
414#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
415#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
416#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
417#define AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
418#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
419
420#define HDMI_NV_PDISP_AUDIO_N 0x8c
421#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
422#define AUDIO_N_RESETF (1 << 20)
423#define AUDIO_N_GENERATE_NORMAL (0 << 24)
424#define AUDIO_N_GENERATE_ALTERNALTE (1 << 24)
425#define AUDIO_N_LOOKUP_ENABLE (1 << 28)
426
427#define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94
428#define HDMI_NV_PDISP_SOR_REFCLK 0x95
429#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
430#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x3) << 6)
431
432#define HDMI_NV_PDISP_CRC_CONTROL 0x96
433#define HDMI_NV_PDISP_INPUT_CONTROL 0x97
434#define HDMI_SRC_DISPLAYA (0 << 0)
435#define HDMI_SRC_DISPLAYB (1 << 0)
436#define ARM_VIDEO_RANGE_FULL (0 << 1)
437#define ARM_VIDEO_RANGE_LIMITED (1 << 1)
438
439#define HDMI_NV_PDISP_SCRATCH 0x98
440#define HDMI_NV_PDISP_PE_CURRENT 0x99
441#define PE_CURRENT0(x) (((x) & 0xf) << 0)
442#define PE_CURRENT1(x) (((x) & 0xf) << 8)
443#define PE_CURRENT2(x) (((x) & 0xf) << 16)
444#define PE_CURRENT3(x) (((x) & 0xf) << 24)
445#define PE_CURRENT_0_0_mA 0x0
446#define PE_CURRENT_0_5_mA 0x1
447#define PE_CURRENT_1_0_mA 0x2
448#define PE_CURRENT_1_5_mA 0x3
449#define PE_CURRENT_2_0_mA 0x4
450#define PE_CURRENT_2_5_mA 0x5
451#define PE_CURRENT_3_0_mA 0x6
452#define PE_CURRENT_3_5_mA 0x7
453#define PE_CURRENT_4_0_mA 0x8
454#define PE_CURRENT_4_5_mA 0x9
455#define PE_CURRENT_5_0_mA 0xa
456#define PE_CURRENT_5_5_mA 0xb
457#define PE_CURRENT_6_0_mA 0xc
458#define PE_CURRENT_6_5_mA 0xd
459#define PE_CURRENT_7_0_mA 0xe
460#define PE_CURRENT_7_5_mA 0xf
461
462#define HDMI_NV_PDISP_KEY_CTRL 0x9a
463#define LOCAL_KEYS (1 << 0)
464#define AUTOINC (1 << 1)
465#define WRITE16 (1 << 4)
466#define PKEY_REQUEST_RELOAD_TRIGGER (1 << 5)
467#define PKEY_LOADED (1 << 6)
468#define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
469#define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
470#define HDMI_NV_PDISP_KEY_DEBUG2 0x9d
471#define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e
472#define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f
473#define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0
474#define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1
475#define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2
476#define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
477
478#endif