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path: root/drivers/video/mbx/mbxfb.c
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Diffstat (limited to 'drivers/video/mbx/mbxfb.c')
-rw-r--r--drivers/video/mbx/mbxfb.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
index 6849ab75d40..cfc6bf3615b 100644
--- a/drivers/video/mbx/mbxfb.c
+++ b/drivers/video/mbx/mbxfb.c
@@ -118,8 +118,19 @@ static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps,
118 /* convert pixclock to KHz */ 118 /* convert pixclock to KHz */
119 pixclock = PICOS2KHZ(pixclock_ps); 119 pixclock = PICOS2KHZ(pixclock_ps);
120 120
121 /* PLL output freq = (ref_clk * M) / (N * 2^P)
122 *
123 * M: 1 to 63
124 * N: 1 to 7
125 * P: 0 to 7
126 */
127
128 /* RAPH: When N==1, the resulting pixel clock appears to
129 * get divided by 2. Preventing N=1 by starting the following
130 * loop at 2 prevents this. Is this a bug with my chip
131 * revision or something I dont understand? */
121 for (m = 1; m < 64; m++) { 132 for (m = 1; m < 64; m++) {
122 for (n = 1; n < 8; n++) { 133 for (n = 2; n < 8; n++) {
123 for (p = 0; p < 8; p++) { 134 for (p = 0; p < 8; p++) {
124 clk = (ref_clk * m) / (n * (1 << p)); 135 clk = (ref_clk * m) / (n * (1 << p));
125 err = (clk > pixclock) ? (clk - pixclock) : 136 err = (clk > pixclock) ? (clk - pixclock) :