diff options
Diffstat (limited to 'drivers/usb')
-rw-r--r-- | drivers/usb/dwc3/ep0.c | 6 | ||||
-rw-r--r-- | drivers/usb/dwc3/gadget.c | 40 | ||||
-rw-r--r-- | drivers/usb/dwc3/gadget.h | 139 |
3 files changed, 48 insertions, 137 deletions
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 2def48ed30e..69a4e43ddf5 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c | |||
@@ -103,10 +103,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |||
103 | dwc3_trb_to_hw(&trb, trb_hw); | 103 | dwc3_trb_to_hw(&trb, trb_hw); |
104 | 104 | ||
105 | memset(¶ms, 0, sizeof(params)); | 105 | memset(¶ms, 0, sizeof(params)); |
106 | params.param0.depstrtxfer.transfer_desc_addr_high = | 106 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
107 | upper_32_bits(dwc->ep0_trb_addr); | 107 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); |
108 | params.param1.depstrtxfer.transfer_desc_addr_low = | ||
109 | lower_32_bits(dwc->ep0_trb_addr); | ||
110 | 108 | ||
111 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | 109 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
112 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | 110 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); |
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index fd1ac4dd560..fa824cfdd2e 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c | |||
@@ -158,12 +158,12 @@ int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, | |||
158 | 158 | ||
159 | dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", | 159 | dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", |
160 | dep->name, | 160 | dep->name, |
161 | dwc3_gadget_ep_cmd_string(cmd), params->param0.raw, | 161 | dwc3_gadget_ep_cmd_string(cmd), params->param0, |
162 | params->param1.raw, params->param2.raw); | 162 | params->param1, params->param2); |
163 | 163 | ||
164 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0.raw); | 164 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
165 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1.raw); | 165 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); |
166 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2.raw); | 166 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); |
167 | 167 | ||
168 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | 168 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); |
169 | do { | 169 | do { |
@@ -257,21 +257,21 @@ static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |||
257 | 257 | ||
258 | memset(¶ms, 0x00, sizeof(params)); | 258 | memset(¶ms, 0x00, sizeof(params)); |
259 | 259 | ||
260 | params.param0.depcfg.ep_type = usb_endpoint_type(desc); | 260 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
261 | params.param0.depcfg.max_packet_size = usb_endpoint_maxp(desc); | 261 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) |
262 | params.param0.depcfg.burst_size = dep->endpoint.maxburst; | 262 | | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); |
263 | 263 | ||
264 | params.param1.depcfg.xfer_complete_enable = true; | 264 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
265 | params.param1.depcfg.xfer_not_ready_enable = true; | 265 | | DWC3_DEPCFG_XFER_NOT_READY_EN; |
266 | 266 | ||
267 | if (usb_endpoint_xfer_bulk(desc) && dep->endpoint.max_streams) { | 267 | if (usb_endpoint_xfer_bulk(desc) && dep->endpoint.max_streams) { |
268 | params.param1.depcfg.stream_capable = true; | 268 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
269 | params.param1.depcfg.stream_event_enable = true; | 269 | | DWC3_DEPCFG_STREAM_EVENT_EN; |
270 | dep->stream_capable = true; | 270 | dep->stream_capable = true; |
271 | } | 271 | } |
272 | 272 | ||
273 | if (usb_endpoint_xfer_isoc(desc)) | 273 | if (usb_endpoint_xfer_isoc(desc)) |
274 | params.param1.depcfg.xfer_in_progress_enable = true; | 274 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
275 | 275 | ||
276 | /* | 276 | /* |
277 | * We are doing 1:1 mapping for endpoints, meaning | 277 | * We are doing 1:1 mapping for endpoints, meaning |
@@ -279,17 +279,17 @@ static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |||
279 | * so on. We consider the direction bit as part of the physical | 279 | * so on. We consider the direction bit as part of the physical |
280 | * endpoint number. So USB endpoint 0x81 is 0x03. | 280 | * endpoint number. So USB endpoint 0x81 is 0x03. |
281 | */ | 281 | */ |
282 | params.param1.depcfg.ep_number = dep->number; | 282 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
283 | 283 | ||
284 | /* | 284 | /* |
285 | * We must use the lower 16 TX FIFOs even though | 285 | * We must use the lower 16 TX FIFOs even though |
286 | * HW might have more | 286 | * HW might have more |
287 | */ | 287 | */ |
288 | if (dep->direction) | 288 | if (dep->direction) |
289 | params.param0.depcfg.fifo_number = dep->number >> 1; | 289 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
290 | 290 | ||
291 | if (desc->bInterval) { | 291 | if (desc->bInterval) { |
292 | params.param1.depcfg.binterval_m1 = desc->bInterval - 1; | 292 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
293 | dep->interval = 1 << (desc->bInterval - 1); | 293 | dep->interval = 1 << (desc->bInterval - 1); |
294 | } | 294 | } |
295 | 295 | ||
@@ -303,7 +303,7 @@ static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |||
303 | 303 | ||
304 | memset(¶ms, 0x00, sizeof(params)); | 304 | memset(¶ms, 0x00, sizeof(params)); |
305 | 305 | ||
306 | params.param0.depxfercfg.number_xfer_resources = 1; | 306 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
307 | 307 | ||
308 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | 308 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, |
309 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | 309 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); |
@@ -719,10 +719,8 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |||
719 | } | 719 | } |
720 | 720 | ||
721 | memset(¶ms, 0, sizeof(params)); | 721 | memset(¶ms, 0, sizeof(params)); |
722 | params.param0.depstrtxfer.transfer_desc_addr_high = | 722 | params.param0 = upper_32_bits(req->trb_dma); |
723 | upper_32_bits(req->trb_dma); | 723 | params.param1 = lower_32_bits(req->trb_dma); |
724 | params.param1.depstrtxfer.transfer_desc_addr_low = | ||
725 | lower_32_bits(req->trb_dma); | ||
726 | 724 | ||
727 | if (start_new) | 725 | if (start_new) |
728 | cmd = DWC3_DEPCMD_STARTTRANSFER; | 726 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index b025651e013..71145a449d9 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h | |||
@@ -47,120 +47,35 @@ struct dwc3; | |||
47 | #define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint)) | 47 | #define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint)) |
48 | #define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget)) | 48 | #define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget)) |
49 | 49 | ||
50 | /** | 50 | /* DEPCFG parameter 1 */ |
51 | * struct dwc3_gadget_ep_depcfg_param1 - DEPCMDPAR0 for DEPCFG command | 51 | #define DWC3_DEPCFG_INT_NUM(n) ((n) << 0) |
52 | * @interrupt_number: self-explanatory | 52 | #define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8) |
53 | * @reserved7_5: set to zero | 53 | #define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9) |
54 | * @xfer_complete_enable: event generated when transfer completed | 54 | #define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10) |
55 | * @xfer_in_progress_enable: event generated when transfer in progress | 55 | #define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11) |
56 | * @xfer_not_ready_enable: event generated when transfer not read | 56 | #define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13) |
57 | * @fifo_error_enable: generates events when FIFO Underrun (IN eps) | 57 | #define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16) |
58 | * or FIFO Overrun (OUT) eps | 58 | #define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24) |
59 | * @reserved_12: set to zero | 59 | #define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25) |
60 | * @stream_event_enable: event generated on stream | 60 | #define DWC3_DEPCFG_BULK_BASED (1 << 30) |
61 | * @reserved14_15: set to zero | 61 | #define DWC3_DEPCFG_FIFO_BASED (1 << 31) |
62 | * @binterval_m1: bInterval minus 1 | 62 | |
63 | * @stream_capable: this EP is capable of handling streams | 63 | /* DEPCFG parameter 0 */ |
64 | * @ep_number: self-explanatory | 64 | #define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1) |
65 | * @bulk_based: Set to ‘1’ if this isochronous endpoint represents a bulk | 65 | #define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3) |
66 | * data stream that ignores the relationship of bus time to the | 66 | #define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17) |
67 | * intervals programmed in TRBs. | 67 | #define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22) |
68 | * @fifo_based: Set to ‘1’ if this isochronous endpoint represents a | 68 | #define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) |
69 | * FIFO-based data stream where TRBs have fixed values and are never | 69 | #define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31) |
70 | * written back by the core. | 70 | |
71 | */ | 71 | /* DEPXFERCFG parameter 0 */ |
72 | struct dwc3_gadget_ep_depcfg_param1 { | 72 | #define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff) |
73 | u32 interrupt_number:5; | ||
74 | u32 reserved7_5:3; /* set to zero */ | ||
75 | u32 xfer_complete_enable:1; | ||
76 | u32 xfer_in_progress_enable:1; | ||
77 | u32 xfer_not_ready_enable:1; | ||
78 | u32 fifo_error_enable:1; /* IN-underrun, OUT-overrun */ | ||
79 | u32 reserved12:1; /* set to zero */ | ||
80 | u32 stream_event_enable:1; | ||
81 | u32 reserved14_15:2; | ||
82 | u32 binterval_m1:8; /* bInterval minus 1 */ | ||
83 | u32 stream_capable:1; | ||
84 | u32 ep_number:5; | ||
85 | u32 bulk_based:1; | ||
86 | u32 fifo_based:1; | ||
87 | } __packed; | ||
88 | |||
89 | /** | ||
90 | * struct dwc3_gadget_ep_depcfg_param0 - Parameter 0 for DEPCFG | ||
91 | * @reserved0: set to zero | ||
92 | * @ep_type: Endpoint Type (control, bulk, iso, interrupt) | ||
93 | * @max_packet_size: max packet size in bytes | ||
94 | * @reserved16_14: set to zero | ||
95 | * @fifo_number: self-explanatory | ||
96 | * @burst_size: burst size minus 1 | ||
97 | * @data_sequence_number: Must be 0 when an endpoint is initially configured | ||
98 | * May be non-zero when an endpoint is configured after a power transition | ||
99 | * that requires a save/restore. | ||
100 | * @ignore_sequence_number: Set to ‘1’ to avoid resetting the sequence | ||
101 | * number. This setting is used by software to modify the DEPEVTEN | ||
102 | * event enable bits without modifying other endpoint settings. | ||
103 | */ | ||
104 | struct dwc3_gadget_ep_depcfg_param0 { | ||
105 | u32 reserved0:1; | ||
106 | u32 ep_type:2; | ||
107 | u32 max_packet_size:11; | ||
108 | u32 reserved16_14:3; | ||
109 | u32 fifo_number:5; | ||
110 | u32 burst_size:4; | ||
111 | u32 data_sequence_number:5; | ||
112 | u32 ignore_sequence_number:1; | ||
113 | } __packed; | ||
114 | |||
115 | /** | ||
116 | * struct dwc3_gadget_ep_depxfercfg_param0 - Parameter 0 of DEPXFERCFG | ||
117 | * @number_xfer_resources: Defines the number of Transfer Resources allocated | ||
118 | * to this endpoint. This field must be set to 1. | ||
119 | * @reserved16_31: set to zero; | ||
120 | */ | ||
121 | struct dwc3_gadget_ep_depxfercfg_param0 { | ||
122 | u32 number_xfer_resources:16; | ||
123 | u32 reserved16_31:16; | ||
124 | } __packed; | ||
125 | |||
126 | /** | ||
127 | * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER | ||
128 | * @transfer_desc_addr_low: Indicates the lower 32 bits of the external | ||
129 | * memory's start address for the transfer descriptor. Because TRBs | ||
130 | * must be aligned to a 16-byte boundary, the lower 4 bits of this | ||
131 | * address must be 0. | ||
132 | */ | ||
133 | struct dwc3_gadget_ep_depstrtxfer_param1 { | ||
134 | u32 transfer_desc_addr_low; | ||
135 | } __packed; | ||
136 | |||
137 | /** | ||
138 | * struct dwc3_gadget_ep_depstrtxfer_param1 - Parameter 1 of DEPSTRTXFER | ||
139 | * @transfer_desc_addr_high: Indicates the higher 32 bits of the external | ||
140 | * memory’s start address for the transfer descriptor. | ||
141 | */ | ||
142 | struct dwc3_gadget_ep_depstrtxfer_param0 { | ||
143 | u32 transfer_desc_addr_high; | ||
144 | } __packed; | ||
145 | 73 | ||
146 | struct dwc3_gadget_ep_cmd_params { | 74 | struct dwc3_gadget_ep_cmd_params { |
147 | union { | 75 | u32 param2; |
148 | u32 raw; | 76 | u32 param1; |
149 | } param2; | 77 | u32 param0; |
150 | 78 | }; | |
151 | union { | ||
152 | u32 raw; | ||
153 | struct dwc3_gadget_ep_depcfg_param1 depcfg; | ||
154 | struct dwc3_gadget_ep_depstrtxfer_param1 depstrtxfer; | ||
155 | } param1; | ||
156 | |||
157 | union { | ||
158 | u32 raw; | ||
159 | struct dwc3_gadget_ep_depcfg_param0 depcfg; | ||
160 | struct dwc3_gadget_ep_depxfercfg_param0 depxfercfg; | ||
161 | struct dwc3_gadget_ep_depstrtxfer_param0 depstrtxfer; | ||
162 | } param0; | ||
163 | } __packed; | ||
164 | 79 | ||
165 | /* -------------------------------------------------------------------------- */ | 80 | /* -------------------------------------------------------------------------- */ |
166 | 81 | ||