diff options
Diffstat (limited to 'drivers/usb/gadget/s3c-hsotg.h')
| -rw-r--r-- | drivers/usb/gadget/s3c-hsotg.h | 377 |
1 files changed, 377 insertions, 0 deletions
diff --git a/drivers/usb/gadget/s3c-hsotg.h b/drivers/usb/gadget/s3c-hsotg.h new file mode 100644 index 00000000000..d650b129583 --- /dev/null +++ b/drivers/usb/gadget/s3c-hsotg.h | |||
| @@ -0,0 +1,377 @@ | |||
| 1 | /* drivers/usb/gadget/s3c-hsotg.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * USB2.0 Highspeed/OtG Synopsis DWC2 device block registers | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __REGS_USB_HSOTG_H | ||
| 16 | #define __REGS_USB_HSOTG_H __FILE__ | ||
| 17 | |||
| 18 | #define HSOTG_REG(x) (x) | ||
| 19 | |||
| 20 | #define GOTGCTL HSOTG_REG(0x000) | ||
| 21 | #define GOTGCTL_BSESVLD (1 << 19) | ||
| 22 | #define GOTGCTL_ASESVLD (1 << 18) | ||
| 23 | #define GOTGCTL_DBNC_SHORT (1 << 17) | ||
| 24 | #define GOTGCTL_CONID_B (1 << 16) | ||
| 25 | #define GOTGCTL_DEVHNPEN (1 << 11) | ||
| 26 | #define GOTGCTL_HSSETHNPEN (1 << 10) | ||
| 27 | #define GOTGCTL_HNPREQ (1 << 9) | ||
| 28 | #define GOTGCTL_HSTNEGSCS (1 << 8) | ||
| 29 | #define GOTGCTL_SESREQ (1 << 1) | ||
| 30 | #define GOTGCTL_SESREQSCS (1 << 0) | ||
| 31 | |||
| 32 | #define GOTGINT HSOTG_REG(0x004) | ||
| 33 | #define GOTGINT_DbnceDone (1 << 19) | ||
| 34 | #define GOTGINT_ADevTOUTChg (1 << 18) | ||
| 35 | #define GOTGINT_HstNegDet (1 << 17) | ||
| 36 | #define GOTGINT_HstnegSucStsChng (1 << 9) | ||
| 37 | #define GOTGINT_SesReqSucStsChng (1 << 8) | ||
| 38 | #define GOTGINT_SesEndDet (1 << 2) | ||
| 39 | |||
| 40 | #define GAHBCFG HSOTG_REG(0x008) | ||
| 41 | #define GAHBCFG_PTxFEmpLvl (1 << 8) | ||
| 42 | #define GAHBCFG_NPTxFEmpLvl (1 << 7) | ||
| 43 | #define GAHBCFG_DMAEn (1 << 5) | ||
| 44 | #define GAHBCFG_HBstLen_MASK (0xf << 1) | ||
| 45 | #define GAHBCFG_HBstLen_SHIFT (1) | ||
| 46 | #define GAHBCFG_HBstLen_Single (0x0 << 1) | ||
| 47 | #define GAHBCFG_HBstLen_Incr (0x1 << 1) | ||
| 48 | #define GAHBCFG_HBstLen_Incr4 (0x3 << 1) | ||
| 49 | #define GAHBCFG_HBstLen_Incr8 (0x5 << 1) | ||
| 50 | #define GAHBCFG_HBstLen_Incr16 (0x7 << 1) | ||
| 51 | #define GAHBCFG_GlblIntrEn (1 << 0) | ||
| 52 | |||
| 53 | #define GUSBCFG HSOTG_REG(0x00C) | ||
| 54 | #define GUSBCFG_PHYLPClkSel (1 << 15) | ||
| 55 | #define GUSBCFG_HNPCap (1 << 9) | ||
| 56 | #define GUSBCFG_SRPCap (1 << 8) | ||
| 57 | #define GUSBCFG_PHYIf16 (1 << 3) | ||
| 58 | #define GUSBCFG_TOutCal_MASK (0x7 << 0) | ||
| 59 | #define GUSBCFG_TOutCal_SHIFT (0) | ||
| 60 | #define GUSBCFG_TOutCal_LIMIT (0x7) | ||
| 61 | #define GUSBCFG_TOutCal(_x) ((_x) << 0) | ||
| 62 | |||
| 63 | #define GRSTCTL HSOTG_REG(0x010) | ||
| 64 | |||
| 65 | #define GRSTCTL_AHBIdle (1 << 31) | ||
| 66 | #define GRSTCTL_DMAReq (1 << 30) | ||
| 67 | #define GRSTCTL_TxFNum_MASK (0x1f << 6) | ||
| 68 | #define GRSTCTL_TxFNum_SHIFT (6) | ||
| 69 | #define GRSTCTL_TxFNum_LIMIT (0x1f) | ||
| 70 | #define GRSTCTL_TxFNum(_x) ((_x) << 6) | ||
| 71 | #define GRSTCTL_TxFFlsh (1 << 5) | ||
| 72 | #define GRSTCTL_RxFFlsh (1 << 4) | ||
| 73 | #define GRSTCTL_INTknQFlsh (1 << 3) | ||
| 74 | #define GRSTCTL_FrmCntrRst (1 << 2) | ||
| 75 | #define GRSTCTL_HSftRst (1 << 1) | ||
| 76 | #define GRSTCTL_CSftRst (1 << 0) | ||
| 77 | |||
| 78 | #define GINTSTS HSOTG_REG(0x014) | ||
| 79 | #define GINTMSK HSOTG_REG(0x018) | ||
| 80 | |||
| 81 | #define GINTSTS_WkUpInt (1 << 31) | ||
| 82 | #define GINTSTS_SessReqInt (1 << 30) | ||
| 83 | #define GINTSTS_DisconnInt (1 << 29) | ||
| 84 | #define GINTSTS_ConIDStsChng (1 << 28) | ||
| 85 | #define GINTSTS_PTxFEmp (1 << 26) | ||
| 86 | #define GINTSTS_HChInt (1 << 25) | ||
| 87 | #define GINTSTS_PrtInt (1 << 24) | ||
| 88 | #define GINTSTS_FetSusp (1 << 22) | ||
| 89 | #define GINTSTS_incompIP (1 << 21) | ||
| 90 | #define GINTSTS_IncomplSOIN (1 << 20) | ||
| 91 | #define GINTSTS_OEPInt (1 << 19) | ||
| 92 | #define GINTSTS_IEPInt (1 << 18) | ||
| 93 | #define GINTSTS_EPMis (1 << 17) | ||
| 94 | #define GINTSTS_EOPF (1 << 15) | ||
| 95 | #define GINTSTS_ISOutDrop (1 << 14) | ||
| 96 | #define GINTSTS_EnumDone (1 << 13) | ||
| 97 | #define GINTSTS_USBRst (1 << 12) | ||
| 98 | #define GINTSTS_USBSusp (1 << 11) | ||
| 99 | #define GINTSTS_ErlySusp (1 << 10) | ||
| 100 | #define GINTSTS_GOUTNakEff (1 << 7) | ||
| 101 | #define GINTSTS_GINNakEff (1 << 6) | ||
| 102 | #define GINTSTS_NPTxFEmp (1 << 5) | ||
| 103 | #define GINTSTS_RxFLvl (1 << 4) | ||
| 104 | #define GINTSTS_SOF (1 << 3) | ||
| 105 | #define GINTSTS_OTGInt (1 << 2) | ||
| 106 | #define GINTSTS_ModeMis (1 << 1) | ||
| 107 | #define GINTSTS_CurMod_Host (1 << 0) | ||
| 108 | |||
| 109 | #define GRXSTSR HSOTG_REG(0x01C) | ||
| 110 | #define GRXSTSP HSOTG_REG(0x020) | ||
| 111 | |||
| 112 | #define GRXSTS_FN_MASK (0x7f << 25) | ||
| 113 | #define GRXSTS_FN_SHIFT (25) | ||
| 114 | |||
| 115 | #define GRXSTS_PktSts_MASK (0xf << 17) | ||
| 116 | #define GRXSTS_PktSts_SHIFT (17) | ||
| 117 | #define GRXSTS_PktSts_GlobalOutNAK (0x1 << 17) | ||
| 118 | #define GRXSTS_PktSts_OutRX (0x2 << 17) | ||
| 119 | #define GRXSTS_PktSts_OutDone (0x3 << 17) | ||
| 120 | #define GRXSTS_PktSts_SetupDone (0x4 << 17) | ||
| 121 | #define GRXSTS_PktSts_SetupRX (0x6 << 17) | ||
| 122 | |||
| 123 | #define GRXSTS_DPID_MASK (0x3 << 15) | ||
| 124 | #define GRXSTS_DPID_SHIFT (15) | ||
| 125 | #define GRXSTS_ByteCnt_MASK (0x7ff << 4) | ||
| 126 | #define GRXSTS_ByteCnt_SHIFT (4) | ||
| 127 | #define GRXSTS_EPNum_MASK (0xf << 0) | ||
| 128 | #define GRXSTS_EPNum_SHIFT (0) | ||
| 129 | |||
| 130 | #define GRXFSIZ HSOTG_REG(0x024) | ||
| 131 | |||
| 132 | #define GNPTXFSIZ HSOTG_REG(0x028) | ||
| 133 | |||
| 134 | #define GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16) | ||
| 135 | #define GNPTXFSIZ_NPTxFDep_SHIFT (16) | ||
| 136 | #define GNPTXFSIZ_NPTxFDep_LIMIT (0xffff) | ||
| 137 | #define GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16) | ||
| 138 | #define GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0) | ||
| 139 | #define GNPTXFSIZ_NPTxFStAddr_SHIFT (0) | ||
| 140 | #define GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff) | ||
| 141 | #define GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0) | ||
| 142 | |||
| 143 | #define GNPTXSTS HSOTG_REG(0x02C) | ||
| 144 | |||
| 145 | #define GNPTXSTS_NPtxQTop_MASK (0x7f << 24) | ||
| 146 | #define GNPTXSTS_NPtxQTop_SHIFT (24) | ||
| 147 | |||
| 148 | #define GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16) | ||
| 149 | #define GNPTXSTS_NPTxQSpcAvail_SHIFT (16) | ||
| 150 | #define GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff) | ||
| 151 | |||
| 152 | #define GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0) | ||
| 153 | #define GNPTXSTS_NPTxFSpcAvail_SHIFT (0) | ||
| 154 | #define GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff) | ||
| 155 | |||
| 156 | |||
| 157 | #define HPTXFSIZ HSOTG_REG(0x100) | ||
| 158 | |||
| 159 | #define DPTXFSIZn(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) | ||
| 160 | |||
| 161 | #define DPTXFSIZn_DPTxFSize_MASK (0xffff << 16) | ||
| 162 | #define DPTXFSIZn_DPTxFSize_SHIFT (16) | ||
| 163 | #define DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff) | ||
| 164 | #define DPTXFSIZn_DPTxFSize_LIMIT (0xffff) | ||
| 165 | #define DPTXFSIZn_DPTxFSize(_x) ((_x) << 16) | ||
| 166 | |||
| 167 | #define DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0) | ||
| 168 | #define DPTXFSIZn_DPTxFStAddr_SHIFT (0) | ||
| 169 | |||
| 170 | /* Device mode registers */ | ||
| 171 | #define DCFG HSOTG_REG(0x800) | ||
| 172 | |||
| 173 | #define DCFG_EPMisCnt_MASK (0x1f << 18) | ||
| 174 | #define DCFG_EPMisCnt_SHIFT (18) | ||
| 175 | #define DCFG_EPMisCnt_LIMIT (0x1f) | ||
| 176 | #define DCFG_EPMisCnt(_x) ((_x) << 18) | ||
| 177 | |||
| 178 | #define DCFG_PerFrInt_MASK (0x3 << 11) | ||
| 179 | #define DCFG_PerFrInt_SHIFT (11) | ||
| 180 | #define DCFG_PerFrInt_LIMIT (0x3) | ||
| 181 | #define DCFG_PerFrInt(_x) ((_x) << 11) | ||
| 182 | |||
| 183 | #define DCFG_DevAddr_MASK (0x7f << 4) | ||
| 184 | #define DCFG_DevAddr_SHIFT (4) | ||
| 185 | #define DCFG_DevAddr_LIMIT (0x7f) | ||
| 186 | #define DCFG_DevAddr(_x) ((_x) << 4) | ||
| 187 | |||
| 188 | #define DCFG_NZStsOUTHShk (1 << 2) | ||
| 189 | |||
| 190 | #define DCFG_DevSpd_MASK (0x3 << 0) | ||
| 191 | #define DCFG_DevSpd_SHIFT (0) | ||
| 192 | #define DCFG_DevSpd_HS (0x0 << 0) | ||
| 193 | #define DCFG_DevSpd_FS (0x1 << 0) | ||
| 194 | #define DCFG_DevSpd_LS (0x2 << 0) | ||
| 195 | #define DCFG_DevSpd_FS48 (0x3 << 0) | ||
| 196 | |||
| 197 | #define DCTL HSOTG_REG(0x804) | ||
| 198 | |||
| 199 | #define DCTL_PWROnPrgDone (1 << 11) | ||
| 200 | #define DCTL_CGOUTNak (1 << 10) | ||
| 201 | #define DCTL_SGOUTNak (1 << 9) | ||
| 202 | #define DCTL_CGNPInNAK (1 << 8) | ||
| 203 | #define DCTL_SGNPInNAK (1 << 7) | ||
| 204 | #define DCTL_TstCtl_MASK (0x7 << 4) | ||
| 205 | #define DCTL_TstCtl_SHIFT (4) | ||
| 206 | #define DCTL_GOUTNakSts (1 << 3) | ||
| 207 | #define DCTL_GNPINNakSts (1 << 2) | ||
| 208 | #define DCTL_SftDiscon (1 << 1) | ||
| 209 | #define DCTL_RmtWkUpSig (1 << 0) | ||
| 210 | |||
| 211 | #define DSTS HSOTG_REG(0x808) | ||
| 212 | |||
| 213 | #define DSTS_SOFFN_MASK (0x3fff << 8) | ||
| 214 | #define DSTS_SOFFN_SHIFT (8) | ||
| 215 | #define DSTS_SOFFN_LIMIT (0x3fff) | ||
| 216 | #define DSTS_SOFFN(_x) ((_x) << 8) | ||
| 217 | #define DSTS_ErraticErr (1 << 3) | ||
| 218 | #define DSTS_EnumSpd_MASK (0x3 << 1) | ||
| 219 | #define DSTS_EnumSpd_SHIFT (1) | ||
| 220 | #define DSTS_EnumSpd_HS (0x0 << 1) | ||
| 221 | #define DSTS_EnumSpd_FS (0x1 << 1) | ||
| 222 | #define DSTS_EnumSpd_LS (0x2 << 1) | ||
| 223 | #define DSTS_EnumSpd_FS48 (0x3 << 1) | ||
| 224 | |||
| 225 | #define DSTS_SuspSts (1 << 0) | ||
| 226 | |||
| 227 | #define DIEPMSK HSOTG_REG(0x810) | ||
| 228 | |||
| 229 | #define DIEPMSK_TxFIFOEmpty (1 << 7) | ||
| 230 | #define DIEPMSK_INEPNakEffMsk (1 << 6) | ||
| 231 | #define DIEPMSK_INTknEPMisMsk (1 << 5) | ||
| 232 | #define DIEPMSK_INTknTXFEmpMsk (1 << 4) | ||
| 233 | #define DIEPMSK_TimeOUTMsk (1 << 3) | ||
| 234 | #define DIEPMSK_AHBErrMsk (1 << 2) | ||
| 235 | #define DIEPMSK_EPDisbldMsk (1 << 1) | ||
| 236 | #define DIEPMSK_XferComplMsk (1 << 0) | ||
| 237 | |||
| 238 | #define DOEPMSK HSOTG_REG(0x814) | ||
| 239 | |||
| 240 | #define DOEPMSK_Back2BackSetup (1 << 6) | ||
| 241 | #define DOEPMSK_OUTTknEPdisMsk (1 << 4) | ||
| 242 | #define DOEPMSK_SetupMsk (1 << 3) | ||
| 243 | #define DOEPMSK_AHBErrMsk (1 << 2) | ||
| 244 | #define DOEPMSK_EPDisbldMsk (1 << 1) | ||
| 245 | #define DOEPMSK_XferComplMsk (1 << 0) | ||
| 246 | |||
| 247 | #define DAINT HSOTG_REG(0x818) | ||
| 248 | #define DAINTMSK HSOTG_REG(0x81C) | ||
| 249 | |||
| 250 | #define DAINT_OutEP_SHIFT (16) | ||
| 251 | #define DAINT_OutEP(x) (1 << ((x) + 16)) | ||
| 252 | #define DAINT_InEP(x) (1 << (x)) | ||
| 253 | |||
| 254 | #define DTKNQR1 HSOTG_REG(0x820) | ||
| 255 | #define DTKNQR2 HSOTG_REG(0x824) | ||
| 256 | #define DTKNQR3 HSOTG_REG(0x830) | ||
| 257 | #define DTKNQR4 HSOTG_REG(0x834) | ||
| 258 | |||
| 259 | #define DVBUSDIS HSOTG_REG(0x828) | ||
| 260 | #define DVBUSPULSE HSOTG_REG(0x82C) | ||
| 261 | |||
| 262 | #define DIEPCTL0 HSOTG_REG(0x900) | ||
| 263 | #define DOEPCTL0 HSOTG_REG(0xB00) | ||
| 264 | #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) | ||
| 265 | #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) | ||
| 266 | |||
| 267 | /* EP0 specialness: | ||
| 268 | * bits[29..28] - reserved (no SetD0PID, SetD1PID) | ||
| 269 | * bits[25..22] - should always be zero, this isn't a periodic endpoint | ||
| 270 | * bits[10..0] - MPS setting differenct for EP0 | ||
| 271 | */ | ||
| 272 | #define D0EPCTL_MPS_MASK (0x3 << 0) | ||
| 273 | #define D0EPCTL_MPS_SHIFT (0) | ||
| 274 | #define D0EPCTL_MPS_64 (0x0 << 0) | ||
| 275 | #define D0EPCTL_MPS_32 (0x1 << 0) | ||
| 276 | #define D0EPCTL_MPS_16 (0x2 << 0) | ||
| 277 | #define D0EPCTL_MPS_8 (0x3 << 0) | ||
| 278 | |||
| 279 | #define DxEPCTL_EPEna (1 << 31) | ||
| 280 | #define DxEPCTL_EPDis (1 << 30) | ||
| 281 | #define DxEPCTL_SetD1PID (1 << 29) | ||
| 282 | #define DxEPCTL_SetOddFr (1 << 29) | ||
| 283 | #define DxEPCTL_SetD0PID (1 << 28) | ||
| 284 | #define DxEPCTL_SetEvenFr (1 << 28) | ||
| 285 | #define DxEPCTL_SNAK (1 << 27) | ||
| 286 | #define DxEPCTL_CNAK (1 << 26) | ||
| 287 | #define DxEPCTL_TxFNum_MASK (0xf << 22) | ||
| 288 | #define DxEPCTL_TxFNum_SHIFT (22) | ||
| 289 | #define DxEPCTL_TxFNum_LIMIT (0xf) | ||
| 290 | #define DxEPCTL_TxFNum(_x) ((_x) << 22) | ||
| 291 | |||
| 292 | #define DxEPCTL_Stall (1 << 21) | ||
| 293 | #define DxEPCTL_Snp (1 << 20) | ||
| 294 | #define DxEPCTL_EPType_MASK (0x3 << 18) | ||
| 295 | #define DxEPCTL_EPType_SHIFT (18) | ||
| 296 | #define DxEPCTL_EPType_Control (0x0 << 18) | ||
| 297 | #define DxEPCTL_EPType_Iso (0x1 << 18) | ||
| 298 | #define DxEPCTL_EPType_Bulk (0x2 << 18) | ||
| 299 | #define DxEPCTL_EPType_Intterupt (0x3 << 18) | ||
| 300 | |||
| 301 | #define DxEPCTL_NAKsts (1 << 17) | ||
| 302 | #define DxEPCTL_DPID (1 << 16) | ||
| 303 | #define DxEPCTL_EOFrNum (1 << 16) | ||
| 304 | #define DxEPCTL_USBActEp (1 << 15) | ||
| 305 | #define DxEPCTL_NextEp_MASK (0xf << 11) | ||
| 306 | #define DxEPCTL_NextEp_SHIFT (11) | ||
| 307 | #define DxEPCTL_NextEp_LIMIT (0xf) | ||
| 308 | #define DxEPCTL_NextEp(_x) ((_x) << 11) | ||
| 309 | |||
| 310 | #define DxEPCTL_MPS_MASK (0x7ff << 0) | ||
| 311 | #define DxEPCTL_MPS_SHIFT (0) | ||
| 312 | #define DxEPCTL_MPS_LIMIT (0x7ff) | ||
| 313 | #define DxEPCTL_MPS(_x) ((_x) << 0) | ||
| 314 | |||
| 315 | #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) | ||
| 316 | #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) | ||
| 317 | |||
| 318 | #define DxEPINT_INEPNakEff (1 << 6) | ||
| 319 | #define DxEPINT_Back2BackSetup (1 << 6) | ||
| 320 | #define DxEPINT_INTknEPMis (1 << 5) | ||
| 321 | #define DxEPINT_INTknTXFEmp (1 << 4) | ||
| 322 | #define DxEPINT_OUTTknEPdis (1 << 4) | ||
| 323 | #define DxEPINT_Timeout (1 << 3) | ||
| 324 | #define DxEPINT_Setup (1 << 3) | ||
| 325 | #define DxEPINT_AHBErr (1 << 2) | ||
| 326 | #define DxEPINT_EPDisbld (1 << 1) | ||
| 327 | #define DxEPINT_XferCompl (1 << 0) | ||
| 328 | |||
| 329 | #define DIEPTSIZ0 HSOTG_REG(0x910) | ||
| 330 | |||
| 331 | #define DIEPTSIZ0_PktCnt_MASK (0x3 << 19) | ||
| 332 | #define DIEPTSIZ0_PktCnt_SHIFT (19) | ||
| 333 | #define DIEPTSIZ0_PktCnt_LIMIT (0x3) | ||
| 334 | #define DIEPTSIZ0_PktCnt(_x) ((_x) << 19) | ||
| 335 | |||
| 336 | #define DIEPTSIZ0_XferSize_MASK (0x7f << 0) | ||
| 337 | #define DIEPTSIZ0_XferSize_SHIFT (0) | ||
| 338 | #define DIEPTSIZ0_XferSize_LIMIT (0x7f) | ||
| 339 | #define DIEPTSIZ0_XferSize(_x) ((_x) << 0) | ||
| 340 | |||
| 341 | #define DOEPTSIZ0 HSOTG_REG(0xB10) | ||
| 342 | #define DOEPTSIZ0_SUPCnt_MASK (0x3 << 29) | ||
| 343 | #define DOEPTSIZ0_SUPCnt_SHIFT (29) | ||
| 344 | #define DOEPTSIZ0_SUPCnt_LIMIT (0x3) | ||
| 345 | #define DOEPTSIZ0_SUPCnt(_x) ((_x) << 29) | ||
| 346 | |||
| 347 | #define DOEPTSIZ0_PktCnt (1 << 19) | ||
| 348 | #define DOEPTSIZ0_XferSize_MASK (0x7f << 0) | ||
| 349 | #define DOEPTSIZ0_XferSize_SHIFT (0) | ||
| 350 | |||
| 351 | #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) | ||
| 352 | #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) | ||
| 353 | |||
| 354 | #define DxEPTSIZ_MC_MASK (0x3 << 29) | ||
| 355 | #define DxEPTSIZ_MC_SHIFT (29) | ||
| 356 | #define DxEPTSIZ_MC_LIMIT (0x3) | ||
| 357 | #define DxEPTSIZ_MC(_x) ((_x) << 29) | ||
| 358 | |||
| 359 | #define DxEPTSIZ_PktCnt_MASK (0x3ff << 19) | ||
| 360 | #define DxEPTSIZ_PktCnt_SHIFT (19) | ||
| 361 | #define DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff) | ||
| 362 | #define DxEPTSIZ_PktCnt_LIMIT (0x3ff) | ||
| 363 | #define DxEPTSIZ_PktCnt(_x) ((_x) << 19) | ||
| 364 | |||
| 365 | #define DxEPTSIZ_XferSize_MASK (0x7ffff << 0) | ||
| 366 | #define DxEPTSIZ_XferSize_SHIFT (0) | ||
| 367 | #define DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff) | ||
| 368 | #define DxEPTSIZ_XferSize_LIMIT (0x7ffff) | ||
| 369 | #define DxEPTSIZ_XferSize(_x) ((_x) << 0) | ||
| 370 | |||
| 371 | #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) | ||
| 372 | #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) | ||
| 373 | #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) | ||
| 374 | |||
| 375 | #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) | ||
| 376 | |||
| 377 | #endif /* __REGS_USB_HSOTG_H */ | ||