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-rw-r--r--drivers/tty/serial/tegra_hsuart.c1682
1 files changed, 1682 insertions, 0 deletions
diff --git a/drivers/tty/serial/tegra_hsuart.c b/drivers/tty/serial/tegra_hsuart.c
new file mode 100644
index 00000000000..4169cbcbf29
--- /dev/null
+++ b/drivers/tty/serial/tegra_hsuart.c
@@ -0,0 +1,1682 @@
1/*
2 * drivers/serial/tegra_hsuart.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (C) 2009-2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmapool.h>
30#include <linux/termios.h>
31#include <linux/irq.h>
32#include <linux/delay.h>
33#include <linux/clk.h>
34#include <linux/string.h>
35#include <linux/pagemap.h>
36#include <linux/serial_reg.h>
37#include <linux/serial_8250.h>
38#include <linux/debugfs.h>
39#include <linux/slab.h>
40#include <linux/workqueue.h>
41#include <linux/tegra_uart.h>
42
43#include <mach/dma.h>
44#include <mach/clk.h>
45
46#define TEGRA_UART_TYPE "TEGRA_UART"
47
48#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
49
50#define BYTES_TO_ALIGN(x) ((unsigned long)(ALIGN((x), sizeof(u32))) - \
51 (unsigned long)(x))
52
53#define UART_RX_DMA_BUFFER_SIZE (2048*8)
54
55#define UART_LSR_FIFOE 0x80
56#define UART_LSR_TXFIFO_FULL 0x100
57#define UART_IER_EORD 0x20
58#define UART_MCR_RTS_EN 0x40
59#define UART_MCR_CTS_EN 0x20
60#define UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
61 UART_LSR_PE | UART_LSR_FE)
62
63#define TX_FORCE_PIO 0
64#define RX_FORCE_PIO 0
65
66const int dma_req_sel[] = {
67 TEGRA_DMA_REQ_SEL_UARTA,
68 TEGRA_DMA_REQ_SEL_UARTB,
69 TEGRA_DMA_REQ_SEL_UARTC,
70 TEGRA_DMA_REQ_SEL_UARTD,
71 TEGRA_DMA_REQ_SEL_UARTE,
72};
73
74#define TEGRA_TX_PIO 1
75#define TEGRA_TX_DMA 2
76
77#define TEGRA_UART_MIN_DMA 16
78#define TEGRA_UART_FIFO_SIZE 8
79
80#define TEGRA_UART_CLOSED 0
81#define TEGRA_UART_OPENED 1
82#define TEGRA_UART_CLOCK_OFF 2
83#define TEGRA_UART_SUSPEND 3
84
85/* Tx fifo trigger level setting in tegra uart is in
86 * reverse way then conventional uart */
87#define TEGRA_UART_TX_TRIG_16B 0x00
88#define TEGRA_UART_TX_TRIG_8B 0x10
89#define TEGRA_UART_TX_TRIG_4B 0x20
90#define TEGRA_UART_TX_TRIG_1B 0x30
91
92struct tegra_uart_port {
93 struct uart_port uport;
94 char port_name[32];
95
96 /* Module info */
97 unsigned long size;
98 struct clk *clk;
99 unsigned int baud;
100
101 /* Register shadow */
102 unsigned char fcr_shadow;
103 unsigned char mcr_shadow;
104 unsigned char lcr_shadow;
105 unsigned char ier_shadow;
106 bool use_cts_control;
107 bool rts_active;
108
109 int tx_in_progress;
110 unsigned int tx_bytes;
111
112 dma_addr_t xmit_dma_addr;
113
114 /* TX DMA */
115 struct tegra_dma_req tx_dma_req;
116 struct tegra_dma_channel *tx_dma;
117
118 /* RX DMA */
119 struct tegra_dma_req rx_dma_req;
120 struct tegra_dma_channel *rx_dma;
121
122 bool use_rx_dma;
123 bool use_tx_dma;
124 int uart_state;
125 bool rx_timeout;
126 int rx_in_progress;
127};
128
129static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud);
130static void do_handle_rx_pio(struct tegra_uart_port *t);
131static void do_handle_rx_dma(struct tegra_uart_port *t);
132static void set_rts(struct tegra_uart_port *t, bool active);
133
134static inline u8 uart_readb(struct tegra_uart_port *t, unsigned long reg)
135{
136 u8 val = readb(t->uport.membase + (reg << t->uport.regshift));
137 dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__,
138 t->uport.membase, reg << t->uport.regshift, val);
139 return val;
140}
141
142static inline u32 uart_readl(struct tegra_uart_port *t, unsigned long reg)
143{
144 u32 val = readl(t->uport.membase + (reg << t->uport.regshift));
145 dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__,
146 t->uport.membase, reg << t->uport.regshift, val);
147 return val;
148}
149
150static inline void uart_writeb(struct tegra_uart_port *t, u8 val,
151 unsigned long reg)
152{
153 dev_vdbg(t->uport.dev, "%s: %p %03lx %02x\n",
154 __func__, t->uport.membase, reg << t->uport.regshift, val);
155 writeb(val, t->uport.membase + (reg << t->uport.regshift));
156}
157
158static inline void uart_writel(struct tegra_uart_port *t, u32 val,
159 unsigned long reg)
160{
161 dev_vdbg(t->uport.dev, "%s: %p %03lx %08x\n",
162 __func__, t->uport.membase, reg << t->uport.regshift, val);
163 writel(val, t->uport.membase + (reg << t->uport.regshift));
164}
165
166static void fill_tx_fifo(struct tegra_uart_port *t, int max_bytes)
167{
168 int i;
169 struct circ_buf *xmit = &t->uport.state->xmit;
170#ifndef CONFIG_ARCH_TEGRA_2x_SOC
171 unsigned long lsr;
172#endif
173
174 for (i = 0; i < max_bytes; i++) {
175 BUG_ON(uart_circ_empty(xmit));
176#ifndef CONFIG_ARCH_TEGRA_2x_SOC
177 lsr = uart_readl(t, UART_LSR);
178 if ((lsr & UART_LSR_TXFIFO_FULL))
179 break;
180#endif
181 uart_writeb(t, xmit->buf[xmit->tail], UART_TX);
182 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
183 t->uport.icount.tx++;
184 }
185}
186
187static void tegra_start_pio_tx(struct tegra_uart_port *t, unsigned int bytes)
188{
189 if (bytes > TEGRA_UART_FIFO_SIZE)
190 bytes = TEGRA_UART_FIFO_SIZE;
191
192 t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
193 t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
194 uart_writeb(t, t->fcr_shadow, UART_FCR);
195 t->tx_in_progress = TEGRA_TX_PIO;
196 t->tx_bytes = bytes;
197 t->ier_shadow |= UART_IER_THRI;
198 uart_writeb(t, t->ier_shadow, UART_IER);
199}
200
201static void tegra_start_dma_tx(struct tegra_uart_port *t, unsigned long bytes)
202{
203 struct circ_buf *xmit;
204 xmit = &t->uport.state->xmit;
205
206 dma_sync_single_for_device(t->uport.dev, t->xmit_dma_addr,
207 UART_XMIT_SIZE, DMA_TO_DEVICE);
208
209 t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
210 t->fcr_shadow |= TEGRA_UART_TX_TRIG_4B;
211 uart_writeb(t, t->fcr_shadow, UART_FCR);
212
213 t->tx_bytes = bytes & ~(sizeof(u32)-1);
214 t->tx_dma_req.source_addr = t->xmit_dma_addr + xmit->tail;
215 t->tx_dma_req.size = t->tx_bytes;
216
217 t->tx_in_progress = TEGRA_TX_DMA;
218
219 tegra_dma_enqueue_req(t->tx_dma, &t->tx_dma_req);
220}
221
222/* Called with u->lock taken */
223static void tegra_start_next_tx(struct tegra_uart_port *t)
224{
225 unsigned long tail;
226 unsigned long count;
227
228 struct circ_buf *xmit;
229
230 xmit = &t->uport.state->xmit;
231 tail = (unsigned long)&xmit->buf[xmit->tail];
232 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
233
234
235 dev_vdbg(t->uport.dev, "+%s %lu %d\n", __func__, count,
236 t->tx_in_progress);
237
238 if (count == 0)
239 goto out;
240
241 if (!t->use_tx_dma || count < TEGRA_UART_MIN_DMA)
242 tegra_start_pio_tx(t, count);
243 else if (BYTES_TO_ALIGN(tail) > 0)
244 tegra_start_pio_tx(t, BYTES_TO_ALIGN(tail));
245 else
246 tegra_start_dma_tx(t, count);
247
248out:
249 dev_vdbg(t->uport.dev, "-%s", __func__);
250}
251
252/* Called by serial core driver with u->lock taken. */
253static void tegra_start_tx(struct uart_port *u)
254{
255 struct tegra_uart_port *t;
256 struct circ_buf *xmit;
257
258 t = container_of(u, struct tegra_uart_port, uport);
259 xmit = &u->state->xmit;
260
261 if (!uart_circ_empty(xmit) && !t->tx_in_progress)
262 tegra_start_next_tx(t);
263}
264
265static int tegra_start_dma_rx(struct tegra_uart_port *t)
266{
267 wmb();
268 dma_sync_single_for_device(t->uport.dev, t->rx_dma_req.dest_addr,
269 t->rx_dma_req.size, DMA_TO_DEVICE);
270 if (tegra_dma_enqueue_req(t->rx_dma, &t->rx_dma_req)) {
271 dev_err(t->uport.dev, "Could not enqueue Rx DMA req\n");
272 return -EINVAL;
273 }
274 return 0;
275}
276
277static void tegra_rx_dma_threshold_callback(struct tegra_dma_req *req)
278{
279 struct tegra_uart_port *t = req->dev;
280 struct uart_port *u = &t->uport;
281 unsigned long flags;
282
283 spin_lock_irqsave(&u->lock, flags);
284
285 do_handle_rx_dma(t);
286
287 spin_unlock_irqrestore(&u->lock, flags);
288}
289
290/*
291 * It is expected that the callers take the UART lock when this API is called.
292 *
293 * There are 2 contexts when this function is called:
294 *
295 * 1. DMA ISR - DMA ISR triggers the threshold complete calback, which calls the
296 * dequue API which in-turn calls this callback. UART lock is taken during
297 * the call to the threshold callback.
298 *
299 * 2. UART ISR - UART calls the dequue API which in-turn will call this API.
300 * In this case, UART ISR takes the UART lock.
301 */
302static void tegra_rx_dma_complete_callback(struct tegra_dma_req *req)
303{
304 struct tegra_uart_port *t = req->dev;
305 struct uart_port *u = &t->uport;
306 struct tty_struct *tty = u->state->port.tty;
307 int copied;
308
309 /* If we are here, DMA is stopped */
310
311 dev_dbg(t->uport.dev, "%s: %d %d\n", __func__, req->bytes_transferred,
312 req->status);
313 if (req->bytes_transferred) {
314 t->uport.icount.rx += req->bytes_transferred;
315 dma_sync_single_for_cpu(t->uport.dev, req->dest_addr,
316 req->size, DMA_FROM_DEVICE);
317 copied = tty_insert_flip_string(tty,
318 ((unsigned char *)(req->virt_addr)),
319 req->bytes_transferred);
320 if (copied != req->bytes_transferred) {
321 WARN_ON(1);
322 dev_err(t->uport.dev, "Not able to copy uart data "
323 "to tty layer Req %d and coped %d\n",
324 req->bytes_transferred, copied);
325 }
326 dma_sync_single_for_device(t->uport.dev, req->dest_addr,
327 req->size, DMA_TO_DEVICE);
328 }
329
330 do_handle_rx_pio(t);
331
332 /* Push the read data later in caller place. */
333 if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED)
334 return;
335
336 spin_unlock(&u->lock);
337 tty_flip_buffer_push(u->state->port.tty);
338 spin_lock(&u->lock);
339}
340
341/* Lock already taken */
342static void do_handle_rx_dma(struct tegra_uart_port *t)
343{
344 struct uart_port *u = &t->uport;
345 if (t->rts_active)
346 set_rts(t, false);
347 tegra_dma_dequeue_req(t->rx_dma, &t->rx_dma_req);
348 tty_flip_buffer_push(u->state->port.tty);
349 /* enqueue the request again */
350 tegra_start_dma_rx(t);
351 if (t->rts_active)
352 set_rts(t, true);
353}
354
355/* Wait for a symbol-time. */
356static void wait_sym_time(struct tegra_uart_port *t, unsigned int syms)
357{
358
359 /* Definitely have a start bit. */
360 unsigned int bits = 1;
361 switch (t->lcr_shadow & 3) {
362 case UART_LCR_WLEN5:
363 bits += 5;
364 break;
365 case UART_LCR_WLEN6:
366 bits += 6;
367 break;
368 case UART_LCR_WLEN7:
369 bits += 7;
370 break;
371 default:
372 bits += 8;
373 break;
374 }
375
376 /* Technically 5 bits gets 1.5 bits of stop... */
377 if (t->lcr_shadow & UART_LCR_STOP)
378 bits += 2;
379 else
380 bits++;
381
382 if (t->lcr_shadow & UART_LCR_PARITY)
383 bits++;
384
385 if (likely(t->baud))
386 udelay(DIV_ROUND_UP(syms * bits * 1000000, t->baud));
387}
388
389/* Flush desired FIFO. */
390static void tegra_fifo_reset(struct tegra_uart_port *t, u8 fcr_bits)
391{
392 unsigned char fcr = t->fcr_shadow;
393#ifdef CONFIG_ARCH_TEGRA_2x_SOC
394 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
395 uart_writeb(t, fcr, UART_FCR);
396#else
397 /*Hw issue: Resetting tx fifo with non-fifo
398 mode to avoid any extra character to be sent*/
399 fcr &= ~UART_FCR_ENABLE_FIFO;
400 uart_writeb(t, fcr, UART_FCR);
401 udelay(60);
402 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
403 uart_writeb(t, fcr, UART_FCR);
404 fcr |= UART_FCR_ENABLE_FIFO;
405 uart_writeb(t, fcr, UART_FCR);
406#endif
407 uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
408 wait_sym_time(t, 1); /* Wait for the flush to propagate. */
409}
410
411static char do_decode_rx_error(struct tegra_uart_port *t, u8 lsr)
412{
413 char flag = TTY_NORMAL;
414
415 if (unlikely(lsr & UART_LSR_ANY)) {
416 if (lsr & UART_LSR_OE) {
417 /* Overrrun error */
418 flag |= TTY_OVERRUN;
419 t->uport.icount.overrun++;
420 dev_err(t->uport.dev, "Got overrun errors\n");
421 } else if (lsr & UART_LSR_PE) {
422 /* Parity error */
423 flag |= TTY_PARITY;
424 t->uport.icount.parity++;
425 dev_err(t->uport.dev, "Got Parity errors\n");
426 } else if (lsr & UART_LSR_FE) {
427 flag |= TTY_FRAME;
428 t->uport.icount.frame++;
429 dev_err(t->uport.dev, "Got frame errors\n");
430 } else if (lsr & UART_LSR_BI) {
431 dev_err(t->uport.dev, "Got Break\n");
432 t->uport.icount.brk++;
433 /* If FIFO read error without any data, reset Rx FIFO */
434 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
435 tegra_fifo_reset(t, UART_FCR_CLEAR_RCVR);
436 }
437 }
438 return flag;
439}
440
441static void do_handle_rx_pio(struct tegra_uart_port *t)
442{
443 int count = 0;
444 do {
445 char flag = TTY_NORMAL;
446 unsigned char lsr = 0;
447 unsigned char ch;
448
449
450 lsr = uart_readb(t, UART_LSR);
451 if (!(lsr & UART_LSR_DR))
452 break;
453
454 flag = do_decode_rx_error(t, lsr);
455 ch = uart_readb(t, UART_RX);
456 t->uport.icount.rx++;
457 count++;
458
459 if (!uart_handle_sysrq_char(&t->uport, c))
460 uart_insert_char(&t->uport, lsr, UART_LSR_OE, ch, flag);
461 } while (1);
462
463 dev_dbg(t->uport.dev, "PIO received %d bytes\n", count);
464 return;
465}
466
467static void do_handle_modem_signal(struct uart_port *u)
468{
469 unsigned char msr;
470 struct tegra_uart_port *t;
471
472 t = container_of(u, struct tegra_uart_port, uport);
473 msr = uart_readb(t, UART_MSR);
474 if (msr & UART_MSR_CTS)
475 dev_dbg(u->dev, "CTS triggered\n");
476 if (msr & UART_MSR_DSR)
477 dev_dbg(u->dev, "DSR enabled\n");
478 if (msr & UART_MSR_DCD)
479 dev_dbg(u->dev, "CD enabled\n");
480 if (msr & UART_MSR_RI)
481 dev_dbg(u->dev, "RI enabled\n");
482 return;
483}
484
485static void do_handle_tx_pio(struct tegra_uart_port *t)
486{
487 struct circ_buf *xmit = &t->uport.state->xmit;
488
489 fill_tx_fifo(t, t->tx_bytes);
490
491 t->tx_in_progress = 0;
492
493 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
494 uart_write_wakeup(&t->uport);
495
496 tegra_start_next_tx(t);
497 return;
498}
499
500static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
501{
502 struct tegra_uart_port *t = req->dev;
503 struct circ_buf *xmit = &t->uport.state->xmit;
504 int count = req->bytes_transferred;
505 unsigned long flags;
506
507 dev_vdbg(t->uport.dev, "%s: %d\n", __func__, count);
508
509 /* Update xmit pointers without lock if dma aborted. */
510 if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED) {
511 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
512 t->tx_in_progress = 0;
513 return;
514 }
515
516 spin_lock_irqsave(&t->uport.lock, flags);
517 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
518 t->tx_in_progress = 0;
519
520 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
521 uart_write_wakeup(&t->uport);
522
523 tegra_start_next_tx(t);
524
525 spin_unlock_irqrestore(&t->uport.lock, flags);
526}
527
528static irqreturn_t tegra_uart_isr(int irq, void *data)
529{
530 struct tegra_uart_port *t = data;
531 struct uart_port *u = &t->uport;
532 unsigned char iir;
533 unsigned char ier;
534 bool is_rx_int = false;
535 unsigned long flags;
536
537 spin_lock_irqsave(&u->lock, flags);
538 t = container_of(u, struct tegra_uart_port, uport);
539 while (1) {
540 iir = uart_readb(t, UART_IIR);
541 if (iir & UART_IIR_NO_INT) {
542 if (likely(t->use_rx_dma) && is_rx_int) {
543 do_handle_rx_dma(t);
544
545 if (t->rx_in_progress) {
546 ier = t->ier_shadow;
547 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
548 UART_IER_EORD);
549 t->ier_shadow = ier;
550 uart_writeb(t, ier, UART_IER);
551 }
552 }
553 spin_unlock_irqrestore(&u->lock, flags);
554 return IRQ_HANDLED;
555 }
556
557 dev_dbg(u->dev, "tegra_uart_isr iir = 0x%x (%d)\n", iir,
558 (iir >> 1) & 0x7);
559 switch ((iir >> 1) & 0x7) {
560 case 0: /* Modem signal change interrupt */
561 do_handle_modem_signal(u);
562 break;
563 case 1: /* Transmit interrupt only triggered when using PIO */
564 t->ier_shadow &= ~UART_IER_THRI;
565 uart_writeb(t, t->ier_shadow, UART_IER);
566 do_handle_tx_pio(t);
567 break;
568 case 4: /* End of data */
569 case 6: /* Rx timeout */
570 case 2: /* Receive */
571 if (likely(t->use_rx_dma)) {
572 if (!is_rx_int) {
573 is_rx_int = true;
574 /* Disable interrups */
575 ier = t->ier_shadow;
576 ier |= UART_IER_RDI;
577 uart_writeb(t, ier, UART_IER);
578 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
579 UART_IER_RTOIE | UART_IER_EORD);
580 t->ier_shadow = ier;
581 uart_writeb(t, ier, UART_IER);
582 }
583 } else {
584 do_handle_rx_pio(t);
585
586 spin_unlock_irqrestore(&u->lock, flags);
587 tty_flip_buffer_push(u->state->port.tty);
588 spin_lock_irqsave(&u->lock, flags);
589 }
590 break;
591 case 3: /* Receive error */
592 /* FIXME how to handle this? Why do we get here */
593 do_decode_rx_error(t, uart_readb(t, UART_LSR));
594 break;
595 case 5: /* break nothing to handle */
596 case 7: /* break nothing to handle */
597 break;
598 }
599 }
600}
601
602static void tegra_stop_rx(struct uart_port *u)
603{
604 struct tegra_uart_port *t;
605 unsigned char ier;
606
607 t = container_of(u, struct tegra_uart_port, uport);
608
609 if (t->rts_active)
610 set_rts(t, false);
611
612 if (t->rx_in_progress) {
613 wait_sym_time(t, 1); /* wait a character interval */
614
615 ier = t->ier_shadow;
616 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
617 UART_IER_EORD);
618 t->ier_shadow = ier;
619 uart_writeb(t, ier, UART_IER);
620 t->rx_in_progress = 0;
621
622 if (t->use_rx_dma && t->rx_dma)
623 tegra_dma_dequeue_req(t->rx_dma, &t->rx_dma_req);
624 else
625 do_handle_rx_pio(t);
626
627 tty_flip_buffer_push(u->state->port.tty);
628 }
629
630 return;
631}
632
633static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
634{
635 unsigned long flags;
636 unsigned long char_time = DIV_ROUND_UP(10000000, t->baud);
637 unsigned long fifo_empty_time = t->uport.fifosize * char_time;
638 unsigned long wait_time;
639 unsigned char lsr;
640 unsigned char msr;
641 unsigned char mcr;
642
643 /* Disable interrupts */
644 uart_writeb(t, 0, UART_IER);
645
646 lsr = uart_readb(t, UART_LSR);
647 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
648 msr = uart_readb(t, UART_MSR);
649 mcr = uart_readb(t, UART_MCR);
650 if ((mcr & UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
651 dev_err(t->uport.dev, "%s: Tx fifo not empty and "
652 "slave disabled CTS, Waiting for slave to"
653 " be ready\n", __func__);
654
655 /* Wait for Tx fifo to be empty */
656 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
657 wait_time = min(fifo_empty_time, 100lu);
658 udelay(wait_time);
659 fifo_empty_time -= wait_time;
660 if (!fifo_empty_time) {
661 msr = uart_readb(t, UART_MSR);
662 mcr = uart_readb(t, UART_MCR);
663 if ((mcr & UART_MCR_CTS_EN) &&
664 (msr & UART_MSR_CTS))
665 dev_err(t->uport.dev, "%s: Slave is "
666 "still not ready!\n", __func__);
667 break;
668 }
669 lsr = uart_readb(t, UART_LSR);
670 }
671 }
672
673 spin_lock_irqsave(&t->uport.lock, flags);
674
675 /* Reset the Rx and Tx FIFOs */
676 tegra_fifo_reset(t, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
677
678 t->baud = 0;
679 t->uart_state = TEGRA_UART_CLOSED;
680
681 spin_unlock_irqrestore(&t->uport.lock, flags);
682
683 clk_disable(t->clk);
684}
685
686static void tegra_uart_free_rx_dma_buffer(struct tegra_uart_port *t)
687{
688 if (likely(t->rx_dma_req.dest_addr))
689 dma_free_coherent(t->uport.dev, t->rx_dma_req.size,
690 t->rx_dma_req.virt_addr, t->rx_dma_req.dest_addr);
691 t->rx_dma_req.dest_addr = 0;
692 t->rx_dma_req.virt_addr = NULL;
693}
694
695static void tegra_uart_free_rx_dma(struct tegra_uart_port *t)
696{
697 if (!t->use_rx_dma)
698 return;
699
700 tegra_dma_free_channel(t->rx_dma);
701 t->rx_dma = NULL;
702 t->use_rx_dma = false;
703}
704
705static int tegra_uart_hw_init(struct tegra_uart_port *t)
706{
707 unsigned char ier;
708
709 dev_vdbg(t->uport.dev, "+tegra_uart_hw_init\n");
710
711 t->fcr_shadow = 0;
712 t->mcr_shadow = 0;
713 t->lcr_shadow = 0;
714 t->ier_shadow = 0;
715 t->baud = 0;
716
717 clk_enable(t->clk);
718
719 /* Reset the UART controller to clear all previous status.*/
720 tegra_periph_reset_assert(t->clk);
721 udelay(100);
722 tegra_periph_reset_deassert(t->clk);
723 udelay(100);
724
725 t->rx_in_progress = 0;
726
727 /*
728 * Set the trigger level
729 *
730 * For PIO mode:
731 *
732 * For receive, this will interrupt the CPU after that many number of
733 * bytes are received, for the remaining bytes the receive timeout
734 * interrupt is received.
735 *
736 * Rx high watermark is set to 4.
737 *
738 * For transmit, if the trasnmit interrupt is enabled, this will
739 * interrupt the CPU when the number of entries in the FIFO reaches the
740 * low watermark.
741 *
742 * Tx low watermark is set to 8.
743 *
744 * For DMA mode:
745 *
746 * Set the Tx trigger to 4. This should match the DMA burst size that
747 * programmed in the DMA registers.
748 */
749 t->fcr_shadow = UART_FCR_ENABLE_FIFO;
750 t->fcr_shadow |= UART_FCR_R_TRIG_01;
751 t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
752 uart_writeb(t, t->fcr_shadow, UART_FCR);
753
754 if (t->use_rx_dma) {
755 /*
756 * Initialize the UART for a simple default configuration
757 * so that the receive DMA buffer may be enqueued */
758 t->lcr_shadow = 3; /* no parity, stop, 8 data bits */
759 tegra_set_baudrate(t, 115200);
760 t->fcr_shadow |= UART_FCR_DMA_SELECT;
761 uart_writeb(t, t->fcr_shadow, UART_FCR);
762 if (tegra_start_dma_rx(t)) {
763 dev_err(t->uport.dev, "Rx DMA enqueue failed\n");
764 tegra_uart_free_rx_dma(t);
765 t->fcr_shadow &= ~UART_FCR_DMA_SELECT;
766 uart_writeb(t, t->fcr_shadow, UART_FCR);
767 }
768 } else {
769 uart_writeb(t, t->fcr_shadow, UART_FCR);
770 }
771
772 t->rx_in_progress = 1;
773
774 /*
775 * Enable IE_RXS for the receive status interrupts like line errros.
776 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
777 *
778 * If using DMA mode, enable EORD instead of receive interrupt which
779 * will interrupt after the UART is done with the receive instead of
780 * the interrupt when the FIFO "threshold" is reached.
781 *
782 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
783 * the DATA is sitting in the FIFO and couldn't be transferred to the
784 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
785 * triggered when there is a pause of the incomming data stream for 4
786 * characters long.
787 *
788 * For pauses in the data which is not aligned to 4 bytes, we get
789 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
790 * then the EORD.
791 *
792 * Don't get confused, believe in the magic of nvidia hw...:-)
793 */
794 ier = 0;
795 ier |= UART_IER_RLSI | UART_IER_RTOIE;
796 if (t->use_rx_dma)
797 ier |= UART_IER_EORD;
798 else
799 ier |= UART_IER_RDI;
800 t->ier_shadow = ier;
801 uart_writeb(t, ier, UART_IER);
802
803 t->uart_state = TEGRA_UART_OPENED;
804 dev_vdbg(t->uport.dev, "-tegra_uart_hw_init\n");
805 return 0;
806}
807
808static int tegra_uart_init_rx_dma_buffer(struct tegra_uart_port *t)
809{
810 dma_addr_t rx_dma_phys;
811 void *rx_dma_virt;
812
813 t->rx_dma_req.size = UART_RX_DMA_BUFFER_SIZE;
814 rx_dma_virt = dma_alloc_coherent(t->uport.dev,
815 t->rx_dma_req.size, &rx_dma_phys, GFP_KERNEL);
816 if (!rx_dma_virt) {
817 dev_err(t->uport.dev, "DMA buffers allocate failed\n");
818 return -ENOMEM;
819 }
820 t->rx_dma_req.dest_addr = rx_dma_phys;
821 t->rx_dma_req.virt_addr = rx_dma_virt;
822
823 t->rx_dma_req.source_addr = (unsigned long)t->uport.mapbase;
824 t->rx_dma_req.source_wrap = 4;
825 t->rx_dma_req.dest_wrap = 0;
826 t->rx_dma_req.to_memory = 1;
827 t->rx_dma_req.source_bus_width = 8;
828 t->rx_dma_req.dest_bus_width = 32;
829 t->rx_dma_req.req_sel = dma_req_sel[t->uport.line];
830 t->rx_dma_req.complete = tegra_rx_dma_complete_callback;
831 t->rx_dma_req.threshold = tegra_rx_dma_threshold_callback;
832 t->rx_dma_req.dev = t;
833
834 return 0;
835}
836
837static int tegra_uart_init_rx_dma(struct tegra_uart_port *t)
838{
839 t->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_CONTINUOUS,
840 "uart_rx_%d", t->uport.line);
841 if (!t->rx_dma) {
842 dev_err(t->uport.dev, "%s: failed to allocate RX DMA.\n",
843 __func__);
844 return -ENODEV;
845 }
846 return 0;
847}
848
849static int tegra_startup(struct uart_port *u)
850{
851 struct tegra_uart_port *t = container_of(u,
852 struct tegra_uart_port, uport);
853 int ret = 0;
854 struct tegra_uart_platform_data *pdata;
855
856 t = container_of(u, struct tegra_uart_port, uport);
857 sprintf(t->port_name, "tegra_uart_%d", u->line);
858
859 t->use_tx_dma = false;
860 if (!TX_FORCE_PIO) {
861 t->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
862 "uart_tx_%d", u->line);
863 if (t->tx_dma)
864 t->use_tx_dma = true;
865 else
866 pr_err("%s: failed to allocate TX DMA.\n", __func__);
867 }
868 if (t->use_tx_dma) {
869 t->tx_dma_req.instance = u->line;
870 t->tx_dma_req.complete = tegra_tx_dma_complete_callback;
871 t->tx_dma_req.to_memory = 0;
872
873 t->tx_dma_req.dest_addr = (unsigned long)t->uport.mapbase;
874 t->tx_dma_req.dest_wrap = 4;
875 t->tx_dma_req.source_wrap = 0;
876 t->tx_dma_req.source_bus_width = 32;
877 t->tx_dma_req.dest_bus_width = 8;
878 t->tx_dma_req.req_sel = dma_req_sel[t->uport.line];
879 t->tx_dma_req.dev = t;
880 t->tx_dma_req.size = 0;
881 t->xmit_dma_addr = dma_map_single(t->uport.dev,
882 t->uport.state->xmit.buf, UART_XMIT_SIZE,
883 DMA_TO_DEVICE);
884 }
885 t->tx_in_progress = 0;
886
887 t->use_rx_dma = false;
888 if (!RX_FORCE_PIO && t->rx_dma_req.virt_addr) {
889 if (!tegra_uart_init_rx_dma(t))
890 t->use_rx_dma = true;
891 }
892
893 ret = tegra_uart_hw_init(t);
894 if (ret)
895 goto fail;
896
897 pdata = u->dev->platform_data;
898 if (pdata->is_loopback)
899 t->mcr_shadow |= UART_MCR_LOOP;
900
901 dev_dbg(u->dev, "Requesting IRQ %d\n", u->irq);
902 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
903 t->port_name, t);
904 if (ret) {
905 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
906 goto fail;
907 }
908
909 dev_dbg(u->dev, "Started UART port %d\n", u->line);
910 return 0;
911fail:
912 dev_err(u->dev, "Tegra UART startup failed\n");
913 return ret;
914}
915
916static void tegra_shutdown(struct uart_port *u)
917{
918 struct tegra_uart_port *t;
919
920 t = container_of(u, struct tegra_uart_port, uport);
921 dev_vdbg(u->dev, "+tegra_shutdown\n");
922
923 tegra_uart_hw_deinit(t);
924
925 t->rx_in_progress = 0;
926 t->tx_in_progress = 0;
927
928 tegra_uart_free_rx_dma(t);
929 if (t->use_tx_dma) {
930 tegra_dma_free_channel(t->tx_dma);
931 t->tx_dma = NULL;
932 t->use_tx_dma = false;
933 dma_unmap_single(t->uport.dev, t->xmit_dma_addr, UART_XMIT_SIZE,
934 DMA_TO_DEVICE);
935 t->xmit_dma_addr = 0;
936 }
937
938 free_irq(u->irq, t);
939 dev_vdbg(u->dev, "-tegra_shutdown\n");
940}
941
942static void tegra_wake_peer(struct uart_port *u)
943{
944 struct tegra_uart_platform_data *pdata = u->dev->platform_data;
945
946 if (pdata && pdata->wake_peer)
947 pdata->wake_peer(u);
948}
949
950static unsigned int tegra_get_mctrl(struct uart_port *u)
951{
952 /*
953 * RI - Ring detector is active
954 * CD/DCD/CAR - Carrier detect is always active. For some reason
955 * linux has different names for carrier detect.
956 * DSR - Data Set ready is active as the hardware doesn't support it.
957 * Don't know if the linux support this yet?
958 * CTS - Clear to send. Always set to active, as the hardware handles
959 * CTS automatically.
960 */
961 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
962}
963
964static void set_rts(struct tegra_uart_port *t, bool active)
965{
966 unsigned char mcr;
967 mcr = t->mcr_shadow;
968 if (active)
969 mcr |= UART_MCR_RTS_EN;
970 else
971 mcr &= ~UART_MCR_RTS_EN;
972 if (mcr != t->mcr_shadow) {
973 uart_writeb(t, mcr, UART_MCR);
974 t->mcr_shadow = mcr;
975 }
976 return;
977}
978
979static void set_dtr(struct tegra_uart_port *t, bool active)
980{
981 unsigned char mcr;
982 mcr = t->mcr_shadow;
983 if (active)
984 mcr |= UART_MCR_DTR;
985 else
986 mcr &= ~UART_MCR_DTR;
987 if (mcr != t->mcr_shadow) {
988 uart_writeb(t, mcr, UART_MCR);
989 t->mcr_shadow = mcr;
990 }
991 return;
992}
993
994static void tegra_set_mctrl(struct uart_port *u, unsigned int mctrl)
995{
996 unsigned char mcr;
997 struct tegra_uart_port *t;
998
999 dev_dbg(u->dev, "tegra_set_mctrl called with %d\n", mctrl);
1000 t = container_of(u, struct tegra_uart_port, uport);
1001
1002 mcr = t->mcr_shadow;
1003 if (mctrl & TIOCM_RTS) {
1004 t->rts_active = true;
1005 set_rts(t, true);
1006 } else {
1007 t->rts_active = false;
1008 set_rts(t, false);
1009 }
1010
1011 if (mctrl & TIOCM_DTR)
1012 set_dtr(t, true);
1013 else
1014 set_dtr(t, false);
1015 return;
1016}
1017
1018static void tegra_break_ctl(struct uart_port *u, int break_ctl)
1019{
1020 struct tegra_uart_port *t;
1021 unsigned char lcr;
1022
1023 t = container_of(u, struct tegra_uart_port, uport);
1024 lcr = t->lcr_shadow;
1025 if (break_ctl)
1026 lcr |= UART_LCR_SBC;
1027 else
1028 lcr &= ~UART_LCR_SBC;
1029 uart_writeb(t, lcr, UART_LCR);
1030 t->lcr_shadow = lcr;
1031}
1032
1033static int tegra_request_port(struct uart_port *u)
1034{
1035 return 0;
1036}
1037
1038static void tegra_release_port(struct uart_port *u)
1039{
1040 /* Nothing to do here */
1041}
1042
1043static unsigned int tegra_tx_empty(struct uart_port *u)
1044{
1045 struct tegra_uart_port *t;
1046 unsigned int ret = 0;
1047 unsigned long flags;
1048 unsigned char lsr;
1049
1050 t = container_of(u, struct tegra_uart_port, uport);
1051 dev_vdbg(u->dev, "+tegra_tx_empty\n");
1052
1053 spin_lock_irqsave(&u->lock, flags);
1054 if (!t->tx_in_progress) {
1055 lsr = uart_readb(t, UART_LSR);
1056 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
1057 ret = TIOCSER_TEMT;
1058 }
1059 spin_unlock_irqrestore(&u->lock, flags);
1060
1061 dev_vdbg(u->dev, "-tegra_tx_empty\n");
1062 return ret;
1063}
1064
1065static void tegra_stop_tx(struct uart_port *u)
1066{
1067 struct tegra_uart_port *t;
1068
1069 t = container_of(u, struct tegra_uart_port, uport);
1070
1071 if (t->use_tx_dma)
1072 tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
1073
1074 return;
1075}
1076
1077static void tegra_enable_ms(struct uart_port *u)
1078{
1079}
1080
1081#ifndef CONFIG_ARCH_TEGRA_2x_SOC
1082static int clk_div71_get_divider(unsigned long parent_rate,
1083 unsigned long rate)
1084{
1085 s64 divider_u71 = parent_rate;
1086 if (!rate)
1087 return -EINVAL;
1088
1089 divider_u71 *= 2;
1090 divider_u71 += rate - 1;
1091 do_div(divider_u71, rate);
1092
1093 if ((divider_u71 - 2) < 0)
1094 return 0;
1095
1096 if ((divider_u71 - 2) > 255)
1097 return -EINVAL;
1098
1099 return divider_u71 - 2;
1100}
1101#endif
1102
1103static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
1104{
1105 s64 divider_u16;
1106
1107 divider_u16 = parent_rate;
1108 if (!rate)
1109 return -EINVAL;
1110 divider_u16 += rate - 1;
1111 do_div(divider_u16, rate);
1112
1113 if (divider_u16 > 0xFFFF)
1114 return -EINVAL;
1115
1116 return divider_u16;
1117}
1118
1119static unsigned long find_best_clock_source(struct tegra_uart_port *t,
1120 unsigned long rate)
1121{
1122 struct uart_port *u = &t->uport;
1123 struct tegra_uart_platform_data *pdata;
1124 int i;
1125 int divider;
1126 unsigned long parent_rate;
1127 unsigned long new_rate;
1128 unsigned long err_rate;
1129 unsigned int fin_err = rate;
1130 unsigned long fin_rate = rate;
1131 int final_index = -1;
1132 int count;
1133 unsigned long error_2perc;
1134
1135 pdata = u->dev->platform_data;
1136 if (!pdata || !pdata->parent_clk_count)
1137 return fin_rate;
1138
1139 error_2perc = (rate / 50);
1140
1141 for (count = 0; count < pdata->parent_clk_count; ++count) {
1142 parent_rate = pdata->parent_clk_list[count].fixed_clk_rate;
1143
1144 if (parent_rate < rate)
1145 continue;
1146
1147#ifndef CONFIG_ARCH_TEGRA_2x_SOC
1148 divider = clk_div71_get_divider(parent_rate, rate);
1149
1150 /* Get the best divider around calculated value */
1151 if (divider > 2) {
1152 for (i = divider - 2; i < (divider + 2); ++i) {
1153 new_rate = ((parent_rate << 1) + i + 1) /
1154 (i + 2);
1155 err_rate = abs(new_rate - rate);
1156 if (err_rate < fin_err) {
1157 final_index = count;
1158 fin_err = err_rate;
1159 fin_rate = new_rate;
1160 if (fin_err < error_2perc)
1161 break;
1162 }
1163 }
1164 if (fin_err < error_2perc)
1165 break;
1166 }
1167#endif
1168 /* Get the divisor by uart controller dll/dlm */
1169 divider = clk_div16_get_divider(parent_rate, rate);
1170
1171 /* Get the best divider around calculated value */
1172 if (divider > 2) {
1173 for (i = divider - 2; i < (divider + 2); ++i) {
1174 new_rate = parent_rate/i;
1175 err_rate = abs(new_rate - rate);
1176 if (err_rate < fin_err) {
1177 final_index = count;
1178 fin_err = err_rate;
1179 fin_rate = parent_rate;
1180 if (fin_err < error_2perc)
1181 break;
1182 }
1183 }
1184 if (fin_err < error_2perc)
1185 break;
1186 }
1187 }
1188
1189 if (final_index >= 0) {
1190 dev_info(t->uport.dev, "Setting clk_src %s\n",
1191 pdata->parent_clk_list[final_index].name);
1192 clk_set_parent(t->clk,
1193 pdata->parent_clk_list[final_index].parent_clk);
1194 }
1195 return fin_rate;
1196}
1197
1198#define UART_CLOCK_ACCURACY 5
1199static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud)
1200{
1201 unsigned long rate;
1202 unsigned int divisor;
1203 unsigned char lcr;
1204 unsigned int baud_actual;
1205 unsigned int baud_delta;
1206 unsigned long best_rate;
1207
1208 if (t->baud == baud)
1209 return;
1210
1211 rate = baud * 16;
1212 best_rate = find_best_clock_source(t, rate);
1213 clk_set_rate(t->clk, best_rate);
1214
1215 rate = clk_get_rate(t->clk);
1216
1217 divisor = rate;
1218 do_div(divisor, 16);
1219 divisor += baud/2;
1220 do_div(divisor, baud);
1221
1222 /* The allowable baudrate error from desired baudrate is 5% */
1223 baud_actual = divisor ? rate / (16 * divisor) : 0;
1224 baud_delta = abs(baud_actual - baud);
1225 if (WARN_ON(baud_delta * 20 > baud)) {
1226 dev_err(t->uport.dev, "requested baud %u, actual %u\n",
1227 baud, baud_actual);
1228 }
1229
1230 lcr = t->lcr_shadow;
1231 lcr |= UART_LCR_DLAB;
1232 uart_writeb(t, lcr, UART_LCR);
1233
1234 uart_writel(t, divisor & 0xFF, UART_TX);
1235 uart_writel(t, ((divisor >> 8) & 0xFF), UART_IER);
1236
1237 lcr &= ~UART_LCR_DLAB;
1238 uart_writeb(t, lcr, UART_LCR);
1239 uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
1240
1241 t->baud = baud;
1242 wait_sym_time(t, 2); /* wait two character intervals at new rate */
1243 dev_dbg(t->uport.dev, "Baud %u clock freq %lu and divisor of %u\n",
1244 baud, rate, divisor);
1245}
1246
1247static void tegra_set_termios(struct uart_port *u, struct ktermios *termios,
1248 struct ktermios *oldtermios)
1249{
1250 struct tegra_uart_port *t;
1251 unsigned int baud;
1252 unsigned long flags;
1253 unsigned int lcr;
1254 unsigned int c_cflag = termios->c_cflag;
1255 unsigned char mcr;
1256
1257 t = container_of(u, struct tegra_uart_port, uport);
1258 dev_vdbg(t->uport.dev, "+tegra_set_termios\n");
1259
1260 spin_lock_irqsave(&u->lock, flags);
1261
1262 /* Changing configuration, it is safe to stop any rx now */
1263 if (t->rts_active)
1264 set_rts(t, false);
1265
1266 /* Parity */
1267 lcr = t->lcr_shadow;
1268 lcr &= ~UART_LCR_PARITY;
1269 if (PARENB == (c_cflag & PARENB)) {
1270 if (CMSPAR == (c_cflag & CMSPAR)) {
1271 /* FIXME What is space parity? */
1272 /* data |= SPACE_PARITY; */
1273 } else if (c_cflag & PARODD) {
1274 lcr |= UART_LCR_PARITY;
1275 lcr &= ~UART_LCR_EPAR;
1276 lcr &= ~UART_LCR_SPAR;
1277 } else {
1278 lcr |= UART_LCR_PARITY;
1279 lcr |= UART_LCR_EPAR;
1280 lcr &= ~UART_LCR_SPAR;
1281 }
1282 }
1283
1284 lcr &= ~UART_LCR_WLEN8;
1285 switch (c_cflag & CSIZE) {
1286 case CS5:
1287 lcr |= UART_LCR_WLEN5;
1288 break;
1289 case CS6:
1290 lcr |= UART_LCR_WLEN6;
1291 break;
1292 case CS7:
1293 lcr |= UART_LCR_WLEN7;
1294 break;
1295 default:
1296 lcr |= UART_LCR_WLEN8;
1297 break;
1298 }
1299
1300 /* Stop bits */
1301 if (termios->c_cflag & CSTOPB)
1302 lcr |= UART_LCR_STOP;
1303 else
1304 lcr &= ~UART_LCR_STOP;
1305
1306 uart_writeb(t, lcr, UART_LCR);
1307 t->lcr_shadow = lcr;
1308
1309 /* Baud rate. */
1310 baud = uart_get_baud_rate(u, termios, oldtermios, 200, 4000000);
1311 spin_unlock_irqrestore(&u->lock, flags);
1312 tegra_set_baudrate(t, baud);
1313 spin_lock_irqsave(&u->lock, flags);
1314
1315 /* Flow control */
1316 if (termios->c_cflag & CRTSCTS) {
1317 mcr = t->mcr_shadow;
1318 mcr |= UART_MCR_CTS_EN;
1319 mcr &= ~UART_MCR_RTS_EN;
1320 t->mcr_shadow = mcr;
1321 uart_writeb(t, mcr, UART_MCR);
1322 t->use_cts_control = true;
1323 /* if top layer has asked to set rts active then do so here */
1324 if (t->rts_active)
1325 set_rts(t, true);
1326 } else {
1327 mcr = t->mcr_shadow;
1328 mcr &= ~UART_MCR_CTS_EN;
1329 mcr &= ~UART_MCR_RTS_EN;
1330 t->mcr_shadow = mcr;
1331 uart_writeb(t, mcr, UART_MCR);
1332 t->use_cts_control = false;
1333 }
1334
1335 /* update the port timeout based on new settings */
1336 uart_update_timeout(u, termios->c_cflag, baud);
1337
1338 spin_unlock_irqrestore(&u->lock, flags);
1339 dev_vdbg(t->uport.dev, "-tegra_set_termios\n");
1340 return;
1341}
1342
1343/*
1344 * Flush any TX data submitted for DMA and PIO. Called when the
1345 * TX circular buffer is reset.
1346 */
1347static void tegra_flush_buffer(struct uart_port *u)
1348{
1349 struct tegra_uart_port *t;
1350
1351 dev_vdbg(u->dev, "%s called", __func__);
1352
1353 t = container_of(u, struct tegra_uart_port, uport);
1354
1355 t->tx_bytes = 0;
1356
1357 if (t->use_tx_dma) {
1358 tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
1359 t->tx_dma_req.size = 0;
1360 }
1361 return;
1362}
1363
1364
1365static void tegra_pm(struct uart_port *u, unsigned int state,
1366 unsigned int oldstate)
1367{
1368
1369}
1370
1371static const char *tegra_type(struct uart_port *u)
1372{
1373 return TEGRA_UART_TYPE;
1374}
1375
1376static struct uart_ops tegra_uart_ops = {
1377 .tx_empty = tegra_tx_empty,
1378 .set_mctrl = tegra_set_mctrl,
1379 .get_mctrl = tegra_get_mctrl,
1380 .stop_tx = tegra_stop_tx,
1381 .start_tx = tegra_start_tx,
1382 .stop_rx = tegra_stop_rx,
1383 .flush_buffer = tegra_flush_buffer,
1384 .enable_ms = tegra_enable_ms,
1385 .break_ctl = tegra_break_ctl,
1386 .startup = tegra_startup,
1387 .shutdown = tegra_shutdown,
1388 .wake_peer = tegra_wake_peer,
1389 .set_termios = tegra_set_termios,
1390 .pm = tegra_pm,
1391 .type = tegra_type,
1392 .request_port = tegra_request_port,
1393 .release_port = tegra_release_port,
1394};
1395
1396static struct uart_driver tegra_uart_driver = {
1397 .owner = THIS_MODULE,
1398 .driver_name = "tegra_uart",
1399 .dev_name = "ttyHS",
1400 .cons = 0,
1401 .nr = 5,
1402};
1403
1404static int __init tegra_uart_probe(struct platform_device *pdev)
1405{
1406 struct tegra_uart_port *t;
1407 struct uart_port *u;
1408 struct resource *resource;
1409 int ret;
1410 char name[64];
1411 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr) {
1412 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1413 return -ENODEV;
1414 }
1415
1416 t = kzalloc(sizeof(struct tegra_uart_port), GFP_KERNEL);
1417 if (!t) {
1418 pr_err("%s: Failed to allocate memory\n", __func__);
1419 return -ENOMEM;
1420 }
1421 u = &t->uport;
1422 u->dev = &pdev->dev;
1423 platform_set_drvdata(pdev, u);
1424 u->line = pdev->id;
1425 u->ops = &tegra_uart_ops;
1426 u->type = PORT_TEGRA;
1427 u->fifosize = 32;
1428
1429 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1430 if (unlikely(!resource)) {
1431 ret = -ENXIO;
1432 goto fail;
1433 }
1434
1435 u->mapbase = resource->start;
1436 u->membase = IO_ADDRESS(u->mapbase);
1437 if (unlikely(!u->membase)) {
1438 ret = -ENOMEM;
1439 goto fail;
1440 }
1441 u->iotype = UPIO_MEM32;
1442
1443 u->irq = platform_get_irq(pdev, 0);
1444 if (unlikely(u->irq < 0)) {
1445 ret = -ENXIO;
1446 goto fail;
1447 }
1448
1449 u->regshift = 2;
1450
1451 t->clk = clk_get(&pdev->dev, NULL);
1452 if (IS_ERR_OR_NULL(t->clk)) {
1453 dev_err(&pdev->dev, "Couldn't get the clock\n");
1454 ret = -ENODEV;
1455 goto fail;
1456 }
1457
1458 ret = uart_add_one_port(&tegra_uart_driver, u);
1459 if (ret) {
1460 pr_err("%s: Failed(%d) to add uart port %s%d\n",
1461 __func__, ret, tegra_uart_driver.dev_name, u->line);
1462 goto fail;
1463 }
1464
1465 snprintf(name, sizeof(name), "tegra_hsuart_%d", u->line);
1466 pr_info("Registered UART port %s%d\n",
1467 tegra_uart_driver.dev_name, u->line);
1468 t->uart_state = TEGRA_UART_CLOSED;
1469
1470 if (!RX_FORCE_PIO) {
1471 ret = tegra_uart_init_rx_dma_buffer(t);
1472 if (ret < 0) {
1473 pr_err("%s: Failed(%d) to allocate rx dma buffer "
1474 "%s%d\n", __func__, ret,
1475 tegra_uart_driver.dev_name, u->line);
1476 goto rx_dma_buff_fail;
1477 }
1478 }
1479 return ret;
1480
1481rx_dma_buff_fail:
1482 uart_remove_one_port(&tegra_uart_driver, u);
1483fail:
1484 if (t->clk)
1485 clk_put(t->clk);
1486 platform_set_drvdata(pdev, NULL);
1487 kfree(t);
1488 return ret;
1489}
1490
1491static int __devexit tegra_uart_remove(struct platform_device *pdev)
1492{
1493 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1494 struct uart_port *u;
1495
1496 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1497 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1498
1499 u = &t->uport;
1500 uart_remove_one_port(&tegra_uart_driver, u);
1501
1502 tegra_uart_free_rx_dma_buffer(t);
1503
1504 platform_set_drvdata(pdev, NULL);
1505
1506 pr_info("Unregistered UART port %s%d\n",
1507 tegra_uart_driver.dev_name, u->line);
1508 kfree(t);
1509 return 0;
1510}
1511
1512static int tegra_uart_suspend(struct platform_device *pdev, pm_message_t state)
1513{
1514 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1515 struct uart_port *u;
1516
1517 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1518 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1519
1520 u = &t->uport;
1521 dev_dbg(t->uport.dev, "tegra_uart_suspend called\n");
1522
1523 /* enable clock before calling suspend so that controller
1524 register can be accessible */
1525 if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
1526 clk_enable(t->clk);
1527 t->uart_state = TEGRA_UART_OPENED;
1528 }
1529
1530 uart_suspend_port(&tegra_uart_driver, u);
1531 t->uart_state = TEGRA_UART_SUSPEND;
1532
1533 return 0;
1534}
1535
1536static int tegra_uart_resume(struct platform_device *pdev)
1537{
1538 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1539 struct uart_port *u;
1540
1541 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1542 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1543
1544 u = &t->uport;
1545 dev_dbg(t->uport.dev, "tegra_uart_resume called\n");
1546
1547 if (t->uart_state == TEGRA_UART_SUSPEND)
1548 uart_resume_port(&tegra_uart_driver, u);
1549 return 0;
1550}
1551
1552/* Switch off the clock of the uart controller. */
1553void tegra_uart_request_clock_off(struct uart_port *uport)
1554{
1555 unsigned long flags;
1556 struct tegra_uart_port *t;
1557 bool is_clk_disable = false;
1558
1559 if (IS_ERR_OR_NULL(uport))
1560 BUG();
1561
1562 dev_vdbg(uport->dev, "tegra_uart_request_clock_off");
1563
1564 t = container_of(uport, struct tegra_uart_port, uport);
1565 spin_lock_irqsave(&uport->lock, flags);
1566 if (t->uart_state == TEGRA_UART_OPENED) {
1567 is_clk_disable = true;
1568 t->uart_state = TEGRA_UART_CLOCK_OFF;
1569 }
1570 spin_unlock_irqrestore(&uport->lock, flags);
1571
1572 if (is_clk_disable)
1573 clk_disable(t->clk);
1574
1575 return;
1576}
1577
1578/* Switch on the clock of the uart controller */
1579void tegra_uart_request_clock_on(struct uart_port *uport)
1580{
1581 unsigned long flags;
1582 struct tegra_uart_port *t;
1583 bool is_clk_enable = false;
1584
1585 if (IS_ERR_OR_NULL(uport))
1586 BUG();
1587
1588 t = container_of(uport, struct tegra_uart_port, uport);
1589 spin_lock_irqsave(&uport->lock, flags);
1590 if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
1591 is_clk_enable = true;
1592 t->uart_state = TEGRA_UART_OPENED;
1593 }
1594 spin_unlock_irqrestore(&uport->lock, flags);
1595
1596 if (is_clk_enable)
1597 clk_enable(t->clk);
1598
1599 return;
1600}
1601
1602/* Set the modem control signals state of uart controller. */
1603void tegra_uart_set_mctrl(struct uart_port *uport, unsigned int mctrl)
1604{
1605 unsigned long flags;
1606 struct tegra_uart_port *t;
1607
1608 t = container_of(uport, struct tegra_uart_port, uport);
1609 if (t->uart_state != TEGRA_UART_OPENED) {
1610 dev_err(t->uport.dev, "Uart is in invalid state\n");
1611 return;
1612 }
1613
1614 spin_lock_irqsave(&uport->lock, flags);
1615 if (mctrl & TIOCM_RTS) {
1616 t->rts_active = true;
1617 set_rts(t, true);
1618 } else {
1619 t->rts_active = false;
1620 set_rts(t, false);
1621 }
1622
1623 if (mctrl & TIOCM_DTR)
1624 set_dtr(t, true);
1625 else
1626 set_dtr(t, false);
1627 spin_unlock_irqrestore(&uport->lock, flags);
1628 return;
1629}
1630
1631/*
1632 * Return the status of the transmit fifo whether empty or not.
1633 * Return 0 if tx fifo is not empty.
1634 * Return TIOCSER_TEMT if tx fifo is empty.
1635 */
1636int tegra_uart_is_tx_empty(struct uart_port *uport)
1637{
1638 return tegra_tx_empty(uport);
1639}
1640
1641static struct platform_driver tegra_uart_platform_driver = {
1642 .probe = tegra_uart_probe,
1643 .remove = __devexit_p(tegra_uart_remove),
1644 .suspend = tegra_uart_suspend,
1645 .resume = tegra_uart_resume,
1646 .driver = {
1647 .name = "tegra_uart"
1648 }
1649};
1650
1651static int __init tegra_uart_init(void)
1652{
1653 int ret;
1654
1655 ret = uart_register_driver(&tegra_uart_driver);
1656 if (unlikely(ret)) {
1657 pr_err("Could not register %s driver\n",
1658 tegra_uart_driver.driver_name);
1659 return ret;
1660 }
1661
1662 ret = platform_driver_register(&tegra_uart_platform_driver);
1663 if (unlikely(ret)) {
1664 pr_err("Could not register the UART platfrom driver\n");
1665 uart_unregister_driver(&tegra_uart_driver);
1666 return ret;
1667 }
1668
1669 pr_info("Initialized tegra uart driver\n");
1670 return 0;
1671}
1672
1673static void __exit tegra_uart_exit(void)
1674{
1675 pr_info("Unloading tegra uart driver\n");
1676 platform_driver_unregister(&tegra_uart_platform_driver);
1677 uart_unregister_driver(&tegra_uart_driver);
1678}
1679
1680module_init(tegra_uart_init);
1681module_exit(tegra_uart_exit);
1682MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 22:17:29 -0400