aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/tty/serial/pch_uart.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/tty/serial/pch_uart.c')
-rw-r--r--drivers/tty/serial/pch_uart.c452
1 files changed, 85 insertions, 367 deletions
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index 8318925fbf6..f913ed054c1 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -1,5 +1,5 @@
1/* 1/*
2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 * 3 *
4 *This program is free software; you can redistribute it and/or modify 4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by 5 *it under the terms of the GNU General Public License as published by
@@ -20,16 +20,10 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/pci.h> 21#include <linux/pci.h>
22#include <linux/serial_core.h> 22#include <linux/serial_core.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/interrupt.h> 23#include <linux/interrupt.h>
26#include <linux/io.h> 24#include <linux/io.h>
27#include <linux/dmi.h> 25#include <linux/dmi.h>
28#include <linux/console.h>
29#include <linux/nmi.h>
30#include <linux/delay.h>
31 26
32#include <linux/debugfs.h>
33#include <linux/dmaengine.h> 27#include <linux/dmaengine.h>
34#include <linux/pch_dma.h> 28#include <linux/pch_dma.h>
35 29
@@ -39,7 +33,6 @@ enum {
39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 33 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 34 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
41 PCH_UART_HANDLED_MS_INT_SHIFT, 35 PCH_UART_HANDLED_MS_INT_SHIFT,
42 PCH_UART_HANDLED_LS_INT_SHIFT,
43}; 36};
44 37
45enum { 38enum {
@@ -51,8 +44,8 @@ enum {
51 44
52/* Set the max number of UART port 45/* Set the max number of UART port
53 * Intel EG20T PCH: 4 port 46 * Intel EG20T PCH: 4 port
54 * LAPIS Semiconductor ML7213 IOH: 3 port 47 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
55 * LAPIS Semiconductor ML7223 IOH: 2 port 48 * OKI SEMICONDUCTOR ML7223 IOH: 2 port
56*/ 49*/
57#define PCH_UART_NR 4 50#define PCH_UART_NR 4
58 51
@@ -64,8 +57,6 @@ enum {
64 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 57 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
65#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 58#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
66 59
67#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
68
69#define PCH_UART_RBR 0x00 60#define PCH_UART_RBR 0x00
70#define PCH_UART_THR 0x00 61#define PCH_UART_THR 0x00
71 62
@@ -148,8 +139,6 @@ enum {
148#define PCH_UART_DLL 0x00 139#define PCH_UART_DLL 0x00
149#define PCH_UART_DLM 0x01 140#define PCH_UART_DLM 0x01
150 141
151#define PCH_UART_BRCSR 0x0E
152
153#define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 142#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
154#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 143#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
155#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 144#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
@@ -207,14 +196,6 @@ enum {
207 196
208#define PCI_VENDOR_ID_ROHM 0x10DB 197#define PCI_VENDOR_ID_ROHM 0x10DB
209 198
210#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
211
212#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
213#define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
214#define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
215#define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
216#define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
217
218struct pch_uart_buffer { 199struct pch_uart_buffer {
219 unsigned char *buf; 200 unsigned char *buf;
220 int size; 201 int size;
@@ -228,10 +209,11 @@ struct eg20t_port {
228 unsigned int iobase; 209 unsigned int iobase;
229 struct pci_dev *pdev; 210 struct pci_dev *pdev;
230 int fifo_size; 211 int fifo_size;
231 int uartclk; 212 int base_baud;
232 int start_tx; 213 int start_tx;
233 int start_rx; 214 int start_rx;
234 int tx_empty; 215 int tx_empty;
216 int int_dis_flag;
235 int trigger; 217 int trigger;
236 int trigger_level; 218 int trigger_level;
237 struct pch_uart_buffer rxbuf; 219 struct pch_uart_buffer rxbuf;
@@ -239,6 +221,7 @@ struct eg20t_port {
239 unsigned int fcr; 221 unsigned int fcr;
240 unsigned int mcr; 222 unsigned int mcr;
241 unsigned int use_dma; 223 unsigned int use_dma;
224 unsigned int use_dma_flag;
242 struct dma_async_tx_descriptor *desc_tx; 225 struct dma_async_tx_descriptor *desc_tx;
243 struct dma_async_tx_descriptor *desc_rx; 226 struct dma_async_tx_descriptor *desc_rx;
244 struct pch_dma_slave param_tx; 227 struct pch_dma_slave param_tx;
@@ -251,11 +234,6 @@ struct eg20t_port {
251 int tx_dma_use; 234 int tx_dma_use;
252 void *rx_buf_virt; 235 void *rx_buf_virt;
253 dma_addr_t rx_buf_dma; 236 dma_addr_t rx_buf_dma;
254
255 struct dentry *debugfs;
256
257 /* protect the eg20t_port private structure and io access to membase */
258 spinlock_t lock;
259}; 237};
260 238
261/** 239/**
@@ -296,106 +274,27 @@ static struct pch_uart_driver_data drv_dat[] = {
296 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 274 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
297}; 275};
298 276
299#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
300static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
301#endif
302static unsigned int default_baud = 9600; 277static unsigned int default_baud = 9600;
303static unsigned int user_uartclk = 0;
304static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 278static const int trigger_level_256[4] = { 1, 64, 128, 224 };
305static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 279static const int trigger_level_64[4] = { 1, 16, 32, 56 };
306static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 280static const int trigger_level_16[4] = { 1, 4, 8, 14 };
307static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 281static const int trigger_level_1[4] = { 1, 1, 1, 1 };
308 282
309#ifdef CONFIG_DEBUG_FS 283static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
310 284 int base_baud)
311#define PCH_REGS_BUFSIZE 1024
312
313
314static ssize_t port_show_regs(struct file *file, char __user *user_buf,
315 size_t count, loff_t *ppos)
316{ 285{
317 struct eg20t_port *priv = file->private_data; 286 struct eg20t_port *priv = pci_get_drvdata(pdev);
318 char *buf;
319 u32 len = 0;
320 ssize_t ret;
321 unsigned char lcr;
322
323 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
324 if (!buf)
325 return 0;
326
327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
328 "PCH EG20T port[%d] regs:\n", priv->port.line);
329
330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
331 "=================================\n");
332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
333 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345 "BRCSR: \t0x%02x\n",
346 ioread8(priv->membase + PCH_UART_BRCSR));
347
348 lcr = ioread8(priv->membase + UART_LCR);
349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
350 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
351 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
352 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
353 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
354 iowrite8(lcr, priv->membase + UART_LCR);
355
356 if (len > PCH_REGS_BUFSIZE)
357 len = PCH_REGS_BUFSIZE;
358 287
359 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 288 priv->trigger_level = 1;
360 kfree(buf); 289 priv->fcr = 0;
361 return ret;
362} 290}
363 291
364static const struct file_operations port_regs_ops = { 292static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
365 .owner = THIS_MODULE,
366 .open = simple_open,
367 .read = port_show_regs,
368 .llseek = default_llseek,
369};
370#endif /* CONFIG_DEBUG_FS */
371
372/* Return UART clock, checking for board specific clocks. */
373static int pch_uart_get_uartclk(void)
374{ 293{
375 const char *cmp; 294 unsigned int msr = ioread8(base + UART_MSR);
295 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
376 296
377 if (user_uartclk) 297 return msr;
378 return user_uartclk;
379
380 cmp = dmi_get_system_info(DMI_BOARD_NAME);
381 if (cmp && strstr(cmp, "CM-iTC"))
382 return CMITC_UARTCLK;
383
384 cmp = dmi_get_system_info(DMI_BIOS_VERSION);
385 if (cmp && strnstr(cmp, "FRI2", 4))
386 return FRI2_64_UARTCLK;
387
388 cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
389 if (cmp && strstr(cmp, "Fish River Island II"))
390 return FRI2_48_UARTCLK;
391
392 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
393 cmp = dmi_get_system_info(DMI_BOARD_NAME);
394 if (cmp && (strstr(cmp, "COMe-mTT") ||
395 strstr(cmp, "nanoETXexpress-TT")))
396 return NTC1_UARTCLK;
397
398 return DEFAULT_UARTCLK;
399} 298}
400 299
401static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 300static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
@@ -421,7 +320,7 @@ static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
421 unsigned int dll, dlm, lcr; 320 unsigned int dll, dlm, lcr;
422 int div; 321 int div;
423 322
424 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 323 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
425 if (div < 0 || USHRT_MAX <= div) { 324 if (div < 0 || USHRT_MAX <= div) {
426 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 325 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
427 return -EINVAL; 326 return -EINVAL;
@@ -531,9 +430,8 @@ static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
531 430
532static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 431static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
533{ 432{
534 unsigned int msr = ioread8(priv->membase + UART_MSR); 433 priv->dmsr = 0;
535 priv->dmsr = msr & PCH_UART_MSR_DELTA; 434 return get_msr(priv, priv->membase);
536 return (u8)msr;
537} 435}
538 436
539static void pch_uart_hal_write(struct eg20t_port *priv, 437static void pch_uart_hal_write(struct eg20t_port *priv,
@@ -564,10 +462,14 @@ static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
564 return i; 462 return i;
565} 463}
566 464
567static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 465static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
568{ 466{
569 return ioread8(priv->membase + UART_IIR) &\ 467 unsigned int iir;
570 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 468 int ret;
469
470 iir = ioread8(priv->membase + UART_IIR);
471 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
472 return ret;
571} 473}
572 474
573static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 475static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
@@ -610,7 +512,7 @@ static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
610 512
611static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 513static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
612{ 514{
613 int ret = 0; 515 int ret;
614 struct uart_port *port = &priv->port; 516 struct uart_port *port = &priv->port;
615 517
616 if (port->x_char) { 518 if (port->x_char) {
@@ -619,6 +521,8 @@ static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
619 buf[0] = port->x_char; 521 buf[0] = port->x_char;
620 port->x_char = 0; 522 port->x_char = 0;
621 ret = 1; 523 ret = 1;
524 } else {
525 ret = 0;
622 } 526 }
623 527
624 return ret; 528 return ret;
@@ -666,13 +570,10 @@ static void pch_free_dma(struct uart_port *port)
666 dma_release_channel(priv->chan_rx); 570 dma_release_channel(priv->chan_rx);
667 priv->chan_rx = NULL; 571 priv->chan_rx = NULL;
668 } 572 }
669 573 if (sg_dma_address(&priv->sg_rx))
670 if (priv->rx_buf_dma) { 574 dma_free_coherent(port->dev, port->fifosize,
671 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 575 sg_virt(&priv->sg_rx),
672 priv->rx_buf_dma); 576 sg_dma_address(&priv->sg_rx));
673 priv->rx_buf_virt = NULL;
674 priv->rx_buf_dma = 0;
675 }
676 577
677 return; 578 return;
678} 579}
@@ -757,8 +658,7 @@ static void pch_dma_rx_complete(void *arg)
757 tty_flip_buffer_push(tty); 658 tty_flip_buffer_push(tty);
758 tty_kref_put(tty); 659 tty_kref_put(tty);
759 async_tx_ack(priv->desc_rx); 660 async_tx_ack(priv->desc_rx);
760 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 661 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
761 PCH_UART_HAL_RX_ERR_INT);
762} 662}
763 663
764static void pch_dma_tx_complete(void *arg) 664static void pch_dma_tx_complete(void *arg)
@@ -813,8 +713,7 @@ static int handle_rx_to(struct eg20t_port *priv)
813 int rx_size; 713 int rx_size;
814 int ret; 714 int ret;
815 if (!priv->start_rx) { 715 if (!priv->start_rx) {
816 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 716 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
817 PCH_UART_HAL_RX_ERR_INT);
818 return 0; 717 return 0;
819 } 718 }
820 buf = &priv->rxbuf; 719 buf = &priv->rxbuf;
@@ -852,8 +751,8 @@ static int dma_handle_rx(struct eg20t_port *priv)
852 751
853 sg_dma_address(sg) = priv->rx_buf_dma; 752 sg_dma_address(sg) = priv->rx_buf_dma;
854 753
855 desc = dmaengine_prep_slave_sg(priv->chan_rx, 754 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
856 sg, 1, DMA_DEV_TO_MEM, 755 sg, 1, DMA_FROM_DEVICE,
857 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 756 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
858 757
859 if (!desc) 758 if (!desc)
@@ -979,10 +878,6 @@ static unsigned int dma_handle_tx(struct eg20t_port *priv)
979 priv->tx_dma_use = 1; 878 priv->tx_dma_use = 1;
980 879
981 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 880 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
982 if (!priv->sg_tx_p) {
983 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
984 return 0;
985 }
986 881
987 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 882 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
988 sg = priv->sg_tx_p; 883 sg = priv->sg_tx_p;
@@ -1015,8 +910,8 @@ static unsigned int dma_handle_tx(struct eg20t_port *priv)
1015 sg_dma_len(sg) = size; 910 sg_dma_len(sg) = size;
1016 } 911 }
1017 912
1018 desc = dmaengine_prep_slave_sg(priv->chan_tx, 913 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
1019 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 914 priv->sg_tx_p, nent, DMA_TO_DEVICE,
1020 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 915 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1021 if (!desc) { 916 if (!desc) {
1022 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 917 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
@@ -1062,17 +957,12 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1062 unsigned int handled; 957 unsigned int handled;
1063 u8 lsr; 958 u8 lsr;
1064 int ret = 0; 959 int ret = 0;
1065 unsigned char iid; 960 unsigned int iid;
1066 unsigned long flags; 961 unsigned long flags;
1067 int next = 1;
1068 u8 msr;
1069 962
1070 spin_lock_irqsave(&priv->lock, flags); 963 spin_lock_irqsave(&priv->port.lock, flags);
1071 handled = 0; 964 handled = 0;
1072 while (next) { 965 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
1073 iid = pch_uart_hal_get_iid(priv);
1074 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1075 break;
1076 switch (iid) { 966 switch (iid) {
1077 case PCH_UART_IID_RLS: /* Receiver Line Status */ 967 case PCH_UART_IID_RLS: /* Receiver Line Status */
1078 lsr = pch_uart_hal_get_line_status(priv); 968 lsr = pch_uart_hal_get_line_status(priv);
@@ -1080,20 +970,16 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1080 UART_LSR_PE | UART_LSR_OE)) { 970 UART_LSR_PE | UART_LSR_OE)) {
1081 pch_uart_err_ir(priv, lsr); 971 pch_uart_err_ir(priv, lsr);
1082 ret = PCH_UART_HANDLED_RX_ERR_INT; 972 ret = PCH_UART_HANDLED_RX_ERR_INT;
1083 } else {
1084 ret = PCH_UART_HANDLED_LS_INT;
1085 } 973 }
1086 break; 974 break;
1087 case PCH_UART_IID_RDR: /* Received Data Ready */ 975 case PCH_UART_IID_RDR: /* Received Data Ready */
1088 if (priv->use_dma) { 976 if (priv->use_dma) {
1089 pch_uart_hal_disable_interrupt(priv, 977 pch_uart_hal_disable_interrupt(priv,
1090 PCH_UART_HAL_RX_INT | 978 PCH_UART_HAL_RX_INT);
1091 PCH_UART_HAL_RX_ERR_INT);
1092 ret = dma_handle_rx(priv); 979 ret = dma_handle_rx(priv);
1093 if (!ret) 980 if (!ret)
1094 pch_uart_hal_enable_interrupt(priv, 981 pch_uart_hal_enable_interrupt(priv,
1095 PCH_UART_HAL_RX_INT | 982 PCH_UART_HAL_RX_INT);
1096 PCH_UART_HAL_RX_ERR_INT);
1097 } else { 983 } else {
1098 ret = handle_rx(priv); 984 ret = handle_rx(priv);
1099 } 985 }
@@ -1110,24 +996,22 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1110 ret = handle_tx(priv); 996 ret = handle_tx(priv);
1111 break; 997 break;
1112 case PCH_UART_IID_MS: /* Modem Status */ 998 case PCH_UART_IID_MS: /* Modem Status */
1113 msr = pch_uart_hal_get_modem(priv); 999 ret = PCH_UART_HANDLED_MS_INT;
1114 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1115 means final interrupt */
1116 if ((msr & UART_MSR_ANY_DELTA) == 0)
1117 break;
1118 ret |= PCH_UART_HANDLED_MS_INT;
1119 break; 1000 break;
1120 default: /* Never junp to this label */ 1001 default: /* Never junp to this label */
1121 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1002 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1122 iid, jiffies); 1003 iid, jiffies);
1123 ret = -1; 1004 ret = -1;
1124 next = 0;
1125 break; 1005 break;
1126 } 1006 }
1127 handled |= (unsigned int)ret; 1007 handled |= (unsigned int)ret;
1128 } 1008 }
1009 if (handled == 0 && iid <= 1) {
1010 if (priv->int_dis_flag)
1011 priv->int_dis_flag = 0;
1012 }
1129 1013
1130 spin_unlock_irqrestore(&priv->lock, flags); 1014 spin_unlock_irqrestore(&priv->port.lock, flags);
1131 return IRQ_RETVAL(handled); 1015 return IRQ_RETVAL(handled);
1132} 1016}
1133 1017
@@ -1136,12 +1020,14 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1136static unsigned int pch_uart_tx_empty(struct uart_port *port) 1020static unsigned int pch_uart_tx_empty(struct uart_port *port)
1137{ 1021{
1138 struct eg20t_port *priv; 1022 struct eg20t_port *priv;
1139 1023 int ret;
1140 priv = container_of(port, struct eg20t_port, port); 1024 priv = container_of(port, struct eg20t_port, port);
1141 if (priv->tx_empty) 1025 if (priv->tx_empty)
1142 return TIOCSER_TEMT; 1026 ret = TIOCSER_TEMT;
1143 else 1027 else
1144 return 0; 1028 ret = 0;
1029
1030 return ret;
1145} 1031}
1146 1032
1147/* Returns the current state of modem control inputs. */ 1033/* Returns the current state of modem control inputs. */
@@ -1219,8 +1105,8 @@ static void pch_uart_stop_rx(struct uart_port *port)
1219 struct eg20t_port *priv; 1105 struct eg20t_port *priv;
1220 priv = container_of(port, struct eg20t_port, port); 1106 priv = container_of(port, struct eg20t_port, port);
1221 priv->start_rx = 0; 1107 priv->start_rx = 0;
1222 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1108 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1223 PCH_UART_HAL_RX_ERR_INT); 1109 priv->int_dis_flag = 1;
1224} 1110}
1225 1111
1226/* Enable the modem status interrupts. */ 1112/* Enable the modem status interrupts. */
@@ -1238,9 +1124,9 @@ static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1238 unsigned long flags; 1124 unsigned long flags;
1239 1125
1240 priv = container_of(port, struct eg20t_port, port); 1126 priv = container_of(port, struct eg20t_port, port);
1241 spin_lock_irqsave(&priv->lock, flags); 1127 spin_lock_irqsave(&port->lock, flags);
1242 pch_uart_hal_set_break(priv, ctl); 1128 pch_uart_hal_set_break(priv, ctl);
1243 spin_unlock_irqrestore(&priv->lock, flags); 1129 spin_unlock_irqrestore(&port->lock, flags);
1244} 1130}
1245 1131
1246/* Grab any interrupt resources and initialise any low level driver state. */ 1132/* Grab any interrupt resources and initialise any low level driver state. */
@@ -1255,9 +1141,9 @@ static int pch_uart_startup(struct uart_port *port)
1255 priv->tx_empty = 1; 1141 priv->tx_empty = 1;
1256 1142
1257 if (port->uartclk) 1143 if (port->uartclk)
1258 priv->uartclk = port->uartclk; 1144 priv->base_baud = port->uartclk;
1259 else 1145 else
1260 port->uartclk = priv->uartclk; 1146 port->uartclk = priv->base_baud;
1261 1147
1262 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1148 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1263 ret = pch_uart_hal_set_line(priv, default_baud, 1149 ret = pch_uart_hal_set_line(priv, default_baud,
@@ -1275,7 +1161,6 @@ static int pch_uart_startup(struct uart_port *port)
1275 break; 1161 break;
1276 case 16: 1162 case 16:
1277 fifo_size = PCH_UART_HAL_FIFO16; 1163 fifo_size = PCH_UART_HAL_FIFO16;
1278 break;
1279 case 1: 1164 case 1:
1280 default: 1165 default:
1281 fifo_size = PCH_UART_HAL_FIFO_DIS; 1166 fifo_size = PCH_UART_HAL_FIFO_DIS;
@@ -1313,8 +1198,7 @@ static int pch_uart_startup(struct uart_port *port)
1313 pch_request_dma(port); 1198 pch_request_dma(port);
1314 1199
1315 priv->start_rx = 1; 1200 priv->start_rx = 1;
1316 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1201 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1317 PCH_UART_HAL_RX_ERR_INT);
1318 uart_update_timeout(port, CS8, default_baud); 1202 uart_update_timeout(port, CS8, default_baud);
1319 1203
1320 return 0; 1204 return 0;
@@ -1372,13 +1256,14 @@ static void pch_uart_set_termios(struct uart_port *port,
1372 stb = PCH_UART_HAL_STB1; 1256 stb = PCH_UART_HAL_STB1;
1373 1257
1374 if (termios->c_cflag & PARENB) { 1258 if (termios->c_cflag & PARENB) {
1375 if (termios->c_cflag & PARODD) 1259 if (!(termios->c_cflag & PARODD))
1376 parity = PCH_UART_HAL_PARITY_ODD; 1260 parity = PCH_UART_HAL_PARITY_ODD;
1377 else 1261 else
1378 parity = PCH_UART_HAL_PARITY_EVEN; 1262 parity = PCH_UART_HAL_PARITY_EVEN;
1379 1263
1380 } else 1264 } else {
1381 parity = PCH_UART_HAL_PARITY_NONE; 1265 parity = PCH_UART_HAL_PARITY_NONE;
1266 }
1382 1267
1383 /* Only UART0 has auto hardware flow function */ 1268 /* Only UART0 has auto hardware flow function */
1384 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1269 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
@@ -1390,8 +1275,7 @@ static void pch_uart_set_termios(struct uart_port *port,
1390 1275
1391 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1276 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1392 1277
1393 spin_lock_irqsave(&priv->lock, flags); 1278 spin_lock_irqsave(&port->lock, flags);
1394 spin_lock(&port->lock);
1395 1279
1396 uart_update_timeout(port, termios->c_cflag, baud); 1280 uart_update_timeout(port, termios->c_cflag, baud);
1397 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1281 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
@@ -1404,8 +1288,7 @@ static void pch_uart_set_termios(struct uart_port *port,
1404 tty_termios_encode_baud_rate(termios, baud, baud); 1288 tty_termios_encode_baud_rate(termios, baud, baud);
1405 1289
1406out: 1290out:
1407 spin_unlock(&port->lock); 1291 spin_unlock_irqrestore(&port->lock, flags);
1408 spin_unlock_irqrestore(&priv->lock, flags);
1409} 1292}
1410 1293
1411static const char *pch_uart_type(struct uart_port *port) 1294static const char *pch_uart_type(struct uart_port *port)
@@ -1471,10 +1354,9 @@ static int pch_uart_verify_port(struct uart_port *port,
1471 __func__); 1354 __func__);
1472 return -EOPNOTSUPP; 1355 return -EOPNOTSUPP;
1473#endif 1356#endif
1474 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1475 if (!priv->use_dma)
1476 pch_request_dma(port);
1477 priv->use_dma = 1; 1357 priv->use_dma = 1;
1358 priv->use_dma_flag = 1;
1359 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1478 } 1360 }
1479 1361
1480 return 0; 1362 return 0;
@@ -1501,148 +1383,6 @@ static struct uart_ops pch_uart_ops = {
1501 .verify_port = pch_uart_verify_port 1383 .verify_port = pch_uart_verify_port
1502}; 1384};
1503 1385
1504#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1505
1506/*
1507 * Wait for transmitter & holding register to empty
1508 */
1509static void wait_for_xmitr(struct eg20t_port *up, int bits)
1510{
1511 unsigned int status, tmout = 10000;
1512
1513 /* Wait up to 10ms for the character(s) to be sent. */
1514 for (;;) {
1515 status = ioread8(up->membase + UART_LSR);
1516
1517 if ((status & bits) == bits)
1518 break;
1519 if (--tmout == 0)
1520 break;
1521 udelay(1);
1522 }
1523
1524 /* Wait up to 1s for flow control if necessary */
1525 if (up->port.flags & UPF_CONS_FLOW) {
1526 unsigned int tmout;
1527 for (tmout = 1000000; tmout; tmout--) {
1528 unsigned int msr = ioread8(up->membase + UART_MSR);
1529 if (msr & UART_MSR_CTS)
1530 break;
1531 udelay(1);
1532 touch_nmi_watchdog();
1533 }
1534 }
1535}
1536
1537static void pch_console_putchar(struct uart_port *port, int ch)
1538{
1539 struct eg20t_port *priv =
1540 container_of(port, struct eg20t_port, port);
1541
1542 wait_for_xmitr(priv, UART_LSR_THRE);
1543 iowrite8(ch, priv->membase + PCH_UART_THR);
1544}
1545
1546/*
1547 * Print a string to the serial port trying not to disturb
1548 * any possible real use of the port...
1549 *
1550 * The console_lock must be held when we get here.
1551 */
1552static void
1553pch_console_write(struct console *co, const char *s, unsigned int count)
1554{
1555 struct eg20t_port *priv;
1556 unsigned long flags;
1557 int priv_locked = 1;
1558 int port_locked = 1;
1559 u8 ier;
1560
1561 priv = pch_uart_ports[co->index];
1562
1563 touch_nmi_watchdog();
1564
1565 local_irq_save(flags);
1566 if (priv->port.sysrq) {
1567 spin_lock(&priv->lock);
1568 /* serial8250_handle_port() already took the port lock */
1569 port_locked = 0;
1570 } else if (oops_in_progress) {
1571 priv_locked = spin_trylock(&priv->lock);
1572 port_locked = spin_trylock(&priv->port.lock);
1573 } else {
1574 spin_lock(&priv->lock);
1575 spin_lock(&priv->port.lock);
1576 }
1577
1578 /*
1579 * First save the IER then disable the interrupts
1580 */
1581 ier = ioread8(priv->membase + UART_IER);
1582
1583 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1584
1585 uart_console_write(&priv->port, s, count, pch_console_putchar);
1586
1587 /*
1588 * Finally, wait for transmitter to become empty
1589 * and restore the IER
1590 */
1591 wait_for_xmitr(priv, BOTH_EMPTY);
1592 iowrite8(ier, priv->membase + UART_IER);
1593
1594 if (port_locked)
1595 spin_unlock(&priv->port.lock);
1596 if (priv_locked)
1597 spin_unlock(&priv->lock);
1598 local_irq_restore(flags);
1599}
1600
1601static int __init pch_console_setup(struct console *co, char *options)
1602{
1603 struct uart_port *port;
1604 int baud = default_baud;
1605 int bits = 8;
1606 int parity = 'n';
1607 int flow = 'n';
1608
1609 /*
1610 * Check whether an invalid uart number has been specified, and
1611 * if so, search for the first available port that does have
1612 * console support.
1613 */
1614 if (co->index >= PCH_UART_NR)
1615 co->index = 0;
1616 port = &pch_uart_ports[co->index]->port;
1617
1618 if (!port || (!port->iobase && !port->membase))
1619 return -ENODEV;
1620
1621 port->uartclk = pch_uart_get_uartclk();
1622
1623 if (options)
1624 uart_parse_options(options, &baud, &parity, &bits, &flow);
1625
1626 return uart_set_options(port, co, baud, parity, bits, flow);
1627}
1628
1629static struct uart_driver pch_uart_driver;
1630
1631static struct console pch_console = {
1632 .name = PCH_UART_DRIVER_DEVICE,
1633 .write = pch_console_write,
1634 .device = uart_console_device,
1635 .setup = pch_console_setup,
1636 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1637 .index = -1,
1638 .data = &pch_uart_driver,
1639};
1640
1641#define PCH_CONSOLE (&pch_console)
1642#else
1643#define PCH_CONSOLE NULL
1644#endif
1645
1646static struct uart_driver pch_uart_driver = { 1386static struct uart_driver pch_uart_driver = {
1647 .owner = THIS_MODULE, 1387 .owner = THIS_MODULE,
1648 .driver_name = KBUILD_MODNAME, 1388 .driver_name = KBUILD_MODNAME,
@@ -1650,7 +1390,6 @@ static struct uart_driver pch_uart_driver = {
1650 .major = 0, 1390 .major = 0,
1651 .minor = 0, 1391 .minor = 0,
1652 .nr = PCH_UART_NR, 1392 .nr = PCH_UART_NR,
1653 .cons = PCH_CONSOLE,
1654}; 1393};
1655 1394
1656static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1395static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
@@ -1661,10 +1400,10 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1661 unsigned int iobase; 1400 unsigned int iobase;
1662 unsigned int mapbase; 1401 unsigned int mapbase;
1663 unsigned char *rxbuf; 1402 unsigned char *rxbuf;
1664 int fifosize; 1403 int fifosize, base_baud;
1665 int port_type; 1404 int port_type;
1666 struct pch_uart_driver_data *board; 1405 struct pch_uart_driver_data *board;
1667 char name[32]; /* for debugfs file name */ 1406 const char *board_name;
1668 1407
1669 board = &drv_dat[id->driver_data]; 1408 board = &drv_dat[id->driver_data];
1670 port_type = board->port_type; 1409 port_type = board->port_type;
@@ -1677,6 +1416,13 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1677 if (!rxbuf) 1416 if (!rxbuf)
1678 goto init_port_free_txbuf; 1417 goto init_port_free_txbuf;
1679 1418
1419 base_baud = 1843200; /* 1.8432MHz */
1420
1421 /* quirk for CM-iTC board */
1422 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1423 if (board_name && strstr(board_name, "CM-iTC"))
1424 base_baud = 192000000; /* 192.0MHz */
1425
1680 switch (port_type) { 1426 switch (port_type) {
1681 case PORT_UNKNOWN: 1427 case PORT_UNKNOWN:
1682 fifosize = 256; /* EG20T/ML7213: UART0 */ 1428 fifosize = 256; /* EG20T/ML7213: UART0 */
@@ -1690,9 +1436,6 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1690 } 1436 }
1691 1437
1692 pci_enable_msi(pdev); 1438 pci_enable_msi(pdev);
1693 pci_set_master(pdev);
1694
1695 spin_lock_init(&priv->lock);
1696 1439
1697 iobase = pci_resource_start(pdev, 0); 1440 iobase = pci_resource_start(pdev, 0);
1698 mapbase = pci_resource_start(pdev, 1); 1441 mapbase = pci_resource_start(pdev, 1);
@@ -1704,7 +1447,7 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1704 priv->rxbuf.size = PAGE_SIZE; 1447 priv->rxbuf.size = PAGE_SIZE;
1705 1448
1706 priv->fifo_size = fifosize; 1449 priv->fifo_size = fifosize;
1707 priv->uartclk = pch_uart_get_uartclk(); 1450 priv->base_baud = base_baud;
1708 priv->port_type = PORT_MAX_8250 + port_type + 1; 1451 priv->port_type = PORT_MAX_8250 + port_type + 1;
1709 priv->port.dev = &pdev->dev; 1452 priv->port.dev = &pdev->dev;
1710 priv->port.iobase = iobase; 1453 priv->port.iobase = iobase;
@@ -1721,28 +1464,15 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1721 spin_lock_init(&priv->port.lock); 1464 spin_lock_init(&priv->port.lock);
1722 1465
1723 pci_set_drvdata(pdev, priv); 1466 pci_set_drvdata(pdev, priv);
1724 priv->trigger_level = 1; 1467 pch_uart_hal_request(pdev, fifosize, base_baud);
1725 priv->fcr = 0;
1726 1468
1727#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1728 pch_uart_ports[board->line_no] = priv;
1729#endif
1730 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1469 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1731 if (ret < 0) 1470 if (ret < 0)
1732 goto init_port_hal_free; 1471 goto init_port_hal_free;
1733 1472
1734#ifdef CONFIG_DEBUG_FS
1735 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1736 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1737 NULL, priv, &port_regs_ops);
1738#endif
1739
1740 return priv; 1473 return priv;
1741 1474
1742init_port_hal_free: 1475init_port_hal_free:
1743#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1744 pch_uart_ports[board->line_no] = NULL;
1745#endif
1746 free_page((unsigned long)rxbuf); 1476 free_page((unsigned long)rxbuf);
1747init_port_free_txbuf: 1477init_port_free_txbuf:
1748 kfree(priv); 1478 kfree(priv);
@@ -1753,11 +1483,6 @@ init_port_alloc_err:
1753 1483
1754static void pch_uart_exit_port(struct eg20t_port *priv) 1484static void pch_uart_exit_port(struct eg20t_port *priv)
1755{ 1485{
1756
1757#ifdef CONFIG_DEBUG_FS
1758 if (priv->debugfs)
1759 debugfs_remove(priv->debugfs);
1760#endif
1761 uart_remove_one_port(&pch_uart_driver, &priv->port); 1486 uart_remove_one_port(&pch_uart_driver, &priv->port);
1762 pci_set_drvdata(priv->pdev, NULL); 1487 pci_set_drvdata(priv->pdev, NULL);
1763 free_page((unsigned long)priv->rxbuf.buf); 1488 free_page((unsigned long)priv->rxbuf.buf);
@@ -1765,13 +1490,11 @@ static void pch_uart_exit_port(struct eg20t_port *priv)
1765 1490
1766static void pch_uart_pci_remove(struct pci_dev *pdev) 1491static void pch_uart_pci_remove(struct pci_dev *pdev)
1767{ 1492{
1768 struct eg20t_port *priv = pci_get_drvdata(pdev); 1493 struct eg20t_port *priv;
1769 1494
1770 pci_disable_msi(pdev); 1495 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1771 1496
1772#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1497 pci_disable_msi(pdev);
1773 pch_uart_ports[priv->port.line] = NULL;
1774#endif
1775 pch_uart_exit_port(priv); 1498 pch_uart_exit_port(priv);
1776 pci_disable_device(pdev); 1499 pci_disable_device(pdev);
1777 kfree(priv); 1500 kfree(priv);
@@ -1839,7 +1562,7 @@ static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1839 {0,}, 1562 {0,},
1840}; 1563};
1841 1564
1842static int pch_uart_pci_probe(struct pci_dev *pdev, 1565static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1843 const struct pci_device_id *id) 1566 const struct pci_device_id *id)
1844{ 1567{
1845 int ret; 1568 int ret;
@@ -1869,7 +1592,7 @@ static struct pci_driver pch_uart_pci_driver = {
1869 .name = "pch_uart", 1592 .name = "pch_uart",
1870 .id_table = pch_uart_pci_id, 1593 .id_table = pch_uart_pci_id,
1871 .probe = pch_uart_pci_probe, 1594 .probe = pch_uart_pci_probe,
1872 .remove = pch_uart_pci_remove, 1595 .remove = __devexit_p(pch_uart_pci_remove),
1873 .suspend = pch_uart_pci_suspend, 1596 .suspend = pch_uart_pci_suspend,
1874 .resume = pch_uart_pci_resume, 1597 .resume = pch_uart_pci_resume,
1875}; 1598};
@@ -1902,8 +1625,3 @@ module_exit(pch_uart_module_exit);
1902MODULE_LICENSE("GPL v2"); 1625MODULE_LICENSE("GPL v2");
1903MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1626MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1904module_param(default_baud, uint, S_IRUGO); 1627module_param(default_baud, uint, S_IRUGO);
1905MODULE_PARM_DESC(default_baud,
1906 "Default BAUD for initial driver state and console (default 9600)");
1907module_param(user_uartclk, uint, S_IRUGO);
1908MODULE_PARM_DESC(user_uartclk,
1909 "Override UART default or board specific UART clock");