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-rw-r--r--drivers/staging/sxg/sxg_os.h41
-rw-r--r--drivers/staging/sxg/sxghif.h410
-rw-r--r--drivers/staging/sxg/sxghw.h284
-rw-r--r--drivers/staging/sxg/sxgphycode.h12
4 files changed, 368 insertions, 379 deletions
diff --git a/drivers/staging/sxg/sxg_os.h b/drivers/staging/sxg/sxg_os.h
index 26fb0ffafa5..01182689aab 100644
--- a/drivers/staging/sxg/sxg_os.h
+++ b/drivers/staging/sxg/sxg_os.h
@@ -44,7 +44,6 @@
44#define FALSE (0) 44#define FALSE (0)
45#define TRUE (1) 45#define TRUE (1)
46 46
47
48typedef struct _LIST_ENTRY { 47typedef struct _LIST_ENTRY {
49 struct _LIST_ENTRY *nle_flink; 48 struct _LIST_ENTRY *nle_flink;
50 struct _LIST_ENTRY *nle_blink; 49 struct _LIST_ENTRY *nle_blink;
@@ -69,35 +68,32 @@ typedef struct _LIST_ENTRY {
69 68
70/* These two have to be inlined since they return things. */ 69/* These two have to be inlined since they return things. */
71 70
72static __inline PLIST_ENTRY 71static __inline PLIST_ENTRY RemoveHeadList(list_entry * l)
73RemoveHeadList(list_entry *l)
74{ 72{
75 list_entry *f; 73 list_entry *f;
76 list_entry *e; 74 list_entry *e;
77 75
78 e = l->nle_flink; 76 e = l->nle_flink;
79 f = e->nle_flink; 77 f = e->nle_flink;
80 l->nle_flink = f; 78 l->nle_flink = f;
81 f->nle_blink = l; 79 f->nle_blink = l;
82 80
83 return (e); 81 return (e);
84} 82}
85 83
86static __inline PLIST_ENTRY 84static __inline PLIST_ENTRY RemoveTailList(list_entry * l)
87RemoveTailList(list_entry *l)
88{ 85{
89 list_entry *b; 86 list_entry *b;
90 list_entry *e; 87 list_entry *e;
91 88
92 e = l->nle_blink; 89 e = l->nle_blink;
93 b = e->nle_blink; 90 b = e->nle_blink;
94 l->nle_blink = b; 91 l->nle_blink = b;
95 b->nle_flink = l; 92 b->nle_flink = l;
96 93
97 return (e); 94 return (e);
98} 95}
99 96
100
101#define InsertTailList(l, e) \ 97#define InsertTailList(l, e) \
102 do { \ 98 do { \
103 list_entry *b; \ 99 list_entry *b; \
@@ -120,7 +116,6 @@ RemoveTailList(list_entry *l)
120 (l)->nle_flink = (e); \ 116 (l)->nle_flink = (e); \
121 } while (0) 117 } while (0)
122 118
123
124#define ATK_DEBUG 1 119#define ATK_DEBUG 1
125 120
126#if ATK_DEBUG 121#if ATK_DEBUG
@@ -133,7 +128,6 @@ RemoveTailList(list_entry *l)
133#define SLIC_TIMESTAMP(value) 128#define SLIC_TIMESTAMP(value)
134#endif 129#endif
135 130
136
137/****************** SXG DEFINES *****************************************/ 131/****************** SXG DEFINES *****************************************/
138 132
139#ifdef ATKDBG 133#ifdef ATKDBG
@@ -150,5 +144,4 @@ RemoveTailList(list_entry *l)
150#define WRITE_REG64(a,reg,value,cpu) sxg_reg64_write((a),(&reg),(value),(cpu)) 144#define WRITE_REG64(a,reg,value,cpu) sxg_reg64_write((a),(&reg),(value),(cpu))
151#define READ_REG(reg,value) (value) = readl((void __iomem *)(&reg)) 145#define READ_REG(reg,value) (value) = readl((void __iomem *)(&reg))
152 146
153#endif /* _SLIC_OS_SPECIFIC_H_ */ 147#endif /* _SLIC_OS_SPECIFIC_H_ */
154
diff --git a/drivers/staging/sxg/sxghif.h b/drivers/staging/sxg/sxghif.h
index ed26ceaa131..88bffbaa3be 100644
--- a/drivers/staging/sxg/sxghif.h
+++ b/drivers/staging/sxg/sxghif.h
@@ -14,119 +14,119 @@
14 *******************************************************************************/ 14 *******************************************************************************/
15typedef struct _SXG_UCODE_REGS { 15typedef struct _SXG_UCODE_REGS {
16 // Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0 16 // Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0
17 u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control 17 u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control
18 u32 RsvdReg1; // Code = 1 - TOE -NA 18 u32 RsvdReg1; // Code = 1 - TOE -NA
19 u32 RsvdReg2; // Code = 2 - TOE -NA 19 u32 RsvdReg2; // Code = 2 - TOE -NA
20 u32 RsvdReg3; // Code = 3 - TOE -NA 20 u32 RsvdReg3; // Code = 3 - TOE -NA
21 u32 RsvdReg4; // Code = 4 - TOE -NA 21 u32 RsvdReg4; // Code = 4 - TOE -NA
22 u32 RsvdReg5; // Code = 5 - TOE -NA 22 u32 RsvdReg5; // Code = 5 - TOE -NA
23 u32 CardUp; // Code = 6 - Microcode initialized when 1 23 u32 CardUp; // Code = 6 - Microcode initialized when 1
24 u32 RsvdReg7; // Code = 7 - TOE -NA 24 u32 RsvdReg7; // Code = 7 - TOE -NA
25 u32 CodeNotUsed[8]; // Codes 8-15 not used. ExCode = 0 25 u32 CodeNotUsed[8]; // Codes 8-15 not used. ExCode = 0
26 // This brings us to ExCode 1 at address 0x40 = Interrupt status pointer 26 // This brings us to ExCode 1 at address 0x40 = Interrupt status pointer
27 u32 Isp; // Code = 0 (extended), ExCode = 1 27 u32 Isp; // Code = 0 (extended), ExCode = 1
28 u32 PadEx1[15]; // Codes 1-15 not used with extended codes 28 u32 PadEx1[15]; // Codes 1-15 not used with extended codes
29 // ExCode 2 = Interrupt Status Register 29 // ExCode 2 = Interrupt Status Register
30 u32 Isr; // Code = 0 (extended), ExCode = 2 30 u32 Isr; // Code = 0 (extended), ExCode = 2
31 u32 PadEx2[15]; 31 u32 PadEx2[15];
32 // ExCode 3 = Event base register. Location of event rings 32 // ExCode 3 = Event base register. Location of event rings
33 u32 EventBase; // Code = 0 (extended), ExCode = 3 33 u32 EventBase; // Code = 0 (extended), ExCode = 3
34 u32 PadEx3[15]; 34 u32 PadEx3[15];
35 // ExCode 4 = Event ring size 35 // ExCode 4 = Event ring size
36 u32 EventSize; // Code = 0 (extended), ExCode = 4 36 u32 EventSize; // Code = 0 (extended), ExCode = 4
37 u32 PadEx4[15]; 37 u32 PadEx4[15];
38 // ExCode 5 = TCB Buffers base address 38 // ExCode 5 = TCB Buffers base address
39 u32 TcbBase; // Code = 0 (extended), ExCode = 5 39 u32 TcbBase; // Code = 0 (extended), ExCode = 5
40 u32 PadEx5[15]; 40 u32 PadEx5[15];
41 // ExCode 6 = TCB Composite Buffers base address 41 // ExCode 6 = TCB Composite Buffers base address
42 u32 TcbCompBase; // Code = 0 (extended), ExCode = 6 42 u32 TcbCompBase; // Code = 0 (extended), ExCode = 6
43 u32 PadEx6[15]; 43 u32 PadEx6[15];
44 // ExCode 7 = Transmit ring base address 44 // ExCode 7 = Transmit ring base address
45 u32 XmtBase; // Code = 0 (extended), ExCode = 7 45 u32 XmtBase; // Code = 0 (extended), ExCode = 7
46 u32 PadEx7[15]; 46 u32 PadEx7[15];
47 // ExCode 8 = Transmit ring size 47 // ExCode 8 = Transmit ring size
48 u32 XmtSize; // Code = 0 (extended), ExCode = 8 48 u32 XmtSize; // Code = 0 (extended), ExCode = 8
49 u32 PadEx8[15]; 49 u32 PadEx8[15];
50 // ExCode 9 = Receive ring base address 50 // ExCode 9 = Receive ring base address
51 u32 RcvBase; // Code = 0 (extended), ExCode = 9 51 u32 RcvBase; // Code = 0 (extended), ExCode = 9
52 u32 PadEx9[15]; 52 u32 PadEx9[15];
53 // ExCode 10 = Receive ring size 53 // ExCode 10 = Receive ring size
54 u32 RcvSize; // Code = 0 (extended), ExCode = 10 54 u32 RcvSize; // Code = 0 (extended), ExCode = 10
55 u32 PadEx10[15]; 55 u32 PadEx10[15];
56 // ExCode 11 = Read EEPROM Config 56 // ExCode 11 = Read EEPROM Config
57 u32 Config; // Code = 0 (extended), ExCode = 11 57 u32 Config; // Code = 0 (extended), ExCode = 11
58 u32 PadEx11[15]; 58 u32 PadEx11[15];
59 // ExCode 12 = Multicast bits 31:0 59 // ExCode 12 = Multicast bits 31:0
60 u32 McastLow; // Code = 0 (extended), ExCode = 12 60 u32 McastLow; // Code = 0 (extended), ExCode = 12
61 u32 PadEx12[15]; 61 u32 PadEx12[15];
62 // ExCode 13 = Multicast bits 63:32 62 // ExCode 13 = Multicast bits 63:32
63 u32 McastHigh; // Code = 0 (extended), ExCode = 13 63 u32 McastHigh; // Code = 0 (extended), ExCode = 13
64 u32 PadEx13[15]; 64 u32 PadEx13[15];
65 // ExCode 14 = Ping 65 // ExCode 14 = Ping
66 u32 Ping; // Code = 0 (extended), ExCode = 14 66 u32 Ping; // Code = 0 (extended), ExCode = 14
67 u32 PadEx14[15]; 67 u32 PadEx14[15];
68 // ExCode 15 = Link MTU 68 // ExCode 15 = Link MTU
69 u32 LinkMtu; // Code = 0 (extended), ExCode = 15 69 u32 LinkMtu; // Code = 0 (extended), ExCode = 15
70 u32 PadEx15[15]; 70 u32 PadEx15[15];
71 // ExCode 16 = Download synchronization 71 // ExCode 16 = Download synchronization
72 u32 LoadSync; // Code = 0 (extended), ExCode = 16 72 u32 LoadSync; // Code = 0 (extended), ExCode = 16
73 u32 PadEx16[15]; 73 u32 PadEx16[15];
74 // ExCode 17 = Upper DRAM address bits on 32-bit systems 74 // ExCode 17 = Upper DRAM address bits on 32-bit systems
75 u32 Upper; // Code = 0 (extended), ExCode = 17 75 u32 Upper; // Code = 0 (extended), ExCode = 17
76 u32 PadEx17[15]; 76 u32 PadEx17[15];
77 // ExCode 18 = Slowpath Send Index Address 77 // ExCode 18 = Slowpath Send Index Address
78 u32 SPSendIndex; // Code = 0 (extended), ExCode = 18 78 u32 SPSendIndex; // Code = 0 (extended), ExCode = 18
79 u32 PadEx18[15]; 79 u32 PadEx18[15];
80 u32 RsvdXF; // Code = 0 (extended), ExCode = 19 80 u32 RsvdXF; // Code = 0 (extended), ExCode = 19
81 u32 PadEx19[15]; 81 u32 PadEx19[15];
82 // ExCode 20 = Aggregation 82 // ExCode 20 = Aggregation
83 u32 Aggregation; // Code = 0 (extended), ExCode = 20 83 u32 Aggregation; // Code = 0 (extended), ExCode = 20
84 u32 PadEx20[15]; 84 u32 PadEx20[15];
85 // ExCode 21 = Receive MDL push timer 85 // ExCode 21 = Receive MDL push timer
86 u32 PushTicks; // Code = 0 (extended), ExCode = 21 86 u32 PushTicks; // Code = 0 (extended), ExCode = 21
87 u32 PadEx21[15]; 87 u32 PadEx21[15];
88 // ExCode 22 = TOE NA 88 // ExCode 22 = TOE NA
89 u32 AckFrequency; // Code = 0 (extended), ExCode = 22 89 u32 AckFrequency; // Code = 0 (extended), ExCode = 22
90 u32 PadEx22[15]; 90 u32 PadEx22[15];
91 // ExCode 23 = TOE NA 91 // ExCode 23 = TOE NA
92 u32 RsvdReg23; 92 u32 RsvdReg23;
93 u32 PadEx23[15]; 93 u32 PadEx23[15];
94 // ExCode 24 = TOE NA 94 // ExCode 24 = TOE NA
95 u32 RsvdReg24; 95 u32 RsvdReg24;
96 u32 PadEx24[15]; 96 u32 PadEx24[15];
97 // ExCode 25 = TOE NA 97 // ExCode 25 = TOE NA
98 u32 RsvdReg25; // Code = 0 (extended), ExCode = 25 98 u32 RsvdReg25; // Code = 0 (extended), ExCode = 25
99 u32 PadEx25[15]; 99 u32 PadEx25[15];
100 // ExCode 26 = Receive checksum requirements 100 // ExCode 26 = Receive checksum requirements
101 u32 ReceiveChecksum; // Code = 0 (extended), ExCode = 26 101 u32 ReceiveChecksum; // Code = 0 (extended), ExCode = 26
102 u32 PadEx26[15]; 102 u32 PadEx26[15];
103 // ExCode 27 = RSS Requirements 103 // ExCode 27 = RSS Requirements
104 u32 Rss; // Code = 0 (extended), ExCode = 27 104 u32 Rss; // Code = 0 (extended), ExCode = 27
105 u32 PadEx27[15]; 105 u32 PadEx27[15];
106 // ExCode 28 = RSS Table 106 // ExCode 28 = RSS Table
107 u32 RssTable; // Code = 0 (extended), ExCode = 28 107 u32 RssTable; // Code = 0 (extended), ExCode = 28
108 u32 PadEx28[15]; 108 u32 PadEx28[15];
109 // ExCode 29 = Event ring release entries 109 // ExCode 29 = Event ring release entries
110 u32 EventRelease; // Code = 0 (extended), ExCode = 29 110 u32 EventRelease; // Code = 0 (extended), ExCode = 29
111 u32 PadEx29[15]; 111 u32 PadEx29[15];
112 // ExCode 30 = Number of receive bufferlist commands on ring 0 112 // ExCode 30 = Number of receive bufferlist commands on ring 0
113 u32 RcvCmd; // Code = 0 (extended), ExCode = 30 113 u32 RcvCmd; // Code = 0 (extended), ExCode = 30
114 u32 PadEx30[15]; 114 u32 PadEx30[15];
115 // ExCode 31 = slowpath transmit command - Data[31:0] = 1 115 // ExCode 31 = slowpath transmit command - Data[31:0] = 1
116 u32 XmtCmd; // Code = 0 (extended), ExCode = 31 116 u32 XmtCmd; // Code = 0 (extended), ExCode = 31
117 u32 PadEx31[15]; 117 u32 PadEx31[15];
118 // ExCode 32 = Dump command 118 // ExCode 32 = Dump command
119 u32 DumpCmd; // Code = 0 (extended), ExCode = 32 119 u32 DumpCmd; // Code = 0 (extended), ExCode = 32
120 u32 PadEx32[15]; 120 u32 PadEx32[15];
121 // ExCode 33 = Debug command 121 // ExCode 33 = Debug command
122 u32 DebugCmd; // Code = 0 (extended), ExCode = 33 122 u32 DebugCmd; // Code = 0 (extended), ExCode = 33
123 u32 PadEx33[15]; 123 u32 PadEx33[15];
124 // There are 128 possible extended commands - each of account for 16 124 // There are 128 possible extended commands - each of account for 16
125 // words (including the non-relevent base command codes 1-15). 125 // words (including the non-relevent base command codes 1-15).
126 // Pad for the remainder of these here to bring us to the next CPU 126 // Pad for the remainder of these here to bring us to the next CPU
127 // base. As extended codes are added, reduce the first array value in 127 // base. As extended codes are added, reduce the first array value in
128 // the following field 128 // the following field
129 u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33) 129 u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33)
130} SXG_UCODE_REGS, *PSXG_UCODE_REGS; 130} SXG_UCODE_REGS, *PSXG_UCODE_REGS;
131 131
132// Interrupt control register (0) values 132// Interrupt control register (0) values
@@ -141,7 +141,7 @@ typedef struct _SXG_UCODE_REGS {
141 141
142// The Microcode supports up to 16 RSS queues 142// The Microcode supports up to 16 RSS queues
143#define SXG_MAX_RSS 16 143#define SXG_MAX_RSS 16
144#define SXG_MAX_RSS_TABLE_SIZE 256 // 256-byte max 144#define SXG_MAX_RSS_TABLE_SIZE 256 // 256-byte max
145 145
146#define SXG_RSS_TCP6 0x00000001 // RSS TCP over IPv6 146#define SXG_RSS_TCP6 0x00000001 // RSS TCP over IPv6
147#define SXG_RSS_TCP4 0x00000002 // RSS TCP over IPv4 147#define SXG_RSS_TCP4 0x00000002 // RSS TCP over IPv4
@@ -170,16 +170,16 @@ typedef struct _SXG_UCODE_REGS {
170 * SXG_UCODE_REGS definition above 170 * SXG_UCODE_REGS definition above
171 */ 171 */
172typedef struct _SXG_TCB_REGS { 172typedef struct _SXG_TCB_REGS {
173 u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */ 173 u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */
174 u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */ 174 u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */
175 u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */ 175 u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */
176 u32 Rsvd1; /* Code = 3 - TOE NA */ 176 u32 Rsvd1; /* Code = 3 - TOE NA */
177 u32 Rsvd2; /* Code = 4 - TOE NA */ 177 u32 Rsvd2; /* Code = 4 - TOE NA */
178 u32 Rsvd3; /* Code = 5 - TOE NA */ 178 u32 Rsvd3; /* Code = 5 - TOE NA */
179 u32 Invalid; /* Code = 6 - Reserved for "CardUp" see above */ 179 u32 Invalid; /* Code = 6 - Reserved for "CardUp" see above */
180 u32 Rsvd4; /* Code = 7 - TOE NA */ 180 u32 Rsvd4; /* Code = 7 - TOE NA */
181 u32 Rsvd5; /* Code = 8 - TOE NA */ 181 u32 Rsvd5; /* Code = 8 - TOE NA */
182 u32 Pad[7]; /* Codes 8-15 - Not used. */ 182 u32 Pad[7]; /* Codes 8-15 - Not used. */
183} SXG_TCB_REGS, *PSXG_TCB_REGS; 183} SXG_TCB_REGS, *PSXG_TCB_REGS;
184 184
185/*************************************************************************** 185/***************************************************************************
@@ -273,27 +273,27 @@ typedef struct _SXG_TCB_REGS {
273 */ 273 */
274#pragma pack(push, 1) 274#pragma pack(push, 1)
275typedef struct _SXG_EVENT { 275typedef struct _SXG_EVENT {
276 u32 Pad[1]; // not used 276 u32 Pad[1]; // not used
277 u32 SndUna; // SndUna value 277 u32 SndUna; // SndUna value
278 u32 Resid; // receive MDL resid 278 u32 Resid; // receive MDL resid
279 union { 279 union {
280 void * HostHandle; // Receive host handle 280 void *HostHandle; // Receive host handle
281 u32 Rsvd1; // TOE NA 281 u32 Rsvd1; // TOE NA
282 struct { 282 struct {
283 u32 NotUsed; 283 u32 NotUsed;
284 u32 Rsvd2; // TOE NA 284 u32 Rsvd2; // TOE NA
285 } Flush; 285 } Flush;
286 }; 286 };
287 u32 Toeplitz; // RSS Toeplitz hash 287 u32 Toeplitz; // RSS Toeplitz hash
288 union { 288 union {
289 ushort Rsvd3; // TOE NA 289 ushort Rsvd3; // TOE NA
290 ushort HdrOffset; // Slowpath 290 ushort HdrOffset; // Slowpath
291 }; 291 };
292 ushort Length; // 292 ushort Length; //
293 unsigned char Rsvd4; // TOE NA 293 unsigned char Rsvd4; // TOE NA
294 unsigned char Code; // Event code 294 unsigned char Code; // Event code
295 unsigned char CommandIndex; // New ring index 295 unsigned char CommandIndex; // New ring index
296 unsigned char Status; // Event status 296 unsigned char Status; // Event status
297} SXG_EVENT, *PSXG_EVENT; 297} SXG_EVENT, *PSXG_EVENT;
298#pragma pack(pop) 298#pragma pack(pop)
299 299
@@ -318,12 +318,12 @@ typedef struct _SXG_EVENT {
318// Event ring 318// Event ring
319// Size must be power of 2, between 128 and 16k 319// Size must be power of 2, between 128 and 16k
320#define EVENT_RING_SIZE 4096 // ?? 320#define EVENT_RING_SIZE 4096 // ??
321#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time. 321#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time.
322#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16) 322#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16)
323 323
324typedef struct _SXG_EVENT_RING { 324typedef struct _SXG_EVENT_RING {
325 SXG_EVENT Ring[EVENT_RING_SIZE]; 325 SXG_EVENT Ring[EVENT_RING_SIZE];
326}SXG_EVENT_RING, *PSXG_EVENT_RING; 326} SXG_EVENT_RING, *PSXG_EVENT_RING;
327 327
328/*************************************************************************** 328/***************************************************************************
329 * 329 *
@@ -341,7 +341,7 @@ typedef struct _SXG_EVENT_RING {
341#define SXG_TCB_PER_BUCKET 16 341#define SXG_TCB_PER_BUCKET 16
342#define SXG_TCB_BUCKET_MASK 0xFF0 // Bucket portion of TCB ID 342#define SXG_TCB_BUCKET_MASK 0xFF0 // Bucket portion of TCB ID
343#define SXG_TCB_ELEMENT_MASK 0x00F // Element within bucket 343#define SXG_TCB_ELEMENT_MASK 0x00F // Element within bucket
344#define SXG_TCB_BUCKETS 256 // 256 * 16 = 4k 344#define SXG_TCB_BUCKETS 256 // 256 * 16 = 4k
345 345
346#define SXG_TCB_BUFFER_SIZE 512 // ASSERT format is correct 346#define SXG_TCB_BUFFER_SIZE 512 // ASSERT format is correct
347 347
@@ -368,7 +368,6 @@ typedef struct _SXG_EVENT_RING {
368 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \ 368 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \
369 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip 369 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
370 370
371
372#if DBG 371#if DBG
373// Horrible kludge to distinguish dumb-nic, slowpath, and 372// Horrible kludge to distinguish dumb-nic, slowpath, and
374// fastpath traffic. Decrement the HopLimit by one 373// fastpath traffic. Decrement the HopLimit by one
@@ -396,16 +395,16 @@ typedef struct _SXG_EVENT_RING {
396 * Receive and transmit rings 395 * Receive and transmit rings
397 ***************************************************************************/ 396 ***************************************************************************/
398#define SXG_MAX_RING_SIZE 256 397#define SXG_MAX_RING_SIZE 256
399#define SXG_XMT_RING_SIZE 128 // Start with 128 398#define SXG_XMT_RING_SIZE 128 // Start with 128
400#define SXG_RCV_RING_SIZE 128 // Start with 128 399#define SXG_RCV_RING_SIZE 128 // Start with 128
401#define SXG_MAX_ENTRIES 4096 400#define SXG_MAX_ENTRIES 4096
402 401
403// Structure and macros to manage a ring 402// Structure and macros to manage a ring
404typedef struct _SXG_RING_INFO { 403typedef struct _SXG_RING_INFO {
405 unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE 404 unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE
406 unsigned char Tail; // Where we pull off completed entries 405 unsigned char Tail; // Where we pull off completed entries
407 ushort Size; // Ring size - Must be multiple of 2 406 ushort Size; // Ring size - Must be multiple of 2
408 void * Context[SXG_MAX_RING_SIZE]; // Shadow ring 407 void *Context[SXG_MAX_RING_SIZE]; // Shadow ring
409} SXG_RING_INFO, *PSXG_RING_INFO; 408} SXG_RING_INFO, *PSXG_RING_INFO;
410 409
411#define SXG_INITIALIZE_RING(_ring, _size) { \ 410#define SXG_INITIALIZE_RING(_ring, _size) { \
@@ -483,40 +482,40 @@ typedef struct _SXG_RING_INFO {
483 */ 482 */
484#pragma pack(push, 1) 483#pragma pack(push, 1)
485typedef struct _SXG_CMD { 484typedef struct _SXG_CMD {
486 dma_addr_t Sgl; // Physical address of SGL 485 dma_addr_t Sgl; // Physical address of SGL
487 union { 486 union {
488 struct { 487 struct {
489 dma64_addr_t FirstSgeAddress;// Address of first SGE 488 dma64_addr_t FirstSgeAddress; // Address of first SGE
490 u32 FirstSgeLength; // Length of first SGE 489 u32 FirstSgeLength; // Length of first SGE
491 union { 490 union {
492 u32 Rsvd1; // TOE NA 491 u32 Rsvd1; // TOE NA
493 u32 SgeOffset; // Slowpath - 2nd SGE offset 492 u32 SgeOffset; // Slowpath - 2nd SGE offset
494 u32 Resid; // MDL completion - clobbers update 493 u32 Resid; // MDL completion - clobbers update
495 }; 494 };
496 union { 495 union {
497 u32 TotalLength; // Total transfer length 496 u32 TotalLength; // Total transfer length
498 u32 Mss; // LSO MSS 497 u32 Mss; // LSO MSS
499 }; 498 };
500 } Buffer; 499 } Buffer;
501 }; 500 };
502 union { 501 union {
503 struct { 502 struct {
504 unsigned char Flags:4; // slowpath flags 503 unsigned char Flags:4; // slowpath flags
505 unsigned char IpHl:4; // Ip header length (>>2) 504 unsigned char IpHl:4; // Ip header length (>>2)
506 unsigned char MacLen; // Mac header len 505 unsigned char MacLen; // Mac header len
507 } CsumFlags; 506 } CsumFlags;
508 struct { 507 struct {
509 ushort Flags:4; // slowpath flags 508 ushort Flags:4; // slowpath flags
510 ushort TcpHdrOff:7; // TCP 509 ushort TcpHdrOff:7; // TCP
511 ushort MacLen:5; // Mac header len 510 ushort MacLen:5; // Mac header len
512 } LsoFlags; 511 } LsoFlags;
513 ushort Flags; // flags 512 ushort Flags; // flags
514 }; 513 };
515 union { 514 union {
516 ushort SgEntries; // SG entry count including first sge 515 ushort SgEntries; // SG entry count including first sge
517 struct { 516 struct {
518 unsigned char Status; // Copied from event status 517 unsigned char Status; // Copied from event status
519 unsigned char NotUsed; 518 unsigned char NotUsed;
520 } Status; 519 } Status;
521 }; 520 };
522} SXG_CMD, *PSXG_CMD; 521} SXG_CMD, *PSXG_CMD;
@@ -524,8 +523,8 @@ typedef struct _SXG_CMD {
524 523
525#pragma pack(push, 1) 524#pragma pack(push, 1)
526typedef struct _VLAN_HDR { 525typedef struct _VLAN_HDR {
527 ushort VlanTci; 526 ushort VlanTci;
528 ushort VlanTpid; 527 ushort VlanTpid;
529} VLAN_HDR, *PVLAN_HDR; 528} VLAN_HDR, *PVLAN_HDR;
530#pragma pack(pop) 529#pragma pack(pop)
531 530
@@ -561,16 +560,16 @@ typedef struct _VLAN_HDR {
561 * 560 *
562 */ 561 */
563// Slowpath CMD flags 562// Slowpath CMD flags
564#define SXG_SLOWCMD_CSUM_IP 0x01 // Checksum IP 563#define SXG_SLOWCMD_CSUM_IP 0x01 // Checksum IP
565#define SXG_SLOWCMD_CSUM_TCP 0x02 // Checksum TCP 564#define SXG_SLOWCMD_CSUM_TCP 0x02 // Checksum TCP
566#define SXG_SLOWCMD_LSO 0x04 // Large segment send 565#define SXG_SLOWCMD_LSO 0x04 // Large segment send
567 566
568typedef struct _SXG_XMT_RING { 567typedef struct _SXG_XMT_RING {
569 SXG_CMD Descriptors[SXG_XMT_RING_SIZE]; 568 SXG_CMD Descriptors[SXG_XMT_RING_SIZE];
570} SXG_XMT_RING, *PSXG_XMT_RING; 569} SXG_XMT_RING, *PSXG_XMT_RING;
571 570
572typedef struct _SXG_RCV_RING { 571typedef struct _SXG_RCV_RING {
573 SXG_CMD Descriptors[SXG_RCV_RING_SIZE]; 572 SXG_CMD Descriptors[SXG_RCV_RING_SIZE];
574} SXG_RCV_RING, *PSXG_RCV_RING; 573} SXG_RCV_RING, *PSXG_RCV_RING;
575 574
576/*************************************************************************** 575/***************************************************************************
@@ -578,8 +577,8 @@ typedef struct _SXG_RCV_RING {
578 * shared memory allocation 577 * shared memory allocation
579 ***************************************************************************/ 578 ***************************************************************************/
580typedef enum { 579typedef enum {
581 SXG_BUFFER_TYPE_RCV, // Receive buffer 580 SXG_BUFFER_TYPE_RCV, // Receive buffer
582 SXG_BUFFER_TYPE_SGL // SGL buffer 581 SXG_BUFFER_TYPE_SGL // SGL buffer
583} SXG_BUFFER_TYPE; 582} SXG_BUFFER_TYPE;
584 583
585// State for SXG buffers 584// State for SXG buffers
@@ -668,60 +667,60 @@ typedef enum {
668#define SXG_RCV_DATA_BUFFERS 4096 // Amount to give to the card 667#define SXG_RCV_DATA_BUFFERS 4096 // Amount to give to the card
669#define SXG_INITIAL_RCV_DATA_BUFFERS 8192 // Initial pool of buffers 668#define SXG_INITIAL_RCV_DATA_BUFFERS 8192 // Initial pool of buffers
670#define SXG_MIN_RCV_DATA_BUFFERS 2048 // Minimum amount and when to get more 669#define SXG_MIN_RCV_DATA_BUFFERS 2048 // Minimum amount and when to get more
671#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers 670#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers
672 671
673// Receive buffer header 672// Receive buffer header
674typedef struct _SXG_RCV_DATA_BUFFER_HDR { 673typedef struct _SXG_RCV_DATA_BUFFER_HDR {
675 dma_addr_t PhysicalAddress; // Buffer physical address 674 dma_addr_t PhysicalAddress; // Buffer physical address
676 // Note - DO NOT USE the VirtualAddress field to locate data. 675 // Note - DO NOT USE the VirtualAddress field to locate data.
677 // Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead. 676 // Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
678 void *VirtualAddress; // Start of buffer 677 void *VirtualAddress; // Start of buffer
679 LIST_ENTRY FreeList; // Free queue of buffers 678 LIST_ENTRY FreeList; // Free queue of buffers
680 struct _SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue 679 struct _SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue
681 u32 Size; // Buffer size 680 u32 Size; // Buffer size
682 u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET 681 u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET
683 unsigned char State; // See SXG_BUFFER state above 682 unsigned char State; // See SXG_BUFFER state above
684 unsigned char Status; // Event status (to log PUSH) 683 unsigned char Status; // Event status (to log PUSH)
685 struct sk_buff * skb; // Double mapped (nbl and pkt) 684 struct sk_buff *skb; // Double mapped (nbl and pkt)
686} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR; 685} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR;
687 686
688// SxgSlowReceive uses the PACKET (skb) contained 687// SxgSlowReceive uses the PACKET (skb) contained
689// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data 688// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data
690#define SxgDumbRcvPacket skb 689#define SxgDumbRcvPacket skb
691 690
692#define SXG_RCV_DATA_HDR_SIZE 256 // Space for SXG_RCV_DATA_BUFFER_HDR 691#define SXG_RCV_DATA_HDR_SIZE 256 // Space for SXG_RCV_DATA_BUFFER_HDR
693#define SXG_RCV_DATA_BUFFER_SIZE 2048 // Non jumbo = 2k including HDR 692#define SXG_RCV_DATA_BUFFER_SIZE 2048 // Non jumbo = 2k including HDR
694#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR 693#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR
695 694
696// Receive data descriptor 695// Receive data descriptor
697typedef struct _SXG_RCV_DATA_DESCRIPTOR { 696typedef struct _SXG_RCV_DATA_DESCRIPTOR {
698 union { 697 union {
699 struct sk_buff * VirtualAddress; // Host handle 698 struct sk_buff *VirtualAddress; // Host handle
700 u64 ForceTo8Bytes; // Force x86 to 8-byte boundary 699 u64 ForceTo8Bytes; // Force x86 to 8-byte boundary
701 }; 700 };
702 dma_addr_t PhysicalAddress; 701 dma_addr_t PhysicalAddress;
703} SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR; 702} SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR;
704 703
705// Receive descriptor block 704// Receive descriptor block
706#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128 705#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128
707#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check 706#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check
708typedef struct _SXG_RCV_DESCRIPTOR_BLOCK { 707typedef struct _SXG_RCV_DESCRIPTOR_BLOCK {
709 SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK]; 708 SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
710} SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK; 709} SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK;
711 710
712// Receive descriptor block header 711// Receive descriptor block header
713typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR { 712typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
714 void * VirtualAddress; // Start of 2k buffer 713 void *VirtualAddress; // Start of 2k buffer
715 dma_addr_t PhysicalAddress; // ..and it's physical address 714 dma_addr_t PhysicalAddress; // ..and it's physical address
716 LIST_ENTRY FreeList; // Free queue of descriptor blocks 715 LIST_ENTRY FreeList; // Free queue of descriptor blocks
717 unsigned char State; // See SXG_BUFFER state above 716 unsigned char State; // See SXG_BUFFER state above
718} SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR; 717} SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR;
719 718
720// Receive block header 719// Receive block header
721typedef struct _SXG_RCV_BLOCK_HDR { 720typedef struct _SXG_RCV_BLOCK_HDR {
722 void * VirtualAddress; // Start of virtual memory 721 void *VirtualAddress; // Start of virtual memory
723 dma_addr_t PhysicalAddress; // ..and it's physical address 722 dma_addr_t PhysicalAddress; // ..and it's physical address
724 LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS 723 LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
725} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR; 724} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR;
726 725
727// Macros to determine data structure offsets into receive block 726// Macros to determine data structure offsets into receive block
@@ -747,8 +746,8 @@ typedef struct _SXG_RCV_BLOCK_HDR {
747// Use the miniport reserved portion of the NBL to locate 746// Use the miniport reserved portion of the NBL to locate
748// our SXG_RCV_DATA_BUFFER_HDR structure. 747// our SXG_RCV_DATA_BUFFER_HDR structure.
749typedef struct _SXG_RCV_NBL_RESERVED { 748typedef struct _SXG_RCV_NBL_RESERVED {
750 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr; 749 PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
751 void * Available; 750 void *Available;
752} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED; 751} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED;
753 752
754#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr) 753#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
@@ -760,12 +759,11 @@ typedef struct _SXG_RCV_NBL_RESERVED {
760#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more 759#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more
761#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort) 760#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort)
762 761
763
764// Self identifying structure type 762// Self identifying structure type
765typedef enum _SXG_SGL_TYPE { 763typedef enum _SXG_SGL_TYPE {
766 SXG_SGL_DUMB, // Dumb NIC SGL 764 SXG_SGL_DUMB, // Dumb NIC SGL
767 SXG_SGL_SLOW, // Slowpath protocol header - see below 765 SXG_SGL_SLOW, // Slowpath protocol header - see below
768 SXG_SGL_CHIMNEY // Chimney offload SGL 766 SXG_SGL_CHIMNEY // Chimney offload SGL
769} SXG_SGL_TYPE, PSXG_SGL_TYPE; 767} SXG_SGL_TYPE, PSXG_SGL_TYPE;
770 768
771// Note - the description below is Microsoft specific 769// Note - the description below is Microsoft specific
@@ -774,14 +772,14 @@ typedef enum _SXG_SGL_TYPE {
774// for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure. 772// for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure.
775// The following considerations apply when setting this value: 773// The following considerations apply when setting this value:
776// - First, the Sahara card is designed to read the Microsoft SGL structure 774// - First, the Sahara card is designed to read the Microsoft SGL structure
777// straight out of host memory. This means that the SGL must reside in 775// straight out of host memory. This means that the SGL must reside in
778// shared memory. If the length here is smaller than the SGL for the 776// shared memory. If the length here is smaller than the SGL for the
779// NET_BUFFER, then NDIS will allocate its own buffer. The buffer 777// NET_BUFFER, then NDIS will allocate its own buffer. The buffer
780// that NDIS allocates is not in shared memory, so when this happens, 778// that NDIS allocates is not in shared memory, so when this happens,
781// the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers. 779// the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers.
782// In other words.. we don't want this value to be too small. 780// In other words.. we don't want this value to be too small.
783// - On the other hand.. we're allocating up to 16k of these things. If 781// - On the other hand.. we're allocating up to 16k of these things. If
784// we make this too big, we start to consume a ton of memory.. 782// we make this too big, we start to consume a ton of memory..
785// At the moment, I'm going to limit the number of SG entries to 150. 783// At the moment, I'm going to limit the number of SG entries to 150.
786// If each entry maps roughly 4k, then this should cover roughly 600kB 784// If each entry maps roughly 4k, then this should cover roughly 600kB
787// NET_BUFFERs. Furthermore, since each entry is 24 bytes, the total 785// NET_BUFFERs. Furthermore, since each entry is 24 bytes, the total
@@ -801,24 +799,23 @@ typedef enum _SXG_SGL_TYPE {
801// the SGL. The following structure defines an x64 799// the SGL. The following structure defines an x64
802// formatted SGL entry 800// formatted SGL entry
803typedef struct _SXG_X64_SGE { 801typedef struct _SXG_X64_SGE {
804 dma64_addr_t Address; // same as wdm.h 802 dma64_addr_t Address; // same as wdm.h
805 u32 Length; // same as wdm.h 803 u32 Length; // same as wdm.h
806 u32 CompilerPad;// The compiler pads to 8-bytes 804 u32 CompilerPad; // The compiler pads to 8-bytes
807 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes 805 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
808} SXG_X64_SGE, *PSXG_X64_SGE; 806} SXG_X64_SGE, *PSXG_X64_SGE;
809 807
810typedef struct _SCATTER_GATHER_ELEMENT { 808typedef struct _SCATTER_GATHER_ELEMENT {
811 dma64_addr_t Address; // same as wdm.h 809 dma64_addr_t Address; // same as wdm.h
812 u32 Length; // same as wdm.h 810 u32 Length; // same as wdm.h
813 u32 CompilerPad;// The compiler pads to 8-bytes 811 u32 CompilerPad; // The compiler pads to 8-bytes
814 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes 812 u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
815} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT; 813} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT;
816 814
817
818typedef struct _SCATTER_GATHER_LIST { 815typedef struct _SCATTER_GATHER_LIST {
819 u32 NumberOfElements; 816 u32 NumberOfElements;
820 u32 * Reserved; 817 u32 *Reserved;
821 SCATTER_GATHER_ELEMENT Elements[]; 818 SCATTER_GATHER_ELEMENT Elements[];
822} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST; 819} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST;
823 820
824// The card doesn't care about anything except elements, so 821// The card doesn't care about anything except elements, so
@@ -826,26 +823,26 @@ typedef struct _SCATTER_GATHER_LIST {
826// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so 823// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so
827// we can specify SXG_X64_SGE and define a fixed number of elements 824// we can specify SXG_X64_SGE and define a fixed number of elements
828typedef struct _SXG_X64_SGL { 825typedef struct _SXG_X64_SGL {
829 u32 NumberOfElements; 826 u32 NumberOfElements;
830 u32 * Reserved; 827 u32 *Reserved;
831 SXG_X64_SGE Elements[SXG_SGL_ENTRIES]; 828 SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
832} SXG_X64_SGL, *PSXG_X64_SGL; 829} SXG_X64_SGL, *PSXG_X64_SGL;
833 830
834typedef struct _SXG_SCATTER_GATHER { 831typedef struct _SXG_SCATTER_GATHER {
835 SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload 832 SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
836 void * adapter; // Back pointer to adapter 833 void *adapter; // Back pointer to adapter
837 LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks 834 LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
838 LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks 835 LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
839 dma_addr_t PhysicalAddress;// physical address 836 dma_addr_t PhysicalAddress; // physical address
840 unsigned char State; // See SXG_BUFFER state above 837 unsigned char State; // See SXG_BUFFER state above
841 unsigned char CmdIndex; // Command ring index 838 unsigned char CmdIndex; // Command ring index
842 struct sk_buff * DumbPacket; // Associated Packet 839 struct sk_buff *DumbPacket; // Associated Packet
843 u32 Direction; // For asynchronous completions 840 u32 Direction; // For asynchronous completions
844 u32 CurOffset; // Current SGL offset 841 u32 CurOffset; // Current SGL offset
845 u32 SglRef; // SGL reference count 842 u32 SglRef; // SGL reference count
846 VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL 843 VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL
847 PSCATTER_GATHER_LIST pSgl; // SGL Addr. Possibly &Sgl 844 PSCATTER_GATHER_LIST pSgl; // SGL Addr. Possibly &Sgl
848 SXG_X64_SGL Sgl; // SGL handed to card 845 SXG_X64_SGL Sgl; // SGL handed to card
849} SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER; 846} SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER;
850 847
851#if defined(CONFIG_X86_64) 848#if defined(CONFIG_X86_64)
@@ -856,6 +853,5 @@ typedef struct _SXG_SCATTER_GATHER {
856#define SXG_SGL_BUFFER(_SxgSgl) NULL 853#define SXG_SGL_BUFFER(_SxgSgl) NULL
857#define SXG_SGL_BUF_SIZE 0 854#define SXG_SGL_BUF_SIZE 0
858#else 855#else
859 Stop Compilation; 856Stop Compilation;
860#endif 857#endif
861
diff --git a/drivers/staging/sxg/sxghw.h b/drivers/staging/sxg/sxghw.h
index 8f4f6effdd9..870eef3f9d5 100644
--- a/drivers/staging/sxg/sxghw.h
+++ b/drivers/staging/sxg/sxghw.h
@@ -141,7 +141,7 @@ typedef struct _SXG_HW_REGS {
141#define SXG_REGISTER_SIZE_PER_CPU 0x00002000 // Used to sanity check UCODE_REGS structure 141#define SXG_REGISTER_SIZE_PER_CPU 0x00002000 // Used to sanity check UCODE_REGS structure
142 142
143// Sahara receive sequencer status values 143// Sahara receive sequencer status values
144#define SXG_RCV_STATUS_ATTN 0x80000000 // Attention 144#define SXG_RCV_STATUS_ATTN 0x80000000 // Attention
145#define SXG_RCV_STATUS_TRANSPORT_MASK 0x3F000000 // Transport mask 145#define SXG_RCV_STATUS_TRANSPORT_MASK 0x3F000000 // Transport mask
146#define SXG_RCV_STATUS_TRANSPORT_ERROR 0x20000000 // Transport error 146#define SXG_RCV_STATUS_TRANSPORT_ERROR 0x20000000 // Transport error
147#define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000 // Transport cksum error 147#define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000 // Transport cksum error
@@ -156,9 +156,9 @@ typedef struct _SXG_HW_REGS {
156#define SXG_RCV_STATUS_TRANSPORT_FTP 0x03000000 // Transport FTP 156#define SXG_RCV_STATUS_TRANSPORT_FTP 0x03000000 // Transport FTP
157#define SXG_RCV_STATUS_TRANSPORT_HTTP 0x02000000 // Transport HTTP 157#define SXG_RCV_STATUS_TRANSPORT_HTTP 0x02000000 // Transport HTTP
158#define SXG_RCV_STATUS_TRANSPORT_SMB 0x01000000 // Transport SMB 158#define SXG_RCV_STATUS_TRANSPORT_SMB 0x01000000 // Transport SMB
159#define SXG_RCV_STATUS_NETWORK_MASK 0x00FF0000 // Network mask 159#define SXG_RCV_STATUS_NETWORK_MASK 0x00FF0000 // Network mask
160#define SXG_RCV_STATUS_NETWORK_ERROR 0x00800000 // Network error 160#define SXG_RCV_STATUS_NETWORK_ERROR 0x00800000 // Network error
161#define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000 // Network cksum error 161#define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000 // Network cksum error
162#define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000 // Network underflow error 162#define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000 // Network underflow error
163#define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000 // Network header length 163#define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000 // Network header length
164#define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000 // Network overflow detected 164#define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000 // Network overflow detected
@@ -167,67 +167,67 @@ typedef struct _SXG_HW_REGS {
167#define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000 // Network offset detected 167#define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000 // Network offset detected
168#define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000 // Network fragment detected 168#define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000 // Network fragment detected
169#define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000 // Network transport type mask 169#define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000 // Network transport type mask
170#define SXG_RCV_STATUS_NETWORK_UDP 0x00020000 // UDP 170#define SXG_RCV_STATUS_NETWORK_UDP 0x00020000 // UDP
171#define SXG_RCV_STATUS_NETWORK_TCP 0x00010000 // TCP 171#define SXG_RCV_STATUS_NETWORK_TCP 0x00010000 // TCP
172#define SXG_RCV_STATUS_IPONLY 0x00008000 // IP-only not TCP 172#define SXG_RCV_STATUS_IPONLY 0x00008000 // IP-only not TCP
173#define SXG_RCV_STATUS_PKT_PRI 0x00006000 // Receive priority 173#define SXG_RCV_STATUS_PKT_PRI 0x00006000 // Receive priority
174#define SXG_RCV_STATUS_PKT_PRI_SHFT 13 // Receive priority shift 174#define SXG_RCV_STATUS_PKT_PRI_SHFT 13 // Receive priority shift
175#define SXG_RCV_STATUS_PARITY 0x00001000 // MAC Receive RAM parity error 175#define SXG_RCV_STATUS_PARITY 0x00001000 // MAC Receive RAM parity error
176#define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00 // Link address detection mask 176#define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00 // Link address detection mask
177#define SXG_RCV_STATUS_ADDRESS_D 0x00000B00 // Link address D 177#define SXG_RCV_STATUS_ADDRESS_D 0x00000B00 // Link address D
178#define SXG_RCV_STATUS_ADDRESS_C 0x00000A00 // Link address C 178#define SXG_RCV_STATUS_ADDRESS_C 0x00000A00 // Link address C
179#define SXG_RCV_STATUS_ADDRESS_B 0x00000900 // Link address B 179#define SXG_RCV_STATUS_ADDRESS_B 0x00000900 // Link address B
180#define SXG_RCV_STATUS_ADDRESS_A 0x00000800 // Link address A 180#define SXG_RCV_STATUS_ADDRESS_A 0x00000800 // Link address A
181#define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300 // Link address broadcast 181#define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300 // Link address broadcast
182#define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200 // Link address multicast 182#define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200 // Link address multicast
183#define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100 // Link control multicast 183#define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100 // Link control multicast
184#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask 184#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
185#define SXG_RCV_STATUS_LINK_ERROR 0x00000080 // Link error 185#define SXG_RCV_STATUS_LINK_ERROR 0x00000080 // Link error
186#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask 186#define SXG_RCV_STATUS_LINK_MASK 0x000000FF // Link status mask
187#define SXG_RCV_STATUS_LINK_PARITY 0x00000087 // RcvMacQ parity error 187#define SXG_RCV_STATUS_LINK_PARITY 0x00000087 // RcvMacQ parity error
188#define SXG_RCV_STATUS_LINK_EARLY 0x00000086 // Data early 188#define SXG_RCV_STATUS_LINK_EARLY 0x00000086 // Data early
189#define SXG_RCV_STATUS_LINK_BUFOFLOW 0x00000085 // Buffer overflow 189#define SXG_RCV_STATUS_LINK_BUFOFLOW 0x00000085 // Buffer overflow
190#define SXG_RCV_STATUS_LINK_CODE 0x00000084 // Link code error 190#define SXG_RCV_STATUS_LINK_CODE 0x00000084 // Link code error
191#define SXG_RCV_STATUS_LINK_DRIBBLE 0x00000083 // Dribble nibble 191#define SXG_RCV_STATUS_LINK_DRIBBLE 0x00000083 // Dribble nibble
192#define SXG_RCV_STATUS_LINK_CRC 0x00000082 // CRC error 192#define SXG_RCV_STATUS_LINK_CRC 0x00000082 // CRC error
193#define SXG_RCV_STATUS_LINK_OFLOW 0x00000081 // Link overflow 193#define SXG_RCV_STATUS_LINK_OFLOW 0x00000081 // Link overflow
194#define SXG_RCV_STATUS_LINK_UFLOW 0x00000080 // Link underflow 194#define SXG_RCV_STATUS_LINK_UFLOW 0x00000080 // Link underflow
195#define SXG_RCV_STATUS_LINK_8023 0x00000020 // 802.3 195#define SXG_RCV_STATUS_LINK_8023 0x00000020 // 802.3
196#define SXG_RCV_STATUS_LINK_SNAP 0x00000010 // Snap 196#define SXG_RCV_STATUS_LINK_SNAP 0x00000010 // Snap
197#define SXG_RCV_STATUS_LINK_VLAN 0x00000008 // VLAN 197#define SXG_RCV_STATUS_LINK_VLAN 0x00000008 // VLAN
198#define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007 // Network type mask 198#define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007 // Network type mask
199#define SXG_RCV_STATUS_LINK_CONTROL 0x00000003 // Control packet 199#define SXG_RCV_STATUS_LINK_CONTROL 0x00000003 // Control packet
200#define SXG_RCV_STATUS_LINK_IPV6 0x00000002 // IPv6 packet 200#define SXG_RCV_STATUS_LINK_IPV6 0x00000002 // IPv6 packet
201#define SXG_RCV_STATUS_LINK_IPV4 0x00000001 // IPv4 packet 201#define SXG_RCV_STATUS_LINK_IPV4 0x00000001 // IPv4 packet
202 202
203/*************************************************************************** 203/***************************************************************************
204 * Sahara receive and transmit configuration registers 204 * Sahara receive and transmit configuration registers
205 ***************************************************************************/ 205 ***************************************************************************/
206#define RCV_CONFIG_RESET 0x80000000 // RcvConfig register reset 206#define RCV_CONFIG_RESET 0x80000000 // RcvConfig register reset
207#define RCV_CONFIG_ENABLE 0x40000000 // Enable the receive logic 207#define RCV_CONFIG_ENABLE 0x40000000 // Enable the receive logic
208#define RCV_CONFIG_ENPARSE 0x20000000 // Enable the receive parser 208#define RCV_CONFIG_ENPARSE 0x20000000 // Enable the receive parser
209#define RCV_CONFIG_SOCKET 0x10000000 // Enable the socket detector 209#define RCV_CONFIG_SOCKET 0x10000000 // Enable the socket detector
210#define RCV_CONFIG_RCVBAD 0x08000000 // Receive all bad frames 210#define RCV_CONFIG_RCVBAD 0x08000000 // Receive all bad frames
211#define RCV_CONFIG_CONTROL 0x04000000 // Receive all control frames 211#define RCV_CONFIG_CONTROL 0x04000000 // Receive all control frames
212#define RCV_CONFIG_RCVPAUSE 0x02000000 // Enable pause transmit when attn 212#define RCV_CONFIG_RCVPAUSE 0x02000000 // Enable pause transmit when attn
213#define RCV_CONFIG_TZIPV6 0x01000000 // Include TCP port w/ IPv6 toeplitz 213#define RCV_CONFIG_TZIPV6 0x01000000 // Include TCP port w/ IPv6 toeplitz
214#define RCV_CONFIG_TZIPV4 0x00800000 // Include TCP port w/ IPv4 toeplitz 214#define RCV_CONFIG_TZIPV4 0x00800000 // Include TCP port w/ IPv4 toeplitz
215#define RCV_CONFIG_FLUSH 0x00400000 // Flush buffers 215#define RCV_CONFIG_FLUSH 0x00400000 // Flush buffers
216#define RCV_CONFIG_PRIORITY_MASK 0x00300000 // Priority level 216#define RCV_CONFIG_PRIORITY_MASK 0x00300000 // Priority level
217#define RCV_CONFIG_HASH_MASK 0x00030000 // Hash depth 217#define RCV_CONFIG_HASH_MASK 0x00030000 // Hash depth
218#define RCV_CONFIG_HASH_8 0x00000000 // Hash depth 8 218#define RCV_CONFIG_HASH_8 0x00000000 // Hash depth 8
219#define RCV_CONFIG_HASH_16 0x00010000 // Hash depth 16 219#define RCV_CONFIG_HASH_16 0x00010000 // Hash depth 16
220#define RCV_CONFIG_HASH_4 0x00020000 // Hash depth 4 220#define RCV_CONFIG_HASH_4 0x00020000 // Hash depth 4
221#define RCV_CONFIG_HASH_2 0x00030000 // Hash depth 2 221#define RCV_CONFIG_HASH_2 0x00030000 // Hash depth 2
222#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 // Buffer length bits 15:4. ie multiple of 16. 222#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 // Buffer length bits 15:4. ie multiple of 16.
223#define RCV_CONFIG_SKT_DIS 0x00000008 // Disable socket detection on attn 223#define RCV_CONFIG_SKT_DIS 0x00000008 // Disable socket detection on attn
224// Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size. 224// Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
225// We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC, 225// We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
226// and round up to nearest 16 byte boundary 226// and round up to nearest 16 byte boundary
227#define RCV_CONFIG_BUFSIZE(_MaxFrame) ((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK) 227#define RCV_CONFIG_BUFSIZE(_MaxFrame) ((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK)
228 228
229#define XMT_CONFIG_RESET 0x80000000 // XmtConfig register reset 229#define XMT_CONFIG_RESET 0x80000000 // XmtConfig register reset
230#define XMT_CONFIG_ENABLE 0x40000000 // Enable transmit logic 230#define XMT_CONFIG_ENABLE 0x40000000 // Enable transmit logic
231#define XMT_CONFIG_MAC_PARITY 0x20000000 // Inhibit MAC RAM parity error 231#define XMT_CONFIG_MAC_PARITY 0x20000000 // Inhibit MAC RAM parity error
232#define XMT_CONFIG_BUF_PARITY 0x10000000 // Inhibit D2F buffer parity error 232#define XMT_CONFIG_BUF_PARITY 0x10000000 // Inhibit D2F buffer parity error
233#define XMT_CONFIG_MEM_PARITY 0x08000000 // Inhibit 1T SRAM parity error 233#define XMT_CONFIG_MEM_PARITY 0x08000000 // Inhibit 1T SRAM parity error
@@ -249,9 +249,9 @@ typedef struct _SXG_HW_REGS {
249 249
250// A-XGMAC Configuration Register 1 250// A-XGMAC Configuration Register 1
251#define AXGMAC_CFG1_XMT_PAUSE 0x80000000 // Allow the sending of Pause frames 251#define AXGMAC_CFG1_XMT_PAUSE 0x80000000 // Allow the sending of Pause frames
252#define AXGMAC_CFG1_XMT_EN 0x40000000 // Enable transmit 252#define AXGMAC_CFG1_XMT_EN 0x40000000 // Enable transmit
253#define AXGMAC_CFG1_RCV_PAUSE 0x20000000 // Allow the detection of Pause frames 253#define AXGMAC_CFG1_RCV_PAUSE 0x20000000 // Allow the detection of Pause frames
254#define AXGMAC_CFG1_RCV_EN 0x10000000 // Enable receive 254#define AXGMAC_CFG1_RCV_EN 0x10000000 // Enable receive
255#define AXGMAC_CFG1_XMT_STATE 0x04000000 // Current transmit state - READ ONLY 255#define AXGMAC_CFG1_XMT_STATE 0x04000000 // Current transmit state - READ ONLY
256#define AXGMAC_CFG1_RCV_STATE 0x01000000 // Current receive state - READ ONLY 256#define AXGMAC_CFG1_RCV_STATE 0x01000000 // Current receive state - READ ONLY
257#define AXGMAC_CFG1_XOFF_SHORT 0x00001000 // Only pause for 64 slot on XOFF 257#define AXGMAC_CFG1_XOFF_SHORT 0x00001000 // Only pause for 64 slot on XOFF
@@ -262,24 +262,24 @@ typedef struct _SXG_HW_REGS {
262#define AXGMAC_CFG1_RCV_FCS2 0x00000200 // Delay receive FCS 2 4-byte words 262#define AXGMAC_CFG1_RCV_FCS2 0x00000200 // Delay receive FCS 2 4-byte words
263#define AXGMAC_CFG1_RCV_FCS3 0x00000300 // Delay receive FCS 3 4-byte words 263#define AXGMAC_CFG1_RCV_FCS3 0x00000300 // Delay receive FCS 3 4-byte words
264#define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080 // Per-packet override enable 264#define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080 // Per-packet override enable
265#define AXGMAC_CFG1_SWAP 0x00000040 // Byte swap enable 265#define AXGMAC_CFG1_SWAP 0x00000040 // Byte swap enable
266#define AXGMAC_CFG1_SHORT_ASSERT 0x00000020 // ASSERT srdrpfrm on short frame (<64) 266#define AXGMAC_CFG1_SHORT_ASSERT 0x00000020 // ASSERT srdrpfrm on short frame (<64)
267#define AXGMAC_CFG1_RCV_STRICT 0x00000010 // RCV only 802.3AE when CLEAR 267#define AXGMAC_CFG1_RCV_STRICT 0x00000010 // RCV only 802.3AE when CLEAR
268#define AXGMAC_CFG1_CHECK_LEN 0x00000008 // Verify frame length 268#define AXGMAC_CFG1_CHECK_LEN 0x00000008 // Verify frame length
269#define AXGMAC_CFG1_GEN_FCS 0x00000004 // Generate FCS 269#define AXGMAC_CFG1_GEN_FCS 0x00000004 // Generate FCS
270#define AXGMAC_CFG1_PAD_MASK 0x00000003 // Mask for pad bits 270#define AXGMAC_CFG1_PAD_MASK 0x00000003 // Mask for pad bits
271#define AXGMAC_CFG1_PAD_64 0x00000001 // Pad frames to 64 bytes 271#define AXGMAC_CFG1_PAD_64 0x00000001 // Pad frames to 64 bytes
272#define AXGMAC_CFG1_PAD_VLAN 0x00000002 // Detect VLAN and pad to 68 bytes 272#define AXGMAC_CFG1_PAD_VLAN 0x00000002 // Detect VLAN and pad to 68 bytes
273#define AXGMAC_CFG1_PAD_68 0x00000003 // Pad to 68 bytes 273#define AXGMAC_CFG1_PAD_68 0x00000003 // Pad to 68 bytes
274 274
275// A-XGMAC Configuration Register 2 275// A-XGMAC Configuration Register 2
276#define AXGMAC_CFG2_GEN_PAUSE 0x80000000 // Generate single pause frame (test) 276#define AXGMAC_CFG2_GEN_PAUSE 0x80000000 // Generate single pause frame (test)
277#define AXGMAC_CFG2_LF_MANUAL 0x08000000 // Manual link fault sequence 277#define AXGMAC_CFG2_LF_MANUAL 0x08000000 // Manual link fault sequence
278#define AXGMAC_CFG2_LF_AUTO 0x04000000 // Auto link fault sequence 278#define AXGMAC_CFG2_LF_AUTO 0x04000000 // Auto link fault sequence
279#define AXGMAC_CFG2_LF_REMOTE 0x02000000 // Remote link fault (READ ONLY) 279#define AXGMAC_CFG2_LF_REMOTE 0x02000000 // Remote link fault (READ ONLY)
280#define AXGMAC_CFG2_LF_LOCAL 0x01000000 // Local link fault (READ ONLY) 280#define AXGMAC_CFG2_LF_LOCAL 0x01000000 // Local link fault (READ ONLY)
281#define AXGMAC_CFG2_IPG_MASK 0x001F0000 // Inter packet gap 281#define AXGMAC_CFG2_IPG_MASK 0x001F0000 // Inter packet gap
282#define AXGMAC_CFG2_IPG_SHIFT 16 282#define AXGMAC_CFG2_IPG_SHIFT 16
283#define AXGMAC_CFG2_PAUSE_XMT 0x00008000 // Pause transmit module 283#define AXGMAC_CFG2_PAUSE_XMT 0x00008000 // Pause transmit module
284#define AXGMAC_CFG2_IPG_EXTEN 0x00000020 // Enable IPG extension algorithm 284#define AXGMAC_CFG2_IPG_EXTEN 0x00000020 // Enable IPG extension algorithm
285#define AXGMAC_CFG2_IPGEX_MASK 0x0000001F // IPG extension 285#define AXGMAC_CFG2_IPGEX_MASK 0x0000001F // IPG extension
@@ -299,9 +299,9 @@ typedef struct _SXG_HW_REGS {
299#define AXGMAC_SARHIGH_OCTET_SIX 0x00FF0000 // Sixth octet 299#define AXGMAC_SARHIGH_OCTET_SIX 0x00FF0000 // Sixth octet
300 300
301// A-XGMAC Maximum frame length register 301// A-XGMAC Maximum frame length register
302#define AXGMAC_MAXFRAME_XMT 0x3FFF0000 // Maximum transmit frame length 302#define AXGMAC_MAXFRAME_XMT 0x3FFF0000 // Maximum transmit frame length
303#define AXGMAC_MAXFRAME_XMT_SHIFT 16 303#define AXGMAC_MAXFRAME_XMT_SHIFT 16
304#define AXGMAC_MAXFRAME_RCV 0x0000FFFF // Maximum receive frame length 304#define AXGMAC_MAXFRAME_RCV 0x0000FFFF // Maximum receive frame length
305// This register doesn't need to be written for standard MTU. 305// This register doesn't need to be written for standard MTU.
306// For jumbo, I'll just statically define the value here. This 306// For jumbo, I'll just statically define the value here. This
307// value sets the receive byte count to 9036 (0x234C) and the 307// value sets the receive byte count to 9036 (0x234C) and the
@@ -324,34 +324,34 @@ typedef struct _SXG_HW_REGS {
324 324
325// A-XGMAC AMIIM Field Register 325// A-XGMAC AMIIM Field Register
326#define AXGMAC_AMIIM_FIELD_ST 0xC0000000 // 2-bit ST field 326#define AXGMAC_AMIIM_FIELD_ST 0xC0000000 // 2-bit ST field
327#define AXGMAC_AMIIM_FIELD_ST_SHIFT 30 327#define AXGMAC_AMIIM_FIELD_ST_SHIFT 30
328#define AXGMAC_AMIIM_FIELD_OP 0x30000000 // 2-bit OP field 328#define AXGMAC_AMIIM_FIELD_OP 0x30000000 // 2-bit OP field
329#define AXGMAC_AMIIM_FIELD_OP_SHIFT 28 329#define AXGMAC_AMIIM_FIELD_OP_SHIFT 28
330#define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000 // Port address field (hstphyadx in spec) 330#define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000 // Port address field (hstphyadx in spec)
331#define AXGMAC_AMIIM_FIELD_PORT_SHIFT 23 331#define AXGMAC_AMIIM_FIELD_PORT_SHIFT 23
332#define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000 // Device address field (hstregadx in spec) 332#define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000 // Device address field (hstregadx in spec)
333#define AXGMAC_AMIIM_FIELD_DEV_SHIFT 18 333#define AXGMAC_AMIIM_FIELD_DEV_SHIFT 18
334#define AXGMAC_AMIIM_FIELD_TA 0x00030000 // 2-bit TA field 334#define AXGMAC_AMIIM_FIELD_TA 0x00030000 // 2-bit TA field
335#define AXGMAC_AMIIM_FIELD_TA_SHIFT 16 335#define AXGMAC_AMIIM_FIELD_TA_SHIFT 16
336#define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF // Data field 336#define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF // Data field
337 337
338// Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register 338// Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register
339#define MIIM_OP_ADDR 0 // MIIM Address set operation 339#define MIIM_OP_ADDR 0 // MIIM Address set operation
340#define MIIM_OP_WRITE 1 // MIIM Write register operation 340#define MIIM_OP_WRITE 1 // MIIM Write register operation
341#define MIIM_OP_READ 2 // MIIM Read register operation 341#define MIIM_OP_READ 2 // MIIM Read register operation
342#define MIIM_OP_ADDR_SHIFT (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) 342#define MIIM_OP_ADDR_SHIFT (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT)
343 343
344// Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM Field Register 344// Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM Field Register
345#define MIIM_PORT_NUM 1 // All Sahara MIIM modules use port 1 345#define MIIM_PORT_NUM 1 // All Sahara MIIM modules use port 1
346 346
347// Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM Field Register 347// Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM Field Register
348#define MIIM_DEV_PHY_PMA 1 // PHY PMA/PMD module MIIM device number 348#define MIIM_DEV_PHY_PMA 1 // PHY PMA/PMD module MIIM device number
349#define MIIM_DEV_PHY_PCS 3 // PHY PCS module MIIM device number 349#define MIIM_DEV_PHY_PCS 3 // PHY PCS module MIIM device number
350#define MIIM_DEV_PHY_XS 4 // PHY XS module MIIM device number 350#define MIIM_DEV_PHY_XS 4 // PHY XS module MIIM device number
351#define MIIM_DEV_XGXS 5 // XGXS MIIM device number 351#define MIIM_DEV_XGXS 5 // XGXS MIIM device number
352 352
353// Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field Register 353// Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field Register
354#define MIIM_TA_10GB 2 // set to 2 for 10 GB operation 354#define MIIM_TA_10GB 2 // set to 2 for 10 GB operation
355 355
356// A-XGMAC AMIIM Configuration Register 356// A-XGMAC AMIIM Configuration Register
357#define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080 // Bypass preamble of mngmt frame 357#define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080 // Bypass preamble of mngmt frame
@@ -365,25 +365,25 @@ typedef struct _SXG_HW_REGS {
365#define AXGMAC_AMIIM_INDC_BUSY 0x00000001 // Set until cmd operation complete 365#define AXGMAC_AMIIM_INDC_BUSY 0x00000001 // Set until cmd operation complete
366 366
367// Link Status and Control Register 367// Link Status and Control Register
368#define LS_PHY_CLR_RESET 0x80000000 // Clear reset signal to PHY 368#define LS_PHY_CLR_RESET 0x80000000 // Clear reset signal to PHY
369#define LS_SERDES_POWER_DOWN 0x40000000 // Power down the Sahara Serdes 369#define LS_SERDES_POWER_DOWN 0x40000000 // Power down the Sahara Serdes
370#define LS_XGXS_ENABLE 0x20000000 // Enable the XAUI XGXS logic 370#define LS_XGXS_ENABLE 0x20000000 // Enable the XAUI XGXS logic
371#define LS_XGXS_CTL 0x10000000 // Hold XAUI XGXS logic reset until Serdes is up 371#define LS_XGXS_CTL 0x10000000 // Hold XAUI XGXS logic reset until Serdes is up
372#define LS_SERDES_DOWN 0x08000000 // When 0, XAUI Serdes is up and initialization is complete 372#define LS_SERDES_DOWN 0x08000000 // When 0, XAUI Serdes is up and initialization is complete
373#define LS_TRACE_DOWN 0x04000000 // When 0, Trace Serdes is up and initialization is complete 373#define LS_TRACE_DOWN 0x04000000 // When 0, Trace Serdes is up and initialization is complete
374#define LS_PHY_CLK_25MHZ 0x02000000 // Set PHY clock to 25 MHz (else 156.125 MHz) 374#define LS_PHY_CLK_25MHZ 0x02000000 // Set PHY clock to 25 MHz (else 156.125 MHz)
375#define LS_PHY_CLK_EN 0x01000000 // Enable clock to PHY 375#define LS_PHY_CLK_EN 0x01000000 // Enable clock to PHY
376#define LS_XAUI_LINK_UP 0x00000010 // XAUI link is up 376#define LS_XAUI_LINK_UP 0x00000010 // XAUI link is up
377#define LS_XAUI_LINK_CHNG 0x00000008 // XAUI link status has changed 377#define LS_XAUI_LINK_CHNG 0x00000008 // XAUI link status has changed
378#define LS_LINK_ALARM 0x00000004 // Link alarm pin 378#define LS_LINK_ALARM 0x00000004 // Link alarm pin
379#define LS_ATTN_CTRL_MASK 0x00000003 // Mask link attention control bits 379#define LS_ATTN_CTRL_MASK 0x00000003 // Mask link attention control bits
380#define LS_ATTN_ALARM 0x00000000 // 00 => Attn on link alarm 380#define LS_ATTN_ALARM 0x00000000 // 00 => Attn on link alarm
381#define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001 // 01 => Attn on link alarm or status change 381#define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001 // 01 => Attn on link alarm or status change
382#define LS_ATTN_STAT_CHNG 0x00000002 // 10 => Attn on link status change 382#define LS_ATTN_STAT_CHNG 0x00000002 // 10 => Attn on link status change
383#define LS_ATTN_NONE 0x00000003 // 11 => no Attn 383#define LS_ATTN_NONE 0x00000003 // 11 => no Attn
384 384
385// Link Address High Registers 385// Link Address High Registers
386#define LINK_ADDR_ENABLE 0x80000000 // Enable this link address 386#define LINK_ADDR_ENABLE 0x80000000 // Enable this link address
387 387
388 388
389/*************************************************************************** 389/***************************************************************************
@@ -396,7 +396,7 @@ typedef struct _SXG_HW_REGS {
396#define XGXS_ADDRESS_STATUS1 0x0001 // XS Status 1 396#define XGXS_ADDRESS_STATUS1 0x0001 // XS Status 1
397#define XGXS_ADDRESS_DEVID_LOW 0x0002 // XS Device ID (low) 397#define XGXS_ADDRESS_DEVID_LOW 0x0002 // XS Device ID (low)
398#define XGXS_ADDRESS_DEVID_HIGH 0x0003 // XS Device ID (high) 398#define XGXS_ADDRESS_DEVID_HIGH 0x0003 // XS Device ID (high)
399#define XGXS_ADDRESS_SPEED 0x0004 // XS Speed ability 399#define XGXS_ADDRESS_SPEED 0x0004 // XS Speed ability
400#define XGXS_ADDRESS_DEV_LOW 0x0005 // XS Devices in package 400#define XGXS_ADDRESS_DEV_LOW 0x0005 // XS Devices in package
401#define XGXS_ADDRESS_DEV_HIGH 0x0006 // XS Devices in package 401#define XGXS_ADDRESS_DEV_HIGH 0x0006 // XS Devices in package
402#define XGXS_ADDRESS_STATUS2 0x0008 // XS Status 2 402#define XGXS_ADDRESS_STATUS2 0x0008 // XS Status 2
@@ -410,27 +410,27 @@ typedef struct _SXG_HW_REGS {
410#define XGXS_ADDRESS_RESET_HI2 0x8003 // Vendor-Specific Reset Hi 2 410#define XGXS_ADDRESS_RESET_HI2 0x8003 // Vendor-Specific Reset Hi 2
411 411
412// XS Control 1 register bit definitions 412// XS Control 1 register bit definitions
413#define XGXS_CONTROL1_RESET 0x8000 // Reset - self clearing 413#define XGXS_CONTROL1_RESET 0x8000 // Reset - self clearing
414#define XGXS_CONTROL1_LOOPBACK 0x4000 // Enable loopback 414#define XGXS_CONTROL1_LOOPBACK 0x4000 // Enable loopback
415#define XGXS_CONTROL1_SPEED1 0x2000 // 0 = unspecified, 1 = 10Gb+ 415#define XGXS_CONTROL1_SPEED1 0x2000 // 0 = unspecified, 1 = 10Gb+
416#define XGXS_CONTROL1_LOWPOWER 0x0400 // 1 = Low power mode 416#define XGXS_CONTROL1_LOWPOWER 0x0400 // 1 = Low power mode
417#define XGXS_CONTROL1_SPEED2 0x0040 // Same as SPEED1 (?) 417#define XGXS_CONTROL1_SPEED2 0x0040 // Same as SPEED1 (?)
418#define XGXS_CONTROL1_SPEED 0x003C // Everything reserved except zero (?) 418#define XGXS_CONTROL1_SPEED 0x003C // Everything reserved except zero (?)
419 419
420// XS Status 1 register bit definitions 420// XS Status 1 register bit definitions
421#define XGXS_STATUS1_FAULT 0x0080 // Fault detected 421#define XGXS_STATUS1_FAULT 0x0080 // Fault detected
422#define XGXS_STATUS1_LINK 0x0004 // 1 = Link up 422#define XGXS_STATUS1_LINK 0x0004 // 1 = Link up
423#define XGXS_STATUS1_LOWPOWER 0x0002 // 1 = Low power supported 423#define XGXS_STATUS1_LOWPOWER 0x0002 // 1 = Low power supported
424 424
425// XS Speed register bit definitions 425// XS Speed register bit definitions
426#define XGXS_SPEED_10G 0x0001 // 1 = 10G capable 426#define XGXS_SPEED_10G 0x0001 // 1 = 10G capable
427 427
428// XS Devices register bit definitions 428// XS Devices register bit definitions
429#define XGXS_DEVICES_DTE 0x0020 // DTE XS Present 429#define XGXS_DEVICES_DTE 0x0020 // DTE XS Present
430#define XGXS_DEVICES_PHY 0x0010 // PHY XS Present 430#define XGXS_DEVICES_PHY 0x0010 // PHY XS Present
431#define XGXS_DEVICES_PCS 0x0008 // PCS Present 431#define XGXS_DEVICES_PCS 0x0008 // PCS Present
432#define XGXS_DEVICES_WIS 0x0004 // WIS Present 432#define XGXS_DEVICES_WIS 0x0004 // WIS Present
433#define XGXS_DEVICES_PMD 0x0002 // PMD/PMA Present 433#define XGXS_DEVICES_PMD 0x0002 // PMD/PMA Present
434#define XGXS_DEVICES_CLAUSE22 0x0001 // Clause 22 registers present 434#define XGXS_DEVICES_CLAUSE22 0x0001 // Clause 22 registers present
435 435
436// XS Devices High register bit definitions 436// XS Devices High register bit definitions
@@ -444,18 +444,18 @@ typedef struct _SXG_HW_REGS {
444#define XGXS_STATUS2_RCV_FAULT 0x0400 // Receive fault 444#define XGXS_STATUS2_RCV_FAULT 0x0400 // Receive fault
445 445
446// XS Package ID High register bit definitions 446// XS Package ID High register bit definitions
447#define XGXS_PKGID_HIGH_ORG 0xFC00 // Organizationally Unique 447#define XGXS_PKGID_HIGH_ORG 0xFC00 // Organizationally Unique
448#define XGXS_PKGID_HIGH_MFG 0x03F0 // Manufacturer Model 448#define XGXS_PKGID_HIGH_MFG 0x03F0 // Manufacturer Model
449#define XGXS_PKGID_HIGH_REV 0x000F // Revision Number 449#define XGXS_PKGID_HIGH_REV 0x000F // Revision Number
450 450
451// XS Lane Status register bit definitions 451// XS Lane Status register bit definitions
452#define XGXS_LANE_PHY 0x1000 // PHY/DTE lane alignment status 452#define XGXS_LANE_PHY 0x1000 // PHY/DTE lane alignment status
453#define XGXS_LANE_PATTERN 0x0800 // Pattern testing ability 453#define XGXS_LANE_PATTERN 0x0800 // Pattern testing ability
454#define XGXS_LANE_LOOPBACK 0x0400 // PHY loopback ability 454#define XGXS_LANE_LOOPBACK 0x0400 // PHY loopback ability
455#define XGXS_LANE_SYNC3 0x0008 // Lane 3 sync 455#define XGXS_LANE_SYNC3 0x0008 // Lane 3 sync
456#define XGXS_LANE_SYNC2 0x0004 // Lane 2 sync 456#define XGXS_LANE_SYNC2 0x0004 // Lane 2 sync
457#define XGXS_LANE_SYNC1 0x0002 // Lane 1 sync 457#define XGXS_LANE_SYNC1 0x0002 // Lane 1 sync
458#define XGXS_LANE_SYNC0 0x0001 // Lane 0 sync 458#define XGXS_LANE_SYNC0 0x0001 // Lane 0 sync
459 459
460// XS Test Control register bit definitions 460// XS Test Control register bit definitions
461#define XGXS_TEST_PATTERN_ENABLE 0x0004 // Test pattern enabled 461#define XGXS_TEST_PATTERN_ENABLE 0x0004 // Test pattern enabled
@@ -473,10 +473,10 @@ typedef struct _SXG_HW_REGS {
473// LASI (Link Alarm Status Interrupt) Registers (located in MIIM_DEV_PHY_PMA device) 473// LASI (Link Alarm Status Interrupt) Registers (located in MIIM_DEV_PHY_PMA device)
474#define LASI_RX_ALARM_CONTROL 0x9000 // LASI RX_ALARM Control 474#define LASI_RX_ALARM_CONTROL 0x9000 // LASI RX_ALARM Control
475#define LASI_TX_ALARM_CONTROL 0x9001 // LASI TX_ALARM Control 475#define LASI_TX_ALARM_CONTROL 0x9001 // LASI TX_ALARM Control
476#define LASI_CONTROL 0x9002 // LASI Control 476#define LASI_CONTROL 0x9002 // LASI Control
477#define LASI_RX_ALARM_STATUS 0x9003 // LASI RX_ALARM Status 477#define LASI_RX_ALARM_STATUS 0x9003 // LASI RX_ALARM Status
478#define LASI_TX_ALARM_STATUS 0x9004 // LASI TX_ALARM Status 478#define LASI_TX_ALARM_STATUS 0x9004 // LASI TX_ALARM Status
479#define LASI_STATUS 0x9005 // LASI Status 479#define LASI_STATUS 0x9005 // LASI Status
480 480
481// LASI_CONTROL bit definitions 481// LASI_CONTROL bit definitions
482#define LASI_CTL_RX_ALARM_ENABLE 0x0004 // Enable RX_ALARM interrupts 482#define LASI_CTL_RX_ALARM_ENABLE 0x0004 // Enable RX_ALARM interrupts
@@ -489,34 +489,34 @@ typedef struct _SXG_HW_REGS {
489#define LASI_STATUS_LS_ALARM 0x0001 // Link Status 489#define LASI_STATUS_LS_ALARM 0x0001 // Link Status
490 490
491// PHY registers - PMA/PMD (device 1) 491// PHY registers - PMA/PMD (device 1)
492#define PHY_PMA_CONTROL1 0x0000 // PMA/PMD Control 1 492#define PHY_PMA_CONTROL1 0x0000 // PMA/PMD Control 1
493#define PHY_PMA_STATUS1 0x0001 // PMA/PMD Status 1 493#define PHY_PMA_STATUS1 0x0001 // PMA/PMD Status 1
494#define PHY_PMA_RCV_DET 0x000A // PMA/PMD Receive Signal Detect 494#define PHY_PMA_RCV_DET 0x000A // PMA/PMD Receive Signal Detect
495 // other PMA/PMD registers exist and can be defined as needed 495 // other PMA/PMD registers exist and can be defined as needed
496 496
497// PHY registers - PCS (device 3) 497// PHY registers - PCS (device 3)
498#define PHY_PCS_CONTROL1 0x0000 // PCS Control 1 498#define PHY_PCS_CONTROL1 0x0000 // PCS Control 1
499#define PHY_PCS_STATUS1 0x0001 // PCS Status 1 499#define PHY_PCS_STATUS1 0x0001 // PCS Status 1
500#define PHY_PCS_10G_STATUS1 0x0020 // PCS 10GBASE-R Status 1 500#define PHY_PCS_10G_STATUS1 0x0020 // PCS 10GBASE-R Status 1
501 // other PCS registers exist and can be defined as needed 501 // other PCS registers exist and can be defined as needed
502 502
503// PHY registers - XS (device 4) 503// PHY registers - XS (device 4)
504#define PHY_XS_CONTROL1 0x0000 // XS Control 1 504#define PHY_XS_CONTROL1 0x0000 // XS Control 1
505#define PHY_XS_STATUS1 0x0001 // XS Status 1 505#define PHY_XS_STATUS1 0x0001 // XS Status 1
506#define PHY_XS_LANE_STATUS 0x0018 // XS Lane Status 506#define PHY_XS_LANE_STATUS 0x0018 // XS Lane Status
507 // other XS registers exist and can be defined as needed 507 // other XS registers exist and can be defined as needed
508 508
509// PHY_PMA_CONTROL1 register bit definitions 509// PHY_PMA_CONTROL1 register bit definitions
510#define PMA_CONTROL1_RESET 0x8000 // PMA/PMD reset 510#define PMA_CONTROL1_RESET 0x8000 // PMA/PMD reset
511 511
512// PHY_PMA_RCV_DET register bit definitions 512// PHY_PMA_RCV_DET register bit definitions
513#define PMA_RCV_DETECT 0x0001 // PMA/PMD receive signal detect 513#define PMA_RCV_DETECT 0x0001 // PMA/PMD receive signal detect
514 514
515// PHY_PCS_10G_STATUS1 register bit definitions 515// PHY_PCS_10G_STATUS1 register bit definitions
516#define PCS_10B_BLOCK_LOCK 0x0001 // PCS 10GBASE-R locked to receive blocks 516#define PCS_10B_BLOCK_LOCK 0x0001 // PCS 10GBASE-R locked to receive blocks
517 517
518// PHY_XS_LANE_STATUS register bit definitions 518// PHY_XS_LANE_STATUS register bit definitions
519#define XS_LANE_ALIGN 0x1000 // XS transmit lanes aligned 519#define XS_LANE_ALIGN 0x1000 // XS transmit lanes aligned
520 520
521// PHY Microcode download data structure 521// PHY Microcode download data structure
522typedef struct _PHY_UCODE { 522typedef struct _PHY_UCODE {
@@ -558,8 +558,8 @@ typedef struct _XMT_DESC {
558 // command codes 558 // command codes
559#define XMT_DESC_CMD_RAW_SEND 0 // raw send descriptor 559#define XMT_DESC_CMD_RAW_SEND 0 // raw send descriptor
560#define XMT_DESC_CMD_CSUM_INSERT 1 // checksum insert descriptor 560#define XMT_DESC_CMD_CSUM_INSERT 1 // checksum insert descriptor
561#define XMT_DESC_CMD_FORMAT 2 // format descriptor 561#define XMT_DESC_CMD_FORMAT 2 // format descriptor
562#define XMT_DESC_CMD_PRIME 3 // prime descriptor 562#define XMT_DESC_CMD_PRIME 3 // prime descriptor
563#define XMT_DESC_CMD_CODE_SHFT 6 // comand code shift (shift to bits [31:30] in word 0) 563#define XMT_DESC_CMD_CODE_SHFT 6 // comand code shift (shift to bits [31:30] in word 0)
564 // shifted command codes 564 // shifted command codes
565#define XMT_RAW_SEND (XMT_DESC_CMD_RAW_SEND << XMT_DESC_CMD_CODE_SHFT) 565#define XMT_RAW_SEND (XMT_DESC_CMD_RAW_SEND << XMT_DESC_CMD_CODE_SHFT)
@@ -569,22 +569,22 @@ typedef struct _XMT_DESC {
569 569
570// XMT_DESC Control Byte (XmtCtl) definitions 570// XMT_DESC Control Byte (XmtCtl) definitions
571// NOTE: These bits do not work on Sahara (Rev A)! 571// NOTE: These bits do not work on Sahara (Rev A)!
572#define XMT_CTL_PAUSE_FRAME 0x80 // current frame is a pause control frame (for statistics) 572#define XMT_CTL_PAUSE_FRAME 0x80 // current frame is a pause control frame (for statistics)
573#define XMT_CTL_CONTROL_FRAME 0x40 // current frame is a control frame (for statistics) 573#define XMT_CTL_CONTROL_FRAME 0x40 // current frame is a control frame (for statistics)
574#define XMT_CTL_PER_PKT_QUAL 0x20 // per packet qualifier 574#define XMT_CTL_PER_PKT_QUAL 0x20 // per packet qualifier
575#define XMT_CTL_PAD_MODE_NONE 0x00 // do not pad frame 575#define XMT_CTL_PAD_MODE_NONE 0x00 // do not pad frame
576#define XMT_CTL_PAD_MODE_64 0x08 // pad frame to 64 bytes 576#define XMT_CTL_PAD_MODE_64 0x08 // pad frame to 64 bytes
577#define XMT_CTL_PAD_MODE_VLAN_68 0x10 // pad frame to 64 bytes, and VLAN frames to 68 bytes 577#define XMT_CTL_PAD_MODE_VLAN_68 0x10 // pad frame to 64 bytes, and VLAN frames to 68 bytes
578#define XMT_CTL_PAD_MODE_68 0x18 // pad frame to 68 bytes 578#define XMT_CTL_PAD_MODE_68 0x18 // pad frame to 68 bytes
579#define XMT_CTL_GEN_FCS 0x04 // generate FCS (CRC) for this frame 579#define XMT_CTL_GEN_FCS 0x04 // generate FCS (CRC) for this frame
580#define XMT_CTL_DELAY_FCS_0 0x00 // do not delay FCS calcution 580#define XMT_CTL_DELAY_FCS_0 0x00 // do not delay FCS calcution
581#define XMT_CTL_DELAY_FCS_1 0x01 // delay FCS calculation by 1 (4-byte) word 581#define XMT_CTL_DELAY_FCS_1 0x01 // delay FCS calculation by 1 (4-byte) word
582#define XMT_CTL_DELAY_FCS_2 0x02 // delay FCS calculation by 2 (4-byte) words 582#define XMT_CTL_DELAY_FCS_2 0x02 // delay FCS calculation by 2 (4-byte) words
583#define XMT_CTL_DELAY_FCS_3 0x03 // delay FCS calculation by 3 (4-byte) words 583#define XMT_CTL_DELAY_FCS_3 0x03 // delay FCS calculation by 3 (4-byte) words
584 584
585// XMT_DESC XmtBufId definition 585// XMT_DESC XmtBufId definition
586#define XMT_BUF_ID_SHFT 8 // The Xmt buffer ID is formed by dividing 586#define XMT_BUF_ID_SHFT 8 // The Xmt buffer ID is formed by dividing
587 // the buffer (DRAM) address by 256 (or << 8) 587 // the buffer (DRAM) address by 256 (or << 8)
588 588
589/***************************************************************************** 589/*****************************************************************************
590 * Receiver Sequencer Definitions 590 * Receiver Sequencer Definitions
@@ -594,8 +594,8 @@ typedef struct _XMT_DESC {
594#define RCV_EVTQ_RBFID_MASK 0x0000FFFF // bit mask for the Receive Buffer ID 594#define RCV_EVTQ_RBFID_MASK 0x0000FFFF // bit mask for the Receive Buffer ID
595 595
596// Receive Buffer ID definition 596// Receive Buffer ID definition
597#define RCV_BUF_ID_SHFT 5 // The Rcv buffer ID is formed by dividing 597#define RCV_BUF_ID_SHFT 5 // The Rcv buffer ID is formed by dividing
598 // the buffer (DRAM) address by 32 (or << 5) 598 // the buffer (DRAM) address by 32 (or << 5)
599 599
600// Format of the 18 byte Receive Buffer returned by the 600// Format of the 18 byte Receive Buffer returned by the
601// Receive Sequencer for received packets 601// Receive Sequencer for received packets
@@ -723,12 +723,12 @@ typedef struct _SXG_CONFIG {
723 *****************************************************************************/ 723 *****************************************************************************/
724 724
725// Sahara (ASIC level) defines 725// Sahara (ASIC level) defines
726#define SAHARA_GRAM_SIZE 0x020000 // GRAM size - 128 KB 726#define SAHARA_GRAM_SIZE 0x020000 // GRAM size - 128 KB
727#define SAHARA_DRAM_SIZE 0x200000 // DRAM size - 2 MB 727#define SAHARA_DRAM_SIZE 0x200000 // DRAM size - 2 MB
728#define SAHARA_QRAM_SIZE 0x004000 // QRAM size - 16K entries (64 KB) 728#define SAHARA_QRAM_SIZE 0x004000 // QRAM size - 16K entries (64 KB)
729#define SAHARA_WCS_SIZE 0x002000 // WCS - 8K instructions (x 108 bits) 729#define SAHARA_WCS_SIZE 0x002000 // WCS - 8K instructions (x 108 bits)
730 730
731// Arabia (board level) defines 731// Arabia (board level) defines
732#define FLASH_SIZE 0x080000 // 512 KB (4 Mb) 732#define FLASH_SIZE 0x080000 // 512 KB (4 Mb)
733#define EEPROM_SIZE_XFMR 512 // true EEPROM size (bytes), including xfmr area 733#define EEPROM_SIZE_XFMR 512 // true EEPROM size (bytes), including xfmr area
734#define EEPROM_SIZE_NO_XFMR 256 // EEPROM size excluding xfmr area 734#define EEPROM_SIZE_NO_XFMR 256 // EEPROM size excluding xfmr area
diff --git a/drivers/staging/sxg/sxgphycode.h b/drivers/staging/sxg/sxgphycode.h
index 26b36c81eb1..8dbaeda7eca 100644
--- a/drivers/staging/sxg/sxgphycode.h
+++ b/drivers/staging/sxg/sxgphycode.h
@@ -34,7 +34,7 @@ static PHY_UCODE PhyUcode[] = {
34 */ 34 */
35 /* Addr, Data */ 35 /* Addr, Data */
36 {0xc017, 0xfeb0}, /* flip RX_LOS polarity (mandatory */ 36 {0xc017, 0xfeb0}, /* flip RX_LOS polarity (mandatory */
37 /* patch for SFP+ applications) */ 37 /* patch for SFP+ applications) */
38 {0xC001, 0x0428}, /* flip RX serial polarity */ 38 {0xC001, 0x0428}, /* flip RX serial polarity */
39 39
40 {0xc013, 0xf341}, /* invert lxmit clock (mandatory patch) */ 40 {0xc013, 0xf341}, /* invert lxmit clock (mandatory patch) */
@@ -43,7 +43,7 @@ static PHY_UCODE PhyUcode[] = {
43 {0xc210, 0x8000}, /* reset datapath (mandatory patch) */ 43 {0xc210, 0x8000}, /* reset datapath (mandatory patch) */
44 {0xc210, 0x0000}, /* reset datapath (mandatory patch) */ 44 {0xc210, 0x0000}, /* reset datapath (mandatory patch) */
45 {0x0000, 0x0032}, /* wait for 50ms for datapath reset to */ 45 {0x0000, 0x0032}, /* wait for 50ms for datapath reset to */
46 /* complete. (mandatory patch) */ 46 /* complete. (mandatory patch) */
47 47
48 /* Configure the LED's */ 48 /* Configure the LED's */
49 {0xc214, 0x0099}, /* configure the LED drivers */ 49 {0xc214, 0x0099}, /* configure the LED drivers */
@@ -52,15 +52,15 @@ static PHY_UCODE PhyUcode[] = {
52 52
53 /* Transceiver-specific MDIO Patches: */ 53 /* Transceiver-specific MDIO Patches: */
54 {0xc010, 0x448a}, /* (bit 14) mask out high BER input from the */ 54 {0xc010, 0x448a}, /* (bit 14) mask out high BER input from the */
55 /* LOS signal in 1.000A */ 55 /* LOS signal in 1.000A */
56 /* (mandatory patch for SR code)*/ 56 /* (mandatory patch for SR code) */
57 {0xc003, 0x0181}, /* (bit 7) enable the CDR inc setting in */ 57 {0xc003, 0x0181}, /* (bit 7) enable the CDR inc setting in */
58 /* 1.C005 (mandatory patch for SR code) */ 58 /* 1.C005 (mandatory patch for SR code) */
59 59
60 /* Transceiver-specific Microcontroller Initialization: */ 60 /* Transceiver-specific Microcontroller Initialization: */
61 {0xc04a, 0x5200}, /* activate microcontroller and pause */ 61 {0xc04a, 0x5200}, /* activate microcontroller and pause */
62 {0x0000, 0x0032}, /* wait 50ms for microcontroller before */ 62 {0x0000, 0x0032}, /* wait 50ms for microcontroller before */
63 /* writing in code. */ 63 /* writing in code. */
64 64
65 /* code block starts here: */ 65 /* code block starts here: */
66 {0xcc00, 0x2009}, 66 {0xcc00, 0x2009},
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 09:21:28 -0400