aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/staging/vt6655/mac.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/staging/vt6655/mac.c')
-rw-r--r--drivers/staging/vt6655/mac.c75
1 files changed, 37 insertions, 38 deletions
diff --git a/drivers/staging/vt6655/mac.c b/drivers/staging/vt6655/mac.c
index 889866c13c7..cdd7cd5e409 100644
--- a/drivers/staging/vt6655/mac.c
+++ b/drivers/staging/vt6655/mac.c
@@ -69,7 +69,6 @@
69 */ 69 */
70 70
71#include "tmacro.h" 71#include "tmacro.h"
72#include "tbit.h"
73#include "tether.h" 72#include "tether.h"
74#include "mac.h" 73#include "mac.h"
75 74
@@ -146,7 +145,7 @@ BOOL MACbIsRegBitsOn (DWORD_PTR dwIoBase, BYTE byRegOfs, BYTE byTestBits)
146 BYTE byData; 145 BYTE byData;
147 146
148 VNSvInPortB(dwIoBase + byRegOfs, &byData); 147 VNSvInPortB(dwIoBase + byRegOfs, &byData);
149 return BITbIsAllBitsOn(byData, byTestBits); 148 return (byData & byTestBits) == byTestBits;
150} 149}
151 150
152/* 151/*
@@ -169,7 +168,7 @@ BOOL MACbIsRegBitsOff (DWORD_PTR dwIoBase, BYTE byRegOfs, BYTE byTestBits)
169 BYTE byData; 168 BYTE byData;
170 169
171 VNSvInPortB(dwIoBase + byRegOfs, &byData); 170 VNSvInPortB(dwIoBase + byRegOfs, &byData);
172 return BITbIsAllBitsOff(byData, byTestBits); 171 return !(byData & byTestBits);
173} 172}
174 173
175/* 174/*
@@ -565,7 +564,7 @@ BOOL MACbIsInLoopbackMode (DWORD_PTR dwIoBase)
565 BYTE byOrgValue; 564 BYTE byOrgValue;
566 565
567 VNSvInPortB(dwIoBase + MAC_REG_TEST, &byOrgValue); 566 VNSvInPortB(dwIoBase + MAC_REG_TEST, &byOrgValue);
568 if (BITbIsAnyBitsOn(byOrgValue, (TEST_LBINT | TEST_LBEXT))) 567 if (byOrgValue & (TEST_LBINT | TEST_LBEXT))
569 return TRUE; 568 return TRUE;
570 return FALSE; 569 return FALSE;
571} 570}
@@ -592,7 +591,7 @@ void MACvSetPacketFilter (DWORD_PTR dwIoBase, WORD wFilterType)
592 // if only in DIRECTED mode, multicast-address will set to zero, 591 // if only in DIRECTED mode, multicast-address will set to zero,
593 // but if other mode exist (e.g. PROMISCUOUS), multicast-address 592 // but if other mode exist (e.g. PROMISCUOUS), multicast-address
594 // will be open 593 // will be open
595 if (BITbIsBitOn(wFilterType, PKT_TYPE_DIRECTED)) { 594 if (wFilterType & PKT_TYPE_DIRECTED) {
596 // set multicast address to accept none 595 // set multicast address to accept none
597 MACvSelectPage1(dwIoBase); 596 MACvSelectPage1(dwIoBase);
598 VNSvOutPortD(dwIoBase + MAC_REG_MAR0, 0L); 597 VNSvOutPortD(dwIoBase + MAC_REG_MAR0, 0L);
@@ -600,7 +599,7 @@ void MACvSetPacketFilter (DWORD_PTR dwIoBase, WORD wFilterType)
600 MACvSelectPage0(dwIoBase); 599 MACvSelectPage0(dwIoBase);
601 } 600 }
602 601
603 if (BITbIsAnyBitsOn(wFilterType, PKT_TYPE_PROMISCUOUS | PKT_TYPE_ALL_MULTICAST)) { 602 if (wFilterType & (PKT_TYPE_PROMISCUOUS | PKT_TYPE_ALL_MULTICAST)) {
604 // set multicast address to accept all 603 // set multicast address to accept all
605 MACvSelectPage1(dwIoBase); 604 MACvSelectPage1(dwIoBase);
606 VNSvOutPortD(dwIoBase + MAC_REG_MAR0, 0xFFFFFFFFL); 605 VNSvOutPortD(dwIoBase + MAC_REG_MAR0, 0xFFFFFFFFL);
@@ -608,20 +607,20 @@ void MACvSetPacketFilter (DWORD_PTR dwIoBase, WORD wFilterType)
608 MACvSelectPage0(dwIoBase); 607 MACvSelectPage0(dwIoBase);
609 } 608 }
610 609
611 if (BITbIsBitOn(wFilterType, PKT_TYPE_PROMISCUOUS)) { 610 if (wFilterType & PKT_TYPE_PROMISCUOUS) {
612 611
613 byNewRCR |= (RCR_RXALLTYPE | RCR_UNICAST | RCR_MULTICAST | RCR_BROADCAST); 612 byNewRCR |= (RCR_RXALLTYPE | RCR_UNICAST | RCR_MULTICAST | RCR_BROADCAST);
614 613
615 byNewRCR &= ~RCR_BSSID; 614 byNewRCR &= ~RCR_BSSID;
616 } 615 }
617 616
618 if (BITbIsAnyBitsOn(wFilterType, (PKT_TYPE_ALL_MULTICAST | PKT_TYPE_MULTICAST))) 617 if (wFilterType & (PKT_TYPE_ALL_MULTICAST | PKT_TYPE_MULTICAST))
619 byNewRCR |= RCR_MULTICAST; 618 byNewRCR |= RCR_MULTICAST;
620 619
621 if (BITbIsBitOn(wFilterType, PKT_TYPE_BROADCAST)) 620 if (wFilterType & PKT_TYPE_BROADCAST)
622 byNewRCR |= RCR_BROADCAST; 621 byNewRCR |= RCR_BROADCAST;
623 622
624 if (BITbIsBitOn(wFilterType, PKT_TYPE_ERROR_CRC)) 623 if (wFilterType & PKT_TYPE_ERROR_CRC)
625 byNewRCR |= RCR_ERRCRC; 624 byNewRCR |= RCR_ERRCRC;
626 625
627 VNSvInPortB(dwIoBase + MAC_REG_RCR, &byOldRCR); 626 VNSvInPortB(dwIoBase + MAC_REG_RCR, &byOldRCR);
@@ -785,7 +784,7 @@ BOOL MACbSoftwareReset (DWORD_PTR dwIoBase)
785 784
786 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 785 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
787 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData); 786 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
788 if (BITbIsBitOff(byData, HOSTCR_SOFTRST)) 787 if ( !(byData & HOSTCR_SOFTRST))
789 break; 788 break;
790 } 789 }
791 if (ww == W_MAX_TIMEOUT) 790 if (ww == W_MAX_TIMEOUT)
@@ -853,7 +852,7 @@ BOOL MACbSafeRxOff (DWORD_PTR dwIoBase)
853 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_CLRRUN); 852 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_CLRRUN);
854 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 853 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
855 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); 854 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData);
856 if (BITbIsAllBitsOff(dwData, DMACTL_RUN)) 855 if (!(dwData & DMACTL_RUN))
857 break; 856 break;
858 } 857 }
859 if (ww == W_MAX_TIMEOUT) { 858 if (ww == W_MAX_TIMEOUT) {
@@ -863,7 +862,7 @@ BOOL MACbSafeRxOff (DWORD_PTR dwIoBase)
863 } 862 }
864 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 863 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
865 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); 864 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData);
866 if (BITbIsAllBitsOff(dwData, DMACTL_RUN)) 865 if ( !(dwData & DMACTL_RUN))
867 break; 866 break;
868 } 867 }
869 if (ww == W_MAX_TIMEOUT) { 868 if (ww == W_MAX_TIMEOUT) {
@@ -877,7 +876,7 @@ BOOL MACbSafeRxOff (DWORD_PTR dwIoBase)
877 // W_MAX_TIMEOUT is the timeout period 876 // W_MAX_TIMEOUT is the timeout period
878 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 877 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
879 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData); 878 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
880 if (BITbIsAllBitsOff(byData, HOSTCR_RXONST)) 879 if ( !(byData & HOSTCR_RXONST))
881 break; 880 break;
882 } 881 }
883 if (ww == W_MAX_TIMEOUT) { 882 if (ww == W_MAX_TIMEOUT) {
@@ -916,7 +915,7 @@ BOOL MACbSafeTxOff (DWORD_PTR dwIoBase)
916 915
917 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 916 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
918 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); 917 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData);
919 if (BITbIsAllBitsOff(dwData, DMACTL_RUN)) 918 if ( !(dwData & DMACTL_RUN))
920 break; 919 break;
921 } 920 }
922 if (ww == W_MAX_TIMEOUT) { 921 if (ww == W_MAX_TIMEOUT) {
@@ -926,7 +925,7 @@ BOOL MACbSafeTxOff (DWORD_PTR dwIoBase)
926 } 925 }
927 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 926 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
928 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); 927 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData);
929 if (BITbIsAllBitsOff(dwData, DMACTL_RUN)) 928 if ( !(dwData & DMACTL_RUN))
930 break; 929 break;
931 } 930 }
932 if (ww == W_MAX_TIMEOUT) { 931 if (ww == W_MAX_TIMEOUT) {
@@ -941,7 +940,7 @@ BOOL MACbSafeTxOff (DWORD_PTR dwIoBase)
941 // W_MAX_TIMEOUT is the timeout period 940 // W_MAX_TIMEOUT is the timeout period
942 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 941 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
943 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData); 942 VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
944 if (BITbIsAllBitsOff(byData, HOSTCR_TXONST)) 943 if ( !(byData & HOSTCR_TXONST))
945 break; 944 break;
946 } 945 }
947 if (ww == W_MAX_TIMEOUT) { 946 if (ww == W_MAX_TIMEOUT) {
@@ -1049,7 +1048,7 @@ void MACvInitialize (DWORD_PTR dwIoBase)
1049 //while (TRUE) { 1048 //while (TRUE) {
1050 // U8 u8Data; 1049 // U8 u8Data;
1051 // VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &u8Data); 1050 // VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &u8Data);
1052 // if (BITbIsBitOff(u8Data, I2MCSR_AUTOLD)) 1051 // if ( !(u8Data & I2MCSR_AUTOLD))
1053 // break; 1052 // break;
1054 //} 1053 //}
1055 1054
@@ -1087,19 +1086,19 @@ BYTE byData;
1087BYTE byOrgDMACtl; 1086BYTE byOrgDMACtl;
1088 1087
1089 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byOrgDMACtl); 1088 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byOrgDMACtl);
1090 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1089 if (byOrgDMACtl & DMACTL_RUN) {
1091 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0+2, DMACTL_RUN); 1090 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0+2, DMACTL_RUN);
1092 } 1091 }
1093 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1092 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1094 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byData); 1093 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byData);
1095 if (BITbIsAllBitsOff(byData, DMACTL_RUN)) 1094 if ( !(byData & DMACTL_RUN))
1096 break; 1095 break;
1097 } 1096 }
1098 if (ww == W_MAX_TIMEOUT) { 1097 if (ww == W_MAX_TIMEOUT) {
1099 DBG_PORT80(0x13); 1098 DBG_PORT80(0x13);
1100 } 1099 }
1101 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR0, dwCurrDescAddr); 1100 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR0, dwCurrDescAddr);
1102 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1101 if (byOrgDMACtl & DMACTL_RUN) {
1103 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); 1102 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN);
1104 } 1103 }
1105} 1104}
@@ -1125,19 +1124,19 @@ BYTE byData;
1125BYTE byOrgDMACtl; 1124BYTE byOrgDMACtl;
1126 1125
1127 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byOrgDMACtl); 1126 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byOrgDMACtl);
1128 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1127 if (byOrgDMACtl & DMACTL_RUN) {
1129 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1+2, DMACTL_RUN); 1128 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1+2, DMACTL_RUN);
1130 } 1129 }
1131 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1130 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1132 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byData); 1131 VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byData);
1133 if (BITbIsAllBitsOff(byData, DMACTL_RUN)) 1132 if ( !(byData & DMACTL_RUN))
1134 break; 1133 break;
1135 } 1134 }
1136 if (ww == W_MAX_TIMEOUT) { 1135 if (ww == W_MAX_TIMEOUT) {
1137 DBG_PORT80(0x14); 1136 DBG_PORT80(0x14);
1138 } 1137 }
1139 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR1, dwCurrDescAddr); 1138 VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR1, dwCurrDescAddr);
1140 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1139 if (byOrgDMACtl & DMACTL_RUN) {
1141 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); 1140 VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN);
1142 } 1141 }
1143} 1142}
@@ -1163,19 +1162,19 @@ BYTE byData;
1163BYTE byOrgDMACtl; 1162BYTE byOrgDMACtl;
1164 1163
1165 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byOrgDMACtl); 1164 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byOrgDMACtl);
1166 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1165 if (byOrgDMACtl & DMACTL_RUN) {
1167 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0+2, DMACTL_RUN); 1166 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0+2, DMACTL_RUN);
1168 } 1167 }
1169 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1168 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1170 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byData); 1169 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byData);
1171 if (BITbIsAllBitsOff(byData, DMACTL_RUN)) 1170 if ( !(byData & DMACTL_RUN))
1172 break; 1171 break;
1173 } 1172 }
1174 if (ww == W_MAX_TIMEOUT) { 1173 if (ww == W_MAX_TIMEOUT) {
1175 DBG_PORT80(0x25); 1174 DBG_PORT80(0x25);
1176 } 1175 }
1177 VNSvOutPortD(dwIoBase + MAC_REG_TXDMAPTR0, dwCurrDescAddr); 1176 VNSvOutPortD(dwIoBase + MAC_REG_TXDMAPTR0, dwCurrDescAddr);
1178 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1177 if (byOrgDMACtl & DMACTL_RUN) {
1179 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); 1178 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN);
1180 } 1179 }
1181} 1180}
@@ -1202,12 +1201,12 @@ BYTE byData;
1202BYTE byOrgDMACtl; 1201BYTE byOrgDMACtl;
1203 1202
1204 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byOrgDMACtl); 1203 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byOrgDMACtl);
1205 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1204 if (byOrgDMACtl & DMACTL_RUN) {
1206 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL+2, DMACTL_RUN); 1205 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL+2, DMACTL_RUN);
1207 } 1206 }
1208 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1207 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1209 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byData); 1208 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byData);
1210 if (BITbIsAllBitsOff(byData, DMACTL_RUN)) 1209 if (!(byData & DMACTL_RUN))
1211 break; 1210 break;
1212 } 1211 }
1213 if (ww == W_MAX_TIMEOUT) { 1212 if (ww == W_MAX_TIMEOUT) {
@@ -1215,7 +1214,7 @@ BYTE byOrgDMACtl;
1215 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x26)\n"); 1214 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x26)\n");
1216 } 1215 }
1217 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMAPTR, dwCurrDescAddr); 1216 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMAPTR, dwCurrDescAddr);
1218 if (BITbIsAllBitsOn(byOrgDMACtl, DMACTL_RUN)) { 1217 if (byOrgDMACtl & DMACTL_RUN) {
1219 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); 1218 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN);
1220 } 1219 }
1221} 1220}
@@ -1257,7 +1256,7 @@ UINT uu,ii;
1257 for (uu = 0; uu < uDelay; uu++) { 1256 for (uu = 0; uu < uDelay; uu++) {
1258 VNSvInPortB(dwIoBase + MAC_REG_TMCTL0, &byValue); 1257 VNSvInPortB(dwIoBase + MAC_REG_TMCTL0, &byValue);
1259 if ((byValue == 0) || 1258 if ((byValue == 0) ||
1260 (BITbIsAllBitsOn(byValue, TMCTL_TSUSP))) { 1259 (byValue & TMCTL_TSUSP)) {
1261 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0); 1260 VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0);
1262 return; 1261 return;
1263 } 1262 }
@@ -1329,14 +1328,14 @@ UINT ww = 0;
1329 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0+2, DMACTL_RUN); 1328 VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0+2, DMACTL_RUN);
1330 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1329 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1331 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byData); 1330 VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byData);
1332 if (BITbIsAllBitsOff(byData, DMACTL_RUN)) 1331 if ( !(byData & DMACTL_RUN))
1333 break; 1332 break;
1334 } 1333 }
1335 } else if (idx == TYPE_AC0DMA) { 1334 } else if (idx == TYPE_AC0DMA) {
1336 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL+2, DMACTL_RUN); 1335 VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL+2, DMACTL_RUN);
1337 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1336 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1338 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byData); 1337 VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byData);
1339 if (BITbIsAllBitsOff(byData, DMACTL_RUN)) 1338 if ( !(byData & DMACTL_RUN))
1340 break; 1339 break;
1341 } 1340 }
1342 } 1341 }
@@ -1354,14 +1353,14 @@ void MACvClearBusSusInd (DWORD_PTR dwIoBase)
1354 UINT ww; 1353 UINT ww;
1355 // check if BcnSusInd enabled 1354 // check if BcnSusInd enabled
1356 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); 1355 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);
1357 if(BITbIsBitOff(dwOrgValue, EnCFG_BcnSusInd)) 1356 if( !(dwOrgValue & EnCFG_BcnSusInd))
1358 return; 1357 return;
1359 //Set BcnSusClr 1358 //Set BcnSusClr
1360 dwOrgValue = dwOrgValue | EnCFG_BcnSusClr; 1359 dwOrgValue = dwOrgValue | EnCFG_BcnSusClr;
1361 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); 1360 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);
1362 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1361 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1363 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); 1362 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);
1364 if(BITbIsBitOff(dwOrgValue, EnCFG_BcnSusInd)) 1363 if( !(dwOrgValue & EnCFG_BcnSusInd))
1365 break; 1364 break;
1366 } 1365 }
1367 if (ww == W_MAX_TIMEOUT) { 1366 if (ww == W_MAX_TIMEOUT) {
@@ -1383,7 +1382,7 @@ void MACvEnableBusSusEn (DWORD_PTR dwIoBase)
1383 VNSvOutPortB(dwIoBase + MAC_REG_ENCFG, byOrgValue); 1382 VNSvOutPortB(dwIoBase + MAC_REG_ENCFG, byOrgValue);
1384 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1383 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1385 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); 1384 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);
1386 if(BITbIsBitOn(dwOrgValue, EnCFG_BcnSusInd)) 1385 if(dwOrgValue & EnCFG_BcnSusInd)
1387 break; 1386 break;
1388 } 1387 }
1389 if (ww == W_MAX_TIMEOUT) { 1388 if (ww == W_MAX_TIMEOUT) {
@@ -1406,7 +1405,7 @@ BOOL MACbFlushSYNCFifo (DWORD_PTR dwIoBase)
1406 // Check if SyncFlushOK 1405 // Check if SyncFlushOK
1407 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1406 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1408 VNSvInPortB(dwIoBase + MAC_REG_MACCR , &byOrgValue); 1407 VNSvInPortB(dwIoBase + MAC_REG_MACCR , &byOrgValue);
1409 if(BITbIsBitOn(byOrgValue, MACCR_SYNCFLUSHOK)) 1408 if(byOrgValue & MACCR_SYNCFLUSHOK)
1410 break; 1409 break;
1411 } 1410 }
1412 if (ww == W_MAX_TIMEOUT) { 1411 if (ww == W_MAX_TIMEOUT) {
@@ -1430,7 +1429,7 @@ BOOL MACbPSWakeup (DWORD_PTR dwIoBase)
1430 // Check if SyncFlushOK 1429 // Check if SyncFlushOK
1431 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 1430 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1432 VNSvInPortB(dwIoBase + MAC_REG_PSCTL , &byOrgValue); 1431 VNSvInPortB(dwIoBase + MAC_REG_PSCTL , &byOrgValue);
1433 if(BITbIsBitOn(byOrgValue, PSCTL_WAKEDONE)) 1432 if(byOrgValue & PSCTL_WAKEDONE)
1434 break; 1433 break;
1435 } 1434 }
1436 if (ww == W_MAX_TIMEOUT) { 1435 if (ww == W_MAX_TIMEOUT) {