diff options
Diffstat (limited to 'drivers/staging/vme/bridges/vme_ca91cx42.c')
-rw-r--r-- | drivers/staging/vme/bridges/vme_ca91cx42.c | 235 |
1 files changed, 118 insertions, 117 deletions
diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c index 4d745623211..42de83e6f1d 100644 --- a/drivers/staging/vme/bridges/vme_ca91cx42.c +++ b/drivers/staging/vme/bridges/vme_ca91cx42.c | |||
@@ -44,7 +44,7 @@ static int geoid; | |||
44 | 44 | ||
45 | static char driver_name[] = "vme_ca91cx42"; | 45 | static char driver_name[] = "vme_ca91cx42"; |
46 | 46 | ||
47 | static const struct pci_device_id ca91cx42_ids[] = { | 47 | static DEFINE_PCI_DEVICE_TABLE(ca91cx42_ids) = { |
48 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) }, | 48 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) }, |
49 | { }, | 49 | { }, |
50 | }; | 50 | }; |
@@ -58,7 +58,7 @@ static struct pci_driver ca91cx42_driver = { | |||
58 | 58 | ||
59 | static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) | 59 | static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) |
60 | { | 60 | { |
61 | wake_up(&(bridge->dma_queue)); | 61 | wake_up(&bridge->dma_queue); |
62 | 62 | ||
63 | return CA91CX42_LINT_DMA; | 63 | return CA91CX42_LINT_DMA; |
64 | } | 64 | } |
@@ -82,14 +82,14 @@ static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) | |||
82 | /* XXX This needs to be split into 4 queues */ | 82 | /* XXX This needs to be split into 4 queues */ |
83 | static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) | 83 | static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) |
84 | { | 84 | { |
85 | wake_up(&(bridge->mbox_queue)); | 85 | wake_up(&bridge->mbox_queue); |
86 | 86 | ||
87 | return CA91CX42_LINT_MBOX; | 87 | return CA91CX42_LINT_MBOX; |
88 | } | 88 | } |
89 | 89 | ||
90 | static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) | 90 | static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) |
91 | { | 91 | { |
92 | wake_up(&(bridge->iack_queue)); | 92 | wake_up(&bridge->iack_queue); |
93 | 93 | ||
94 | return CA91CX42_LINT_SW_IACK; | 94 | return CA91CX42_LINT_SW_IACK; |
95 | } | 95 | } |
@@ -207,9 +207,9 @@ static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge) | |||
207 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); | 207 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); |
208 | 208 | ||
209 | /* Initialise list for VME bus errors */ | 209 | /* Initialise list for VME bus errors */ |
210 | INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors)); | 210 | INIT_LIST_HEAD(&ca91cx42_bridge->vme_errors); |
211 | 211 | ||
212 | mutex_init(&(ca91cx42_bridge->irq_mtx)); | 212 | mutex_init(&ca91cx42_bridge->irq_mtx); |
213 | 213 | ||
214 | /* Disable interrupts from PCI to VME */ | 214 | /* Disable interrupts from PCI to VME */ |
215 | iowrite32(0, bridge->base + VINT_EN); | 215 | iowrite32(0, bridge->base + VINT_EN); |
@@ -259,8 +259,8 @@ static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, | |||
259 | /* | 259 | /* |
260 | * Set up an VME interrupt | 260 | * Set up an VME interrupt |
261 | */ | 261 | */ |
262 | void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state, | 262 | static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, |
263 | int sync) | 263 | int state, int sync) |
264 | 264 | ||
265 | { | 265 | { |
266 | struct pci_dev *pdev; | 266 | struct pci_dev *pdev; |
@@ -287,7 +287,7 @@ void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state, | |||
287 | } | 287 | } |
288 | } | 288 | } |
289 | 289 | ||
290 | int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, | 290 | static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, |
291 | int statid) | 291 | int statid) |
292 | { | 292 | { |
293 | u32 tmp; | 293 | u32 tmp; |
@@ -299,7 +299,7 @@ int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, | |||
299 | if (statid & 1) | 299 | if (statid & 1) |
300 | return -EINVAL; | 300 | return -EINVAL; |
301 | 301 | ||
302 | mutex_lock(&(bridge->vme_int)); | 302 | mutex_lock(&bridge->vme_int); |
303 | 303 | ||
304 | tmp = ioread32(bridge->base + VINT_EN); | 304 | tmp = ioread32(bridge->base + VINT_EN); |
305 | 305 | ||
@@ -318,12 +318,12 @@ int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, | |||
318 | tmp = tmp & ~(1 << (level + 24)); | 318 | tmp = tmp & ~(1 << (level + 24)); |
319 | iowrite32(tmp, bridge->base + VINT_EN); | 319 | iowrite32(tmp, bridge->base + VINT_EN); |
320 | 320 | ||
321 | mutex_unlock(&(bridge->vme_int)); | 321 | mutex_unlock(&bridge->vme_int); |
322 | 322 | ||
323 | return 0; | 323 | return 0; |
324 | } | 324 | } |
325 | 325 | ||
326 | int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, | 326 | static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, |
327 | unsigned long long vme_base, unsigned long long size, | 327 | unsigned long long vme_base, unsigned long long size, |
328 | dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle) | 328 | dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle) |
329 | { | 329 | { |
@@ -429,7 +429,7 @@ int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, | |||
429 | return 0; | 429 | return 0; |
430 | } | 430 | } |
431 | 431 | ||
432 | int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, | 432 | static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, |
433 | unsigned long long *vme_base, unsigned long long *size, | 433 | unsigned long long *vme_base, unsigned long long *size, |
434 | dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle) | 434 | dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle) |
435 | { | 435 | { |
@@ -518,8 +518,8 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |||
518 | image->kern_base = NULL; | 518 | image->kern_base = NULL; |
519 | if (image->bus_resource.name != NULL) | 519 | if (image->bus_resource.name != NULL) |
520 | kfree(image->bus_resource.name); | 520 | kfree(image->bus_resource.name); |
521 | release_resource(&(image->bus_resource)); | 521 | release_resource(&image->bus_resource); |
522 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | 522 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
523 | } | 523 | } |
524 | 524 | ||
525 | if (image->bus_resource.name == NULL) { | 525 | if (image->bus_resource.name == NULL) { |
@@ -540,7 +540,7 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |||
540 | image->bus_resource.flags = IORESOURCE_MEM; | 540 | image->bus_resource.flags = IORESOURCE_MEM; |
541 | 541 | ||
542 | retval = pci_bus_alloc_resource(pdev->bus, | 542 | retval = pci_bus_alloc_resource(pdev->bus, |
543 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, | 543 | &image->bus_resource, size, size, PCIBIOS_MIN_MEM, |
544 | 0, NULL, NULL); | 544 | 0, NULL, NULL); |
545 | if (retval) { | 545 | if (retval) { |
546 | dev_err(ca91cx42_bridge->parent, "Failed to allocate mem " | 546 | dev_err(ca91cx42_bridge->parent, "Failed to allocate mem " |
@@ -563,10 +563,10 @@ static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |||
563 | iounmap(image->kern_base); | 563 | iounmap(image->kern_base); |
564 | image->kern_base = NULL; | 564 | image->kern_base = NULL; |
565 | err_remap: | 565 | err_remap: |
566 | release_resource(&(image->bus_resource)); | 566 | release_resource(&image->bus_resource); |
567 | err_resource: | 567 | err_resource: |
568 | kfree(image->bus_resource.name); | 568 | kfree(image->bus_resource.name); |
569 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | 569 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
570 | err_name: | 570 | err_name: |
571 | return retval; | 571 | return retval; |
572 | } | 572 | } |
@@ -578,13 +578,13 @@ static void ca91cx42_free_resource(struct vme_master_resource *image) | |||
578 | { | 578 | { |
579 | iounmap(image->kern_base); | 579 | iounmap(image->kern_base); |
580 | image->kern_base = NULL; | 580 | image->kern_base = NULL; |
581 | release_resource(&(image->bus_resource)); | 581 | release_resource(&image->bus_resource); |
582 | kfree(image->bus_resource.name); | 582 | kfree(image->bus_resource.name); |
583 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | 583 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
584 | } | 584 | } |
585 | 585 | ||
586 | 586 | ||
587 | int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | 587 | static int ca91cx42_master_set(struct vme_master_resource *image, int enabled, |
588 | unsigned long long vme_base, unsigned long long size, | 588 | unsigned long long vme_base, unsigned long long size, |
589 | vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) | 589 | vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) |
590 | { | 590 | { |
@@ -620,7 +620,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
620 | goto err_window; | 620 | goto err_window; |
621 | } | 621 | } |
622 | 622 | ||
623 | spin_lock(&(image->lock)); | 623 | spin_lock(&image->lock); |
624 | 624 | ||
625 | /* | 625 | /* |
626 | * Let's allocate the resource here rather than further up the stack as | 626 | * Let's allocate the resource here rather than further up the stack as |
@@ -628,7 +628,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
628 | */ | 628 | */ |
629 | retval = ca91cx42_alloc_resource(image, size); | 629 | retval = ca91cx42_alloc_resource(image, size); |
630 | if (retval) { | 630 | if (retval) { |
631 | spin_unlock(&(image->lock)); | 631 | spin_unlock(&image->lock); |
632 | dev_err(ca91cx42_bridge->parent, "Unable to allocate memory " | 632 | dev_err(ca91cx42_bridge->parent, "Unable to allocate memory " |
633 | "for resource name\n"); | 633 | "for resource name\n"); |
634 | retval = -ENOMEM; | 634 | retval = -ENOMEM; |
@@ -672,7 +672,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
672 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D64; | 672 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D64; |
673 | break; | 673 | break; |
674 | default: | 674 | default: |
675 | spin_unlock(&(image->lock)); | 675 | spin_unlock(&image->lock); |
676 | dev_err(ca91cx42_bridge->parent, "Invalid data width\n"); | 676 | dev_err(ca91cx42_bridge->parent, "Invalid data width\n"); |
677 | retval = -EINVAL; | 677 | retval = -EINVAL; |
678 | goto err_dwidth; | 678 | goto err_dwidth; |
@@ -704,7 +704,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
704 | case VME_USER3: | 704 | case VME_USER3: |
705 | case VME_USER4: | 705 | case VME_USER4: |
706 | default: | 706 | default: |
707 | spin_unlock(&(image->lock)); | 707 | spin_unlock(&image->lock); |
708 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); | 708 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); |
709 | retval = -EINVAL; | 709 | retval = -EINVAL; |
710 | goto err_aspace; | 710 | goto err_aspace; |
@@ -730,7 +730,7 @@ int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |||
730 | 730 | ||
731 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); | 731 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
732 | 732 | ||
733 | spin_unlock(&(image->lock)); | 733 | spin_unlock(&image->lock); |
734 | return 0; | 734 | return 0; |
735 | 735 | ||
736 | err_aspace: | 736 | err_aspace: |
@@ -741,8 +741,8 @@ err_window: | |||
741 | return retval; | 741 | return retval; |
742 | } | 742 | } |
743 | 743 | ||
744 | int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, | 744 | static int __ca91cx42_master_get(struct vme_master_resource *image, |
745 | unsigned long long *vme_base, unsigned long long *size, | 745 | int *enabled, unsigned long long *vme_base, unsigned long long *size, |
746 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) | 746 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) |
747 | { | 747 | { |
748 | unsigned int i, ctl; | 748 | unsigned int i, ctl; |
@@ -828,24 +828,24 @@ int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, | |||
828 | return 0; | 828 | return 0; |
829 | } | 829 | } |
830 | 830 | ||
831 | int ca91cx42_master_get(struct vme_master_resource *image, int *enabled, | 831 | static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled, |
832 | unsigned long long *vme_base, unsigned long long *size, | 832 | unsigned long long *vme_base, unsigned long long *size, |
833 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) | 833 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) |
834 | { | 834 | { |
835 | int retval; | 835 | int retval; |
836 | 836 | ||
837 | spin_lock(&(image->lock)); | 837 | spin_lock(&image->lock); |
838 | 838 | ||
839 | retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace, | 839 | retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace, |
840 | cycle, dwidth); | 840 | cycle, dwidth); |
841 | 841 | ||
842 | spin_unlock(&(image->lock)); | 842 | spin_unlock(&image->lock); |
843 | 843 | ||
844 | return retval; | 844 | return retval; |
845 | } | 845 | } |
846 | 846 | ||
847 | ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf, | 847 | static ssize_t ca91cx42_master_read(struct vme_master_resource *image, |
848 | size_t count, loff_t offset) | 848 | void *buf, size_t count, loff_t offset) |
849 | { | 849 | { |
850 | ssize_t retval; | 850 | ssize_t retval; |
851 | void *addr = image->kern_base + offset; | 851 | void *addr = image->kern_base + offset; |
@@ -855,7 +855,7 @@ ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf, | |||
855 | if (count == 0) | 855 | if (count == 0) |
856 | return 0; | 856 | return 0; |
857 | 857 | ||
858 | spin_lock(&(image->lock)); | 858 | spin_lock(&image->lock); |
859 | 859 | ||
860 | /* The following code handles VME address alignment problem | 860 | /* The following code handles VME address alignment problem |
861 | * in order to assure the maximal data width cycle. | 861 | * in order to assure the maximal data width cycle. |
@@ -899,13 +899,13 @@ ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf, | |||
899 | } | 899 | } |
900 | out: | 900 | out: |
901 | retval = count; | 901 | retval = count; |
902 | spin_unlock(&(image->lock)); | 902 | spin_unlock(&image->lock); |
903 | 903 | ||
904 | return retval; | 904 | return retval; |
905 | } | 905 | } |
906 | 906 | ||
907 | ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, | 907 | static ssize_t ca91cx42_master_write(struct vme_master_resource *image, |
908 | size_t count, loff_t offset) | 908 | void *buf, size_t count, loff_t offset) |
909 | { | 909 | { |
910 | ssize_t retval; | 910 | ssize_t retval; |
911 | void *addr = image->kern_base + offset; | 911 | void *addr = image->kern_base + offset; |
@@ -915,7 +915,7 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, | |||
915 | if (count == 0) | 915 | if (count == 0) |
916 | return 0; | 916 | return 0; |
917 | 917 | ||
918 | spin_lock(&(image->lock)); | 918 | spin_lock(&image->lock); |
919 | 919 | ||
920 | /* Here we apply for the same strategy we do in master_read | 920 | /* Here we apply for the same strategy we do in master_read |
921 | * function in order to assure D16 cycle when required. | 921 | * function in order to assure D16 cycle when required. |
@@ -954,11 +954,12 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, | |||
954 | out: | 954 | out: |
955 | retval = count; | 955 | retval = count; |
956 | 956 | ||
957 | spin_unlock(&(image->lock)); | 957 | spin_unlock(&image->lock); |
958 | |||
958 | return retval; | 959 | return retval; |
959 | } | 960 | } |
960 | 961 | ||
961 | unsigned int ca91cx42_master_rmw(struct vme_master_resource *image, | 962 | static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image, |
962 | unsigned int mask, unsigned int compare, unsigned int swap, | 963 | unsigned int mask, unsigned int compare, unsigned int swap, |
963 | loff_t offset) | 964 | loff_t offset) |
964 | { | 965 | { |
@@ -974,10 +975,10 @@ unsigned int ca91cx42_master_rmw(struct vme_master_resource *image, | |||
974 | i = image->number; | 975 | i = image->number; |
975 | 976 | ||
976 | /* Locking as we can only do one of these at a time */ | 977 | /* Locking as we can only do one of these at a time */ |
977 | mutex_lock(&(bridge->vme_rmw)); | 978 | mutex_lock(&bridge->vme_rmw); |
978 | 979 | ||
979 | /* Lock image */ | 980 | /* Lock image */ |
980 | spin_lock(&(image->lock)); | 981 | spin_lock(&image->lock); |
981 | 982 | ||
982 | pci_addr = (u32)image->kern_base + offset; | 983 | pci_addr = (u32)image->kern_base + offset; |
983 | 984 | ||
@@ -1007,15 +1008,15 @@ unsigned int ca91cx42_master_rmw(struct vme_master_resource *image, | |||
1007 | iowrite32(0, bridge->base + SCYC_CTL); | 1008 | iowrite32(0, bridge->base + SCYC_CTL); |
1008 | 1009 | ||
1009 | out: | 1010 | out: |
1010 | spin_unlock(&(image->lock)); | 1011 | spin_unlock(&image->lock); |
1011 | 1012 | ||
1012 | mutex_unlock(&(bridge->vme_rmw)); | 1013 | mutex_unlock(&bridge->vme_rmw); |
1013 | 1014 | ||
1014 | return result; | 1015 | return result; |
1015 | } | 1016 | } |
1016 | 1017 | ||
1017 | int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | 1018 | static int ca91cx42_dma_list_add(struct vme_dma_list *list, |
1018 | struct vme_dma_attr *dest, size_t count) | 1019 | struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count) |
1019 | { | 1020 | { |
1020 | struct ca91cx42_dma_entry *entry, *prev; | 1021 | struct ca91cx42_dma_entry *entry, *prev; |
1021 | struct vme_dma_pci *pci_attr; | 1022 | struct vme_dma_pci *pci_attr; |
@@ -1036,14 +1037,14 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
1036 | } | 1037 | } |
1037 | 1038 | ||
1038 | /* Test descriptor alignment */ | 1039 | /* Test descriptor alignment */ |
1039 | if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) { | 1040 | if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) { |
1040 | dev_err(dev, "Descriptor not aligned to 16 byte boundary as " | 1041 | dev_err(dev, "Descriptor not aligned to 16 byte boundary as " |
1041 | "required: %p\n", &(entry->descriptor)); | 1042 | "required: %p\n", &entry->descriptor); |
1042 | retval = -EINVAL; | 1043 | retval = -EINVAL; |
1043 | goto err_align; | 1044 | goto err_align; |
1044 | } | 1045 | } |
1045 | 1046 | ||
1046 | memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor)); | 1047 | memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor)); |
1047 | 1048 | ||
1048 | if (dest->type == VME_DMA_VME) { | 1049 | if (dest->type == VME_DMA_VME) { |
1049 | entry->descriptor.dctl |= CA91CX42_DCTL_L2V; | 1050 | entry->descriptor.dctl |= CA91CX42_DCTL_L2V; |
@@ -1138,14 +1139,14 @@ int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, | |||
1138 | entry->descriptor.dcpp = CA91CX42_DCPP_NULL; | 1139 | entry->descriptor.dcpp = CA91CX42_DCPP_NULL; |
1139 | 1140 | ||
1140 | /* Add to list */ | 1141 | /* Add to list */ |
1141 | list_add_tail(&(entry->list), &(list->entries)); | 1142 | list_add_tail(&entry->list, &list->entries); |
1142 | 1143 | ||
1143 | /* Fill out previous descriptors "Next Address" */ | 1144 | /* Fill out previous descriptors "Next Address" */ |
1144 | if (entry->list.prev != &(list->entries)) { | 1145 | if (entry->list.prev != &list->entries) { |
1145 | prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry, | 1146 | prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry, |
1146 | list); | 1147 | list); |
1147 | /* We need the bus address for the pointer */ | 1148 | /* We need the bus address for the pointer */ |
1148 | desc_ptr = virt_to_bus(&(entry->descriptor)); | 1149 | desc_ptr = virt_to_bus(&entry->descriptor); |
1149 | prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M; | 1150 | prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M; |
1150 | } | 1151 | } |
1151 | 1152 | ||
@@ -1175,7 +1176,7 @@ static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge) | |||
1175 | return 1; | 1176 | return 1; |
1176 | } | 1177 | } |
1177 | 1178 | ||
1178 | int ca91cx42_dma_list_exec(struct vme_dma_list *list) | 1179 | static int ca91cx42_dma_list_exec(struct vme_dma_list *list) |
1179 | { | 1180 | { |
1180 | struct vme_dma_resource *ctrlr; | 1181 | struct vme_dma_resource *ctrlr; |
1181 | struct ca91cx42_dma_entry *entry; | 1182 | struct ca91cx42_dma_entry *entry; |
@@ -1190,28 +1191,28 @@ int ca91cx42_dma_list_exec(struct vme_dma_list *list) | |||
1190 | bridge = ctrlr->parent->driver_priv; | 1191 | bridge = ctrlr->parent->driver_priv; |
1191 | dev = ctrlr->parent->parent; | 1192 | dev = ctrlr->parent->parent; |
1192 | 1193 | ||
1193 | mutex_lock(&(ctrlr->mtx)); | 1194 | mutex_lock(&ctrlr->mtx); |
1194 | 1195 | ||
1195 | if (!(list_empty(&(ctrlr->running)))) { | 1196 | if (!(list_empty(&ctrlr->running))) { |
1196 | /* | 1197 | /* |
1197 | * XXX We have an active DMA transfer and currently haven't | 1198 | * XXX We have an active DMA transfer and currently haven't |
1198 | * sorted out the mechanism for "pending" DMA transfers. | 1199 | * sorted out the mechanism for "pending" DMA transfers. |
1199 | * Return busy. | 1200 | * Return busy. |
1200 | */ | 1201 | */ |
1201 | /* Need to add to pending here */ | 1202 | /* Need to add to pending here */ |
1202 | mutex_unlock(&(ctrlr->mtx)); | 1203 | mutex_unlock(&ctrlr->mtx); |
1203 | return -EBUSY; | 1204 | return -EBUSY; |
1204 | } else { | 1205 | } else { |
1205 | list_add(&(list->list), &(ctrlr->running)); | 1206 | list_add(&list->list, &ctrlr->running); |
1206 | } | 1207 | } |
1207 | 1208 | ||
1208 | /* Get first bus address and write into registers */ | 1209 | /* Get first bus address and write into registers */ |
1209 | entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry, | 1210 | entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry, |
1210 | list); | 1211 | list); |
1211 | 1212 | ||
1212 | bus_addr = virt_to_bus(&(entry->descriptor)); | 1213 | bus_addr = virt_to_bus(&entry->descriptor); |
1213 | 1214 | ||
1214 | mutex_unlock(&(ctrlr->mtx)); | 1215 | mutex_unlock(&ctrlr->mtx); |
1215 | 1216 | ||
1216 | iowrite32(0, bridge->base + DTBC); | 1217 | iowrite32(0, bridge->base + DTBC); |
1217 | iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); | 1218 | iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); |
@@ -1249,21 +1250,21 @@ int ca91cx42_dma_list_exec(struct vme_dma_list *list) | |||
1249 | } | 1250 | } |
1250 | 1251 | ||
1251 | /* Remove list from running list */ | 1252 | /* Remove list from running list */ |
1252 | mutex_lock(&(ctrlr->mtx)); | 1253 | mutex_lock(&ctrlr->mtx); |
1253 | list_del(&(list->list)); | 1254 | list_del(&list->list); |
1254 | mutex_unlock(&(ctrlr->mtx)); | 1255 | mutex_unlock(&ctrlr->mtx); |
1255 | 1256 | ||
1256 | return retval; | 1257 | return retval; |
1257 | 1258 | ||
1258 | } | 1259 | } |
1259 | 1260 | ||
1260 | int ca91cx42_dma_list_empty(struct vme_dma_list *list) | 1261 | static int ca91cx42_dma_list_empty(struct vme_dma_list *list) |
1261 | { | 1262 | { |
1262 | struct list_head *pos, *temp; | 1263 | struct list_head *pos, *temp; |
1263 | struct ca91cx42_dma_entry *entry; | 1264 | struct ca91cx42_dma_entry *entry; |
1264 | 1265 | ||
1265 | /* detach and free each entry */ | 1266 | /* detach and free each entry */ |
1266 | list_for_each_safe(pos, temp, &(list->entries)) { | 1267 | list_for_each_safe(pos, temp, &list->entries) { |
1267 | list_del(pos); | 1268 | list_del(pos); |
1268 | entry = list_entry(pos, struct ca91cx42_dma_entry, list); | 1269 | entry = list_entry(pos, struct ca91cx42_dma_entry, list); |
1269 | kfree(entry); | 1270 | kfree(entry); |
@@ -1279,8 +1280,8 @@ int ca91cx42_dma_list_empty(struct vme_dma_list *list) | |||
1279 | * This does not enable the LM monitor - that should be done when the first | 1280 | * This does not enable the LM monitor - that should be done when the first |
1280 | * callback is attached and disabled when the last callback is removed. | 1281 | * callback is attached and disabled when the last callback is removed. |
1281 | */ | 1282 | */ |
1282 | int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | 1283 | static int ca91cx42_lm_set(struct vme_lm_resource *lm, |
1283 | vme_address_t aspace, vme_cycle_t cycle) | 1284 | unsigned long long lm_base, vme_address_t aspace, vme_cycle_t cycle) |
1284 | { | 1285 | { |
1285 | u32 temp_base, lm_ctl = 0; | 1286 | u32 temp_base, lm_ctl = 0; |
1286 | int i; | 1287 | int i; |
@@ -1298,12 +1299,12 @@ int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |||
1298 | return -EINVAL; | 1299 | return -EINVAL; |
1299 | } | 1300 | } |
1300 | 1301 | ||
1301 | mutex_lock(&(lm->mtx)); | 1302 | mutex_lock(&lm->mtx); |
1302 | 1303 | ||
1303 | /* If we already have a callback attached, we can't move it! */ | 1304 | /* If we already have a callback attached, we can't move it! */ |
1304 | for (i = 0; i < lm->monitors; i++) { | 1305 | for (i = 0; i < lm->monitors; i++) { |
1305 | if (bridge->lm_callback[i] != NULL) { | 1306 | if (bridge->lm_callback[i] != NULL) { |
1306 | mutex_unlock(&(lm->mtx)); | 1307 | mutex_unlock(&lm->mtx); |
1307 | dev_err(dev, "Location monitor callback attached, " | 1308 | dev_err(dev, "Location monitor callback attached, " |
1308 | "can't reset\n"); | 1309 | "can't reset\n"); |
1309 | return -EBUSY; | 1310 | return -EBUSY; |
@@ -1321,7 +1322,7 @@ int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |||
1321 | lm_ctl |= CA91CX42_LM_CTL_AS_A32; | 1322 | lm_ctl |= CA91CX42_LM_CTL_AS_A32; |
1322 | break; | 1323 | break; |
1323 | default: | 1324 | default: |
1324 | mutex_unlock(&(lm->mtx)); | 1325 | mutex_unlock(&lm->mtx); |
1325 | dev_err(dev, "Invalid address space\n"); | 1326 | dev_err(dev, "Invalid address space\n"); |
1326 | return -EINVAL; | 1327 | return -EINVAL; |
1327 | break; | 1328 | break; |
@@ -1339,7 +1340,7 @@ int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |||
1339 | iowrite32(lm_base, bridge->base + LM_BS); | 1340 | iowrite32(lm_base, bridge->base + LM_BS); |
1340 | iowrite32(lm_ctl, bridge->base + LM_CTL); | 1341 | iowrite32(lm_ctl, bridge->base + LM_CTL); |
1341 | 1342 | ||
1342 | mutex_unlock(&(lm->mtx)); | 1343 | mutex_unlock(&lm->mtx); |
1343 | 1344 | ||
1344 | return 0; | 1345 | return 0; |
1345 | } | 1346 | } |
@@ -1347,15 +1348,15 @@ int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |||
1347 | /* Get configuration of the callback monitor and return whether it is enabled | 1348 | /* Get configuration of the callback monitor and return whether it is enabled |
1348 | * or disabled. | 1349 | * or disabled. |
1349 | */ | 1350 | */ |
1350 | int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, | 1351 | static int ca91cx42_lm_get(struct vme_lm_resource *lm, |
1351 | vme_address_t *aspace, vme_cycle_t *cycle) | 1352 | unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle) |
1352 | { | 1353 | { |
1353 | u32 lm_ctl, enabled = 0; | 1354 | u32 lm_ctl, enabled = 0; |
1354 | struct ca91cx42_driver *bridge; | 1355 | struct ca91cx42_driver *bridge; |
1355 | 1356 | ||
1356 | bridge = lm->parent->driver_priv; | 1357 | bridge = lm->parent->driver_priv; |
1357 | 1358 | ||
1358 | mutex_lock(&(lm->mtx)); | 1359 | mutex_lock(&lm->mtx); |
1359 | 1360 | ||
1360 | *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); | 1361 | *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); |
1361 | lm_ctl = ioread32(bridge->base + LM_CTL); | 1362 | lm_ctl = ioread32(bridge->base + LM_CTL); |
@@ -1380,7 +1381,7 @@ int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, | |||
1380 | if (lm_ctl & CA91CX42_LM_CTL_DATA) | 1381 | if (lm_ctl & CA91CX42_LM_CTL_DATA) |
1381 | *cycle |= VME_DATA; | 1382 | *cycle |= VME_DATA; |
1382 | 1383 | ||
1383 | mutex_unlock(&(lm->mtx)); | 1384 | mutex_unlock(&lm->mtx); |
1384 | 1385 | ||
1385 | return enabled; | 1386 | return enabled; |
1386 | } | 1387 | } |
@@ -1390,7 +1391,7 @@ int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, | |||
1390 | * | 1391 | * |
1391 | * Callback will be passed the monitor triggered. | 1392 | * Callback will be passed the monitor triggered. |
1392 | */ | 1393 | */ |
1393 | int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, | 1394 | static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, |
1394 | void (*callback)(int)) | 1395 | void (*callback)(int)) |
1395 | { | 1396 | { |
1396 | u32 lm_ctl, tmp; | 1397 | u32 lm_ctl, tmp; |
@@ -1400,19 +1401,19 @@ int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, | |||
1400 | bridge = lm->parent->driver_priv; | 1401 | bridge = lm->parent->driver_priv; |
1401 | dev = lm->parent->parent; | 1402 | dev = lm->parent->parent; |
1402 | 1403 | ||
1403 | mutex_lock(&(lm->mtx)); | 1404 | mutex_lock(&lm->mtx); |
1404 | 1405 | ||
1405 | /* Ensure that the location monitor is configured - need PGM or DATA */ | 1406 | /* Ensure that the location monitor is configured - need PGM or DATA */ |
1406 | lm_ctl = ioread32(bridge->base + LM_CTL); | 1407 | lm_ctl = ioread32(bridge->base + LM_CTL); |
1407 | if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) { | 1408 | if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) { |
1408 | mutex_unlock(&(lm->mtx)); | 1409 | mutex_unlock(&lm->mtx); |
1409 | dev_err(dev, "Location monitor not properly configured\n"); | 1410 | dev_err(dev, "Location monitor not properly configured\n"); |
1410 | return -EINVAL; | 1411 | return -EINVAL; |
1411 | } | 1412 | } |
1412 | 1413 | ||
1413 | /* Check that a callback isn't already attached */ | 1414 | /* Check that a callback isn't already attached */ |
1414 | if (bridge->lm_callback[monitor] != NULL) { | 1415 | if (bridge->lm_callback[monitor] != NULL) { |
1415 | mutex_unlock(&(lm->mtx)); | 1416 | mutex_unlock(&lm->mtx); |
1416 | dev_err(dev, "Existing callback attached\n"); | 1417 | dev_err(dev, "Existing callback attached\n"); |
1417 | return -EBUSY; | 1418 | return -EBUSY; |
1418 | } | 1419 | } |
@@ -1431,7 +1432,7 @@ int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, | |||
1431 | iowrite32(lm_ctl, bridge->base + LM_CTL); | 1432 | iowrite32(lm_ctl, bridge->base + LM_CTL); |
1432 | } | 1433 | } |
1433 | 1434 | ||
1434 | mutex_unlock(&(lm->mtx)); | 1435 | mutex_unlock(&lm->mtx); |
1435 | 1436 | ||
1436 | return 0; | 1437 | return 0; |
1437 | } | 1438 | } |
@@ -1439,14 +1440,14 @@ int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, | |||
1439 | /* | 1440 | /* |
1440 | * Detach a callback function forn a specific location monitor. | 1441 | * Detach a callback function forn a specific location monitor. |
1441 | */ | 1442 | */ |
1442 | int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor) | 1443 | static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor) |
1443 | { | 1444 | { |
1444 | u32 tmp; | 1445 | u32 tmp; |
1445 | struct ca91cx42_driver *bridge; | 1446 | struct ca91cx42_driver *bridge; |
1446 | 1447 | ||
1447 | bridge = lm->parent->driver_priv; | 1448 | bridge = lm->parent->driver_priv; |
1448 | 1449 | ||
1449 | mutex_lock(&(lm->mtx)); | 1450 | mutex_lock(&lm->mtx); |
1450 | 1451 | ||
1451 | /* Disable Location Monitor and ensure previous interrupts are clear */ | 1452 | /* Disable Location Monitor and ensure previous interrupts are clear */ |
1452 | tmp = ioread32(bridge->base + LINT_EN); | 1453 | tmp = ioread32(bridge->base + LINT_EN); |
@@ -1467,12 +1468,12 @@ int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor) | |||
1467 | iowrite32(tmp, bridge->base + LM_CTL); | 1468 | iowrite32(tmp, bridge->base + LM_CTL); |
1468 | } | 1469 | } |
1469 | 1470 | ||
1470 | mutex_unlock(&(lm->mtx)); | 1471 | mutex_unlock(&lm->mtx); |
1471 | 1472 | ||
1472 | return 0; | 1473 | return 0; |
1473 | } | 1474 | } |
1474 | 1475 | ||
1475 | int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge) | 1476 | static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge) |
1476 | { | 1477 | { |
1477 | u32 slot = 0; | 1478 | u32 slot = 0; |
1478 | struct ca91cx42_driver *bridge; | 1479 | struct ca91cx42_driver *bridge; |
@@ -1526,7 +1527,7 @@ static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge, | |||
1526 | 1527 | ||
1527 | /* Allocate mem for CR/CSR image */ | 1528 | /* Allocate mem for CR/CSR image */ |
1528 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, | 1529 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
1529 | &(bridge->crcsr_bus)); | 1530 | &bridge->crcsr_bus); |
1530 | if (bridge->crcsr_kernel == NULL) { | 1531 | if (bridge->crcsr_kernel == NULL) { |
1531 | dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " | 1532 | dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " |
1532 | "image\n"); | 1533 | "image\n"); |
@@ -1632,12 +1633,12 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1632 | } | 1633 | } |
1633 | 1634 | ||
1634 | /* Initialize wait queues & mutual exclusion flags */ | 1635 | /* Initialize wait queues & mutual exclusion flags */ |
1635 | init_waitqueue_head(&(ca91cx42_device->dma_queue)); | 1636 | init_waitqueue_head(&ca91cx42_device->dma_queue); |
1636 | init_waitqueue_head(&(ca91cx42_device->iack_queue)); | 1637 | init_waitqueue_head(&ca91cx42_device->iack_queue); |
1637 | mutex_init(&(ca91cx42_device->vme_int)); | 1638 | mutex_init(&ca91cx42_device->vme_int); |
1638 | mutex_init(&(ca91cx42_device->vme_rmw)); | 1639 | mutex_init(&ca91cx42_device->vme_rmw); |
1639 | 1640 | ||
1640 | ca91cx42_bridge->parent = &(pdev->dev); | 1641 | ca91cx42_bridge->parent = &pdev->dev; |
1641 | strcpy(ca91cx42_bridge->name, driver_name); | 1642 | strcpy(ca91cx42_bridge->name, driver_name); |
1642 | 1643 | ||
1643 | /* Setup IRQ */ | 1644 | /* Setup IRQ */ |
@@ -1648,7 +1649,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1648 | } | 1649 | } |
1649 | 1650 | ||
1650 | /* Add master windows to list */ | 1651 | /* Add master windows to list */ |
1651 | INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources)); | 1652 | INIT_LIST_HEAD(&ca91cx42_bridge->master_resources); |
1652 | for (i = 0; i < CA91C142_MAX_MASTER; i++) { | 1653 | for (i = 0; i < CA91C142_MAX_MASTER; i++) { |
1653 | master_image = kmalloc(sizeof(struct vme_master_resource), | 1654 | master_image = kmalloc(sizeof(struct vme_master_resource), |
1654 | GFP_KERNEL); | 1655 | GFP_KERNEL); |
@@ -1659,7 +1660,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1659 | goto err_master; | 1660 | goto err_master; |
1660 | } | 1661 | } |
1661 | master_image->parent = ca91cx42_bridge; | 1662 | master_image->parent = ca91cx42_bridge; |
1662 | spin_lock_init(&(master_image->lock)); | 1663 | spin_lock_init(&master_image->lock); |
1663 | master_image->locked = 0; | 1664 | master_image->locked = 0; |
1664 | master_image->number = i; | 1665 | master_image->number = i; |
1665 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | | 1666 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | |
@@ -1667,15 +1668,15 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1667 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | 1668 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
1668 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; | 1669 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; |
1669 | master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64; | 1670 | master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64; |
1670 | memset(&(master_image->bus_resource), 0, | 1671 | memset(&master_image->bus_resource, 0, |
1671 | sizeof(struct resource)); | 1672 | sizeof(struct resource)); |
1672 | master_image->kern_base = NULL; | 1673 | master_image->kern_base = NULL; |
1673 | list_add_tail(&(master_image->list), | 1674 | list_add_tail(&master_image->list, |
1674 | &(ca91cx42_bridge->master_resources)); | 1675 | &ca91cx42_bridge->master_resources); |
1675 | } | 1676 | } |
1676 | 1677 | ||
1677 | /* Add slave windows to list */ | 1678 | /* Add slave windows to list */ |
1678 | INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources)); | 1679 | INIT_LIST_HEAD(&ca91cx42_bridge->slave_resources); |
1679 | for (i = 0; i < CA91C142_MAX_SLAVE; i++) { | 1680 | for (i = 0; i < CA91C142_MAX_SLAVE; i++) { |
1680 | slave_image = kmalloc(sizeof(struct vme_slave_resource), | 1681 | slave_image = kmalloc(sizeof(struct vme_slave_resource), |
1681 | GFP_KERNEL); | 1682 | GFP_KERNEL); |
@@ -1686,7 +1687,7 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1686 | goto err_slave; | 1687 | goto err_slave; |
1687 | } | 1688 | } |
1688 | slave_image->parent = ca91cx42_bridge; | 1689 | slave_image->parent = ca91cx42_bridge; |
1689 | mutex_init(&(slave_image->mtx)); | 1690 | mutex_init(&slave_image->mtx); |
1690 | slave_image->locked = 0; | 1691 | slave_image->locked = 0; |
1691 | slave_image->number = i; | 1692 | slave_image->number = i; |
1692 | slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 | | 1693 | slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 | |
@@ -1698,12 +1699,12 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1698 | 1699 | ||
1699 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | 1700 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
1700 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; | 1701 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; |
1701 | list_add_tail(&(slave_image->list), | 1702 | list_add_tail(&slave_image->list, |
1702 | &(ca91cx42_bridge->slave_resources)); | 1703 | &ca91cx42_bridge->slave_resources); |
1703 | } | 1704 | } |
1704 | 1705 | ||
1705 | /* Add dma engines to list */ | 1706 | /* Add dma engines to list */ |
1706 | INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources)); | 1707 | INIT_LIST_HEAD(&ca91cx42_bridge->dma_resources); |
1707 | for (i = 0; i < CA91C142_MAX_DMA; i++) { | 1708 | for (i = 0; i < CA91C142_MAX_DMA; i++) { |
1708 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), | 1709 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), |
1709 | GFP_KERNEL); | 1710 | GFP_KERNEL); |
@@ -1714,19 +1715,19 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1714 | goto err_dma; | 1715 | goto err_dma; |
1715 | } | 1716 | } |
1716 | dma_ctrlr->parent = ca91cx42_bridge; | 1717 | dma_ctrlr->parent = ca91cx42_bridge; |
1717 | mutex_init(&(dma_ctrlr->mtx)); | 1718 | mutex_init(&dma_ctrlr->mtx); |
1718 | dma_ctrlr->locked = 0; | 1719 | dma_ctrlr->locked = 0; |
1719 | dma_ctrlr->number = i; | 1720 | dma_ctrlr->number = i; |
1720 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | | 1721 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | |
1721 | VME_DMA_MEM_TO_VME; | 1722 | VME_DMA_MEM_TO_VME; |
1722 | INIT_LIST_HEAD(&(dma_ctrlr->pending)); | 1723 | INIT_LIST_HEAD(&dma_ctrlr->pending); |
1723 | INIT_LIST_HEAD(&(dma_ctrlr->running)); | 1724 | INIT_LIST_HEAD(&dma_ctrlr->running); |
1724 | list_add_tail(&(dma_ctrlr->list), | 1725 | list_add_tail(&dma_ctrlr->list, |
1725 | &(ca91cx42_bridge->dma_resources)); | 1726 | &ca91cx42_bridge->dma_resources); |
1726 | } | 1727 | } |
1727 | 1728 | ||
1728 | /* Add location monitor to list */ | 1729 | /* Add location monitor to list */ |
1729 | INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources)); | 1730 | INIT_LIST_HEAD(&ca91cx42_bridge->lm_resources); |
1730 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); | 1731 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); |
1731 | if (lm == NULL) { | 1732 | if (lm == NULL) { |
1732 | dev_err(&pdev->dev, "Failed to allocate memory for " | 1733 | dev_err(&pdev->dev, "Failed to allocate memory for " |
@@ -1735,11 +1736,11 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1735 | goto err_lm; | 1736 | goto err_lm; |
1736 | } | 1737 | } |
1737 | lm->parent = ca91cx42_bridge; | 1738 | lm->parent = ca91cx42_bridge; |
1738 | mutex_init(&(lm->mtx)); | 1739 | mutex_init(&lm->mtx); |
1739 | lm->locked = 0; | 1740 | lm->locked = 0; |
1740 | lm->number = 1; | 1741 | lm->number = 1; |
1741 | lm->monitors = 4; | 1742 | lm->monitors = 4; |
1742 | list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources)); | 1743 | list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources); |
1743 | 1744 | ||
1744 | ca91cx42_bridge->slave_get = ca91cx42_slave_get; | 1745 | ca91cx42_bridge->slave_get = ca91cx42_slave_get; |
1745 | ca91cx42_bridge->slave_set = ca91cx42_slave_set; | 1746 | ca91cx42_bridge->slave_set = ca91cx42_slave_set; |
@@ -1786,28 +1787,28 @@ err_reg: | |||
1786 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); | 1787 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); |
1787 | err_lm: | 1788 | err_lm: |
1788 | /* resources are stored in link list */ | 1789 | /* resources are stored in link list */ |
1789 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { | 1790 | list_for_each(pos, &ca91cx42_bridge->lm_resources) { |
1790 | lm = list_entry(pos, struct vme_lm_resource, list); | 1791 | lm = list_entry(pos, struct vme_lm_resource, list); |
1791 | list_del(pos); | 1792 | list_del(pos); |
1792 | kfree(lm); | 1793 | kfree(lm); |
1793 | } | 1794 | } |
1794 | err_dma: | 1795 | err_dma: |
1795 | /* resources are stored in link list */ | 1796 | /* resources are stored in link list */ |
1796 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { | 1797 | list_for_each(pos, &ca91cx42_bridge->dma_resources) { |
1797 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); | 1798 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
1798 | list_del(pos); | 1799 | list_del(pos); |
1799 | kfree(dma_ctrlr); | 1800 | kfree(dma_ctrlr); |
1800 | } | 1801 | } |
1801 | err_slave: | 1802 | err_slave: |
1802 | /* resources are stored in link list */ | 1803 | /* resources are stored in link list */ |
1803 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { | 1804 | list_for_each(pos, &ca91cx42_bridge->slave_resources) { |
1804 | slave_image = list_entry(pos, struct vme_slave_resource, list); | 1805 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
1805 | list_del(pos); | 1806 | list_del(pos); |
1806 | kfree(slave_image); | 1807 | kfree(slave_image); |
1807 | } | 1808 | } |
1808 | err_master: | 1809 | err_master: |
1809 | /* resources are stored in link list */ | 1810 | /* resources are stored in link list */ |
1810 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { | 1811 | list_for_each(pos, &ca91cx42_bridge->master_resources) { |
1811 | master_image = list_entry(pos, struct vme_master_resource, | 1812 | master_image = list_entry(pos, struct vme_master_resource, |
1812 | list); | 1813 | list); |
1813 | list_del(pos); | 1814 | list_del(pos); |
@@ -1831,7 +1832,7 @@ err_struct: | |||
1831 | 1832 | ||
1832 | } | 1833 | } |
1833 | 1834 | ||
1834 | void ca91cx42_remove(struct pci_dev *pdev) | 1835 | static void ca91cx42_remove(struct pci_dev *pdev) |
1835 | { | 1836 | { |
1836 | struct list_head *pos = NULL; | 1837 | struct list_head *pos = NULL; |
1837 | struct vme_master_resource *master_image; | 1838 | struct vme_master_resource *master_image; |
@@ -1870,28 +1871,28 @@ void ca91cx42_remove(struct pci_dev *pdev) | |||
1870 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); | 1871 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); |
1871 | 1872 | ||
1872 | /* resources are stored in link list */ | 1873 | /* resources are stored in link list */ |
1873 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { | 1874 | list_for_each(pos, &ca91cx42_bridge->lm_resources) { |
1874 | lm = list_entry(pos, struct vme_lm_resource, list); | 1875 | lm = list_entry(pos, struct vme_lm_resource, list); |
1875 | list_del(pos); | 1876 | list_del(pos); |
1876 | kfree(lm); | 1877 | kfree(lm); |
1877 | } | 1878 | } |
1878 | 1879 | ||
1879 | /* resources are stored in link list */ | 1880 | /* resources are stored in link list */ |
1880 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { | 1881 | list_for_each(pos, &ca91cx42_bridge->dma_resources) { |
1881 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); | 1882 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
1882 | list_del(pos); | 1883 | list_del(pos); |
1883 | kfree(dma_ctrlr); | 1884 | kfree(dma_ctrlr); |
1884 | } | 1885 | } |
1885 | 1886 | ||
1886 | /* resources are stored in link list */ | 1887 | /* resources are stored in link list */ |
1887 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { | 1888 | list_for_each(pos, &ca91cx42_bridge->slave_resources) { |
1888 | slave_image = list_entry(pos, struct vme_slave_resource, list); | 1889 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
1889 | list_del(pos); | 1890 | list_del(pos); |
1890 | kfree(slave_image); | 1891 | kfree(slave_image); |
1891 | } | 1892 | } |
1892 | 1893 | ||
1893 | /* resources are stored in link list */ | 1894 | /* resources are stored in link list */ |
1894 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { | 1895 | list_for_each(pos, &ca91cx42_bridge->master_resources) { |
1895 | master_image = list_entry(pos, struct vme_master_resource, | 1896 | master_image = list_entry(pos, struct vme_master_resource, |
1896 | list); | 1897 | list); |
1897 | list_del(pos); | 1898 | list_del(pos); |