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path: root/drivers/staging/vme/bridges/vme_ca91cx42.c
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Diffstat (limited to 'drivers/staging/vme/bridges/vme_ca91cx42.c')
-rw-r--r--drivers/staging/vme/bridges/vme_ca91cx42.c1934
1 files changed, 1934 insertions, 0 deletions
diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c
new file mode 100644
index 00000000000..5122c13a956
--- /dev/null
+++ b/drivers/staging/vme/bridges/vme_ca91cx42.c
@@ -0,0 +1,1934 @@
1/*
2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
3 *
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * Derived from ca91c042.c by Michael Wyrick
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/module.h>
19#include <linux/mm.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/pci.h>
23#include <linux/dma-mapping.h>
24#include <linux/poll.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
32
33#include "../vme.h"
34#include "../vme_bridge.h"
35#include "vme_ca91cx42.h"
36
37static int __init ca91cx42_init(void);
38static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
39static void ca91cx42_remove(struct pci_dev *);
40static void __exit ca91cx42_exit(void);
41
42/* Module parameters */
43static int geoid;
44
45static const char driver_name[] = "vme_ca91cx42";
46
47static DEFINE_PCI_DEVICE_TABLE(ca91cx42_ids) = {
48 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
49 { },
50};
51
52static struct pci_driver ca91cx42_driver = {
53 .name = driver_name,
54 .id_table = ca91cx42_ids,
55 .probe = ca91cx42_probe,
56 .remove = ca91cx42_remove,
57};
58
59static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
60{
61 wake_up(&bridge->dma_queue);
62
63 return CA91CX42_LINT_DMA;
64}
65
66static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
67{
68 int i;
69 u32 serviced = 0;
70
71 for (i = 0; i < 4; i++) {
72 if (stat & CA91CX42_LINT_LM[i]) {
73 /* We only enable interrupts if the callback is set */
74 bridge->lm_callback[i](i);
75 serviced |= CA91CX42_LINT_LM[i];
76 }
77 }
78
79 return serviced;
80}
81
82/* XXX This needs to be split into 4 queues */
83static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
84{
85 wake_up(&bridge->mbox_queue);
86
87 return CA91CX42_LINT_MBOX;
88}
89
90static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
91{
92 wake_up(&bridge->iack_queue);
93
94 return CA91CX42_LINT_SW_IACK;
95}
96
97static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
98{
99 int val;
100 struct ca91cx42_driver *bridge;
101
102 bridge = ca91cx42_bridge->driver_priv;
103
104 val = ioread32(bridge->base + DGCS);
105
106 if (!(val & 0x00000800)) {
107 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
108 "Read Error DGCS=%08X\n", val);
109 }
110
111 return CA91CX42_LINT_VERR;
112}
113
114static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
115{
116 int val;
117 struct ca91cx42_driver *bridge;
118
119 bridge = ca91cx42_bridge->driver_priv;
120
121 val = ioread32(bridge->base + DGCS);
122
123 if (!(val & 0x00000800))
124 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
125 "Read Error DGCS=%08X\n", val);
126
127 return CA91CX42_LINT_LERR;
128}
129
130
131static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
132 int stat)
133{
134 int vec, i, serviced = 0;
135 struct ca91cx42_driver *bridge;
136
137 bridge = ca91cx42_bridge->driver_priv;
138
139
140 for (i = 7; i > 0; i--) {
141 if (stat & (1 << i)) {
142 vec = ioread32(bridge->base +
143 CA91CX42_V_STATID[i]) & 0xff;
144
145 vme_irq_handler(ca91cx42_bridge, i, vec);
146
147 serviced |= (1 << i);
148 }
149 }
150
151 return serviced;
152}
153
154static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
155{
156 u32 stat, enable, serviced = 0;
157 struct vme_bridge *ca91cx42_bridge;
158 struct ca91cx42_driver *bridge;
159
160 ca91cx42_bridge = ptr;
161
162 bridge = ca91cx42_bridge->driver_priv;
163
164 enable = ioread32(bridge->base + LINT_EN);
165 stat = ioread32(bridge->base + LINT_STAT);
166
167 /* Only look at unmasked interrupts */
168 stat &= enable;
169
170 if (unlikely(!stat))
171 return IRQ_NONE;
172
173 if (stat & CA91CX42_LINT_DMA)
174 serviced |= ca91cx42_DMA_irqhandler(bridge);
175 if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
176 CA91CX42_LINT_LM3))
177 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
178 if (stat & CA91CX42_LINT_MBOX)
179 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
180 if (stat & CA91CX42_LINT_SW_IACK)
181 serviced |= ca91cx42_IACK_irqhandler(bridge);
182 if (stat & CA91CX42_LINT_VERR)
183 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
184 if (stat & CA91CX42_LINT_LERR)
185 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
186 if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
187 CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
188 CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
189 CA91CX42_LINT_VIRQ7))
190 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
191
192 /* Clear serviced interrupts */
193 iowrite32(serviced, bridge->base + LINT_STAT);
194
195 return IRQ_HANDLED;
196}
197
198static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
199{
200 int result, tmp;
201 struct pci_dev *pdev;
202 struct ca91cx42_driver *bridge;
203
204 bridge = ca91cx42_bridge->driver_priv;
205
206 /* Need pdev */
207 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
208
209 /* Initialise list for VME bus errors */
210 INIT_LIST_HEAD(&ca91cx42_bridge->vme_errors);
211
212 mutex_init(&ca91cx42_bridge->irq_mtx);
213
214 /* Disable interrupts from PCI to VME */
215 iowrite32(0, bridge->base + VINT_EN);
216
217 /* Disable PCI interrupts */
218 iowrite32(0, bridge->base + LINT_EN);
219 /* Clear Any Pending PCI Interrupts */
220 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
221
222 result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
223 driver_name, ca91cx42_bridge);
224 if (result) {
225 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
226 pdev->irq);
227 return result;
228 }
229
230 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
231 iowrite32(0, bridge->base + LINT_MAP0);
232 iowrite32(0, bridge->base + LINT_MAP1);
233 iowrite32(0, bridge->base + LINT_MAP2);
234
235 /* Enable DMA, mailbox & LM Interrupts */
236 tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
237 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
238 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
239
240 iowrite32(tmp, bridge->base + LINT_EN);
241
242 return 0;
243}
244
245static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
246 struct pci_dev *pdev)
247{
248 /* Disable interrupts from PCI to VME */
249 iowrite32(0, bridge->base + VINT_EN);
250
251 /* Disable PCI interrupts */
252 iowrite32(0, bridge->base + LINT_EN);
253 /* Clear Any Pending PCI Interrupts */
254 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
255
256 free_irq(pdev->irq, pdev);
257}
258
259static int ca91cx42_iack_received(struct ca91cx42_driver *bridge, int level)
260{
261 u32 tmp;
262
263 tmp = ioread32(bridge->base + LINT_STAT);
264
265 if (tmp & (1 << level))
266 return 0;
267 else
268 return 1;
269}
270
271/*
272 * Set up an VME interrupt
273 */
274static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
275 int state, int sync)
276
277{
278 struct pci_dev *pdev;
279 u32 tmp;
280 struct ca91cx42_driver *bridge;
281
282 bridge = ca91cx42_bridge->driver_priv;
283
284 /* Enable IRQ level */
285 tmp = ioread32(bridge->base + LINT_EN);
286
287 if (state == 0)
288 tmp &= ~CA91CX42_LINT_VIRQ[level];
289 else
290 tmp |= CA91CX42_LINT_VIRQ[level];
291
292 iowrite32(tmp, bridge->base + LINT_EN);
293
294 if ((state == 0) && (sync != 0)) {
295 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
296 dev);
297
298 synchronize_irq(pdev->irq);
299 }
300}
301
302static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
303 int statid)
304{
305 u32 tmp;
306 struct ca91cx42_driver *bridge;
307
308 bridge = ca91cx42_bridge->driver_priv;
309
310 /* Universe can only generate even vectors */
311 if (statid & 1)
312 return -EINVAL;
313
314 mutex_lock(&bridge->vme_int);
315
316 tmp = ioread32(bridge->base + VINT_EN);
317
318 /* Set Status/ID */
319 iowrite32(statid << 24, bridge->base + STATID);
320
321 /* Assert VMEbus IRQ */
322 tmp = tmp | (1 << (level + 24));
323 iowrite32(tmp, bridge->base + VINT_EN);
324
325 /* Wait for IACK */
326 wait_event_interruptible(bridge->iack_queue,
327 ca91cx42_iack_received(bridge, level));
328
329 /* Return interrupt to low state */
330 tmp = ioread32(bridge->base + VINT_EN);
331 tmp = tmp & ~(1 << (level + 24));
332 iowrite32(tmp, bridge->base + VINT_EN);
333
334 mutex_unlock(&bridge->vme_int);
335
336 return 0;
337}
338
339static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
340 unsigned long long vme_base, unsigned long long size,
341 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
342{
343 unsigned int i, addr = 0, granularity;
344 unsigned int temp_ctl = 0;
345 unsigned int vme_bound, pci_offset;
346 struct vme_bridge *ca91cx42_bridge;
347 struct ca91cx42_driver *bridge;
348
349 ca91cx42_bridge = image->parent;
350
351 bridge = ca91cx42_bridge->driver_priv;
352
353 i = image->number;
354
355 switch (aspace) {
356 case VME_A16:
357 addr |= CA91CX42_VSI_CTL_VAS_A16;
358 break;
359 case VME_A24:
360 addr |= CA91CX42_VSI_CTL_VAS_A24;
361 break;
362 case VME_A32:
363 addr |= CA91CX42_VSI_CTL_VAS_A32;
364 break;
365 case VME_USER1:
366 addr |= CA91CX42_VSI_CTL_VAS_USER1;
367 break;
368 case VME_USER2:
369 addr |= CA91CX42_VSI_CTL_VAS_USER2;
370 break;
371 case VME_A64:
372 case VME_CRCSR:
373 case VME_USER3:
374 case VME_USER4:
375 default:
376 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
377 return -EINVAL;
378 break;
379 }
380
381 /*
382 * Bound address is a valid address for the window, adjust
383 * accordingly
384 */
385 vme_bound = vme_base + size;
386 pci_offset = pci_base - vme_base;
387
388 if ((i == 0) || (i == 4))
389 granularity = 0x1000;
390 else
391 granularity = 0x10000;
392
393 if (vme_base & (granularity - 1)) {
394 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
395 "alignment\n");
396 return -EINVAL;
397 }
398 if (vme_bound & (granularity - 1)) {
399 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
400 "alignment\n");
401 return -EINVAL;
402 }
403 if (pci_offset & (granularity - 1)) {
404 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
405 "alignment\n");
406 return -EINVAL;
407 }
408
409 /* Disable while we are mucking around */
410 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
411 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
412 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
413
414 /* Setup mapping */
415 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
416 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
417 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
418
419 /* Setup address space */
420 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
421 temp_ctl |= addr;
422
423 /* Setup cycle types */
424 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
425 if (cycle & VME_SUPER)
426 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
427 if (cycle & VME_USER)
428 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
429 if (cycle & VME_PROG)
430 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
431 if (cycle & VME_DATA)
432 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
433
434 /* Write ctl reg without enable */
435 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
436
437 if (enabled)
438 temp_ctl |= CA91CX42_VSI_CTL_EN;
439
440 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
441
442 return 0;
443}
444
445static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
446 unsigned long long *vme_base, unsigned long long *size,
447 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
448{
449 unsigned int i, granularity = 0, ctl = 0;
450 unsigned long long vme_bound, pci_offset;
451 struct ca91cx42_driver *bridge;
452
453 bridge = image->parent->driver_priv;
454
455 i = image->number;
456
457 if ((i == 0) || (i == 4))
458 granularity = 0x1000;
459 else
460 granularity = 0x10000;
461
462 /* Read Registers */
463 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
464
465 *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
466 vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
467 pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
468
469 *pci_base = (dma_addr_t)vme_base + pci_offset;
470 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
471
472 *enabled = 0;
473 *aspace = 0;
474 *cycle = 0;
475
476 if (ctl & CA91CX42_VSI_CTL_EN)
477 *enabled = 1;
478
479 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
480 *aspace = VME_A16;
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
482 *aspace = VME_A24;
483 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
484 *aspace = VME_A32;
485 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
486 *aspace = VME_USER1;
487 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
488 *aspace = VME_USER2;
489
490 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
491 *cycle |= VME_SUPER;
492 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
493 *cycle |= VME_USER;
494 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
495 *cycle |= VME_PROG;
496 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
497 *cycle |= VME_DATA;
498
499 return 0;
500}
501
502/*
503 * Allocate and map PCI Resource
504 */
505static int ca91cx42_alloc_resource(struct vme_master_resource *image,
506 unsigned long long size)
507{
508 unsigned long long existing_size;
509 int retval = 0;
510 struct pci_dev *pdev;
511 struct vme_bridge *ca91cx42_bridge;
512
513 ca91cx42_bridge = image->parent;
514
515 /* Find pci_dev container of dev */
516 if (ca91cx42_bridge->parent == NULL) {
517 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
518 return -EINVAL;
519 }
520 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
521
522 existing_size = (unsigned long long)(image->bus_resource.end -
523 image->bus_resource.start);
524
525 /* If the existing size is OK, return */
526 if (existing_size == (size - 1))
527 return 0;
528
529 if (existing_size != 0) {
530 iounmap(image->kern_base);
531 image->kern_base = NULL;
532 kfree(image->bus_resource.name);
533 release_resource(&image->bus_resource);
534 memset(&image->bus_resource, 0, sizeof(struct resource));
535 }
536
537 if (image->bus_resource.name == NULL) {
538 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
539 if (image->bus_resource.name == NULL) {
540 dev_err(ca91cx42_bridge->parent, "Unable to allocate "
541 "memory for resource name\n");
542 retval = -ENOMEM;
543 goto err_name;
544 }
545 }
546
547 sprintf((char *)image->bus_resource.name, "%s.%d",
548 ca91cx42_bridge->name, image->number);
549
550 image->bus_resource.start = 0;
551 image->bus_resource.end = (unsigned long)size;
552 image->bus_resource.flags = IORESOURCE_MEM;
553
554 retval = pci_bus_alloc_resource(pdev->bus,
555 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
556 0, NULL, NULL);
557 if (retval) {
558 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
559 "resource for window %d size 0x%lx start 0x%lx\n",
560 image->number, (unsigned long)size,
561 (unsigned long)image->bus_resource.start);
562 goto err_resource;
563 }
564
565 image->kern_base = ioremap_nocache(
566 image->bus_resource.start, size);
567 if (image->kern_base == NULL) {
568 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
569 retval = -ENOMEM;
570 goto err_remap;
571 }
572
573 return 0;
574
575err_remap:
576 release_resource(&image->bus_resource);
577err_resource:
578 kfree(image->bus_resource.name);
579 memset(&image->bus_resource, 0, sizeof(struct resource));
580err_name:
581 return retval;
582}
583
584/*
585 * Free and unmap PCI Resource
586 */
587static void ca91cx42_free_resource(struct vme_master_resource *image)
588{
589 iounmap(image->kern_base);
590 image->kern_base = NULL;
591 release_resource(&image->bus_resource);
592 kfree(image->bus_resource.name);
593 memset(&image->bus_resource, 0, sizeof(struct resource));
594}
595
596
597static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
598 unsigned long long vme_base, unsigned long long size,
599 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
600{
601 int retval = 0;
602 unsigned int i, granularity = 0;
603 unsigned int temp_ctl = 0;
604 unsigned long long pci_bound, vme_offset, pci_base;
605 struct vme_bridge *ca91cx42_bridge;
606 struct ca91cx42_driver *bridge;
607
608 ca91cx42_bridge = image->parent;
609
610 bridge = ca91cx42_bridge->driver_priv;
611
612 i = image->number;
613
614 if ((i == 0) || (i == 4))
615 granularity = 0x1000;
616 else
617 granularity = 0x10000;
618
619 /* Verify input data */
620 if (vme_base & (granularity - 1)) {
621 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
622 "alignment\n");
623 retval = -EINVAL;
624 goto err_window;
625 }
626 if (size & (granularity - 1)) {
627 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
628 "alignment\n");
629 retval = -EINVAL;
630 goto err_window;
631 }
632
633 spin_lock(&image->lock);
634
635 /*
636 * Let's allocate the resource here rather than further up the stack as
637 * it avoids pushing loads of bus dependent stuff up the stack
638 */
639 retval = ca91cx42_alloc_resource(image, size);
640 if (retval) {
641 spin_unlock(&image->lock);
642 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
643 "for resource name\n");
644 retval = -ENOMEM;
645 goto err_res;
646 }
647
648 pci_base = (unsigned long long)image->bus_resource.start;
649
650 /*
651 * Bound address is a valid address for the window, adjust
652 * according to window granularity.
653 */
654 pci_bound = pci_base + size;
655 vme_offset = vme_base - pci_base;
656
657 /* Disable while we are mucking around */
658 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
659 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
660 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
661
662 /* Setup cycle types */
663 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
664 if (cycle & VME_BLT)
665 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
666 if (cycle & VME_MBLT)
667 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
668
669 /* Setup data width */
670 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
671 switch (dwidth) {
672 case VME_D8:
673 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
674 break;
675 case VME_D16:
676 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
677 break;
678 case VME_D32:
679 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
680 break;
681 case VME_D64:
682 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
683 break;
684 default:
685 spin_unlock(&image->lock);
686 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
687 retval = -EINVAL;
688 goto err_dwidth;
689 break;
690 }
691
692 /* Setup address space */
693 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
694 switch (aspace) {
695 case VME_A16:
696 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
697 break;
698 case VME_A24:
699 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
700 break;
701 case VME_A32:
702 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
703 break;
704 case VME_CRCSR:
705 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
706 break;
707 case VME_USER1:
708 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
709 break;
710 case VME_USER2:
711 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
712 break;
713 case VME_A64:
714 case VME_USER3:
715 case VME_USER4:
716 default:
717 spin_unlock(&image->lock);
718 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
719 retval = -EINVAL;
720 goto err_aspace;
721 break;
722 }
723
724 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
725 if (cycle & VME_SUPER)
726 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
727 if (cycle & VME_PROG)
728 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
729
730 /* Setup mapping */
731 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
732 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
733 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
734
735 /* Write ctl reg without enable */
736 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
737
738 if (enabled)
739 temp_ctl |= CA91CX42_LSI_CTL_EN;
740
741 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
742
743 spin_unlock(&image->lock);
744 return 0;
745
746err_aspace:
747err_dwidth:
748 ca91cx42_free_resource(image);
749err_res:
750err_window:
751 return retval;
752}
753
754static int __ca91cx42_master_get(struct vme_master_resource *image,
755 int *enabled, unsigned long long *vme_base, unsigned long long *size,
756 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
757{
758 unsigned int i, ctl;
759 unsigned long long pci_base, pci_bound, vme_offset;
760 struct ca91cx42_driver *bridge;
761
762 bridge = image->parent->driver_priv;
763
764 i = image->number;
765
766 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
767
768 pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
769 vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
770 pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
771
772 *vme_base = pci_base + vme_offset;
773 *size = (unsigned long long)(pci_bound - pci_base);
774
775 *enabled = 0;
776 *aspace = 0;
777 *cycle = 0;
778 *dwidth = 0;
779
780 if (ctl & CA91CX42_LSI_CTL_EN)
781 *enabled = 1;
782
783 /* Setup address space */
784 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
785 case CA91CX42_LSI_CTL_VAS_A16:
786 *aspace = VME_A16;
787 break;
788 case CA91CX42_LSI_CTL_VAS_A24:
789 *aspace = VME_A24;
790 break;
791 case CA91CX42_LSI_CTL_VAS_A32:
792 *aspace = VME_A32;
793 break;
794 case CA91CX42_LSI_CTL_VAS_CRCSR:
795 *aspace = VME_CRCSR;
796 break;
797 case CA91CX42_LSI_CTL_VAS_USER1:
798 *aspace = VME_USER1;
799 break;
800 case CA91CX42_LSI_CTL_VAS_USER2:
801 *aspace = VME_USER2;
802 break;
803 }
804
805 /* XXX Not sure howto check for MBLT */
806 /* Setup cycle types */
807 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
808 *cycle |= VME_BLT;
809 else
810 *cycle |= VME_SCT;
811
812 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
813 *cycle |= VME_SUPER;
814 else
815 *cycle |= VME_USER;
816
817 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
818 *cycle = VME_PROG;
819 else
820 *cycle = VME_DATA;
821
822 /* Setup data width */
823 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
824 case CA91CX42_LSI_CTL_VDW_D8:
825 *dwidth = VME_D8;
826 break;
827 case CA91CX42_LSI_CTL_VDW_D16:
828 *dwidth = VME_D16;
829 break;
830 case CA91CX42_LSI_CTL_VDW_D32:
831 *dwidth = VME_D32;
832 break;
833 case CA91CX42_LSI_CTL_VDW_D64:
834 *dwidth = VME_D64;
835 break;
836 }
837
838 return 0;
839}
840
841static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
842 unsigned long long *vme_base, unsigned long long *size,
843 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
844{
845 int retval;
846
847 spin_lock(&image->lock);
848
849 retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
850 cycle, dwidth);
851
852 spin_unlock(&image->lock);
853
854 return retval;
855}
856
857static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
858 void *buf, size_t count, loff_t offset)
859{
860 ssize_t retval;
861 void *addr = image->kern_base + offset;
862 unsigned int done = 0;
863 unsigned int count32;
864
865 if (count == 0)
866 return 0;
867
868 spin_lock(&image->lock);
869
870 /* The following code handles VME address alignment problem
871 * in order to assure the maximal data width cycle.
872 * We cannot use memcpy_xxx directly here because it
873 * may cut data transfer in 8-bits cycles, thus making
874 * D16 cycle impossible.
875 * From the other hand, the bridge itself assures that
876 * maximal configured data cycle is used and splits it
877 * automatically for non-aligned addresses.
878 */
879 if ((int)addr & 0x1) {
880 *(u8 *)buf = ioread8(addr);
881 done += 1;
882 if (done == count)
883 goto out;
884 }
885 if ((int)addr & 0x2) {
886 if ((count - done) < 2) {
887 *(u8 *)(buf + done) = ioread8(addr + done);
888 done += 1;
889 goto out;
890 } else {
891 *(u16 *)(buf + done) = ioread16(addr + done);
892 done += 2;
893 }
894 }
895
896 count32 = (count - done) & ~0x3;
897 if (count32 > 0) {
898 memcpy_fromio(buf + done, addr + done, (unsigned int)count);
899 done += count32;
900 }
901
902 if ((count - done) & 0x2) {
903 *(u16 *)(buf + done) = ioread16(addr + done);
904 done += 2;
905 }
906 if ((count - done) & 0x1) {
907 *(u8 *)(buf + done) = ioread8(addr + done);
908 done += 1;
909 }
910out:
911 retval = count;
912 spin_unlock(&image->lock);
913
914 return retval;
915}
916
917static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
918 void *buf, size_t count, loff_t offset)
919{
920 ssize_t retval;
921 void *addr = image->kern_base + offset;
922 unsigned int done = 0;
923 unsigned int count32;
924
925 if (count == 0)
926 return 0;
927
928 spin_lock(&image->lock);
929
930 /* Here we apply for the same strategy we do in master_read
931 * function in order to assure D16 cycle when required.
932 */
933 if ((int)addr & 0x1) {
934 iowrite8(*(u8 *)buf, addr);
935 done += 1;
936 if (done == count)
937 goto out;
938 }
939 if ((int)addr & 0x2) {
940 if ((count - done) < 2) {
941 iowrite8(*(u8 *)(buf + done), addr + done);
942 done += 1;
943 goto out;
944 } else {
945 iowrite16(*(u16 *)(buf + done), addr + done);
946 done += 2;
947 }
948 }
949
950 count32 = (count - done) & ~0x3;
951 if (count32 > 0) {
952 memcpy_toio(addr + done, buf + done, count32);
953 done += count32;
954 }
955
956 if ((count - done) & 0x2) {
957 iowrite16(*(u16 *)(buf + done), addr + done);
958 done += 2;
959 }
960 if ((count - done) & 0x1) {
961 iowrite8(*(u8 *)(buf + done), addr + done);
962 done += 1;
963 }
964out:
965 retval = count;
966
967 spin_unlock(&image->lock);
968
969 return retval;
970}
971
972static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
973 unsigned int mask, unsigned int compare, unsigned int swap,
974 loff_t offset)
975{
976 u32 pci_addr, result;
977 int i;
978 struct ca91cx42_driver *bridge;
979 struct device *dev;
980
981 bridge = image->parent->driver_priv;
982 dev = image->parent->parent;
983
984 /* Find the PCI address that maps to the desired VME address */
985 i = image->number;
986
987 /* Locking as we can only do one of these at a time */
988 mutex_lock(&bridge->vme_rmw);
989
990 /* Lock image */
991 spin_lock(&image->lock);
992
993 pci_addr = (u32)image->kern_base + offset;
994
995 /* Address must be 4-byte aligned */
996 if (pci_addr & 0x3) {
997 dev_err(dev, "RMW Address not 4-byte aligned\n");
998 result = -EINVAL;
999 goto out;
1000 }
1001
1002 /* Ensure RMW Disabled whilst configuring */
1003 iowrite32(0, bridge->base + SCYC_CTL);
1004
1005 /* Configure registers */
1006 iowrite32(mask, bridge->base + SCYC_EN);
1007 iowrite32(compare, bridge->base + SCYC_CMP);
1008 iowrite32(swap, bridge->base + SCYC_SWP);
1009 iowrite32(pci_addr, bridge->base + SCYC_ADDR);
1010
1011 /* Enable RMW */
1012 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1013
1014 /* Kick process off with a read to the required address. */
1015 result = ioread32(image->kern_base + offset);
1016
1017 /* Disable RMW */
1018 iowrite32(0, bridge->base + SCYC_CTL);
1019
1020out:
1021 spin_unlock(&image->lock);
1022
1023 mutex_unlock(&bridge->vme_rmw);
1024
1025 return result;
1026}
1027
1028static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1029 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1030{
1031 struct ca91cx42_dma_entry *entry, *prev;
1032 struct vme_dma_pci *pci_attr;
1033 struct vme_dma_vme *vme_attr;
1034 dma_addr_t desc_ptr;
1035 int retval = 0;
1036 struct device *dev;
1037
1038 dev = list->parent->parent->parent;
1039
1040 /* XXX descriptor must be aligned on 64-bit boundaries */
1041 entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
1042 if (entry == NULL) {
1043 dev_err(dev, "Failed to allocate memory for dma resource "
1044 "structure\n");
1045 retval = -ENOMEM;
1046 goto err_mem;
1047 }
1048
1049 /* Test descriptor alignment */
1050 if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1051 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
1052 "required: %p\n", &entry->descriptor);
1053 retval = -EINVAL;
1054 goto err_align;
1055 }
1056
1057 memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));
1058
1059 if (dest->type == VME_DMA_VME) {
1060 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1061 vme_attr = dest->private;
1062 pci_attr = src->private;
1063 } else {
1064 vme_attr = src->private;
1065 pci_attr = dest->private;
1066 }
1067
1068 /* Check we can do fulfill required attributes */
1069 if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1070 VME_USER2)) != 0) {
1071
1072 dev_err(dev, "Unsupported cycle type\n");
1073 retval = -EINVAL;
1074 goto err_aspace;
1075 }
1076
1077 if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1078 VME_PROG | VME_DATA)) != 0) {
1079
1080 dev_err(dev, "Unsupported cycle type\n");
1081 retval = -EINVAL;
1082 goto err_cycle;
1083 }
1084
1085 /* Check to see if we can fulfill source and destination */
1086 if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1087 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1088
1089 dev_err(dev, "Cannot perform transfer with this "
1090 "source-destination combination\n");
1091 retval = -EINVAL;
1092 goto err_direct;
1093 }
1094
1095 /* Setup cycle types */
1096 if (vme_attr->cycle & VME_BLT)
1097 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1098
1099 /* Setup data width */
1100 switch (vme_attr->dwidth) {
1101 case VME_D8:
1102 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1103 break;
1104 case VME_D16:
1105 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1106 break;
1107 case VME_D32:
1108 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1109 break;
1110 case VME_D64:
1111 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1112 break;
1113 default:
1114 dev_err(dev, "Invalid data width\n");
1115 return -EINVAL;
1116 }
1117
1118 /* Setup address space */
1119 switch (vme_attr->aspace) {
1120 case VME_A16:
1121 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1122 break;
1123 case VME_A24:
1124 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1125 break;
1126 case VME_A32:
1127 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1128 break;
1129 case VME_USER1:
1130 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1131 break;
1132 case VME_USER2:
1133 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1134 break;
1135 default:
1136 dev_err(dev, "Invalid address space\n");
1137 return -EINVAL;
1138 break;
1139 }
1140
1141 if (vme_attr->cycle & VME_SUPER)
1142 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1143 if (vme_attr->cycle & VME_PROG)
1144 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1145
1146 entry->descriptor.dtbc = count;
1147 entry->descriptor.dla = pci_attr->address;
1148 entry->descriptor.dva = vme_attr->address;
1149 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1150
1151 /* Add to list */
1152 list_add_tail(&entry->list, &list->entries);
1153
1154 /* Fill out previous descriptors "Next Address" */
1155 if (entry->list.prev != &list->entries) {
1156 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1157 list);
1158 /* We need the bus address for the pointer */
1159 desc_ptr = virt_to_bus(&entry->descriptor);
1160 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1161 }
1162
1163 return 0;
1164
1165err_cycle:
1166err_aspace:
1167err_direct:
1168err_align:
1169 kfree(entry);
1170err_mem:
1171 return retval;
1172}
1173
1174static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1175{
1176 u32 tmp;
1177 struct ca91cx42_driver *bridge;
1178
1179 bridge = ca91cx42_bridge->driver_priv;
1180
1181 tmp = ioread32(bridge->base + DGCS);
1182
1183 if (tmp & CA91CX42_DGCS_ACT)
1184 return 0;
1185 else
1186 return 1;
1187}
1188
1189static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1190{
1191 struct vme_dma_resource *ctrlr;
1192 struct ca91cx42_dma_entry *entry;
1193 int retval = 0;
1194 dma_addr_t bus_addr;
1195 u32 val;
1196 struct device *dev;
1197 struct ca91cx42_driver *bridge;
1198
1199 ctrlr = list->parent;
1200
1201 bridge = ctrlr->parent->driver_priv;
1202 dev = ctrlr->parent->parent;
1203
1204 mutex_lock(&ctrlr->mtx);
1205
1206 if (!(list_empty(&ctrlr->running))) {
1207 /*
1208 * XXX We have an active DMA transfer and currently haven't
1209 * sorted out the mechanism for "pending" DMA transfers.
1210 * Return busy.
1211 */
1212 /* Need to add to pending here */
1213 mutex_unlock(&ctrlr->mtx);
1214 return -EBUSY;
1215 } else {
1216 list_add(&list->list, &ctrlr->running);
1217 }
1218
1219 /* Get first bus address and write into registers */
1220 entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1221 list);
1222
1223 bus_addr = virt_to_bus(&entry->descriptor);
1224
1225 mutex_unlock(&ctrlr->mtx);
1226
1227 iowrite32(0, bridge->base + DTBC);
1228 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1229
1230 /* Start the operation */
1231 val = ioread32(bridge->base + DGCS);
1232
1233 /* XXX Could set VMEbus On and Off Counters here */
1234 val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1235
1236 val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1237 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1238 CA91CX42_DGCS_PERR);
1239
1240 iowrite32(val, bridge->base + DGCS);
1241
1242 val |= CA91CX42_DGCS_GO;
1243
1244 iowrite32(val, bridge->base + DGCS);
1245
1246 wait_event_interruptible(bridge->dma_queue,
1247 ca91cx42_dma_busy(ctrlr->parent));
1248
1249 /*
1250 * Read status register, this register is valid until we kick off a
1251 * new transfer.
1252 */
1253 val = ioread32(bridge->base + DGCS);
1254
1255 if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1256 CA91CX42_DGCS_PERR)) {
1257
1258 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1259 val = ioread32(bridge->base + DCTL);
1260 }
1261
1262 /* Remove list from running list */
1263 mutex_lock(&ctrlr->mtx);
1264 list_del(&list->list);
1265 mutex_unlock(&ctrlr->mtx);
1266
1267 return retval;
1268
1269}
1270
1271static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1272{
1273 struct list_head *pos, *temp;
1274 struct ca91cx42_dma_entry *entry;
1275
1276 /* detach and free each entry */
1277 list_for_each_safe(pos, temp, &list->entries) {
1278 list_del(pos);
1279 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1280 kfree(entry);
1281 }
1282
1283 return 0;
1284}
1285
1286/*
1287 * All 4 location monitors reside at the same base - this is therefore a
1288 * system wide configuration.
1289 *
1290 * This does not enable the LM monitor - that should be done when the first
1291 * callback is attached and disabled when the last callback is removed.
1292 */
1293static int ca91cx42_lm_set(struct vme_lm_resource *lm,
1294 unsigned long long lm_base, vme_address_t aspace, vme_cycle_t cycle)
1295{
1296 u32 temp_base, lm_ctl = 0;
1297 int i;
1298 struct ca91cx42_driver *bridge;
1299 struct device *dev;
1300
1301 bridge = lm->parent->driver_priv;
1302 dev = lm->parent->parent;
1303
1304 /* Check the alignment of the location monitor */
1305 temp_base = (u32)lm_base;
1306 if (temp_base & 0xffff) {
1307 dev_err(dev, "Location monitor must be aligned to 64KB "
1308 "boundary");
1309 return -EINVAL;
1310 }
1311
1312 mutex_lock(&lm->mtx);
1313
1314 /* If we already have a callback attached, we can't move it! */
1315 for (i = 0; i < lm->monitors; i++) {
1316 if (bridge->lm_callback[i] != NULL) {
1317 mutex_unlock(&lm->mtx);
1318 dev_err(dev, "Location monitor callback attached, "
1319 "can't reset\n");
1320 return -EBUSY;
1321 }
1322 }
1323
1324 switch (aspace) {
1325 case VME_A16:
1326 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1327 break;
1328 case VME_A24:
1329 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1330 break;
1331 case VME_A32:
1332 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1333 break;
1334 default:
1335 mutex_unlock(&lm->mtx);
1336 dev_err(dev, "Invalid address space\n");
1337 return -EINVAL;
1338 break;
1339 }
1340
1341 if (cycle & VME_SUPER)
1342 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1343 if (cycle & VME_USER)
1344 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1345 if (cycle & VME_PROG)
1346 lm_ctl |= CA91CX42_LM_CTL_PGM;
1347 if (cycle & VME_DATA)
1348 lm_ctl |= CA91CX42_LM_CTL_DATA;
1349
1350 iowrite32(lm_base, bridge->base + LM_BS);
1351 iowrite32(lm_ctl, bridge->base + LM_CTL);
1352
1353 mutex_unlock(&lm->mtx);
1354
1355 return 0;
1356}
1357
1358/* Get configuration of the callback monitor and return whether it is enabled
1359 * or disabled.
1360 */
1361static int ca91cx42_lm_get(struct vme_lm_resource *lm,
1362 unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle)
1363{
1364 u32 lm_ctl, enabled = 0;
1365 struct ca91cx42_driver *bridge;
1366
1367 bridge = lm->parent->driver_priv;
1368
1369 mutex_lock(&lm->mtx);
1370
1371 *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1372 lm_ctl = ioread32(bridge->base + LM_CTL);
1373
1374 if (lm_ctl & CA91CX42_LM_CTL_EN)
1375 enabled = 1;
1376
1377 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1378 *aspace = VME_A16;
1379 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1380 *aspace = VME_A24;
1381 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1382 *aspace = VME_A32;
1383
1384 *cycle = 0;
1385 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1386 *cycle |= VME_SUPER;
1387 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1388 *cycle |= VME_USER;
1389 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1390 *cycle |= VME_PROG;
1391 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1392 *cycle |= VME_DATA;
1393
1394 mutex_unlock(&lm->mtx);
1395
1396 return enabled;
1397}
1398
1399/*
1400 * Attach a callback to a specific location monitor.
1401 *
1402 * Callback will be passed the monitor triggered.
1403 */
1404static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1405 void (*callback)(int))
1406{
1407 u32 lm_ctl, tmp;
1408 struct ca91cx42_driver *bridge;
1409 struct device *dev;
1410
1411 bridge = lm->parent->driver_priv;
1412 dev = lm->parent->parent;
1413
1414 mutex_lock(&lm->mtx);
1415
1416 /* Ensure that the location monitor is configured - need PGM or DATA */
1417 lm_ctl = ioread32(bridge->base + LM_CTL);
1418 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1419 mutex_unlock(&lm->mtx);
1420 dev_err(dev, "Location monitor not properly configured\n");
1421 return -EINVAL;
1422 }
1423
1424 /* Check that a callback isn't already attached */
1425 if (bridge->lm_callback[monitor] != NULL) {
1426 mutex_unlock(&lm->mtx);
1427 dev_err(dev, "Existing callback attached\n");
1428 return -EBUSY;
1429 }
1430
1431 /* Attach callback */
1432 bridge->lm_callback[monitor] = callback;
1433
1434 /* Enable Location Monitor interrupt */
1435 tmp = ioread32(bridge->base + LINT_EN);
1436 tmp |= CA91CX42_LINT_LM[monitor];
1437 iowrite32(tmp, bridge->base + LINT_EN);
1438
1439 /* Ensure that global Location Monitor Enable set */
1440 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1441 lm_ctl |= CA91CX42_LM_CTL_EN;
1442 iowrite32(lm_ctl, bridge->base + LM_CTL);
1443 }
1444
1445 mutex_unlock(&lm->mtx);
1446
1447 return 0;
1448}
1449
1450/*
1451 * Detach a callback function forn a specific location monitor.
1452 */
1453static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1454{
1455 u32 tmp;
1456 struct ca91cx42_driver *bridge;
1457
1458 bridge = lm->parent->driver_priv;
1459
1460 mutex_lock(&lm->mtx);
1461
1462 /* Disable Location Monitor and ensure previous interrupts are clear */
1463 tmp = ioread32(bridge->base + LINT_EN);
1464 tmp &= ~CA91CX42_LINT_LM[monitor];
1465 iowrite32(tmp, bridge->base + LINT_EN);
1466
1467 iowrite32(CA91CX42_LINT_LM[monitor],
1468 bridge->base + LINT_STAT);
1469
1470 /* Detach callback */
1471 bridge->lm_callback[monitor] = NULL;
1472
1473 /* If all location monitors disabled, disable global Location Monitor */
1474 if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1475 CA91CX42_LINT_LM3)) == 0) {
1476 tmp = ioread32(bridge->base + LM_CTL);
1477 tmp &= ~CA91CX42_LM_CTL_EN;
1478 iowrite32(tmp, bridge->base + LM_CTL);
1479 }
1480
1481 mutex_unlock(&lm->mtx);
1482
1483 return 0;
1484}
1485
1486static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1487{
1488 u32 slot = 0;
1489 struct ca91cx42_driver *bridge;
1490
1491 bridge = ca91cx42_bridge->driver_priv;
1492
1493 if (!geoid) {
1494 slot = ioread32(bridge->base + VCSR_BS);
1495 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1496 } else
1497 slot = geoid;
1498
1499 return (int)slot;
1500
1501}
1502
1503static int __init ca91cx42_init(void)
1504{
1505 return pci_register_driver(&ca91cx42_driver);
1506}
1507
1508/*
1509 * Configure CR/CSR space
1510 *
1511 * Access to the CR/CSR can be configured at power-up. The location of the
1512 * CR/CSR registers in the CR/CSR address space is determined by the boards
1513 * Auto-ID or Geographic address. This function ensures that the window is
1514 * enabled at an offset consistent with the boards geopgraphic address.
1515 */
1516static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1517 struct pci_dev *pdev)
1518{
1519 unsigned int crcsr_addr;
1520 int tmp, slot;
1521 struct ca91cx42_driver *bridge;
1522
1523 bridge = ca91cx42_bridge->driver_priv;
1524
1525 slot = ca91cx42_slot_get(ca91cx42_bridge);
1526
1527 /* Write CSR Base Address if slot ID is supplied as a module param */
1528 if (geoid)
1529 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1530
1531 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1532 if (slot == 0) {
1533 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1534 "CR/CSR space\n");
1535 return -EINVAL;
1536 }
1537
1538 /* Allocate mem for CR/CSR image */
1539 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1540 &bridge->crcsr_bus);
1541 if (bridge->crcsr_kernel == NULL) {
1542 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1543 "image\n");
1544 return -ENOMEM;
1545 }
1546
1547 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1548
1549 crcsr_addr = slot * (512 * 1024);
1550 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1551
1552 tmp = ioread32(bridge->base + VCSR_CTL);
1553 tmp |= CA91CX42_VCSR_CTL_EN;
1554 iowrite32(tmp, bridge->base + VCSR_CTL);
1555
1556 return 0;
1557}
1558
1559static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1560 struct pci_dev *pdev)
1561{
1562 u32 tmp;
1563 struct ca91cx42_driver *bridge;
1564
1565 bridge = ca91cx42_bridge->driver_priv;
1566
1567 /* Turn off CR/CSR space */
1568 tmp = ioread32(bridge->base + VCSR_CTL);
1569 tmp &= ~CA91CX42_VCSR_CTL_EN;
1570 iowrite32(tmp, bridge->base + VCSR_CTL);
1571
1572 /* Free image */
1573 iowrite32(0, bridge->base + VCSR_TO);
1574
1575 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1576 bridge->crcsr_bus);
1577}
1578
1579static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1580{
1581 int retval, i;
1582 u32 data;
1583 struct list_head *pos = NULL;
1584 struct vme_bridge *ca91cx42_bridge;
1585 struct ca91cx42_driver *ca91cx42_device;
1586 struct vme_master_resource *master_image;
1587 struct vme_slave_resource *slave_image;
1588 struct vme_dma_resource *dma_ctrlr;
1589 struct vme_lm_resource *lm;
1590
1591 /* We want to support more than one of each bridge so we need to
1592 * dynamically allocate the bridge structure
1593 */
1594 ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1595
1596 if (ca91cx42_bridge == NULL) {
1597 dev_err(&pdev->dev, "Failed to allocate memory for device "
1598 "structure\n");
1599 retval = -ENOMEM;
1600 goto err_struct;
1601 }
1602
1603 ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1604
1605 if (ca91cx42_device == NULL) {
1606 dev_err(&pdev->dev, "Failed to allocate memory for device "
1607 "structure\n");
1608 retval = -ENOMEM;
1609 goto err_driver;
1610 }
1611
1612 ca91cx42_bridge->driver_priv = ca91cx42_device;
1613
1614 /* Enable the device */
1615 retval = pci_enable_device(pdev);
1616 if (retval) {
1617 dev_err(&pdev->dev, "Unable to enable device\n");
1618 goto err_enable;
1619 }
1620
1621 /* Map Registers */
1622 retval = pci_request_regions(pdev, driver_name);
1623 if (retval) {
1624 dev_err(&pdev->dev, "Unable to reserve resources\n");
1625 goto err_resource;
1626 }
1627
1628 /* map registers in BAR 0 */
1629 ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1630 4096);
1631 if (!ca91cx42_device->base) {
1632 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1633 retval = -EIO;
1634 goto err_remap;
1635 }
1636
1637 /* Check to see if the mapping worked out */
1638 data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1639 if (data != PCI_VENDOR_ID_TUNDRA) {
1640 dev_err(&pdev->dev, "PCI_ID check failed\n");
1641 retval = -EIO;
1642 goto err_test;
1643 }
1644
1645 /* Initialize wait queues & mutual exclusion flags */
1646 init_waitqueue_head(&ca91cx42_device->dma_queue);
1647 init_waitqueue_head(&ca91cx42_device->iack_queue);
1648 mutex_init(&ca91cx42_device->vme_int);
1649 mutex_init(&ca91cx42_device->vme_rmw);
1650
1651 ca91cx42_bridge->parent = &pdev->dev;
1652 strcpy(ca91cx42_bridge->name, driver_name);
1653
1654 /* Setup IRQ */
1655 retval = ca91cx42_irq_init(ca91cx42_bridge);
1656 if (retval != 0) {
1657 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1658 goto err_irq;
1659 }
1660
1661 /* Add master windows to list */
1662 INIT_LIST_HEAD(&ca91cx42_bridge->master_resources);
1663 for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1664 master_image = kmalloc(sizeof(struct vme_master_resource),
1665 GFP_KERNEL);
1666 if (master_image == NULL) {
1667 dev_err(&pdev->dev, "Failed to allocate memory for "
1668 "master resource structure\n");
1669 retval = -ENOMEM;
1670 goto err_master;
1671 }
1672 master_image->parent = ca91cx42_bridge;
1673 spin_lock_init(&master_image->lock);
1674 master_image->locked = 0;
1675 master_image->number = i;
1676 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1677 VME_CRCSR | VME_USER1 | VME_USER2;
1678 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1679 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1680 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1681 memset(&master_image->bus_resource, 0,
1682 sizeof(struct resource));
1683 master_image->kern_base = NULL;
1684 list_add_tail(&master_image->list,
1685 &ca91cx42_bridge->master_resources);
1686 }
1687
1688 /* Add slave windows to list */
1689 INIT_LIST_HEAD(&ca91cx42_bridge->slave_resources);
1690 for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1691 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1692 GFP_KERNEL);
1693 if (slave_image == NULL) {
1694 dev_err(&pdev->dev, "Failed to allocate memory for "
1695 "slave resource structure\n");
1696 retval = -ENOMEM;
1697 goto err_slave;
1698 }
1699 slave_image->parent = ca91cx42_bridge;
1700 mutex_init(&slave_image->mtx);
1701 slave_image->locked = 0;
1702 slave_image->number = i;
1703 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1704 VME_USER2;
1705
1706 /* Only windows 0 and 4 support A16 */
1707 if (i == 0 || i == 4)
1708 slave_image->address_attr |= VME_A16;
1709
1710 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1711 VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1712 list_add_tail(&slave_image->list,
1713 &ca91cx42_bridge->slave_resources);
1714 }
1715
1716 /* Add dma engines to list */
1717 INIT_LIST_HEAD(&ca91cx42_bridge->dma_resources);
1718 for (i = 0; i < CA91C142_MAX_DMA; i++) {
1719 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1720 GFP_KERNEL);
1721 if (dma_ctrlr == NULL) {
1722 dev_err(&pdev->dev, "Failed to allocate memory for "
1723 "dma resource structure\n");
1724 retval = -ENOMEM;
1725 goto err_dma;
1726 }
1727 dma_ctrlr->parent = ca91cx42_bridge;
1728 mutex_init(&dma_ctrlr->mtx);
1729 dma_ctrlr->locked = 0;
1730 dma_ctrlr->number = i;
1731 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1732 VME_DMA_MEM_TO_VME;
1733 INIT_LIST_HEAD(&dma_ctrlr->pending);
1734 INIT_LIST_HEAD(&dma_ctrlr->running);
1735 list_add_tail(&dma_ctrlr->list,
1736 &ca91cx42_bridge->dma_resources);
1737 }
1738
1739 /* Add location monitor to list */
1740 INIT_LIST_HEAD(&ca91cx42_bridge->lm_resources);
1741 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1742 if (lm == NULL) {
1743 dev_err(&pdev->dev, "Failed to allocate memory for "
1744 "location monitor resource structure\n");
1745 retval = -ENOMEM;
1746 goto err_lm;
1747 }
1748 lm->parent = ca91cx42_bridge;
1749 mutex_init(&lm->mtx);
1750 lm->locked = 0;
1751 lm->number = 1;
1752 lm->monitors = 4;
1753 list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
1754
1755 ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1756 ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1757 ca91cx42_bridge->master_get = ca91cx42_master_get;
1758 ca91cx42_bridge->master_set = ca91cx42_master_set;
1759 ca91cx42_bridge->master_read = ca91cx42_master_read;
1760 ca91cx42_bridge->master_write = ca91cx42_master_write;
1761 ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1762 ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1763 ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1764 ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1765 ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1766 ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1767 ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1768 ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1769 ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1770 ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1771 ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1772
1773 data = ioread32(ca91cx42_device->base + MISC_CTL);
1774 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1775 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1776 dev_info(&pdev->dev, "Slot ID is %d\n",
1777 ca91cx42_slot_get(ca91cx42_bridge));
1778
1779 if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1780 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1781
1782 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1783 * ca91cx42_remove()
1784 */
1785 retval = vme_register_bridge(ca91cx42_bridge);
1786 if (retval != 0) {
1787 dev_err(&pdev->dev, "Chip Registration failed.\n");
1788 goto err_reg;
1789 }
1790
1791 pci_set_drvdata(pdev, ca91cx42_bridge);
1792
1793 return 0;
1794
1795err_reg:
1796 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1797err_lm:
1798 /* resources are stored in link list */
1799 list_for_each(pos, &ca91cx42_bridge->lm_resources) {
1800 lm = list_entry(pos, struct vme_lm_resource, list);
1801 list_del(pos);
1802 kfree(lm);
1803 }
1804err_dma:
1805 /* resources are stored in link list */
1806 list_for_each(pos, &ca91cx42_bridge->dma_resources) {
1807 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1808 list_del(pos);
1809 kfree(dma_ctrlr);
1810 }
1811err_slave:
1812 /* resources are stored in link list */
1813 list_for_each(pos, &ca91cx42_bridge->slave_resources) {
1814 slave_image = list_entry(pos, struct vme_slave_resource, list);
1815 list_del(pos);
1816 kfree(slave_image);
1817 }
1818err_master:
1819 /* resources are stored in link list */
1820 list_for_each(pos, &ca91cx42_bridge->master_resources) {
1821 master_image = list_entry(pos, struct vme_master_resource,
1822 list);
1823 list_del(pos);
1824 kfree(master_image);
1825 }
1826
1827 ca91cx42_irq_exit(ca91cx42_device, pdev);
1828err_irq:
1829err_test:
1830 iounmap(ca91cx42_device->base);
1831err_remap:
1832 pci_release_regions(pdev);
1833err_resource:
1834 pci_disable_device(pdev);
1835err_enable:
1836 kfree(ca91cx42_device);
1837err_driver:
1838 kfree(ca91cx42_bridge);
1839err_struct:
1840 return retval;
1841
1842}
1843
1844static void ca91cx42_remove(struct pci_dev *pdev)
1845{
1846 struct list_head *pos = NULL;
1847 struct vme_master_resource *master_image;
1848 struct vme_slave_resource *slave_image;
1849 struct vme_dma_resource *dma_ctrlr;
1850 struct vme_lm_resource *lm;
1851 struct ca91cx42_driver *bridge;
1852 struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1853
1854 bridge = ca91cx42_bridge->driver_priv;
1855
1856
1857 /* Turn off Ints */
1858 iowrite32(0, bridge->base + LINT_EN);
1859
1860 /* Turn off the windows */
1861 iowrite32(0x00800000, bridge->base + LSI0_CTL);
1862 iowrite32(0x00800000, bridge->base + LSI1_CTL);
1863 iowrite32(0x00800000, bridge->base + LSI2_CTL);
1864 iowrite32(0x00800000, bridge->base + LSI3_CTL);
1865 iowrite32(0x00800000, bridge->base + LSI4_CTL);
1866 iowrite32(0x00800000, bridge->base + LSI5_CTL);
1867 iowrite32(0x00800000, bridge->base + LSI6_CTL);
1868 iowrite32(0x00800000, bridge->base + LSI7_CTL);
1869 iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1870 iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1871 iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1872 iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1873 iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1874 iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1875 iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1876 iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1877
1878 vme_unregister_bridge(ca91cx42_bridge);
1879
1880 ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1881
1882 /* resources are stored in link list */
1883 list_for_each(pos, &ca91cx42_bridge->lm_resources) {
1884 lm = list_entry(pos, struct vme_lm_resource, list);
1885 list_del(pos);
1886 kfree(lm);
1887 }
1888
1889 /* resources are stored in link list */
1890 list_for_each(pos, &ca91cx42_bridge->dma_resources) {
1891 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1892 list_del(pos);
1893 kfree(dma_ctrlr);
1894 }
1895
1896 /* resources are stored in link list */
1897 list_for_each(pos, &ca91cx42_bridge->slave_resources) {
1898 slave_image = list_entry(pos, struct vme_slave_resource, list);
1899 list_del(pos);
1900 kfree(slave_image);
1901 }
1902
1903 /* resources are stored in link list */
1904 list_for_each(pos, &ca91cx42_bridge->master_resources) {
1905 master_image = list_entry(pos, struct vme_master_resource,
1906 list);
1907 list_del(pos);
1908 kfree(master_image);
1909 }
1910
1911 ca91cx42_irq_exit(bridge, pdev);
1912
1913 iounmap(bridge->base);
1914
1915 pci_release_regions(pdev);
1916
1917 pci_disable_device(pdev);
1918
1919 kfree(ca91cx42_bridge);
1920}
1921
1922static void __exit ca91cx42_exit(void)
1923{
1924 pci_unregister_driver(&ca91cx42_driver);
1925}
1926
1927MODULE_PARM_DESC(geoid, "Override geographical addressing");
1928module_param(geoid, int, 0);
1929
1930MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1931MODULE_LICENSE("GPL");
1932
1933module_init(ca91cx42_init);
1934module_exit(ca91cx42_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 02:31:37 -0400