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path: root/drivers/staging/tm6000
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-rw-r--r--drivers/staging/tm6000/tm6000-alsa.c12
-rw-r--r--drivers/staging/tm6000/tm6000-core.c358
-rw-r--r--drivers/staging/tm6000/tm6000-stds.c1206
-rw-r--r--drivers/staging/tm6000/tm6000-video.c16
4 files changed, 796 insertions, 796 deletions
diff --git a/drivers/staging/tm6000/tm6000-alsa.c b/drivers/staging/tm6000/tm6000-alsa.c
index 7cc2ac740d8..bc89f9d2800 100644
--- a/drivers/staging/tm6000/tm6000-alsa.c
+++ b/drivers/staging/tm6000/tm6000-alsa.c
@@ -100,11 +100,11 @@ static int _tm6000_start_audio_dma(struct snd_tm6000_card *chip)
100 int val; 100 int val;
101 101
102 /* Enables audio */ 102 /* Enables audio */
103 val = tm6000_get_reg(core, REQ_07_SET_GET_AVREG, 0xcc, 0x0); 103 val = tm6000_get_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0x0);
104 val |= 0x20; 104 val |= 0x20;
105 tm6000_set_reg(core, REQ_07_SET_GET_AVREG, 0xcc, val); 105 tm6000_set_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
106 106
107 tm6000_set_reg(core, REQ_08_SET_GET_AVREG_BIT, 0x01, 0x80); 107 tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0x80);
108 108
109 return 0; 109 return 0;
110} 110}
@@ -119,11 +119,11 @@ static int _tm6000_stop_audio_dma(struct snd_tm6000_card *chip)
119 dprintk(1, "Stopping audio DMA\n"); 119 dprintk(1, "Stopping audio DMA\n");
120 120
121 /* Enables audio */ 121 /* Enables audio */
122 val = tm6000_get_reg(core, REQ_07_SET_GET_AVREG, 0xcc, 0x0); 122 val = tm6000_get_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0x0);
123 val &= ~0x20; 123 val &= ~0x20;
124 tm6000_set_reg(core, REQ_07_SET_GET_AVREG, 0xcc, val); 124 tm6000_set_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
125 125
126 tm6000_set_reg(core, REQ_08_SET_GET_AVREG_BIT, 0x01, 0); 126 tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0);
127 127
128 return 0; 128 return 0;
129} 129}
diff --git a/drivers/staging/tm6000/tm6000-core.c b/drivers/staging/tm6000/tm6000-core.c
index bf40aa833ed..b9640d74b91 100644
--- a/drivers/staging/tm6000/tm6000-core.c
+++ b/drivers/staging/tm6000/tm6000-core.c
@@ -143,14 +143,14 @@ void tm6000_set_fourcc_format(struct tm6000_core *dev)
143{ 143{
144 if (dev->dev_type == TM6010) { 144 if (dev->dev_type == TM6010) {
145 if (dev->fourcc == V4L2_PIX_FMT_UYVY) 145 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
146 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfc); 146 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfc);
147 else 147 else
148 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfd); 148 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xfd);
149 } else { 149 } else {
150 if (dev->fourcc == V4L2_PIX_FMT_UYVY) 150 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
151 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xd0); 151 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
152 else 152 else
153 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0x90); 153 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
154 } 154 }
155} 155}
156 156
@@ -160,40 +160,40 @@ int tm6000_init_analog_mode (struct tm6000_core *dev)
160 int val; 160 int val;
161 161
162 /* Enable video */ 162 /* Enable video */
163 val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0); 163 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
164 val |= 0x60; 164 val |= 0x60;
165 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val); 165 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
166 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf); 166 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xcf);
167 167
168 } else { 168 } else {
169 /* Enables soft reset */ 169 /* Enables soft reset */
170 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01); 170 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
171 171
172 if (dev->scaler) { 172 if (dev->scaler) {
173 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20); 173 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
174 } else { 174 } else {
175 /* Enable Hfilter and disable TS Drop err */ 175 /* Enable Hfilter and disable TS Drop err */
176 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80); 176 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
177 } 177 }
178 178
179 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88); 179 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
180 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23); 180 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23);
181 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0); 181 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
182 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8); 182 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
183 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06); 183 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
184 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f); 184 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f);
185 185
186 /* AP Software reset */ 186 /* AP Software reset */
187 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08); 187 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
188 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00); 188 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
189 189
190 tm6000_set_fourcc_format(dev); 190 tm6000_set_fourcc_format(dev);
191 191
192 /* Disables soft reset */ 192 /* Disables soft reset */
193 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00); 193 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
194 194
195 /* E3: Select input 0 - TV tuner */ 195 /* E3: Select input 0 - TV tuner */
196 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00); 196 tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00);
197 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60); 197 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60);
198 198
199 /* This controls input */ 199 /* This controls input */
@@ -225,38 +225,38 @@ int tm6000_init_digital_mode (struct tm6000_core *dev)
225 u8 buf[2]; 225 u8 buf[2];
226 226
227 /* digital init */ 227 /* digital init */
228 val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0); 228 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
229 val &= ~0x60; 229 val &= ~0x60;
230 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val); 230 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
231 val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0); 231 val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
232 val |= 0x40; 232 val |= 0x40;
233 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, val); 233 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
234 tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0x28); 234 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
235 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xfc); 235 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
236 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe6, 0xff); 236 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
237 tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe); 237 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
238 tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2); 238 tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
239 printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]); 239 printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]);
240 240
241 241
242 } else { 242 } else {
243 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x08); 243 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
244 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x00); 244 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
245 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x003f, 0x01); 245 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
246 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00df, 0x08); 246 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08);
247 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c); 247 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
248 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff); 248 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
249 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8); 249 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8);
250 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c0, 0x40); 250 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
251 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c1, 0xd0); 251 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
252 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c3, 0x09); 252 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
253 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00da, 0x37); 253 tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37);
254 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d1, 0xd8); 254 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
255 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d2, 0xc0); 255 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
256 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d6, 0x60); 256 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
257 257
258 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c); 258 tm6000_set_reg(dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c);
259 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff); 259 tm6000_set_reg(dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff);
260 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08); 260 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08);
261 msleep(50); 261 msleep(50);
262 262
@@ -279,153 +279,153 @@ struct reg_init {
279/* The meaning of those initializations are unknown */ 279/* The meaning of those initializations are unknown */
280struct reg_init tm6000_init_tab[] = { 280struct reg_init tm6000_init_tab[] = {
281 /* REG VALUE */ 281 /* REG VALUE */
282 { REQ_07_SET_GET_AVREG, 0xdf, 0x1f }, 282 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f },
283 { REQ_07_SET_GET_AVREG, 0xff, 0x08 }, 283 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
284 { REQ_07_SET_GET_AVREG, 0xff, 0x00 }, 284 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
285 { REQ_07_SET_GET_AVREG, 0xd5, 0x4f }, 285 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
286 { REQ_07_SET_GET_AVREG, 0xda, 0x23 }, 286 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 },
287 { REQ_07_SET_GET_AVREG, 0xdb, 0x08 }, 287 { TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 },
288 { REQ_07_SET_GET_AVREG, 0xe2, 0x00 }, 288 { TM6010_REQ07_RE2_OUT_SEL2, 0x00 },
289 { REQ_07_SET_GET_AVREG, 0xe3, 0x10 }, 289 { TM6010_REQ07_RE3_OUT_SEL1, 0x10 },
290 { REQ_07_SET_GET_AVREG, 0xe5, 0x00 }, 290 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 },
291 { REQ_07_SET_GET_AVREG, 0xe8, 0x00 }, 291 { TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 },
292 { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */ 292 { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */
293 { REQ_07_SET_GET_AVREG, 0xee, 0xc2 }, 293 { REQ_07_SET_GET_AVREG, 0xee, 0xc2 },
294 { REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, /* Start of soft reset */ 294 { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */
295 { REQ_07_SET_GET_AVREG, 0x00, 0x00 }, 295 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
296 { REQ_07_SET_GET_AVREG, 0x01, 0x07 }, 296 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
297 { REQ_07_SET_GET_AVREG, 0x02, 0x5f }, 297 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
298 { REQ_07_SET_GET_AVREG, 0x03, 0x00 }, 298 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
299 { REQ_07_SET_GET_AVREG, 0x05, 0x64 }, 299 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
300 { REQ_07_SET_GET_AVREG, 0x07, 0x01 }, 300 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
301 { REQ_07_SET_GET_AVREG, 0x08, 0x82 }, 301 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
302 { REQ_07_SET_GET_AVREG, 0x09, 0x36 }, 302 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
303 { REQ_07_SET_GET_AVREG, 0x0a, 0x50 }, 303 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
304 { REQ_07_SET_GET_AVREG, 0x0c, 0x6a }, 304 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
305 { REQ_07_SET_GET_AVREG, 0x11, 0xc9 }, 305 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
306 { REQ_07_SET_GET_AVREG, 0x12, 0x07 }, 306 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
307 { REQ_07_SET_GET_AVREG, 0x13, 0x3b }, 307 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
308 { REQ_07_SET_GET_AVREG, 0x14, 0x47 }, 308 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
309 { REQ_07_SET_GET_AVREG, 0x15, 0x6f }, 309 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
310 { REQ_07_SET_GET_AVREG, 0x17, 0xcd }, 310 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
311 { REQ_07_SET_GET_AVREG, 0x18, 0x1e }, 311 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
312 { REQ_07_SET_GET_AVREG, 0x19, 0x8b }, 312 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
313 { REQ_07_SET_GET_AVREG, 0x1a, 0xa2 }, 313 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
314 { REQ_07_SET_GET_AVREG, 0x1b, 0xe9 }, 314 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
315 { REQ_07_SET_GET_AVREG, 0x1c, 0x1c }, 315 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
316 { REQ_07_SET_GET_AVREG, 0x1d, 0xcc }, 316 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
317 { REQ_07_SET_GET_AVREG, 0x1e, 0xcc }, 317 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
318 { REQ_07_SET_GET_AVREG, 0x1f, 0xcd }, 318 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
319 { REQ_07_SET_GET_AVREG, 0x20, 0x3c }, 319 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
320 { REQ_07_SET_GET_AVREG, 0x21, 0x3c }, 320 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
321 { REQ_07_SET_GET_AVREG, 0x2d, 0x48 }, 321 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
322 { REQ_07_SET_GET_AVREG, 0x2e, 0x88 }, 322 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
323 { REQ_07_SET_GET_AVREG, 0x30, 0x22 }, 323 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
324 { REQ_07_SET_GET_AVREG, 0x31, 0x61 }, 324 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
325 { REQ_07_SET_GET_AVREG, 0x32, 0x74 }, 325 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
326 { REQ_07_SET_GET_AVREG, 0x33, 0x1c }, 326 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
327 { REQ_07_SET_GET_AVREG, 0x34, 0x74 }, 327 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
328 { REQ_07_SET_GET_AVREG, 0x35, 0x1c }, 328 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
329 { REQ_07_SET_GET_AVREG, 0x36, 0x7a }, 329 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
330 { REQ_07_SET_GET_AVREG, 0x37, 0x26 }, 330 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
331 { REQ_07_SET_GET_AVREG, 0x38, 0x40 }, 331 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
332 { REQ_07_SET_GET_AVREG, 0x39, 0x0a }, 332 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
333 { REQ_07_SET_GET_AVREG, 0x42, 0x55 }, 333 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
334 { REQ_07_SET_GET_AVREG, 0x51, 0x11 }, 334 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
335 { REQ_07_SET_GET_AVREG, 0x55, 0x01 }, 335 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
336 { REQ_07_SET_GET_AVREG, 0x57, 0x02 }, 336 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
337 { REQ_07_SET_GET_AVREG, 0x58, 0x35 }, 337 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
338 { REQ_07_SET_GET_AVREG, 0x59, 0xa0 }, 338 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
339 { REQ_07_SET_GET_AVREG, 0x80, 0x15 }, 339 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
340 { REQ_07_SET_GET_AVREG, 0x82, 0x42 }, 340 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
341 { REQ_07_SET_GET_AVREG, 0xc1, 0xd0 }, 341 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
342 { REQ_07_SET_GET_AVREG, 0xc3, 0x88 }, 342 { TM6010_REQ07_RC3_HSTART1, 0x88 },
343 { REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, /* End of the soft reset */ 343 { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */
344 { REQ_05_SET_GET_USBREG, 0x18, 0x00 }, 344 { REQ_05_SET_GET_USBREG, 0x18, 0x00 },
345}; 345};
346 346
347struct reg_init tm6010_init_tab[] = { 347struct reg_init tm6010_init_tab[] = {
348 { REQ_07_SET_GET_AVREG, 0xc0, 0x00 }, 348 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
349 { REQ_07_SET_GET_AVREG, 0xc4, 0xa0 }, 349 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
350 { REQ_07_SET_GET_AVREG, 0xc6, 0x40 }, 350 { TM6010_REQ07_RC6_HEND0, 0x40 },
351 { REQ_07_SET_GET_AVREG, 0xca, 0x31 }, 351 { TM6010_REQ07_RCA_VEND0, 0x31 },
352 { REQ_07_SET_GET_AVREG, 0xcc, 0xe1 }, 352 { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 },
353 { REQ_07_SET_GET_AVREG, 0xe0, 0x03 }, 353 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
354 { REQ_07_SET_GET_AVREG, 0xfe, 0x7f }, 354 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
355 355
356 { REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 }, 356 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
357 { REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 }, 357 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
358 { REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 }, 358 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
359 { REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 }, 359 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
360 { REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 }, 360 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
361 { REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 }, 361 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
362 { REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 }, 362 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
363 { REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 }, 363 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
364 { REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc }, 364 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
365 365
366 { REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, 366 { TM6010_REQ07_R3F_RESET, 0x01 },
367 { REQ_07_SET_GET_AVREG, 0x00, 0x00 }, 367 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
368 { REQ_07_SET_GET_AVREG, 0x01, 0x07 }, 368 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
369 { REQ_07_SET_GET_AVREG, 0x02, 0x5f }, 369 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
370 { REQ_07_SET_GET_AVREG, 0x03, 0x00 }, 370 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
371 { REQ_07_SET_GET_AVREG, 0x05, 0x64 }, 371 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
372 { REQ_07_SET_GET_AVREG, 0x07, 0x01 }, 372 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
373 { REQ_07_SET_GET_AVREG, 0x08, 0x82 }, 373 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
374 { REQ_07_SET_GET_AVREG, 0x09, 0x36 }, 374 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
375 { REQ_07_SET_GET_AVREG, 0x0a, 0x50 }, 375 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
376 { REQ_07_SET_GET_AVREG, 0x0c, 0x6a }, 376 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
377 { REQ_07_SET_GET_AVREG, 0x11, 0xc9 }, 377 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
378 { REQ_07_SET_GET_AVREG, 0x12, 0x07 }, 378 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
379 { REQ_07_SET_GET_AVREG, 0x13, 0x3b }, 379 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
380 { REQ_07_SET_GET_AVREG, 0x14, 0x47 }, 380 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
381 { REQ_07_SET_GET_AVREG, 0x15, 0x6f }, 381 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
382 { REQ_07_SET_GET_AVREG, 0x17, 0xcd }, 382 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
383 { REQ_07_SET_GET_AVREG, 0x18, 0x1e }, 383 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
384 { REQ_07_SET_GET_AVREG, 0x19, 0x8b }, 384 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
385 { REQ_07_SET_GET_AVREG, 0x1a, 0xa2 }, 385 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
386 { REQ_07_SET_GET_AVREG, 0x1b, 0xe9 }, 386 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
387 { REQ_07_SET_GET_AVREG, 0x1c, 0x1c }, 387 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
388 { REQ_07_SET_GET_AVREG, 0x1d, 0xcc }, 388 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
389 { REQ_07_SET_GET_AVREG, 0x1e, 0xcc }, 389 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
390 { REQ_07_SET_GET_AVREG, 0x1f, 0xcd }, 390 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
391 { REQ_07_SET_GET_AVREG, 0x20, 0x3c }, 391 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
392 { REQ_07_SET_GET_AVREG, 0x21, 0x3c }, 392 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
393 { REQ_07_SET_GET_AVREG, 0x2d, 0x48 }, 393 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
394 { REQ_07_SET_GET_AVREG, 0x2e, 0x88 }, 394 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
395 { REQ_07_SET_GET_AVREG, 0x30, 0x22 }, 395 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
396 { REQ_07_SET_GET_AVREG, 0x31, 0x61 }, 396 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
397 { REQ_07_SET_GET_AVREG, 0x32, 0x74 }, 397 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
398 { REQ_07_SET_GET_AVREG, 0x33, 0x1c }, 398 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
399 { REQ_07_SET_GET_AVREG, 0x34, 0x74 }, 399 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
400 { REQ_07_SET_GET_AVREG, 0x35, 0x1c }, 400 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
401 { REQ_07_SET_GET_AVREG, 0x36, 0x7a }, 401 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
402 { REQ_07_SET_GET_AVREG, 0x37, 0x26 }, 402 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
403 { REQ_07_SET_GET_AVREG, 0x38, 0x40 }, 403 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
404 { REQ_07_SET_GET_AVREG, 0x39, 0x0a }, 404 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
405 { REQ_07_SET_GET_AVREG, 0x42, 0x55 }, 405 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
406 { REQ_07_SET_GET_AVREG, 0x51, 0x11 }, 406 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
407 { REQ_07_SET_GET_AVREG, 0x55, 0x01 }, 407 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
408 { REQ_07_SET_GET_AVREG, 0x57, 0x02 }, 408 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
409 { REQ_07_SET_GET_AVREG, 0x58, 0x35 }, 409 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
410 { REQ_07_SET_GET_AVREG, 0x59, 0xa0 }, 410 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
411 { REQ_07_SET_GET_AVREG, 0x80, 0x15 }, 411 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
412 { REQ_07_SET_GET_AVREG, 0x82, 0x42 }, 412 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
413 { REQ_07_SET_GET_AVREG, 0xc1, 0xd0 }, 413 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
414 { REQ_07_SET_GET_AVREG, 0xc3, 0x88 }, 414 { TM6010_REQ07_RC3_HSTART1, 0x88 },
415 { REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, 415 { TM6010_REQ07_R3F_RESET, 0x00 },
416 416
417 { REQ_05_SET_GET_USBREG, 0x18, 0x00 }, 417 { REQ_05_SET_GET_USBREG, 0x18, 0x00 },
418 418
419 { REQ_07_SET_GET_AVREG, 0xdc, 0xaa }, 419 { TM6010_REQ07_RD8_IR_LEADER1, 0xaa },
420 { REQ_07_SET_GET_AVREG, 0xdd, 0x30 }, 420 { TM6010_REQ07_RD8_IR_LEADER0, 0x30 },
421 { REQ_07_SET_GET_AVREG, 0xde, 0x20 }, 421 { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 },
422 { REQ_07_SET_GET_AVREG, 0xdf, 0xd0 }, 422 { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 },
423 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 }, 423 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
424 { REQ_07_SET_GET_AVREG, 0xd8, 0x2f }, 424 { TM6010_REQ07_RD8_IR, 0x2f },
425 425
426 /* set remote wakeup key:any key wakeup */ 426 /* set remote wakeup key:any key wakeup */
427 { REQ_07_SET_GET_AVREG, 0xe5, 0xfe }, 427 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
428 { REQ_07_SET_GET_AVREG, 0xda, 0xff }, 428 { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff },
429}; 429};
430 430
431int tm6000_init (struct tm6000_core *dev) 431int tm6000_init (struct tm6000_core *dev)
diff --git a/drivers/staging/tm6000/tm6000-stds.c b/drivers/staging/tm6000/tm6000-stds.c
index 1e142e5d59c..b3564f611e5 100644
--- a/drivers/staging/tm6000/tm6000-stds.c
+++ b/drivers/staging/tm6000/tm6000-stds.c
@@ -44,290 +44,290 @@ static struct tm6000_std_tv_settings tv_stds[] = {
44 { 44 {
45 .id = V4L2_STD_PAL_M, 45 .id = V4L2_STD_PAL_M,
46 .sif = { 46 .sif = {
47 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, 47 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
48 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 48 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
49 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 49 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
50 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, 50 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
51 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 51 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
52 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 52 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
53 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 53 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
54 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 54 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
55 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, 55 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
56 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, 56 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
57 {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, 57 {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
58 {0, 0, 0}, 58 {0, 0, 0},
59 }, 59 },
60 .nosif = { 60 .nosif = {
61 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 61 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
62 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 62 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
63 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 63 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
64 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 64 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
65 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 65 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
66 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 66 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
67 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 67 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
68 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 68 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
69 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, 69 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
70 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 70 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
71 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 71 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
72 {0, 0, 0}, 72 {0, 0, 0},
73 }, 73 },
74 .common = { 74 .common = {
75 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 75 {TM6010_REQ07_R3F_RESET, 0x01},
76 {REQ_07_SET_GET_AVREG, 0x00, 0x04}, 76 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04},
77 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 77 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
78 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 78 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
79 {REQ_07_SET_GET_AVREG, 0x03, 0x00}, 79 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
80 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 80 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
81 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 81 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
82 {REQ_07_SET_GET_AVREG, 0x19, 0x83}, 82 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83},
83 {REQ_07_SET_GET_AVREG, 0x1a, 0x0a}, 83 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a},
84 {REQ_07_SET_GET_AVREG, 0x1b, 0xe0}, 84 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0},
85 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 85 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
86 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 86 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
87 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 87 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
88 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 88 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
89 {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, 89 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
90 {REQ_07_SET_GET_AVREG, 0x30, 0x20}, 90 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20},
91 {REQ_07_SET_GET_AVREG, 0x31, 0x61}, 91 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
92 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 92 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
93 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 93 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
94 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 94 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
95 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 95 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
96 96
97 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 97 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
98 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 98 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
99 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 99 {TM6010_REQ07_R3F_RESET, 0x00},
100 {0, 0, 0}, 100 {0, 0, 0},
101 }, 101 },
102 }, { 102 }, {
103 .id = V4L2_STD_PAL_Nc, 103 .id = V4L2_STD_PAL_Nc,
104 .sif = { 104 .sif = {
105 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, 105 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
106 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 106 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
107 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 107 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
108 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, 108 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
109 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 109 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
110 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 110 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
111 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 111 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
112 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 112 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
113 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, 113 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
114 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, 114 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
115 {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, 115 {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
116 {0, 0, 0}, 116 {0, 0, 0},
117 }, 117 },
118 .nosif = { 118 .nosif = {
119 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 119 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
120 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 120 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
121 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 121 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
122 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 122 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
123 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 123 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
124 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 124 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
125 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 125 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
126 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 126 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
127 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, 127 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
128 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 128 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
129 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 129 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
130 {0, 0, 0}, 130 {0, 0, 0},
131 }, 131 },
132 .common = { 132 .common = {
133 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 133 {TM6010_REQ07_R3F_RESET, 0x01},
134 {REQ_07_SET_GET_AVREG, 0x00, 0x36}, 134 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36},
135 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 135 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
136 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 136 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
137 {REQ_07_SET_GET_AVREG, 0x03, 0x02}, 137 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
138 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 138 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
139 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 139 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
140 {REQ_07_SET_GET_AVREG, 0x19, 0x91}, 140 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91},
141 {REQ_07_SET_GET_AVREG, 0x1a, 0x1f}, 141 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f},
142 {REQ_07_SET_GET_AVREG, 0x1b, 0x0c}, 142 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c},
143 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 143 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
144 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 144 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
145 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 145 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
146 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 146 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
147 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 147 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
148 {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, 148 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
149 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 149 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
150 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 150 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
151 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 151 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
152 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 152 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
153 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 153 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
154 154
155 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 155 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
156 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 156 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
157 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 157 {TM6010_REQ07_R3F_RESET, 0x00},
158 {0, 0, 0}, 158 {0, 0, 0},
159 }, 159 },
160 }, { 160 }, {
161 .id = V4L2_STD_PAL, 161 .id = V4L2_STD_PAL,
162 .sif = { 162 .sif = {
163 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, 163 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
164 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 164 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
165 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 165 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
166 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, 166 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
167 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 167 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
168 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 168 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
169 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 169 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
170 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 170 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
171 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, 171 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
172 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, 172 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
173 {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, 173 {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
174 {0, 0, 0} 174 {0, 0, 0}
175 }, 175 },
176 .nosif = { 176 .nosif = {
177 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 177 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
178 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 178 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
179 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 179 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
180 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 180 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
181 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 181 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
182 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 182 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
183 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 183 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
184 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 184 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
185 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, 185 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
186 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 186 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
187 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 187 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
188 {0, 0, 0}, 188 {0, 0, 0},
189 }, 189 },
190 .common = { 190 .common = {
191 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 191 {TM6010_REQ07_R3F_RESET, 0x01},
192 {REQ_07_SET_GET_AVREG, 0x00, 0x32}, 192 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32},
193 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 193 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
194 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 194 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
195 {REQ_07_SET_GET_AVREG, 0x03, 0x02}, 195 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
196 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 196 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
197 {REQ_07_SET_GET_AVREG, 0x18, 0x25}, 197 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25},
198 {REQ_07_SET_GET_AVREG, 0x19, 0xd5}, 198 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5},
199 {REQ_07_SET_GET_AVREG, 0x1a, 0x63}, 199 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63},
200 {REQ_07_SET_GET_AVREG, 0x1b, 0x50}, 200 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50},
201 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 201 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
202 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 202 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
203 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 203 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
204 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 204 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
205 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 205 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
206 {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, 206 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
207 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 207 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
208 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 208 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
209 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 209 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
210 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 210 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
211 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 211 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
212 212
213 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 213 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
214 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 214 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
215 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 215 {TM6010_REQ07_R3F_RESET, 0x00},
216 {0, 0, 0}, 216 {0, 0, 0},
217 }, 217 },
218 }, { 218 }, {
219 .id = V4L2_STD_SECAM, 219 .id = V4L2_STD_SECAM,
220 .sif = { 220 .sif = {
221 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, 221 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
222 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 222 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
223 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 223 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
224 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, 224 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
225 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 225 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
226 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 226 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
227 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 227 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
228 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 228 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
229 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, 229 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
230 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, 230 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
231 {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, 231 {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
232 {0, 0, 0}, 232 {0, 0, 0},
233 }, 233 },
234 .nosif = { 234 .nosif = {
235 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 235 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
236 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 236 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
237 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 237 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
238 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 238 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
239 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 239 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
240 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 240 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
241 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 241 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
242 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 242 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
243 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, 243 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
244 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 244 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
245 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 245 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
246 {0, 0, 0}, 246 {0, 0, 0},
247 }, 247 },
248 .common = { 248 .common = {
249 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 249 {TM6010_REQ07_R3F_RESET, 0x01},
250 {REQ_07_SET_GET_AVREG, 0x00, 0x38}, 250 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38},
251 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 251 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
252 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 252 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
253 {REQ_07_SET_GET_AVREG, 0x03, 0x02}, 253 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
254 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 254 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
255 {REQ_07_SET_GET_AVREG, 0x18, 0x24}, 255 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
256 {REQ_07_SET_GET_AVREG, 0x19, 0x92}, 256 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
257 {REQ_07_SET_GET_AVREG, 0x1a, 0xe8}, 257 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
258 {REQ_07_SET_GET_AVREG, 0x1b, 0xed}, 258 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
259 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 259 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
260 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 260 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
261 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 261 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
262 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 262 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
263 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 263 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
264 {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, 264 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
265 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 265 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
266 {REQ_07_SET_GET_AVREG, 0x33, 0x2c}, 266 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
267 {REQ_07_SET_GET_AVREG, 0x35, 0x18}, 267 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
268 {REQ_07_SET_GET_AVREG, 0x82, 0x42}, 268 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
269 {REQ_07_SET_GET_AVREG, 0x83, 0xFF}, 269 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
270 270
271 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 271 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
272 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 272 {TM6010_REQ07_R3F_RESET, 0x00},
273 {0, 0, 0}, 273 {0, 0, 0},
274 }, 274 },
275 }, { 275 }, {
276 .id = V4L2_STD_NTSC, 276 .id = V4L2_STD_NTSC,
277 .sif = { 277 .sif = {
278 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, 278 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
279 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 279 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
280 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 280 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
281 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, 281 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
282 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 282 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
283 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 283 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
284 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 284 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
285 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 285 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
286 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, 286 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
287 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, 287 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
288 {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, 288 {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
289 {0, 0, 0}, 289 {0, 0, 0},
290 }, 290 },
291 .nosif = { 291 .nosif = {
292 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 292 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
293 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, 293 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
294 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 294 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
295 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 295 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
296 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 296 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
297 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 297 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
298 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 298 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
299 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 299 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
300 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, 300 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
301 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 301 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
302 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 302 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
303 {0, 0, 0}, 303 {0, 0, 0},
304 }, 304 },
305 .common = { 305 .common = {
306 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 306 {TM6010_REQ07_R3F_RESET, 0x01},
307 {REQ_07_SET_GET_AVREG, 0x00, 0x00}, 307 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00},
308 {REQ_07_SET_GET_AVREG, 0x01, 0x0f}, 308 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
309 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 309 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
310 {REQ_07_SET_GET_AVREG, 0x03, 0x00}, 310 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
311 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 311 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
312 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 312 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
313 {REQ_07_SET_GET_AVREG, 0x19, 0x8b}, 313 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b},
314 {REQ_07_SET_GET_AVREG, 0x1a, 0xa2}, 314 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2},
315 {REQ_07_SET_GET_AVREG, 0x1b, 0xe9}, 315 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9},
316 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 316 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
317 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 317 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
318 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 318 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
319 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 319 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
320 {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, 320 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
321 {REQ_07_SET_GET_AVREG, 0x30, 0x22}, 321 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
322 {REQ_07_SET_GET_AVREG, 0x31, 0x61}, 322 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
323 {REQ_07_SET_GET_AVREG, 0x33, 0x1c}, 323 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c},
324 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 324 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
325 {REQ_07_SET_GET_AVREG, 0x82, 0x42}, 325 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
326 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 326 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
327 327
328 {REQ_07_SET_GET_AVREG, 0x04, 0xdd}, 328 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd},
329 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 329 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
330 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 330 {TM6010_REQ07_R3F_RESET, 0x00},
331 {0, 0, 0}, 331 {0, 0, 0},
332 }, 332 },
333 }, 333 },
@@ -337,210 +337,210 @@ static struct tm6000_std_settings composite_stds[] = {
337 { 337 {
338 .id = V4L2_STD_PAL_M, 338 .id = V4L2_STD_PAL_M,
339 .common = { 339 .common = {
340 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 340 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
341 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, 341 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
342 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 342 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
343 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 343 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
344 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 344 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
345 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 345 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
346 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 346 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
347 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 347 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
348 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 348 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
349 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 349 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
350 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 350 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
351 351
352 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 352 {TM6010_REQ07_R3F_RESET, 0x01},
353 {REQ_07_SET_GET_AVREG, 0x00, 0x04}, 353 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04},
354 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 354 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
355 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 355 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
356 {REQ_07_SET_GET_AVREG, 0x03, 0x00}, 356 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
357 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 357 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
358 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 358 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
359 {REQ_07_SET_GET_AVREG, 0x19, 0x83}, 359 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83},
360 {REQ_07_SET_GET_AVREG, 0x1a, 0x0a}, 360 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a},
361 {REQ_07_SET_GET_AVREG, 0x1b, 0xe0}, 361 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0},
362 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 362 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
363 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 363 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
364 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 364 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
365 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 365 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
366 {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, 366 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
367 {REQ_07_SET_GET_AVREG, 0x30, 0x20}, 367 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20},
368 {REQ_07_SET_GET_AVREG, 0x31, 0x61}, 368 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
369 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 369 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
370 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 370 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
371 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 371 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
372 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 372 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
373 373
374 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 374 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
375 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 375 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
376 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 376 {TM6010_REQ07_R3F_RESET, 0x00},
377 {0, 0, 0}, 377 {0, 0, 0},
378 }, 378 },
379 }, { 379 }, {
380 .id = V4L2_STD_PAL_Nc, 380 .id = V4L2_STD_PAL_Nc,
381 .common = { 381 .common = {
382 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 382 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
383 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, 383 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
384 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 384 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
385 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 385 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
386 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 386 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
387 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 387 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
388 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 388 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
389 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 389 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
390 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 390 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
391 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 391 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
392 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 392 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
393 393
394 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 394 {TM6010_REQ07_R3F_RESET, 0x01},
395 {REQ_07_SET_GET_AVREG, 0x00, 0x36}, 395 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36},
396 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 396 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
397 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 397 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
398 {REQ_07_SET_GET_AVREG, 0x03, 0x02}, 398 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
399 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 399 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
400 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 400 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
401 {REQ_07_SET_GET_AVREG, 0x19, 0x91}, 401 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91},
402 {REQ_07_SET_GET_AVREG, 0x1a, 0x1f}, 402 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f},
403 {REQ_07_SET_GET_AVREG, 0x1b, 0x0c}, 403 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c},
404 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 404 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
405 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 405 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
406 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 406 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
407 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 407 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
408 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 408 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
409 {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, 409 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
410 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 410 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
411 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 411 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
412 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 412 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
413 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 413 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
414 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 414 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
415 415
416 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 416 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
417 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 417 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
418 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 418 {TM6010_REQ07_R3F_RESET, 0x00},
419 {0, 0, 0}, 419 {0, 0, 0},
420 }, 420 },
421 }, { 421 }, {
422 .id = V4L2_STD_PAL, 422 .id = V4L2_STD_PAL,
423 .common = { 423 .common = {
424 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 424 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
425 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, 425 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
426 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 426 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
427 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 427 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
428 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 428 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
429 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 429 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
430 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 430 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
431 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 431 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
432 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 432 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
433 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 433 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
434 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 434 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
435 435
436 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 436 {TM6010_REQ07_R3F_RESET, 0x01},
437 {REQ_07_SET_GET_AVREG, 0x00, 0x32}, 437 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32},
438 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 438 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
439 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 439 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
440 {REQ_07_SET_GET_AVREG, 0x03, 0x02}, 440 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
441 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 441 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
442 {REQ_07_SET_GET_AVREG, 0x18, 0x25}, 442 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25},
443 {REQ_07_SET_GET_AVREG, 0x19, 0xd5}, 443 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5},
444 {REQ_07_SET_GET_AVREG, 0x1a, 0x63}, 444 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63},
445 {REQ_07_SET_GET_AVREG, 0x1b, 0x50}, 445 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50},
446 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 446 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
447 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 447 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
448 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 448 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
449 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 449 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
450 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 450 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
451 {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, 451 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
452 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 452 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
453 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 453 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
454 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 454 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
455 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 455 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
456 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 456 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
457 457
458 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 458 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
459 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 459 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
460 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 460 {TM6010_REQ07_R3F_RESET, 0x00},
461 {0, 0, 0}, 461 {0, 0, 0},
462 }, 462 },
463 }, { 463 }, {
464 .id = V4L2_STD_SECAM, 464 .id = V4L2_STD_SECAM,
465 .common = { 465 .common = {
466 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 466 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
467 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, 467 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
468 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 468 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
469 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 469 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
470 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 470 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
471 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 471 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
472 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 472 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
473 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 473 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
474 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 474 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
475 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 475 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
476 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 476 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
477 477
478 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 478 {TM6010_REQ07_R3F_RESET, 0x01},
479 {REQ_07_SET_GET_AVREG, 0x00, 0x38}, 479 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38},
480 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 480 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
481 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 481 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
482 {REQ_07_SET_GET_AVREG, 0x03, 0x02}, 482 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
483 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 483 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
484 {REQ_07_SET_GET_AVREG, 0x18, 0x24}, 484 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
485 {REQ_07_SET_GET_AVREG, 0x19, 0x92}, 485 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
486 {REQ_07_SET_GET_AVREG, 0x1a, 0xe8}, 486 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
487 {REQ_07_SET_GET_AVREG, 0x1b, 0xed}, 487 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
488 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 488 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
489 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 489 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
490 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 490 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
491 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 491 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
492 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 492 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
493 {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, 493 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
494 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 494 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
495 {REQ_07_SET_GET_AVREG, 0x33, 0x2c}, 495 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
496 {REQ_07_SET_GET_AVREG, 0x35, 0x18}, 496 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
497 {REQ_07_SET_GET_AVREG, 0x82, 0x42}, 497 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
498 {REQ_07_SET_GET_AVREG, 0x83, 0xFF}, 498 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
499 499
500 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 500 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
501 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 501 {TM6010_REQ07_R3F_RESET, 0x00},
502 {0, 0, 0}, 502 {0, 0, 0},
503 }, 503 },
504 }, { 504 }, {
505 .id = V4L2_STD_NTSC, 505 .id = V4L2_STD_NTSC,
506 .common = { 506 .common = {
507 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 507 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
508 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, 508 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
509 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, 509 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
510 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, 510 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
511 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, 511 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
512 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, 512 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
513 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 513 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
514 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, 514 {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
515 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 515 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
516 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 516 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
517 {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, 517 {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
518 518
519 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 519 {TM6010_REQ07_R3F_RESET, 0x01},
520 {REQ_07_SET_GET_AVREG, 0x00, 0x00}, 520 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00},
521 {REQ_07_SET_GET_AVREG, 0x01, 0x0f}, 521 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
522 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 522 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
523 {REQ_07_SET_GET_AVREG, 0x03, 0x00}, 523 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
524 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 524 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
525 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 525 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
526 {REQ_07_SET_GET_AVREG, 0x19, 0x8b}, 526 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b},
527 {REQ_07_SET_GET_AVREG, 0x1a, 0xa2}, 527 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2},
528 {REQ_07_SET_GET_AVREG, 0x1b, 0xe9}, 528 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9},
529 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 529 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
530 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 530 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
531 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 531 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
532 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 532 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
533 {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, 533 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
534 {REQ_07_SET_GET_AVREG, 0x30, 0x22}, 534 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
535 {REQ_07_SET_GET_AVREG, 0x31, 0x61}, 535 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
536 {REQ_07_SET_GET_AVREG, 0x33, 0x1c}, 536 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c},
537 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 537 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
538 {REQ_07_SET_GET_AVREG, 0x82, 0x42}, 538 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
539 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 539 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
540 540
541 {REQ_07_SET_GET_AVREG, 0x04, 0xdd}, 541 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd},
542 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 542 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
543 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 543 {TM6010_REQ07_R3F_RESET, 0x00},
544 {0, 0, 0}, 544 {0, 0, 0},
545 }, 545 },
546 }, 546 },
@@ -550,211 +550,211 @@ static struct tm6000_std_settings svideo_stds[] = {
550 { 550 {
551 .id = V4L2_STD_PAL_M, 551 .id = V4L2_STD_PAL_M,
552 .common = { 552 .common = {
553 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 553 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
554 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, 554 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
555 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, 555 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
556 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, 556 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
557 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, 557 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
558 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, 558 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
559 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 559 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
560 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, 560 {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
561 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 561 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
562 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 562 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
563 {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, 563 {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
564 564
565 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 565 {TM6010_REQ07_R3F_RESET, 0x01},
566 {REQ_07_SET_GET_AVREG, 0x00, 0x05}, 566 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05},
567 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 567 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
568 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 568 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
569 {REQ_07_SET_GET_AVREG, 0x03, 0x04}, 569 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04},
570 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 570 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
571 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 571 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
572 {REQ_07_SET_GET_AVREG, 0x19, 0x83}, 572 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83},
573 {REQ_07_SET_GET_AVREG, 0x1a, 0x0a}, 573 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a},
574 {REQ_07_SET_GET_AVREG, 0x1b, 0xe0}, 574 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0},
575 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 575 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
576 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 576 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
577 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 577 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
578 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 578 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
579 {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, 579 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
580 {REQ_07_SET_GET_AVREG, 0x30, 0x22}, 580 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
581 {REQ_07_SET_GET_AVREG, 0x31, 0x61}, 581 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
582 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 582 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
583 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 583 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
584 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 584 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
585 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 585 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
586 586
587 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 587 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
588 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 588 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
589 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 589 {TM6010_REQ07_R3F_RESET, 0x00},
590 {0, 0, 0}, 590 {0, 0, 0},
591 }, 591 },
592 }, { 592 }, {
593 .id = V4L2_STD_PAL_Nc, 593 .id = V4L2_STD_PAL_Nc,
594 .common = { 594 .common = {
595 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 595 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
596 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, 596 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
597 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, 597 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
598 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, 598 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
599 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, 599 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
600 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, 600 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
601 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 601 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
602 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, 602 {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
603 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 603 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
604 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 604 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
605 {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, 605 {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
606 606
607 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 607 {TM6010_REQ07_R3F_RESET, 0x01},
608 {REQ_07_SET_GET_AVREG, 0x00, 0x37}, 608 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37},
609 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 609 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
610 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 610 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
611 {REQ_07_SET_GET_AVREG, 0x03, 0x04}, 611 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04},
612 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 612 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
613 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 613 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
614 {REQ_07_SET_GET_AVREG, 0x19, 0x91}, 614 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91},
615 {REQ_07_SET_GET_AVREG, 0x1a, 0x1f}, 615 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f},
616 {REQ_07_SET_GET_AVREG, 0x1b, 0x0c}, 616 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c},
617 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 617 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
618 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 618 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
619 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 619 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
620 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 620 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
621 {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, 621 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
622 {REQ_07_SET_GET_AVREG, 0x30, 0x22}, 622 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
623 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 623 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
624 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 624 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
625 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 625 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
626 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 626 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
627 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 627 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
628 628
629 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 629 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
630 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 630 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
631 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 631 {TM6010_REQ07_R3F_RESET, 0x00},
632 {0, 0, 0}, 632 {0, 0, 0},
633 }, 633 },
634 }, { 634 }, {
635 .id = V4L2_STD_PAL, 635 .id = V4L2_STD_PAL,
636 .common = { 636 .common = {
637 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 637 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
638 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, 638 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
639 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, 639 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
640 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, 640 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
641 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, 641 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
642 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, 642 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
643 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 643 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
644 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, 644 {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
645 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 645 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
646 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 646 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
647 {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, 647 {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
648 648
649 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 649 {TM6010_REQ07_R3F_RESET, 0x01},
650 {REQ_07_SET_GET_AVREG, 0x00, 0x33}, 650 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33},
651 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 651 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
652 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 652 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
653 {REQ_07_SET_GET_AVREG, 0x03, 0x04}, 653 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04},
654 {REQ_07_SET_GET_AVREG, 0x07, 0x00}, 654 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x00},
655 {REQ_07_SET_GET_AVREG, 0x18, 0x25}, 655 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25},
656 {REQ_07_SET_GET_AVREG, 0x19, 0xd5}, 656 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5},
657 {REQ_07_SET_GET_AVREG, 0x1a, 0x63}, 657 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63},
658 {REQ_07_SET_GET_AVREG, 0x1b, 0x50}, 658 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50},
659 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 659 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
660 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 660 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
661 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 661 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
662 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 662 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
663 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 663 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
664 {REQ_07_SET_GET_AVREG, 0x30, 0x2a}, 664 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a},
665 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 665 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
666 {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, 666 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
667 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 667 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
668 {REQ_07_SET_GET_AVREG, 0x82, 0x52}, 668 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
669 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 669 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
670 670
671 {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, 671 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
672 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 672 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
673 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 673 {TM6010_REQ07_R3F_RESET, 0x00},
674 {0, 0, 0}, 674 {0, 0, 0},
675 }, 675 },
676 }, { 676 }, {
677 .id = V4L2_STD_SECAM, 677 .id = V4L2_STD_SECAM,
678 .common = { 678 .common = {
679 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 679 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
680 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, 680 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
681 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, 681 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
682 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, 682 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
683 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, 683 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
684 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, 684 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
685 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 685 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
686 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, 686 {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
687 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 687 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
688 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 688 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
689 {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, 689 {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
690 690
691 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 691 {TM6010_REQ07_R3F_RESET, 0x01},
692 {REQ_07_SET_GET_AVREG, 0x00, 0x39}, 692 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39},
693 {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, 693 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
694 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 694 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
695 {REQ_07_SET_GET_AVREG, 0x03, 0x03}, 695 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03},
696 {REQ_07_SET_GET_AVREG, 0x07, 0x01}, 696 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01},
697 {REQ_07_SET_GET_AVREG, 0x18, 0x24}, 697 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
698 {REQ_07_SET_GET_AVREG, 0x19, 0x92}, 698 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
699 {REQ_07_SET_GET_AVREG, 0x1a, 0xe8}, 699 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
700 {REQ_07_SET_GET_AVREG, 0x1b, 0xed}, 700 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
701 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 701 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
702 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 702 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
703 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 703 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
704 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 704 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
705 {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, 705 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
706 {REQ_07_SET_GET_AVREG, 0x30, 0x2a}, 706 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a},
707 {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, 707 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
708 {REQ_07_SET_GET_AVREG, 0x33, 0x2c}, 708 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
709 {REQ_07_SET_GET_AVREG, 0x35, 0x18}, 709 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
710 {REQ_07_SET_GET_AVREG, 0x82, 0x42}, 710 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
711 {REQ_07_SET_GET_AVREG, 0x83, 0xFF}, 711 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
712 712
713 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 713 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
714 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 714 {TM6010_REQ07_R3F_RESET, 0x00},
715 {0, 0, 0}, 715 {0, 0, 0},
716 }, 716 },
717 }, { 717 }, {
718 .id = V4L2_STD_NTSC, 718 .id = V4L2_STD_NTSC,
719 .common = { 719 .common = {
720 {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, 720 {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
721 {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, 721 {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
722 {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, 722 {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
723 {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, 723 {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
724 {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, 724 {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
725 {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, 725 {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
726 {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, 726 {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
727 {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, 727 {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
728 {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, 728 {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
729 {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, 729 {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
730 {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, 730 {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
731 731
732 {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, 732 {TM6010_REQ07_R3F_RESET, 0x01},
733 {REQ_07_SET_GET_AVREG, 0x00, 0x01}, 733 {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01},
734 {REQ_07_SET_GET_AVREG, 0x01, 0x0f}, 734 {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
735 {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, 735 {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
736 {REQ_07_SET_GET_AVREG, 0x03, 0x03}, 736 {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03},
737 {REQ_07_SET_GET_AVREG, 0x07, 0x00}, 737 {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x00},
738 {REQ_07_SET_GET_AVREG, 0x17, 0x8b}, 738 {TM6010_REQ07_R17_HLOOP_MAXSTATE, 0x8b},
739 {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, 739 {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
740 {REQ_07_SET_GET_AVREG, 0x19, 0x8b}, 740 {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b},
741 {REQ_07_SET_GET_AVREG, 0x1a, 0xa2}, 741 {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2},
742 {REQ_07_SET_GET_AVREG, 0x1b, 0xe9}, 742 {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9},
743 {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, 743 {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
744 {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, 744 {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
745 {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, 745 {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
746 {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, 746 {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
747 {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, 747 {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
748 {REQ_07_SET_GET_AVREG, 0x30, 0x22}, 748 {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
749 {REQ_07_SET_GET_AVREG, 0x31, 0x61}, 749 {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
750 {REQ_07_SET_GET_AVREG, 0x33, 0x1c}, 750 {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c},
751 {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, 751 {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
752 {REQ_07_SET_GET_AVREG, 0x82, 0x42}, 752 {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
753 {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, 753 {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
754 754
755 {REQ_07_SET_GET_AVREG, 0x04, 0xdd}, 755 {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd},
756 {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, 756 {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
757 {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, 757 {TM6010_REQ07_R3F_RESET, 0x00},
758 {0, 0, 0}, 758 {0, 0, 0},
759 }, 759 },
760 }, 760 },
diff --git a/drivers/staging/tm6000/tm6000-video.c b/drivers/staging/tm6000/tm6000-video.c
index 0bee7dfaae4..67f4d2908c3 100644
--- a/drivers/staging/tm6000/tm6000-video.c
+++ b/drivers/staging/tm6000/tm6000-video.c
@@ -1186,16 +1186,16 @@ static int vidioc_g_ctrl (struct file *file, void *priv,
1186 /* FIXME: Probably, those won't work! Maybe we need shadow regs */ 1186 /* FIXME: Probably, those won't work! Maybe we need shadow regs */
1187 switch (ctrl->id) { 1187 switch (ctrl->id) {
1188 case V4L2_CID_CONTRAST: 1188 case V4L2_CID_CONTRAST:
1189 val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x08, 0); 1189 val = tm6000_get_reg(dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0);
1190 break; 1190 break;
1191 case V4L2_CID_BRIGHTNESS: 1191 case V4L2_CID_BRIGHTNESS:
1192 val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x09, 0); 1192 val = tm6000_get_reg(dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0);
1193 return 0; 1193 return 0;
1194 case V4L2_CID_SATURATION: 1194 case V4L2_CID_SATURATION:
1195 val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x0a, 0); 1195 val = tm6000_get_reg(dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0);
1196 return 0; 1196 return 0;
1197 case V4L2_CID_HUE: 1197 case V4L2_CID_HUE:
1198 val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x0b, 0); 1198 val = tm6000_get_reg(dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, 0);
1199 return 0; 1199 return 0;
1200 default: 1200 default:
1201 return -EINVAL; 1201 return -EINVAL;
@@ -1217,16 +1217,16 @@ static int vidioc_s_ctrl (struct file *file, void *priv,
1217 1217
1218 switch (ctrl->id) { 1218 switch (ctrl->id) {
1219 case V4L2_CID_CONTRAST: 1219 case V4L2_CID_CONTRAST:
1220 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x08, val); 1220 tm6000_set_reg(dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, val);
1221 return 0; 1221 return 0;
1222 case V4L2_CID_BRIGHTNESS: 1222 case V4L2_CID_BRIGHTNESS:
1223 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x09, val); 1223 tm6000_set_reg(dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, val);
1224 return 0; 1224 return 0;
1225 case V4L2_CID_SATURATION: 1225 case V4L2_CID_SATURATION:
1226 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0a, val); 1226 tm6000_set_reg(dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, val);
1227 return 0; 1227 return 0;
1228 case V4L2_CID_HUE: 1228 case V4L2_CID_HUE:
1229 tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0b, val); 1229 tm6000_set_reg(dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, val);
1230 return 0; 1230 return 0;
1231 } 1231 }
1232 return -EINVAL; 1232 return -EINVAL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 01:39:59 -0400