diff options
Diffstat (limited to 'drivers/staging/tm6000/tm6000-regs.h')
| -rw-r--r-- | drivers/staging/tm6000/tm6000-regs.h | 598 |
1 files changed, 598 insertions, 0 deletions
diff --git a/drivers/staging/tm6000/tm6000-regs.h b/drivers/staging/tm6000/tm6000-regs.h new file mode 100644 index 00000000000..5375a834737 --- /dev/null +++ b/drivers/staging/tm6000/tm6000-regs.h | |||
| @@ -0,0 +1,598 @@ | |||
| 1 | /* | ||
| 2 | * tm6000-regs.h - driver for TM5600/TM6000/TM6010 USB video capture devices | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006-2007 Mauro Carvalho Chehab <mchehab@infradead.org> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation version 2 | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Define TV Master TM5600/TM6000/TM6010 Request codes | ||
| 22 | */ | ||
| 23 | #define REQ_00_SET_IR_VALUE 0 | ||
| 24 | #define REQ_01_SET_WAKEUP_IRCODE 1 | ||
| 25 | #define REQ_02_GET_IR_CODE 2 | ||
| 26 | #define REQ_03_SET_GET_MCU_PIN 3 | ||
| 27 | #define REQ_04_EN_DISABLE_MCU_INT 4 | ||
| 28 | #define REQ_05_SET_GET_USBREG 5 | ||
| 29 | /* Write: RegNum, Value, 0 */ | ||
| 30 | /* Read : RegNum, Value, 1, RegStatus */ | ||
| 31 | #define REQ_06_SET_GET_USBREG_BIT 6 | ||
| 32 | #define REQ_07_SET_GET_AVREG 7 | ||
| 33 | /* Write: RegNum, Value, 0 */ | ||
| 34 | /* Read : RegNum, Value, 1, RegStatus */ | ||
| 35 | #define REQ_08_SET_GET_AVREG_BIT 8 | ||
| 36 | #define REQ_09_SET_GET_TUNER_FQ 9 | ||
| 37 | #define REQ_10_SET_TUNER_SYSTEM 10 | ||
| 38 | #define REQ_11_SET_EEPROM_ADDR 11 | ||
| 39 | #define REQ_12_SET_GET_EEPROMBYTE 12 | ||
| 40 | #define REQ_13_GET_EEPROM_SEQREAD 13 | ||
| 41 | #define REQ_14_SET_GET_I2C_WR2_RDN 14 | ||
| 42 | #define REQ_15_SET_GET_I2CBYTE 15 | ||
| 43 | /* Write: Subaddr, Slave Addr, value, 0 */ | ||
| 44 | /* Read : Subaddr, Slave Addr, value, 1 */ | ||
| 45 | #define REQ_16_SET_GET_I2C_WR1_RDN 16 | ||
| 46 | /* Subaddr, Slave Addr, 0, length */ | ||
| 47 | #define REQ_17_SET_GET_I2CFP 17 | ||
| 48 | /* Write: Slave Addr, register, value */ | ||
| 49 | /* Read : Slave Addr, register, 2, data */ | ||
| 50 | #define REQ_20_DATA_TRANSFER 20 | ||
| 51 | #define REQ_30_I2C_WRITE 30 | ||
| 52 | #define REQ_31_I2C_READ 31 | ||
| 53 | #define REQ_35_AFTEK_TUNER_READ 35 | ||
| 54 | #define REQ_40_GET_VERSION 40 | ||
| 55 | #define REQ_50_SET_START 50 | ||
| 56 | #define REQ_51_SET_STOP 51 | ||
| 57 | #define REQ_52_TRANSMIT_DATA 52 | ||
| 58 | #define REQ_53_SPI_INITIAL 53 | ||
| 59 | #define REQ_54_SPI_SETSTART 54 | ||
| 60 | #define REQ_55_SPI_INOUTDATA 55 | ||
| 61 | #define REQ_56_SPI_SETSTOP 56 | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Define TV Master TM5600/TM6000/TM6010 GPIO lines | ||
| 65 | */ | ||
| 66 | |||
| 67 | #define TM6000_GPIO_CLK 0x101 | ||
| 68 | #define TM6000_GPIO_DATA 0x100 | ||
| 69 | |||
| 70 | #define TM6000_GPIO_1 0x102 | ||
| 71 | #define TM6000_GPIO_2 0x103 | ||
| 72 | #define TM6000_GPIO_3 0x104 | ||
| 73 | #define TM6000_GPIO_4 0x300 | ||
| 74 | #define TM6000_GPIO_5 0x301 | ||
| 75 | #define TM6000_GPIO_6 0x304 | ||
| 76 | #define TM6000_GPIO_7 0x305 | ||
| 77 | |||
| 78 | /* tm6010 defines GPIO with different values */ | ||
| 79 | #define TM6010_GPIO_0 0x0102 | ||
| 80 | #define TM6010_GPIO_1 0x0103 | ||
| 81 | #define TM6010_GPIO_2 0x0104 | ||
| 82 | #define TM6010_GPIO_3 0x0105 | ||
| 83 | #define TM6010_GPIO_4 0x0106 | ||
| 84 | #define TM6010_GPIO_5 0x0107 | ||
| 85 | #define TM6010_GPIO_6 0x0300 | ||
| 86 | #define TM6010_GPIO_7 0x0301 | ||
| 87 | #define TM6010_GPIO_9 0x0305 | ||
| 88 | /* | ||
| 89 | * Define TV Master TM5600/TM6000/TM6010 URB message codes and length | ||
| 90 | */ | ||
| 91 | |||
| 92 | enum { | ||
| 93 | TM6000_URB_MSG_VIDEO=1, | ||
| 94 | TM6000_URB_MSG_AUDIO, | ||
| 95 | TM6000_URB_MSG_VBI, | ||
| 96 | TM6000_URB_MSG_PTS, | ||
| 97 | TM6000_URB_MSG_ERR, | ||
| 98 | }; | ||
| 99 | |||
| 100 | /* Define specific TM6000 Video decoder registers */ | ||
| 101 | #define TM6000_REQ07_RD8_TEST_SEL 0x07, 0xd8 | ||
| 102 | #define TM6000_REQ07_RD9_A_SIM_SEL 0x07, 0xd9 | ||
| 103 | #define TM6000_REQ07_RDA_CLK_SEL 0x07, 0xda | ||
| 104 | #define TM6000_REQ07_RDB_OUT_SEL 0x07, 0xdb | ||
| 105 | #define TM6000_REQ07_RDC_NSEL_I2S 0x07, 0xdc | ||
| 106 | #define TM6000_REQ07_RDD_GPIO2_MDRV 0x07, 0xdd | ||
| 107 | #define TM6000_REQ07_RDE_GPIO1_MDRV 0x07, 0xde | ||
| 108 | #define TM6000_REQ07_RDF_PWDOWN_ACLK 0x07, 0xdf | ||
| 109 | #define TM6000_REQ07_RE0_VADC_REF_CTL 0x07, 0xe0 | ||
| 110 | #define TM6000_REQ07_RE1_VADC_DACLIMP 0x07, 0xe1 | ||
| 111 | #define TM6000_REQ07_RE2_VADC_STATUS_CTL 0x07, 0xe2 | ||
| 112 | #define TM6000_REQ07_RE3_VADC_INP_LPF_SEL1 0x07, 0xe3 | ||
| 113 | #define TM6000_REQ07_RE4_VADC_TARGET1 0x07, 0xe4 | ||
| 114 | #define TM6000_REQ07_RE5_VADC_INP_LPF_SEL2 0x07, 0xe5 | ||
| 115 | #define TM6000_REQ07_RE6_VADC_TARGET2 0x07, 0xe6 | ||
| 116 | #define TM6000_REQ07_RE7_VADC_AGAIN_CTL 0x07, 0xe7 | ||
| 117 | #define TM6000_REQ07_RE8_VADC_PWDOWN_CTL 0x07, 0xe8 | ||
| 118 | #define TM6000_REQ07_RE9_VADC_INPUT_CTL1 0x07, 0xe9 | ||
| 119 | #define TM6000_REQ07_REA_VADC_INPUT_CTL2 0x07, 0xea | ||
| 120 | #define TM6000_REQ07_REB_VADC_AADC_MODE 0x07, 0xeb | ||
| 121 | #define TM6000_REQ07_REC_VADC_AADC_LVOL 0x07, 0xec | ||
| 122 | #define TM6000_REQ07_RED_VADC_AADC_RVOL 0x07, 0xed | ||
| 123 | #define TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL 0x07, 0xee | ||
| 124 | #define TM6000_REQ07_REF_VADC_GAIN_MAP_CTL 0x07, 0xef | ||
| 125 | #define TM6000_REQ07_RFD_BIST_ERR_VST_LOW 0x07, 0xfd | ||
| 126 | #define TM6000_REQ07_RFE_BIST_ERR_VST_HIGH 0x07, 0xfe | ||
| 127 | |||
| 128 | /* Define TM6000/TM6010 Video decoder registers */ | ||
| 129 | #define TM6010_REQ07_R00_VIDEO_CONTROL0 0x07, 0x00 | ||
| 130 | #define TM6010_REQ07_R01_VIDEO_CONTROL1 0x07, 0x01 | ||
| 131 | #define TM6010_REQ07_R02_VIDEO_CONTROL2 0x07, 0x02 | ||
| 132 | #define TM6010_REQ07_R03_YC_SEP_CONTROL 0x07, 0x03 | ||
| 133 | #define TM6010_REQ07_R04_LUMA_HAGC_CONTROL 0x07, 0x04 | ||
| 134 | #define TM6010_REQ07_R05_NOISE_THRESHOLD 0x07, 0x05 | ||
| 135 | #define TM6010_REQ07_R06_AGC_GATE_THRESHOLD 0x07, 0x06 | ||
| 136 | #define TM6010_REQ07_R07_OUTPUT_CONTROL 0x07, 0x07 | ||
| 137 | #define TM6010_REQ07_R08_LUMA_CONTRAST_ADJ 0x07, 0x08 | ||
| 138 | #define TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ 0x07, 0x09 | ||
| 139 | #define TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ 0x07, 0x0a | ||
| 140 | #define TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ 0x07, 0x0b | ||
| 141 | #define TM6010_REQ07_R0C_CHROMA_AGC_CONTROL 0x07, 0x0c | ||
| 142 | #define TM6010_REQ07_R0D_CHROMA_KILL_LEVEL 0x07, 0x0d | ||
| 143 | #define TM6010_REQ07_R0F_CHROMA_AUTO_POSITION 0x07, 0x0f | ||
| 144 | #define TM6010_REQ07_R10_AGC_PEAK_NOMINAL 0x07, 0x10 | ||
| 145 | #define TM6010_REQ07_R11_AGC_PEAK_CONTROL 0x07, 0x11 | ||
| 146 | #define TM6010_REQ07_R12_AGC_GATE_STARTH 0x07, 0x12 | ||
| 147 | #define TM6010_REQ07_R13_AGC_GATE_STARTL 0x07, 0x13 | ||
| 148 | #define TM6010_REQ07_R14_AGC_GATE_WIDTH 0x07, 0x14 | ||
| 149 | #define TM6010_REQ07_R15_AGC_BP_DELAY 0x07, 0x15 | ||
| 150 | #define TM6010_REQ07_R16_LOCK_COUNT 0x07, 0x16 | ||
| 151 | #define TM6010_REQ07_R17_HLOOP_MAXSTATE 0x07, 0x17 | ||
| 152 | #define TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3 0x07, 0x18 | ||
| 153 | #define TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2 0x07, 0x19 | ||
| 154 | #define TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1 0x07, 0x1a | ||
| 155 | #define TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0 0x07, 0x1b | ||
| 156 | #define TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3 0x07, 0x1c | ||
| 157 | #define TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2 0x07, 0x1d | ||
| 158 | #define TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1 0x07, 0x1e | ||
| 159 | #define TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0 0x07, 0x1f | ||
| 160 | #define TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME 0x07, 0x20 | ||
| 161 | #define TM6010_REQ07_R21_HSYNC_PHASE_OFFSET 0x07, 0x21 | ||
| 162 | #define TM6010_REQ07_R22_HSYNC_PLL_START_TIME 0x07, 0x22 | ||
| 163 | #define TM6010_REQ07_R23_HSYNC_PLL_END_TIME 0x07, 0x23 | ||
| 164 | #define TM6010_REQ07_R24_HSYNC_TIP_START_TIME 0x07, 0x24 | ||
| 165 | #define TM6010_REQ07_R25_HSYNC_TIP_END_TIME 0x07, 0x25 | ||
| 166 | #define TM6010_REQ07_R26_HSYNC_RISING_EDGE_START 0x07, 0x26 | ||
| 167 | #define TM6010_REQ07_R27_HSYNC_RISING_EDGE_END 0x07, 0x27 | ||
| 168 | #define TM6010_REQ07_R28_BACKPORCH_START 0x07, 0x28 | ||
| 169 | #define TM6010_REQ07_R29_BACKPORCH_END 0x07, 0x29 | ||
| 170 | #define TM6010_REQ07_R2A_HSYNC_FILTER_START 0x07, 0x2a | ||
| 171 | #define TM6010_REQ07_R2B_HSYNC_FILTER_END 0x07, 0x2b | ||
| 172 | #define TM6010_REQ07_R2C_CHROMA_BURST_START 0x07, 0x2c | ||
| 173 | #define TM6010_REQ07_R2D_CHROMA_BURST_END 0x07, 0x2d | ||
| 174 | #define TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART 0x07, 0x2e | ||
| 175 | #define TM6010_REQ07_R2F_ACTIVE_VIDEO_HWIDTH 0x07, 0x2f | ||
| 176 | #define TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART 0x07, 0x30 | ||
| 177 | #define TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT 0x07, 0x31 | ||
| 178 | #define TM6010_REQ07_R32_VSYNC_HLOCK_MIN 0x07, 0x32 | ||
| 179 | #define TM6010_REQ07_R33_VSYNC_HLOCK_MAX 0x07, 0x33 | ||
| 180 | #define TM6010_REQ07_R34_VSYNC_AGC_MIN 0x07, 0x34 | ||
| 181 | #define TM6010_REQ07_R35_VSYNC_AGC_MAX 0x07, 0x35 | ||
| 182 | #define TM6010_REQ07_R36_VSYNC_VBI_MIN 0x07, 0x36 | ||
| 183 | #define TM6010_REQ07_R37_VSYNC_VBI_MAX 0x07, 0x37 | ||
| 184 | #define TM6010_REQ07_R38_VSYNC_THRESHOLD 0x07, 0x38 | ||
| 185 | #define TM6010_REQ07_R39_VSYNC_TIME_CONSTANT 0x07, 0x39 | ||
| 186 | #define TM6010_REQ07_R3A_STATUS1 0x07, 0x3a | ||
| 187 | #define TM6010_REQ07_R3B_STATUS2 0x07, 0x3b | ||
| 188 | #define TM6010_REQ07_R3C_STATUS3 0x07, 0x3c | ||
| 189 | #define TM6010_REQ07_R3F_RESET 0x07, 0x3f | ||
| 190 | #define TM6010_REQ07_R40_TELETEXT_VBI_CODE0 0x07, 0x40 | ||
| 191 | #define TM6010_REQ07_R41_TELETEXT_VBI_CODE1 0x07, 0x41 | ||
| 192 | #define TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL 0x07, 0x42 | ||
| 193 | #define TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7 0x07, 0x43 | ||
| 194 | #define TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8 0x07, 0x44 | ||
| 195 | #define TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9 0x07, 0x45 | ||
| 196 | #define TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10 0x07, 0x46 | ||
| 197 | #define TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11 0x07, 0x47 | ||
| 198 | #define TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12 0x07, 0x48 | ||
| 199 | #define TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13 0x07, 0x49 | ||
| 200 | #define TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14 0x07, 0x4a | ||
| 201 | #define TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15 0x07, 0x4b | ||
| 202 | #define TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16 0x07, 0x4c | ||
| 203 | #define TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17 0x07, 0x4d | ||
| 204 | #define TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18 0x07, 0x4e | ||
| 205 | #define TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19 0x07, 0x4f | ||
| 206 | #define TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20 0x07, 0x50 | ||
| 207 | #define TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21 0x07, 0x51 | ||
| 208 | #define TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22 0x07, 0x52 | ||
| 209 | #define TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23 0x07, 0x53 | ||
| 210 | #define TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES 0x07, 0x54 | ||
| 211 | #define TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN 0x07, 0x55 | ||
| 212 | #define TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN 0x07, 0x56 | ||
| 213 | #define TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN 0x07, 0x57 | ||
| 214 | #define TM6010_REQ07_R58_VBI_CAPTION_DTO1 0x07, 0x58 | ||
| 215 | #define TM6010_REQ07_R59_VBI_CAPTION_DTO0 0x07, 0x59 | ||
| 216 | #define TM6010_REQ07_R5A_VBI_TELETEXT_DTO1 0x07, 0x5a | ||
| 217 | #define TM6010_REQ07_R5B_VBI_TELETEXT_DTO0 0x07, 0x5b | ||
| 218 | #define TM6010_REQ07_R5C_VBI_WSS625_DTO1 0x07, 0x5c | ||
| 219 | #define TM6010_REQ07_R5D_VBI_WSS625_DTO0 0x07, 0x5d | ||
| 220 | #define TM6010_REQ07_R5E_VBI_CAPTION_FRAME_START 0x07, 0x5e | ||
| 221 | #define TM6010_REQ07_R5F_VBI_WSS625_FRAME_START 0x07, 0x5f | ||
| 222 | #define TM6010_REQ07_R60_TELETEXT_FRAME_START 0x07, 0x60 | ||
| 223 | #define TM6010_REQ07_R61_VBI_CCDATA1 0x07, 0x61 | ||
| 224 | #define TM6010_REQ07_R62_VBI_CCDATA2 0x07, 0x62 | ||
| 225 | #define TM6010_REQ07_R63_VBI_WSS625_DATA1 0x07, 0x63 | ||
| 226 | #define TM6010_REQ07_R64_VBI_WSS625_DATA2 0x07, 0x64 | ||
| 227 | #define TM6010_REQ07_R65_VBI_DATA_STATUS 0x07, 0x65 | ||
| 228 | #define TM6010_REQ07_R66_VBI_CAPTION_START 0x07, 0x66 | ||
| 229 | #define TM6010_REQ07_R67_VBI_WSS625_START 0x07, 0x67 | ||
| 230 | #define TM6010_REQ07_R68_VBI_TELETEXT_START 0x07, 0x68 | ||
| 231 | #define TM6010_REQ07_R70_HSYNC_DTO_INC_STATUS3 0x07, 0x70 | ||
| 232 | #define TM6010_REQ07_R71_HSYNC_DTO_INC_STATUS2 0x07, 0x71 | ||
| 233 | #define TM6010_REQ07_R72_HSYNC_DTO_INC_STATUS1 0x07, 0x72 | ||
| 234 | #define TM6010_REQ07_R73_HSYNC_DTO_INC_STATUS0 0x07, 0x73 | ||
| 235 | #define TM6010_REQ07_R74_CHROMA_DTO_INC_STATUS3 0x07, 0x74 | ||
| 236 | #define TM6010_REQ07_R75_CHROMA_DTO_INC_STATUS2 0x07, 0x75 | ||
| 237 | #define TM6010_REQ07_R76_CHROMA_DTO_INC_STATUS1 0x07, 0x76 | ||
| 238 | #define TM6010_REQ07_R77_CHROMA_DTO_INC_STATUS0 0x07, 0x77 | ||
| 239 | #define TM6010_REQ07_R78_AGC_AGAIN_STATUS 0x07, 0x78 | ||
| 240 | #define TM6010_REQ07_R79_AGC_DGAIN_STATUS 0x07, 0x79 | ||
| 241 | #define TM6010_REQ07_R7A_CHROMA_MAG_STATUS 0x07, 0x7a | ||
| 242 | #define TM6010_REQ07_R7B_CHROMA_GAIN_STATUS1 0x07, 0x7b | ||
| 243 | #define TM6010_REQ07_R7C_CHROMA_GAIN_STATUS0 0x07, 0x7c | ||
| 244 | #define TM6010_REQ07_R7D_CORDIC_FREQ_STATUS 0x07, 0x7d | ||
| 245 | #define TM6010_REQ07_R7F_STATUS_NOISE 0x07, 0x7f | ||
| 246 | #define TM6010_REQ07_R80_COMB_FILTER_TRESHOLD 0x07, 0x80 | ||
| 247 | #define TM6010_REQ07_R82_COMB_FILTER_CONFIG 0x07, 0x82 | ||
| 248 | #define TM6010_REQ07_R83_CHROMA_LOCK_CONFIG 0x07, 0x83 | ||
| 249 | #define TM6010_REQ07_R84_NOISE_NTSC_C 0x07, 0x84 | ||
| 250 | #define TM6010_REQ07_R85_NOISE_PAL_C 0x07, 0x85 | ||
| 251 | #define TM6010_REQ07_R86_NOISE_PHASE_C 0x07, 0x86 | ||
| 252 | #define TM6010_REQ07_R87_NOISE_PHASE_Y 0x07, 0x87 | ||
| 253 | #define TM6010_REQ07_R8A_CHROMA_LOOPFILTER_STATE 0x07, 0x8a | ||
| 254 | #define TM6010_REQ07_R8B_CHROMA_HRESAMPLER 0x07, 0x8b | ||
| 255 | #define TM6010_REQ07_R8D_CPUMP_DELAY_ADJ 0x07, 0x8d | ||
| 256 | #define TM6010_REQ07_R8E_CPUMP_ADJ 0x07, 0x8e | ||
| 257 | #define TM6010_REQ07_R8F_CPUMP_DELAY 0x07, 0x8f | ||
| 258 | |||
| 259 | /* Define TM6000/TM6010 Miscellaneous registers */ | ||
| 260 | #define TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE 0x07, 0xc0 | ||
| 261 | #define TM6010_REQ07_RC1_TRESHOLD 0x07, 0xc1 | ||
| 262 | #define TM6010_REQ07_RC2_HSYNC_WIDTH 0x07, 0xc2 | ||
| 263 | #define TM6010_REQ07_RC3_HSTART1 0x07, 0xc3 | ||
| 264 | #define TM6010_REQ07_RC4_HSTART0 0x07, 0xc4 | ||
| 265 | #define TM6010_REQ07_RC5_HEND1 0x07, 0xc5 | ||
| 266 | #define TM6010_REQ07_RC6_HEND0 0x07, 0xc6 | ||
| 267 | #define TM6010_REQ07_RC7_VSTART1 0x07, 0xc7 | ||
| 268 | #define TM6010_REQ07_RC8_VSTART0 0x07, 0xc8 | ||
| 269 | #define TM6010_REQ07_RC9_VEND1 0x07, 0xc9 | ||
| 270 | #define TM6010_REQ07_RCA_VEND0 0x07, 0xca | ||
| 271 | #define TM6010_REQ07_RCB_DELAY 0x07, 0xcb | ||
| 272 | /* ONLY for TM6010 */ | ||
| 273 | #define TM6010_REQ07_RCC_ACTIVE_VIDEO_IF 0x07, 0xcc | ||
| 274 | #define TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL 0x07, 0xd0 | ||
| 275 | #define TM6010_REQ07_RD1_ADDR_FOR_REQ1 0x07, 0xd1 | ||
| 276 | #define TM6010_REQ07_RD2_ADDR_FOR_REQ2 0x07, 0xd2 | ||
| 277 | #define TM6010_REQ07_RD3_ADDR_FOR_REQ3 0x07, 0xd3 | ||
| 278 | #define TM6010_REQ07_RD4_ADDR_FOR_REQ4 0x07, 0xd4 | ||
| 279 | #define TM6010_REQ07_RD5_POWERSAVE 0x07, 0xd5 | ||
| 280 | #define TM6010_REQ07_RD6_ENDP_REQ1_REQ2 0x07, 0xd6 | ||
| 281 | #define TM6010_REQ07_RD7_ENDP_REQ3_REQ4 0x07, 0xd7 | ||
| 282 | /* ONLY for TM6010 */ | ||
| 283 | #define TM6010_REQ07_RD8_IR 0x07, 0xd8 | ||
| 284 | /* ONLY for TM6010 */ | ||
| 285 | #define TM6010_REQ07_RD8_IR_BSIZE 0x07, 0xd9 | ||
| 286 | /* ONLY for TM6010 */ | ||
| 287 | #define TM6010_REQ07_RD8_IR_WAKEUP_SEL 0x07, 0xda | ||
| 288 | /* ONLY for TM6010 */ | ||
| 289 | #define TM6010_REQ07_RD8_IR_WAKEUP_ADD 0x07, 0xdb | ||
| 290 | /* ONLY for TM6010 */ | ||
| 291 | #define TM6010_REQ07_RD8_IR_LEADER1 0x07, 0xdc | ||
| 292 | /* ONLY for TM6010 */ | ||
| 293 | #define TM6010_REQ07_RD8_IR_LEADER0 0x07, 0xdd | ||
| 294 | /* ONLY for TM6010 */ | ||
| 295 | #define TM6010_REQ07_RD8_IR_PULSE_CNT1 0x07, 0xde | ||
| 296 | /* ONLY for TM6010 */ | ||
| 297 | #define TM6010_REQ07_RD8_IR_PULSE_CNT0 0x07, 0xdf | ||
| 298 | /* ONLY for TM6010 */ | ||
| 299 | #define TM6010_REQ07_RE0_DVIDEO_SOURCE 0x07, 0xe0 | ||
| 300 | /* ONLY for TM6010 */ | ||
| 301 | #define TM6010_REQ07_RE0_DVIDEO_SOURCE_IF 0x07, 0xe1 | ||
| 302 | /* ONLY for TM6010 */ | ||
| 303 | #define TM6010_REQ07_RE2_OUT_SEL2 0x07, 0xe2 | ||
| 304 | /* ONLY for TM6010 */ | ||
| 305 | #define TM6010_REQ07_RE3_OUT_SEL1 0x07, 0xe3 | ||
| 306 | /* ONLY for TM6010 */ | ||
| 307 | #define TM6010_REQ07_RE4_OUT_SEL0 0x07, 0xe4 | ||
| 308 | /* ONLY for TM6010 */ | ||
| 309 | #define TM6010_REQ07_RE5_REMOTE_WAKEUP 0x07, 0xe5 | ||
| 310 | /* ONLY for TM6010 */ | ||
| 311 | #define TM6010_REQ07_RE7_PUB_GPIO 0x07, 0xe7 | ||
| 312 | /* ONLY for TM6010 */ | ||
| 313 | #define TM6010_REQ07_RE8_TYPESEL_MOS_I2S 0x07, 0xe8 | ||
| 314 | /* ONLY for TM6010 */ | ||
| 315 | #define TM6010_REQ07_RE9_TYPESEL_MOS_TS 0x07, 0xe9 | ||
| 316 | /* ONLY for TM6010 */ | ||
| 317 | #define TM6010_REQ07_REA_TYPESEL_MOS_CCIR 0x07, 0xea | ||
| 318 | /* ONLY for TM6010 */ | ||
| 319 | #define TM6010_REQ07_RF0_BIST_CRC_RESULT0 0x07, 0xf0 | ||
| 320 | /* ONLY for TM6010 */ | ||
| 321 | #define TM6010_REQ07_RF1_BIST_CRC_RESULT1 0x07, 0xf1 | ||
| 322 | /* ONLY for TM6010 */ | ||
| 323 | #define TM6010_REQ07_RF2_BIST_CRC_RESULT2 0x07, 0xf2 | ||
| 324 | /* ONLY for TM6010 */ | ||
| 325 | #define TM6010_REQ07_RF3_BIST_CRC_RESULT3 0x07, 0xf3 | ||
| 326 | /* ONLY for TM6010 */ | ||
| 327 | #define TM6010_REQ07_RF4_BIST_ERR_VST2 0x07, 0xf4 | ||
| 328 | /* ONLY for TM6010 */ | ||
| 329 | #define TM6010_REQ07_RF5_BIST_ERR_VST1 0x07, 0xf5 | ||
| 330 | /* ONLY for TM6010 */ | ||
| 331 | #define TM6010_REQ07_RF6_BIST_ERR_VST0 0x07, 0xf6 | ||
| 332 | /* ONLY for TM6010 */ | ||
| 333 | #define TM6010_REQ07_RF7_BIST 0x07, 0xf7 | ||
| 334 | /* ONLY for TM6010 */ | ||
| 335 | #define TM6010_REQ07_RFE_POWER_DOWN 0x07, 0xfe | ||
| 336 | #define TM6010_REQ07_RFF_SOFT_RESET 0x07, 0xff | ||
| 337 | |||
| 338 | /* Define TM6000/TM6010 USB registers */ | ||
| 339 | #define TM6010_REQ05_R00_MAIN_CTRL 0x05, 0x00 | ||
| 340 | #define TM6010_REQ05_R01_DEVADDR 0x05, 0x01 | ||
| 341 | #define TM6010_REQ05_R02_TEST 0x05, 0x02 | ||
| 342 | #define TM6010_REQ05_R04_SOFN0 0x05, 0x04 | ||
| 343 | #define TM6010_REQ05_R05_SOFN1 0x05, 0x05 | ||
| 344 | #define TM6010_REQ05_R06_SOFTM0 0x05, 0x06 | ||
| 345 | #define TM6010_REQ05_R07_SOFTM1 0x05, 0x07 | ||
| 346 | #define TM6010_REQ05_R08_PHY_TEST 0x05, 0x08 | ||
| 347 | #define TM6010_REQ05_R09_VCTL 0x05, 0x09 | ||
| 348 | #define TM6010_REQ05_R0A_VSTA 0x05, 0x0a | ||
| 349 | #define TM6010_REQ05_R0B_CX_CFG 0x05, 0x0b | ||
| 350 | #define TM6010_REQ05_R0C_ENDP0_REG0 0x05, 0x0c | ||
| 351 | #define TM6010_REQ05_R10_GMASK 0x05, 0x10 | ||
| 352 | #define TM6010_REQ05_R11_IMASK0 0x05, 0x11 | ||
| 353 | #define TM6010_REQ05_R12_IMASK1 0x05, 0x12 | ||
| 354 | #define TM6010_REQ05_R13_IMASK2 0x05, 0x13 | ||
| 355 | #define TM6010_REQ05_R14_IMASK3 0x05, 0x14 | ||
| 356 | #define TM6010_REQ05_R15_IMASK4 0x05, 0x15 | ||
| 357 | #define TM6010_REQ05_R16_IMASK5 0x05, 0x16 | ||
| 358 | #define TM6010_REQ05_R17_IMASK6 0x05, 0x17 | ||
| 359 | #define TM6010_REQ05_R18_IMASK7 0x05, 0x18 | ||
| 360 | #define TM6010_REQ05_R19_ZEROP0 0x05, 0x19 | ||
| 361 | #define TM6010_REQ05_R1A_ZEROP1 0x05, 0x1a | ||
| 362 | #define TM6010_REQ05_R1C_FIFO_EMP0 0x05, 0x1c | ||
| 363 | #define TM6010_REQ05_R1D_FIFO_EMP1 0x05, 0x1d | ||
| 364 | #define TM6010_REQ05_R20_IRQ_GROUP 0x05, 0x20 | ||
| 365 | #define TM6010_REQ05_R21_IRQ_SOURCE0 0x05, 0x21 | ||
| 366 | #define TM6010_REQ05_R22_IRQ_SOURCE1 0x05, 0x22 | ||
| 367 | #define TM6010_REQ05_R23_IRQ_SOURCE2 0x05, 0x23 | ||
| 368 | #define TM6010_REQ05_R24_IRQ_SOURCE3 0x05, 0x24 | ||
| 369 | #define TM6010_REQ05_R25_IRQ_SOURCE4 0x05, 0x25 | ||
| 370 | #define TM6010_REQ05_R26_IRQ_SOURCE5 0x05, 0x26 | ||
| 371 | #define TM6010_REQ05_R27_IRQ_SOURCE6 0x05, 0x27 | ||
| 372 | #define TM6010_REQ05_R28_IRQ_SOURCE7 0x05, 0x28 | ||
| 373 | #define TM6010_REQ05_R29_SEQ_ERR0 0x05, 0x29 | ||
| 374 | #define TM6010_REQ05_R2A_SEQ_ERR1 0x05, 0x2a | ||
| 375 | #define TM6010_REQ05_R2B_SEQ_ABORT0 0x05, 0x2b | ||
| 376 | #define TM6010_REQ05_R2C_SEQ_ABORT1 0x05, 0x2c | ||
| 377 | #define TM6010_REQ05_R2D_TX_ZERO0 0x05, 0x2d | ||
| 378 | #define TM6010_REQ05_R2E_TX_ZERO1 0x05, 0x2e | ||
| 379 | #define TM6010_REQ05_R2F_IDLE_CNT 0x05, 0x2f | ||
| 380 | #define TM6010_REQ05_R30_FNO_P1 0x05, 0x30 | ||
| 381 | #define TM6010_REQ05_R31_FNO_P2 0x05, 0x31 | ||
| 382 | #define TM6010_REQ05_R32_FNO_P3 0x05, 0x32 | ||
| 383 | #define TM6010_REQ05_R33_FNO_P4 0x05, 0x33 | ||
| 384 | #define TM6010_REQ05_R34_FNO_P5 0x05, 0x34 | ||
| 385 | #define TM6010_REQ05_R35_FNO_P6 0x05, 0x35 | ||
| 386 | #define TM6010_REQ05_R36_FNO_P7 0x05, 0x36 | ||
| 387 | #define TM6010_REQ05_R37_FNO_P8 0x05, 0x37 | ||
| 388 | #define TM6010_REQ05_R38_FNO_P9 0x05, 0x38 | ||
| 389 | #define TM6010_REQ05_R30_FNO_P10 0x05, 0x39 | ||
| 390 | #define TM6010_REQ05_R30_FNO_P11 0x05, 0x3a | ||
| 391 | #define TM6010_REQ05_R30_FNO_P12 0x05, 0x3b | ||
| 392 | #define TM6010_REQ05_R30_FNO_P13 0x05, 0x3c | ||
| 393 | #define TM6010_REQ05_R30_FNO_P14 0x05, 0x3d | ||
| 394 | #define TM6010_REQ05_R30_FNO_P15 0x05, 0x3e | ||
| 395 | #define TM6010_REQ05_R40_IN_MAXPS_LOW1 0x05, 0x40 | ||
| 396 | #define TM6010_REQ05_R41_IN_MAXPS_HIGH1 0x05, 0x41 | ||
| 397 | #define TM6010_REQ05_R42_IN_MAXPS_LOW2 0x05, 0x42 | ||
| 398 | #define TM6010_REQ05_R43_IN_MAXPS_HIGH2 0x05, 0x43 | ||
| 399 | #define TM6010_REQ05_R44_IN_MAXPS_LOW3 0x05, 0x44 | ||
| 400 | #define TM6010_REQ05_R45_IN_MAXPS_HIGH3 0x05, 0x45 | ||
| 401 | #define TM6010_REQ05_R46_IN_MAXPS_LOW4 0x05, 0x46 | ||
| 402 | #define TM6010_REQ05_R47_IN_MAXPS_HIGH4 0x05, 0x47 | ||
| 403 | #define TM6010_REQ05_R48_IN_MAXPS_LOW5 0x05, 0x48 | ||
| 404 | #define TM6010_REQ05_R49_IN_MAXPS_HIGH5 0x05, 0x49 | ||
| 405 | #define TM6010_REQ05_R4A_IN_MAXPS_LOW6 0x05, 0x4a | ||
| 406 | #define TM6010_REQ05_R4B_IN_MAXPS_HIGH6 0x05, 0x4b | ||
| 407 | #define TM6010_REQ05_R4C_IN_MAXPS_LOW7 0x05, 0x4c | ||
| 408 | #define TM6010_REQ05_R4D_IN_MAXPS_HIGH7 0x05, 0x4d | ||
| 409 | #define TM6010_REQ05_R4E_IN_MAXPS_LOW8 0x05, 0x4e | ||
| 410 | #define TM6010_REQ05_R4F_IN_MAXPS_HIGH8 0x05, 0x4f | ||
| 411 | #define TM6010_REQ05_R50_IN_MAXPS_LOW9 0x05, 0x50 | ||
| 412 | #define TM6010_REQ05_R51_IN_MAXPS_HIGH9 0x05, 0x51 | ||
| 413 | #define TM6010_REQ05_R40_IN_MAXPS_LOW10 0x05, 0x52 | ||
| 414 | #define TM6010_REQ05_R41_IN_MAXPS_HIGH10 0x05, 0x53 | ||
| 415 | #define TM6010_REQ05_R40_IN_MAXPS_LOW11 0x05, 0x54 | ||
| 416 | #define TM6010_REQ05_R41_IN_MAXPS_HIGH11 0x05, 0x55 | ||
| 417 | #define TM6010_REQ05_R40_IN_MAXPS_LOW12 0x05, 0x56 | ||
| 418 | #define TM6010_REQ05_R41_IN_MAXPS_HIGH12 0x05, 0x57 | ||
| 419 | #define TM6010_REQ05_R40_IN_MAXPS_LOW13 0x05, 0x58 | ||
| 420 | #define TM6010_REQ05_R41_IN_MAXPS_HIGH13 0x05, 0x59 | ||
| 421 | #define TM6010_REQ05_R40_IN_MAXPS_LOW14 0x05, 0x5a | ||
| 422 | #define TM6010_REQ05_R41_IN_MAXPS_HIGH14 0x05, 0x5b | ||
| 423 | #define TM6010_REQ05_R40_IN_MAXPS_LOW15 0x05, 0x5c | ||
| 424 | #define TM6010_REQ05_R41_IN_MAXPS_HIGH15 0x05, 0x5d | ||
| 425 | #define TM6010_REQ05_R60_OUT_MAXPS_LOW1 0x05, 0x60 | ||
| 426 | #define TM6010_REQ05_R61_OUT_MAXPS_HIGH1 0x05, 0x61 | ||
| 427 | #define TM6010_REQ05_R62_OUT_MAXPS_LOW2 0x05, 0x62 | ||
| 428 | #define TM6010_REQ05_R63_OUT_MAXPS_HIGH2 0x05, 0x63 | ||
| 429 | #define TM6010_REQ05_R64_OUT_MAXPS_LOW3 0x05, 0x64 | ||
| 430 | #define TM6010_REQ05_R65_OUT_MAXPS_HIGH3 0x05, 0x65 | ||
| 431 | #define TM6010_REQ05_R66_OUT_MAXPS_LOW4 0x05, 0x66 | ||
| 432 | #define TM6010_REQ05_R67_OUT_MAXPS_HIGH4 0x05, 0x67 | ||
| 433 | #define TM6010_REQ05_R68_OUT_MAXPS_LOW5 0x05, 0x68 | ||
| 434 | #define TM6010_REQ05_R69_OUT_MAXPS_HIGH5 0x05, 0x69 | ||
| 435 | #define TM6010_REQ05_R6A_OUT_MAXPS_LOW6 0x05, 0x6a | ||
| 436 | #define TM6010_REQ05_R6B_OUT_MAXPS_HIGH6 0x05, 0x6b | ||
| 437 | #define TM6010_REQ05_R6C_OUT_MAXPS_LOW7 0x05, 0x6c | ||
| 438 | #define TM6010_REQ05_R6D_OUT_MAXPS_HIGH7 0x05, 0x6d | ||
| 439 | #define TM6010_REQ05_R6E_OUT_MAXPS_LOW8 0x05, 0x6e | ||
| 440 | #define TM6010_REQ05_R6F_OUT_MAXPS_HIGH8 0x05, 0x6f | ||
| 441 | #define TM6010_REQ05_R70_OUT_MAXPS_LOW9 0x05, 0x70 | ||
| 442 | #define TM6010_REQ05_R71_OUT_MAXPS_HIGH9 0x05, 0x71 | ||
| 443 | #define TM6010_REQ05_R60_OUT_MAXPS_LOW10 0x05, 0x72 | ||
| 444 | #define TM6010_REQ05_R61_OUT_MAXPS_HIGH10 0x05, 0x73 | ||
| 445 | #define TM6010_REQ05_R60_OUT_MAXPS_LOW11 0x05, 0x74 | ||
| 446 | #define TM6010_REQ05_R61_OUT_MAXPS_HIGH11 0x05, 0x75 | ||
| 447 | #define TM6010_REQ05_R60_OUT_MAXPS_LOW12 0x05, 0x76 | ||
| 448 | #define TM6010_REQ05_R61_OUT_MAXPS_HIGH12 0x05, 0x77 | ||
| 449 | #define TM6010_REQ05_R60_OUT_MAXPS_LOW13 0x05, 0x78 | ||
| 450 | #define TM6010_REQ05_R61_OUT_MAXPS_HIGH13 0x05, 0x79 | ||
| 451 | #define TM6010_REQ05_R60_OUT_MAXPS_LOW14 0x05, 0x7a | ||
| 452 | #define TM6010_REQ05_R61_OUT_MAXPS_HIGH14 0x05, 0x7b | ||
| 453 | #define TM6010_REQ05_R60_OUT_MAXPS_LOW15 0x05, 0x7c | ||
| 454 | #define TM6010_REQ05_R61_OUT_MAXPS_HIGH15 0x05, 0x7d | ||
| 455 | #define TM6010_REQ05_R80_FIFO0 0x05, 0x80 | ||
| 456 | #define TM6010_REQ05_R81_FIFO1 0x05, 0x81 | ||
| 457 | #define TM6010_REQ05_R82_FIFO2 0x05, 0x82 | ||
| 458 | #define TM6010_REQ05_R83_FIFO3 0x05, 0x83 | ||
| 459 | #define TM6010_REQ05_R84_FIFO4 0x05, 0x84 | ||
| 460 | #define TM6010_REQ05_R85_FIFO5 0x05, 0x85 | ||
| 461 | #define TM6010_REQ05_R86_FIFO6 0x05, 0x86 | ||
| 462 | #define TM6010_REQ05_R87_FIFO7 0x05, 0x87 | ||
| 463 | #define TM6010_REQ05_R88_FIFO8 0x05, 0x88 | ||
| 464 | #define TM6010_REQ05_R89_FIFO9 0x05, 0x89 | ||
| 465 | #define TM6010_REQ05_R81_FIFO10 0x05, 0x8a | ||
| 466 | #define TM6010_REQ05_R81_FIFO11 0x05, 0x8b | ||
| 467 | #define TM6010_REQ05_R81_FIFO12 0x05, 0x8c | ||
| 468 | #define TM6010_REQ05_R81_FIFO13 0x05, 0x8d | ||
| 469 | #define TM6010_REQ05_R81_FIFO14 0x05, 0x8e | ||
| 470 | #define TM6010_REQ05_R81_FIFO15 0x05, 0x8f | ||
| 471 | #define TM6010_REQ05_R90_CFG_FIFO0 0x05, 0x90 | ||
| 472 | #define TM6010_REQ05_R91_CFG_FIFO1 0x05, 0x91 | ||
| 473 | #define TM6010_REQ05_R92_CFG_FIFO2 0x05, 0x92 | ||
| 474 | #define TM6010_REQ05_R93_CFG_FIFO3 0x05, 0x93 | ||
| 475 | #define TM6010_REQ05_R94_CFG_FIFO4 0x05, 0x94 | ||
| 476 | #define TM6010_REQ05_R95_CFG_FIFO5 0x05, 0x95 | ||
| 477 | #define TM6010_REQ05_R96_CFG_FIFO6 0x05, 0x96 | ||
| 478 | #define TM6010_REQ05_R97_CFG_FIFO7 0x05, 0x97 | ||
| 479 | #define TM6010_REQ05_R98_CFG_FIFO8 0x05, 0x98 | ||
| 480 | #define TM6010_REQ05_R99_CFG_FIFO9 0x05, 0x99 | ||
| 481 | #define TM6010_REQ05_R91_CFG_FIFO10 0x05, 0x9a | ||
| 482 | #define TM6010_REQ05_R91_CFG_FIFO11 0x05, 0x9b | ||
| 483 | #define TM6010_REQ05_R91_CFG_FIFO12 0x05, 0x9c | ||
| 484 | #define TM6010_REQ05_R91_CFG_FIFO13 0x05, 0x9d | ||
| 485 | #define TM6010_REQ05_R91_CFG_FIFO14 0x05, 0x9e | ||
| 486 | #define TM6010_REQ05_R91_CFG_FIFO15 0x05, 0x9f | ||
| 487 | #define TM6010_REQ05_RA0_CTL_FIFO0 0x05, 0xa0 | ||
| 488 | #define TM6010_REQ05_RA1_CTL_FIFO1 0x05, 0xa1 | ||
| 489 | #define TM6010_REQ05_RA2_CTL_FIFO2 0x05, 0xa2 | ||
| 490 | #define TM6010_REQ05_RA3_CTL_FIFO3 0x05, 0xa3 | ||
| 491 | #define TM6010_REQ05_RA4_CTL_FIFO4 0x05, 0xa4 | ||
| 492 | #define TM6010_REQ05_RA5_CTL_FIFO5 0x05, 0xa5 | ||
| 493 | #define TM6010_REQ05_RA6_CTL_FIFO6 0x05, 0xa6 | ||
| 494 | #define TM6010_REQ05_RA7_CTL_FIFO7 0x05, 0xa7 | ||
| 495 | #define TM6010_REQ05_RA8_CTL_FIFO8 0x05, 0xa8 | ||
| 496 | #define TM6010_REQ05_RA9_CTL_FIFO9 0x05, 0xa9 | ||
| 497 | #define TM6010_REQ05_RA1_CTL_FIFO10 0x05, 0xaa | ||
| 498 | #define TM6010_REQ05_RA1_CTL_FIFO11 0x05, 0xab | ||
| 499 | #define TM6010_REQ05_RA1_CTL_FIFO12 0x05, 0xac | ||
| 500 | #define TM6010_REQ05_RA1_CTL_FIFO13 0x05, 0xad | ||
| 501 | #define TM6010_REQ05_RA1_CTL_FIFO14 0x05, 0xae | ||
| 502 | #define TM6010_REQ05_RA1_CTL_FIFO15 0x05, 0xaf | ||
| 503 | #define TM6010_REQ05_RB0_BC_LOW_FIFO0 0x05, 0xb0 | ||
| 504 | #define TM6010_REQ05_RB1_BC_LOW_FIFO1 0x05, 0xb1 | ||
| 505 | #define TM6010_REQ05_RB2_BC_LOW_FIFO2 0x05, 0xb2 | ||
| 506 | #define TM6010_REQ05_RB3_BC_LOW_FIFO3 0x05, 0xb3 | ||
| 507 | #define TM6010_REQ05_RB4_BC_LOW_FIFO4 0x05, 0xb4 | ||
| 508 | #define TM6010_REQ05_RB5_BC_LOW_FIFO5 0x05, 0xb5 | ||
| 509 | #define TM6010_REQ05_RB6_BC_LOW_FIFO6 0x05, 0xb6 | ||
| 510 | #define TM6010_REQ05_RB7_BC_LOW_FIFO7 0x05, 0xb7 | ||
| 511 | #define TM6010_REQ05_RB8_BC_LOW_FIFO8 0x05, 0xb8 | ||
| 512 | #define TM6010_REQ05_RB9_BC_LOW_FIFO9 0x05, 0xb9 | ||
| 513 | #define TM6010_REQ05_RB1_BC_LOW_FIFO10 0x05, 0xba | ||
| 514 | #define TM6010_REQ05_RB1_BC_LOW_FIFO11 0x05, 0xbb | ||
| 515 | #define TM6010_REQ05_RB1_BC_LOW_FIFO12 0x05, 0xbc | ||
| 516 | #define TM6010_REQ05_RB1_BC_LOW_FIFO13 0x05, 0xbd | ||
| 517 | #define TM6010_REQ05_RB1_BC_LOW_FIFO14 0x05, 0xbe | ||
| 518 | #define TM6010_REQ05_RB1_BC_LOW_FIFO15 0x05, 0xbf | ||
| 519 | #define TM6010_REQ05_RC0_DATA_FIFO0 0x05, 0xc0 | ||
| 520 | #define TM6010_REQ05_RC4_DATA_FIFO1 0x05, 0xc4 | ||
| 521 | #define TM6010_REQ05_RC8_DATA_FIFO2 0x05, 0xc8 | ||
| 522 | #define TM6010_REQ05_RCC_DATA_FIFO3 0x05, 0xcc | ||
| 523 | #define TM6010_REQ05_RD0_DATA_FIFO4 0x05, 0xd0 | ||
| 524 | #define TM6010_REQ05_RD4_DATA_FIFO5 0x05, 0xd4 | ||
| 525 | #define TM6010_REQ05_RD8_DATA_FIFO6 0x05, 0xd8 | ||
| 526 | #define TM6010_REQ05_RDC_DATA_FIFO7 0x05, 0xdc | ||
| 527 | #define TM6010_REQ05_RE0_DATA_FIFO8 0x05, 0xe0 | ||
| 528 | #define TM6010_REQ05_RE4_DATA_FIFO9 0x05, 0xe4 | ||
| 529 | #define TM6010_REQ05_RC4_DATA_FIFO10 0x05, 0xe8 | ||
| 530 | #define TM6010_REQ05_RC4_DATA_FIFO11 0x05, 0xec | ||
| 531 | #define TM6010_REQ05_RC4_DATA_FIFO12 0x05, 0xf0 | ||
| 532 | #define TM6010_REQ05_RC4_DATA_FIFO13 0x05, 0xf4 | ||
| 533 | #define TM6010_REQ05_RC4_DATA_FIFO14 0x05, 0xf8 | ||
| 534 | #define TM6010_REQ05_RC4_DATA_FIFO15 0x05, 0xfc | ||
| 535 | |||
| 536 | /* Define TM6010 Audio decoder registers */ | ||
| 537 | /* This core available only in TM6010 */ | ||
| 538 | #define TM6010_REQ08_R00_A_VERSION 0x08, 0x00 | ||
| 539 | #define TM6010_REQ08_R01_A_INIT 0x08, 0x01 | ||
| 540 | #define TM6010_REQ08_R02_A_FIX_GAIN_CTRL 0x08, 0x02 | ||
| 541 | #define TM6010_REQ08_R03_A_AUTO_GAIN_CTRL 0x08, 0x03 | ||
| 542 | #define TM6010_REQ08_R04_A_SIF_AMP_CTRL 0x08, 0x04 | ||
| 543 | #define TM6010_REQ08_R05_A_STANDARD_MOD 0x08, 0x05 | ||
| 544 | #define TM6010_REQ08_R06_A_SOUND_MOD 0x08, 0x06 | ||
| 545 | #define TM6010_REQ08_R07_A_LEFT_VOL 0x08, 0x07 | ||
| 546 | #define TM6010_REQ08_R08_A_RIGHT_VOL 0x08, 0x08 | ||
| 547 | #define TM6010_REQ08_R09_A_MAIN_VOL 0x08, 0x09 | ||
| 548 | #define TM6010_REQ08_R0A_A_I2S_MOD 0x08, 0x0a | ||
| 549 | #define TM6010_REQ08_R0B_A_ASD_THRES1 0x08, 0x0b | ||
| 550 | #define TM6010_REQ08_R0C_A_ASD_THRES2 0x08, 0x0c | ||
| 551 | #define TM6010_REQ08_R0D_A_AMD_THRES 0x08, 0x0d | ||
| 552 | #define TM6010_REQ08_R0E_A_MONO_THRES1 0x08, 0x0e | ||
| 553 | #define TM6010_REQ08_R0F_A_MONO_THRES2 0x08, 0x0f | ||
| 554 | #define TM6010_REQ08_R10_A_MUTE_THRES1 0x08, 0x10 | ||
| 555 | #define TM6010_REQ08_R11_A_MUTE_THRES2 0x08, 0x11 | ||
| 556 | #define TM6010_REQ08_R12_A_AGC_U 0x08, 0x12 | ||
| 557 | #define TM6010_REQ08_R13_A_AGC_ERR_T 0x08, 0x13 | ||
| 558 | #define TM6010_REQ08_R14_A_AGC_GAIN_INIT 0x08, 0x14 | ||
| 559 | #define TM6010_REQ08_R15_A_AGC_STEP_THR 0x08, 0x15 | ||
| 560 | #define TM6010_REQ08_R16_A_AGC_GAIN_MAX 0x08, 0x16 | ||
| 561 | #define TM6010_REQ08_R17_A_AGC_GAIN_MIN 0x08, 0x17 | ||
| 562 | #define TM6010_REQ08_R18_A_TR_CTRL 0x08, 0x18 | ||
| 563 | #define TM6010_REQ08_R19_A_FH_2FH_GAIN 0x08, 0x19 | ||
| 564 | #define TM6010_REQ08_R1A_A_NICAM_SER_MAX 0x08, 0x1a | ||
| 565 | #define TM6010_REQ08_R1B_A_NICAM_SER_MIN 0x08, 0x1b | ||
| 566 | #define TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT 0x08, 0x1e | ||
| 567 | #define TM6010_REQ08_R1F_A_TEST_INTF_SEL 0x08, 0x1f | ||
| 568 | #define TM6010_REQ08_R20_A_TEST_PIN_SEL 0x08, 0x20 | ||
| 569 | #define TM6010_REQ08_R21_A_AGC_ERR 0x08, 0x21 | ||
| 570 | #define TM6010_REQ08_R22_A_AGC_GAIN 0x08, 0x22 | ||
| 571 | #define TM6010_REQ08_R23_A_NICAM_INFO 0x08, 0x23 | ||
| 572 | #define TM6010_REQ08_R24_A_SER 0x08, 0x24 | ||
| 573 | #define TM6010_REQ08_R25_A_C1_AMP 0x08, 0x25 | ||
| 574 | #define TM6010_REQ08_R26_A_C2_AMP 0x08, 0x26 | ||
| 575 | #define TM6010_REQ08_R27_A_NOISE_AMP 0x08, 0x27 | ||
| 576 | #define TM6010_REQ08_R28_A_AUDIO_MODE_RES 0x08, 0x28 | ||
| 577 | |||
| 578 | /* Define TM6010 Video ADC registers */ | ||
| 579 | #define TM6010_REQ08_RE0_ADC_REF 0x08, 0xe0 | ||
| 580 | #define TM6010_REQ08_RE1_DAC_CLMP 0x08, 0xe1 | ||
| 581 | #define TM6010_REQ08_RE2_POWER_DOWN_CTRL1 0x08, 0xe2 | ||
| 582 | #define TM6010_REQ08_RE3_ADC_IN1_SEL 0x08, 0xe3 | ||
| 583 | #define TM6010_REQ08_RE4_ADC_IN2_SEL 0x08, 0xe4 | ||
| 584 | #define TM6010_REQ08_RE5_GAIN_PARAM 0x08, 0xe5 | ||
| 585 | #define TM6010_REQ08_RE6_POWER_DOWN_CTRL2 0x08, 0xe6 | ||
| 586 | #define TM6010_REQ08_RE7_REG_GAIN_Y 0x08, 0xe7 | ||
| 587 | #define TM6010_REQ08_RE8_REG_GAIN_C 0x08, 0xe8 | ||
| 588 | #define TM6010_REQ08_RE9_BIAS_CTRL 0x08, 0xe9 | ||
| 589 | #define TM6010_REQ08_REA_BUFF_DRV_CTRL 0x08, 0xea | ||
| 590 | #define TM6010_REQ08_REB_SIF_GAIN_CTRL 0x08, 0xeb | ||
| 591 | #define TM6010_REQ08_REC_REVERSE_YC_CTRL 0x08, 0xec | ||
| 592 | #define TM6010_REQ08_RED_GAIN_SEL 0x08, 0xed | ||
| 593 | |||
| 594 | /* Define TM6010 Audio ADC registers */ | ||
| 595 | #define TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG 0x08, 0xf0 | ||
| 596 | #define TM6010_REQ08_RF1_AADC_POWER_DOWN 0x08, 0xf1 | ||
| 597 | #define TM6010_REQ08_RF2_LEFT_CHANNEL_VOL 0x08, 0xf2 | ||
| 598 | #define TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL 0x08, 0xf3 | ||