4 files changed, 14 insertions, 14 deletions

diff --git a/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h b/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h
index 14b0567e531..ea547380012 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h
@@ -119,8 +119,8 @@ struct chnl_mgr {
         struct dev_object *hdev_obj;
 
         /* These fields initialized in bridge_chnl_create(): */
-        u32 dw_output_mask;     /* Host output channels w/ full buffers */
-        u32 dw_last_output;     /* Last output channel fired from DPC */
+        u32 output_mask;        /* Host output channels w/ full buffers */
+        u32 last_output;        /* Last output channel fired from DPC */
         /* Critical section object handle */
         spinlock_t chnl_mgr_lock;
         u32 word_size;          /* Size in bytes of DSP word */
diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
index f7c105af3da..60a278136bd 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
@@ -34,28 +34,28 @@ struct cfg_devnode;
 struct cfg_hostres {
         u32 num_mem_windows;    /* Set to default */
         /* This is the base.memory */
-        u32 dw_mem_base[CFG_MAXMEMREGISTERS];   /* shm virtual address */
-        u32 dw_mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */
-        u32 dw_mem_phys[CFG_MAXMEMREGISTERS];   /* shm Physical address */
+        u32 mem_base[CFG_MAXMEMREGISTERS];      /* shm virtual address */
+        u32 mem_length[CFG_MAXMEMREGISTERS];    /* Length of the Base */
+        u32 mem_phys[CFG_MAXMEMREGISTERS];      /* shm Physical address */
         u8 birq_registers;      /* IRQ Number */
         u8 birq_attrib;         /* IRQ Attribute */
-        u32 dw_offset_for_monitor;      /* The Shared memory starts from
-                                         * dw_mem_base + this offset */
+        u32 offset_for_monitor; /* The Shared memory starts from
+                                         * mem_base + this offset */
         /*
          *  Info needed by NODE for allocating channels to communicate with RMS:
          *      chnl_offset:       Offset of RMS channels. Lower channels are
          *                          reserved.
          *      chnl_buf_size:      Size of channel buffer to send to RMS
-         *      dw_num_chnls:           Total number of channels
+         *      num_chnls:              Total number of channels
          *                              (including reserved).
          */
         u32 chnl_offset;
         u32 chnl_buf_size;
-        u32 dw_num_chnls;
-        void __iomem *dw_per_base;
-        u32 dw_per_pm_base;
+        u32 num_chnls;
+        void __iomem *per_base;
+        u32 per_pm_base;
         u32 core_pm_base;
-        void __iomem *dw_dmmu_base;
+        void __iomem *dmmu_base;
 };
 
 #endif /* CFGDEFS_ */
diff --git a/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h b/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h
index 1785c3e8371..29e66dd525e 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h
@@ -58,7 +58,7 @@ struct chnl_info {
         void *event_obj;        /* Channel I/O completion event. */
         /*Abstraction of I/O completion event. */
         struct sync_object *sync_event;
-        s8 dw_mode;             /* Channel mode. */
+        s8 mode;                /* Channel mode. */
         u8 dw_state;            /* Current channel state. */
         u32 bytes_tx;           /* Total bytes transferred. */
         u32 cio_cs;             /* Number of IOCs in queue. */
diff --git a/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h b/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h
index 943d91f809e..8cd1494ccc8 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h
@@ -51,7 +51,7 @@ struct cmm_attrs {
  */
 
 struct cmm_seginfo {
-        u32 dw_seg_base_pa;     /* Start Phys address of SM segment */
+        u32 seg_base_pa;        /* Start Phys address of SM segment */
         /* Total size in bytes of segment: DSP+GPP */
         u32 ul_total_seg_size;
         u32 gpp_base_pa;        /* Start Phys addr of Gpp SM seg */