diff options
Diffstat (limited to 'drivers/staging/spectra/nand_regs.h')
-rw-r--r-- | drivers/staging/spectra/nand_regs.h | 619 |
1 files changed, 619 insertions, 0 deletions
diff --git a/drivers/staging/spectra/nand_regs.h b/drivers/staging/spectra/nand_regs.h new file mode 100644 index 00000000000..e192e4ae8c1 --- /dev/null +++ b/drivers/staging/spectra/nand_regs.h | |||
@@ -0,0 +1,619 @@ | |||
1 | /* | ||
2 | * NAND Flash Controller Device Driver | ||
3 | * Copyright (c) 2009, Intel Corporation and its suppliers. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms and conditions of the GNU General Public License, | ||
7 | * version 2, as published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
12 | * more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along with | ||
15 | * this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
17 | * | ||
18 | */ | ||
19 | |||
20 | #define DEVICE_RESET 0x0 | ||
21 | #define DEVICE_RESET__BANK0 0x0001 | ||
22 | #define DEVICE_RESET__BANK1 0x0002 | ||
23 | #define DEVICE_RESET__BANK2 0x0004 | ||
24 | #define DEVICE_RESET__BANK3 0x0008 | ||
25 | |||
26 | #define TRANSFER_SPARE_REG 0x10 | ||
27 | #define TRANSFER_SPARE_REG__FLAG 0x0001 | ||
28 | |||
29 | #define LOAD_WAIT_CNT 0x20 | ||
30 | #define LOAD_WAIT_CNT__VALUE 0xffff | ||
31 | |||
32 | #define PROGRAM_WAIT_CNT 0x30 | ||
33 | #define PROGRAM_WAIT_CNT__VALUE 0xffff | ||
34 | |||
35 | #define ERASE_WAIT_CNT 0x40 | ||
36 | #define ERASE_WAIT_CNT__VALUE 0xffff | ||
37 | |||
38 | #define INT_MON_CYCCNT 0x50 | ||
39 | #define INT_MON_CYCCNT__VALUE 0xffff | ||
40 | |||
41 | #define RB_PIN_ENABLED 0x60 | ||
42 | #define RB_PIN_ENABLED__BANK0 0x0001 | ||
43 | #define RB_PIN_ENABLED__BANK1 0x0002 | ||
44 | #define RB_PIN_ENABLED__BANK2 0x0004 | ||
45 | #define RB_PIN_ENABLED__BANK3 0x0008 | ||
46 | |||
47 | #define MULTIPLANE_OPERATION 0x70 | ||
48 | #define MULTIPLANE_OPERATION__FLAG 0x0001 | ||
49 | |||
50 | #define MULTIPLANE_READ_ENABLE 0x80 | ||
51 | #define MULTIPLANE_READ_ENABLE__FLAG 0x0001 | ||
52 | |||
53 | #define COPYBACK_DISABLE 0x90 | ||
54 | #define COPYBACK_DISABLE__FLAG 0x0001 | ||
55 | |||
56 | #define CACHE_WRITE_ENABLE 0xa0 | ||
57 | #define CACHE_WRITE_ENABLE__FLAG 0x0001 | ||
58 | |||
59 | #define CACHE_READ_ENABLE 0xb0 | ||
60 | #define CACHE_READ_ENABLE__FLAG 0x0001 | ||
61 | |||
62 | #define PREFETCH_MODE 0xc0 | ||
63 | #define PREFETCH_MODE__PREFETCH_EN 0x0001 | ||
64 | #define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 | ||
65 | |||
66 | #define CHIP_ENABLE_DONT_CARE 0xd0 | ||
67 | #define CHIP_EN_DONT_CARE__FLAG 0x01 | ||
68 | |||
69 | #define ECC_ENABLE 0xe0 | ||
70 | #define ECC_ENABLE__FLAG 0x0001 | ||
71 | |||
72 | #define GLOBAL_INT_ENABLE 0xf0 | ||
73 | #define GLOBAL_INT_EN_FLAG 0x01 | ||
74 | |||
75 | #define WE_2_RE 0x100 | ||
76 | #define WE_2_RE__VALUE 0x003f | ||
77 | |||
78 | #define ADDR_2_DATA 0x110 | ||
79 | #define ADDR_2_DATA__VALUE 0x003f | ||
80 | |||
81 | #define RE_2_WE 0x120 | ||
82 | #define RE_2_WE__VALUE 0x003f | ||
83 | |||
84 | #define ACC_CLKS 0x130 | ||
85 | #define ACC_CLKS__VALUE 0x000f | ||
86 | |||
87 | #define NUMBER_OF_PLANES 0x140 | ||
88 | #define NUMBER_OF_PLANES__VALUE 0x0007 | ||
89 | |||
90 | #define PAGES_PER_BLOCK 0x150 | ||
91 | #define PAGES_PER_BLOCK__VALUE 0xffff | ||
92 | |||
93 | #define DEVICE_WIDTH 0x160 | ||
94 | #define DEVICE_WIDTH__VALUE 0x0003 | ||
95 | |||
96 | #define DEVICE_MAIN_AREA_SIZE 0x170 | ||
97 | #define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff | ||
98 | |||
99 | #define DEVICE_SPARE_AREA_SIZE 0x180 | ||
100 | #define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff | ||
101 | |||
102 | #define TWO_ROW_ADDR_CYCLES 0x190 | ||
103 | #define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 | ||
104 | |||
105 | #define MULTIPLANE_ADDR_RESTRICT 0x1a0 | ||
106 | #define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 | ||
107 | |||
108 | #define ECC_CORRECTION 0x1b0 | ||
109 | #define ECC_CORRECTION__VALUE 0x001f | ||
110 | |||
111 | #define READ_MODE 0x1c0 | ||
112 | #define READ_MODE__VALUE 0x000f | ||
113 | |||
114 | #define WRITE_MODE 0x1d0 | ||
115 | #define WRITE_MODE__VALUE 0x000f | ||
116 | |||
117 | #define COPYBACK_MODE 0x1e0 | ||
118 | #define COPYBACK_MODE__VALUE 0x000f | ||
119 | |||
120 | #define RDWR_EN_LO_CNT 0x1f0 | ||
121 | #define RDWR_EN_LO_CNT__VALUE 0x001f | ||
122 | |||
123 | #define RDWR_EN_HI_CNT 0x200 | ||
124 | #define RDWR_EN_HI_CNT__VALUE 0x001f | ||
125 | |||
126 | #define MAX_RD_DELAY 0x210 | ||
127 | #define MAX_RD_DELAY__VALUE 0x000f | ||
128 | |||
129 | #define CS_SETUP_CNT 0x220 | ||
130 | #define CS_SETUP_CNT__VALUE 0x001f | ||
131 | |||
132 | #define SPARE_AREA_SKIP_BYTES 0x230 | ||
133 | #define SPARE_AREA_SKIP_BYTES__VALUE 0x003f | ||
134 | |||
135 | #define SPARE_AREA_MARKER 0x240 | ||
136 | #define SPARE_AREA_MARKER__VALUE 0xffff | ||
137 | |||
138 | #define DEVICES_CONNECTED 0x250 | ||
139 | #define DEVICES_CONNECTED__VALUE 0x0007 | ||
140 | |||
141 | #define DIE_MASK 0x260 | ||
142 | #define DIE_MASK__VALUE 0x00ff | ||
143 | |||
144 | #define FIRST_BLOCK_OF_NEXT_PLANE 0x270 | ||
145 | #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff | ||
146 | |||
147 | #define WRITE_PROTECT 0x280 | ||
148 | #define WRITE_PROTECT__FLAG 0x0001 | ||
149 | |||
150 | #define RE_2_RE 0x290 | ||
151 | #define RE_2_RE__VALUE 0x003f | ||
152 | |||
153 | #define MANUFACTURER_ID 0x300 | ||
154 | #define MANUFACTURER_ID__VALUE 0x00ff | ||
155 | |||
156 | #define DEVICE_ID 0x310 | ||
157 | #define DEVICE_ID__VALUE 0x00ff | ||
158 | |||
159 | #define DEVICE_PARAM_0 0x320 | ||
160 | #define DEVICE_PARAM_0__VALUE 0x00ff | ||
161 | |||
162 | #define DEVICE_PARAM_1 0x330 | ||
163 | #define DEVICE_PARAM_1__VALUE 0x00ff | ||
164 | |||
165 | #define DEVICE_PARAM_2 0x340 | ||
166 | #define DEVICE_PARAM_2__VALUE 0x00ff | ||
167 | |||
168 | #define LOGICAL_PAGE_DATA_SIZE 0x350 | ||
169 | #define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff | ||
170 | |||
171 | #define LOGICAL_PAGE_SPARE_SIZE 0x360 | ||
172 | #define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff | ||
173 | |||
174 | #define REVISION 0x370 | ||
175 | #define REVISION__VALUE 0xffff | ||
176 | |||
177 | #define ONFI_DEVICE_FEATURES 0x380 | ||
178 | #define ONFI_DEVICE_FEATURES__VALUE 0x003f | ||
179 | |||
180 | #define ONFI_OPTIONAL_COMMANDS 0x390 | ||
181 | #define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f | ||
182 | |||
183 | #define ONFI_TIMING_MODE 0x3a0 | ||
184 | #define ONFI_TIMING_MODE__VALUE 0x003f | ||
185 | |||
186 | #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 | ||
187 | #define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f | ||
188 | |||
189 | #define ONFI_DEVICE_NO_OF_LUNS 0x3c0 | ||
190 | #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff | ||
191 | #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 | ||
192 | |||
193 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 | ||
194 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff | ||
195 | |||
196 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 | ||
197 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff | ||
198 | |||
199 | #define FEATURES 0x3f0 | ||
200 | #define FEATURES__N_BANKS 0x0003 | ||
201 | #define FEATURES__ECC_MAX_ERR 0x003c | ||
202 | #define FEATURES__DMA 0x0040 | ||
203 | #define FEATURES__CMD_DMA 0x0080 | ||
204 | #define FEATURES__PARTITION 0x0100 | ||
205 | #define FEATURES__XDMA_SIDEBAND 0x0200 | ||
206 | #define FEATURES__GPREG 0x0400 | ||
207 | #define FEATURES__INDEX_ADDR 0x0800 | ||
208 | |||
209 | #define TRANSFER_MODE 0x400 | ||
210 | #define TRANSFER_MODE__VALUE 0x0003 | ||
211 | |||
212 | #define INTR_STATUS0 0x410 | ||
213 | #define INTR_STATUS0__ECC_TRANSACTION_DONE 0x0001 | ||
214 | #define INTR_STATUS0__ECC_ERR 0x0002 | ||
215 | #define INTR_STATUS0__DMA_CMD_COMP 0x0004 | ||
216 | #define INTR_STATUS0__TIME_OUT 0x0008 | ||
217 | #define INTR_STATUS0__PROGRAM_FAIL 0x0010 | ||
218 | #define INTR_STATUS0__ERASE_FAIL 0x0020 | ||
219 | #define INTR_STATUS0__LOAD_COMP 0x0040 | ||
220 | #define INTR_STATUS0__PROGRAM_COMP 0x0080 | ||
221 | #define INTR_STATUS0__ERASE_COMP 0x0100 | ||
222 | #define INTR_STATUS0__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
223 | #define INTR_STATUS0__LOCKED_BLK 0x0400 | ||
224 | #define INTR_STATUS0__UNSUP_CMD 0x0800 | ||
225 | #define INTR_STATUS0__INT_ACT 0x1000 | ||
226 | #define INTR_STATUS0__RST_COMP 0x2000 | ||
227 | #define INTR_STATUS0__PIPE_CMD_ERR 0x4000 | ||
228 | #define INTR_STATUS0__PAGE_XFER_INC 0x8000 | ||
229 | |||
230 | #define INTR_EN0 0x420 | ||
231 | #define INTR_EN0__ECC_TRANSACTION_DONE 0x0001 | ||
232 | #define INTR_EN0__ECC_ERR 0x0002 | ||
233 | #define INTR_EN0__DMA_CMD_COMP 0x0004 | ||
234 | #define INTR_EN0__TIME_OUT 0x0008 | ||
235 | #define INTR_EN0__PROGRAM_FAIL 0x0010 | ||
236 | #define INTR_EN0__ERASE_FAIL 0x0020 | ||
237 | #define INTR_EN0__LOAD_COMP 0x0040 | ||
238 | #define INTR_EN0__PROGRAM_COMP 0x0080 | ||
239 | #define INTR_EN0__ERASE_COMP 0x0100 | ||
240 | #define INTR_EN0__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
241 | #define INTR_EN0__LOCKED_BLK 0x0400 | ||
242 | #define INTR_EN0__UNSUP_CMD 0x0800 | ||
243 | #define INTR_EN0__INT_ACT 0x1000 | ||
244 | #define INTR_EN0__RST_COMP 0x2000 | ||
245 | #define INTR_EN0__PIPE_CMD_ERR 0x4000 | ||
246 | #define INTR_EN0__PAGE_XFER_INC 0x8000 | ||
247 | |||
248 | #define PAGE_CNT0 0x430 | ||
249 | #define PAGE_CNT0__VALUE 0x00ff | ||
250 | |||
251 | #define ERR_PAGE_ADDR0 0x440 | ||
252 | #define ERR_PAGE_ADDR0__VALUE 0xffff | ||
253 | |||
254 | #define ERR_BLOCK_ADDR0 0x450 | ||
255 | #define ERR_BLOCK_ADDR0__VALUE 0xffff | ||
256 | |||
257 | #define INTR_STATUS1 0x460 | ||
258 | #define INTR_STATUS1__ECC_TRANSACTION_DONE 0x0001 | ||
259 | #define INTR_STATUS1__ECC_ERR 0x0002 | ||
260 | #define INTR_STATUS1__DMA_CMD_COMP 0x0004 | ||
261 | #define INTR_STATUS1__TIME_OUT 0x0008 | ||
262 | #define INTR_STATUS1__PROGRAM_FAIL 0x0010 | ||
263 | #define INTR_STATUS1__ERASE_FAIL 0x0020 | ||
264 | #define INTR_STATUS1__LOAD_COMP 0x0040 | ||
265 | #define INTR_STATUS1__PROGRAM_COMP 0x0080 | ||
266 | #define INTR_STATUS1__ERASE_COMP 0x0100 | ||
267 | #define INTR_STATUS1__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
268 | #define INTR_STATUS1__LOCKED_BLK 0x0400 | ||
269 | #define INTR_STATUS1__UNSUP_CMD 0x0800 | ||
270 | #define INTR_STATUS1__INT_ACT 0x1000 | ||
271 | #define INTR_STATUS1__RST_COMP 0x2000 | ||
272 | #define INTR_STATUS1__PIPE_CMD_ERR 0x4000 | ||
273 | #define INTR_STATUS1__PAGE_XFER_INC 0x8000 | ||
274 | |||
275 | #define INTR_EN1 0x470 | ||
276 | #define INTR_EN1__ECC_TRANSACTION_DONE 0x0001 | ||
277 | #define INTR_EN1__ECC_ERR 0x0002 | ||
278 | #define INTR_EN1__DMA_CMD_COMP 0x0004 | ||
279 | #define INTR_EN1__TIME_OUT 0x0008 | ||
280 | #define INTR_EN1__PROGRAM_FAIL 0x0010 | ||
281 | #define INTR_EN1__ERASE_FAIL 0x0020 | ||
282 | #define INTR_EN1__LOAD_COMP 0x0040 | ||
283 | #define INTR_EN1__PROGRAM_COMP 0x0080 | ||
284 | #define INTR_EN1__ERASE_COMP 0x0100 | ||
285 | #define INTR_EN1__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
286 | #define INTR_EN1__LOCKED_BLK 0x0400 | ||
287 | #define INTR_EN1__UNSUP_CMD 0x0800 | ||
288 | #define INTR_EN1__INT_ACT 0x1000 | ||
289 | #define INTR_EN1__RST_COMP 0x2000 | ||
290 | #define INTR_EN1__PIPE_CMD_ERR 0x4000 | ||
291 | #define INTR_EN1__PAGE_XFER_INC 0x8000 | ||
292 | |||
293 | #define PAGE_CNT1 0x480 | ||
294 | #define PAGE_CNT1__VALUE 0x00ff | ||
295 | |||
296 | #define ERR_PAGE_ADDR1 0x490 | ||
297 | #define ERR_PAGE_ADDR1__VALUE 0xffff | ||
298 | |||
299 | #define ERR_BLOCK_ADDR1 0x4a0 | ||
300 | #define ERR_BLOCK_ADDR1__VALUE 0xffff | ||
301 | |||
302 | #define INTR_STATUS2 0x4b0 | ||
303 | #define INTR_STATUS2__ECC_TRANSACTION_DONE 0x0001 | ||
304 | #define INTR_STATUS2__ECC_ERR 0x0002 | ||
305 | #define INTR_STATUS2__DMA_CMD_COMP 0x0004 | ||
306 | #define INTR_STATUS2__TIME_OUT 0x0008 | ||
307 | #define INTR_STATUS2__PROGRAM_FAIL 0x0010 | ||
308 | #define INTR_STATUS2__ERASE_FAIL 0x0020 | ||
309 | #define INTR_STATUS2__LOAD_COMP 0x0040 | ||
310 | #define INTR_STATUS2__PROGRAM_COMP 0x0080 | ||
311 | #define INTR_STATUS2__ERASE_COMP 0x0100 | ||
312 | #define INTR_STATUS2__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
313 | #define INTR_STATUS2__LOCKED_BLK 0x0400 | ||
314 | #define INTR_STATUS2__UNSUP_CMD 0x0800 | ||
315 | #define INTR_STATUS2__INT_ACT 0x1000 | ||
316 | #define INTR_STATUS2__RST_COMP 0x2000 | ||
317 | #define INTR_STATUS2__PIPE_CMD_ERR 0x4000 | ||
318 | #define INTR_STATUS2__PAGE_XFER_INC 0x8000 | ||
319 | |||
320 | #define INTR_EN2 0x4c0 | ||
321 | #define INTR_EN2__ECC_TRANSACTION_DONE 0x0001 | ||
322 | #define INTR_EN2__ECC_ERR 0x0002 | ||
323 | #define INTR_EN2__DMA_CMD_COMP 0x0004 | ||
324 | #define INTR_EN2__TIME_OUT 0x0008 | ||
325 | #define INTR_EN2__PROGRAM_FAIL 0x0010 | ||
326 | #define INTR_EN2__ERASE_FAIL 0x0020 | ||
327 | #define INTR_EN2__LOAD_COMP 0x0040 | ||
328 | #define INTR_EN2__PROGRAM_COMP 0x0080 | ||
329 | #define INTR_EN2__ERASE_COMP 0x0100 | ||
330 | #define INTR_EN2__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
331 | #define INTR_EN2__LOCKED_BLK 0x0400 | ||
332 | #define INTR_EN2__UNSUP_CMD 0x0800 | ||
333 | #define INTR_EN2__INT_ACT 0x1000 | ||
334 | #define INTR_EN2__RST_COMP 0x2000 | ||
335 | #define INTR_EN2__PIPE_CMD_ERR 0x4000 | ||
336 | #define INTR_EN2__PAGE_XFER_INC 0x8000 | ||
337 | |||
338 | #define PAGE_CNT2 0x4d0 | ||
339 | #define PAGE_CNT2__VALUE 0x00ff | ||
340 | |||
341 | #define ERR_PAGE_ADDR2 0x4e0 | ||
342 | #define ERR_PAGE_ADDR2__VALUE 0xffff | ||
343 | |||
344 | #define ERR_BLOCK_ADDR2 0x4f0 | ||
345 | #define ERR_BLOCK_ADDR2__VALUE 0xffff | ||
346 | |||
347 | #define INTR_STATUS3 0x500 | ||
348 | #define INTR_STATUS3__ECC_TRANSACTION_DONE 0x0001 | ||
349 | #define INTR_STATUS3__ECC_ERR 0x0002 | ||
350 | #define INTR_STATUS3__DMA_CMD_COMP 0x0004 | ||
351 | #define INTR_STATUS3__TIME_OUT 0x0008 | ||
352 | #define INTR_STATUS3__PROGRAM_FAIL 0x0010 | ||
353 | #define INTR_STATUS3__ERASE_FAIL 0x0020 | ||
354 | #define INTR_STATUS3__LOAD_COMP 0x0040 | ||
355 | #define INTR_STATUS3__PROGRAM_COMP 0x0080 | ||
356 | #define INTR_STATUS3__ERASE_COMP 0x0100 | ||
357 | #define INTR_STATUS3__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
358 | #define INTR_STATUS3__LOCKED_BLK 0x0400 | ||
359 | #define INTR_STATUS3__UNSUP_CMD 0x0800 | ||
360 | #define INTR_STATUS3__INT_ACT 0x1000 | ||
361 | #define INTR_STATUS3__RST_COMP 0x2000 | ||
362 | #define INTR_STATUS3__PIPE_CMD_ERR 0x4000 | ||
363 | #define INTR_STATUS3__PAGE_XFER_INC 0x8000 | ||
364 | |||
365 | #define INTR_EN3 0x510 | ||
366 | #define INTR_EN3__ECC_TRANSACTION_DONE 0x0001 | ||
367 | #define INTR_EN3__ECC_ERR 0x0002 | ||
368 | #define INTR_EN3__DMA_CMD_COMP 0x0004 | ||
369 | #define INTR_EN3__TIME_OUT 0x0008 | ||
370 | #define INTR_EN3__PROGRAM_FAIL 0x0010 | ||
371 | #define INTR_EN3__ERASE_FAIL 0x0020 | ||
372 | #define INTR_EN3__LOAD_COMP 0x0040 | ||
373 | #define INTR_EN3__PROGRAM_COMP 0x0080 | ||
374 | #define INTR_EN3__ERASE_COMP 0x0100 | ||
375 | #define INTR_EN3__PIPE_CPYBCK_CMD_COMP 0x0200 | ||
376 | #define INTR_EN3__LOCKED_BLK 0x0400 | ||
377 | #define INTR_EN3__UNSUP_CMD 0x0800 | ||
378 | #define INTR_EN3__INT_ACT 0x1000 | ||
379 | #define INTR_EN3__RST_COMP 0x2000 | ||
380 | #define INTR_EN3__PIPE_CMD_ERR 0x4000 | ||
381 | #define INTR_EN3__PAGE_XFER_INC 0x8000 | ||
382 | |||
383 | #define PAGE_CNT3 0x520 | ||
384 | #define PAGE_CNT3__VALUE 0x00ff | ||
385 | |||
386 | #define ERR_PAGE_ADDR3 0x530 | ||
387 | #define ERR_PAGE_ADDR3__VALUE 0xffff | ||
388 | |||
389 | #define ERR_BLOCK_ADDR3 0x540 | ||
390 | #define ERR_BLOCK_ADDR3__VALUE 0xffff | ||
391 | |||
392 | #define DATA_INTR 0x550 | ||
393 | #define DATA_INTR__WRITE_SPACE_AV 0x0001 | ||
394 | #define DATA_INTR__READ_DATA_AV 0x0002 | ||
395 | |||
396 | #define DATA_INTR_EN 0x560 | ||
397 | #define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 | ||
398 | #define DATA_INTR_EN__READ_DATA_AV 0x0002 | ||
399 | |||
400 | #define GPREG_0 0x570 | ||
401 | #define GPREG_0__VALUE 0xffff | ||
402 | |||
403 | #define GPREG_1 0x580 | ||
404 | #define GPREG_1__VALUE 0xffff | ||
405 | |||
406 | #define GPREG_2 0x590 | ||
407 | #define GPREG_2__VALUE 0xffff | ||
408 | |||
409 | #define GPREG_3 0x5a0 | ||
410 | #define GPREG_3__VALUE 0xffff | ||
411 | |||
412 | #define ECC_THRESHOLD 0x600 | ||
413 | #define ECC_THRESHOLD__VALUE 0x03ff | ||
414 | |||
415 | #define ECC_ERROR_BLOCK_ADDRESS 0x610 | ||
416 | #define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff | ||
417 | |||
418 | #define ECC_ERROR_PAGE_ADDRESS 0x620 | ||
419 | #define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff | ||
420 | #define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 | ||
421 | |||
422 | #define ECC_ERROR_ADDRESS 0x630 | ||
423 | #define ECC_ERROR_ADDRESS__OFFSET 0x0fff | ||
424 | #define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 | ||
425 | |||
426 | #define ERR_CORRECTION_INFO 0x640 | ||
427 | #define ERR_CORRECTION_INFO__BYTEMASK 0x00ff | ||
428 | #define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 | ||
429 | #define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 | ||
430 | #define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 | ||
431 | |||
432 | #define DMA_ENABLE 0x700 | ||
433 | #define DMA_ENABLE__FLAG 0x0001 | ||
434 | |||
435 | #define IGNORE_ECC_DONE 0x710 | ||
436 | #define IGNORE_ECC_DONE__FLAG 0x0001 | ||
437 | |||
438 | #define DMA_INTR 0x720 | ||
439 | #define DMA_INTR__TARGET_ERROR 0x0001 | ||
440 | #define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 | ||
441 | #define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 | ||
442 | #define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 | ||
443 | #define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 | ||
444 | #define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 | ||
445 | |||
446 | #define DMA_INTR_EN 0x730 | ||
447 | #define DMA_INTR_EN__TARGET_ERROR 0x0001 | ||
448 | #define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 | ||
449 | #define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 | ||
450 | #define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 | ||
451 | #define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 | ||
452 | #define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 | ||
453 | |||
454 | #define TARGET_ERR_ADDR_LO 0x740 | ||
455 | #define TARGET_ERR_ADDR_LO__VALUE 0xffff | ||
456 | |||
457 | #define TARGET_ERR_ADDR_HI 0x750 | ||
458 | #define TARGET_ERR_ADDR_HI__VALUE 0xffff | ||
459 | |||
460 | #define CHNL_ACTIVE 0x760 | ||
461 | #define CHNL_ACTIVE__CHANNEL0 0x0001 | ||
462 | #define CHNL_ACTIVE__CHANNEL1 0x0002 | ||
463 | #define CHNL_ACTIVE__CHANNEL2 0x0004 | ||
464 | #define CHNL_ACTIVE__CHANNEL3 0x0008 | ||
465 | |||
466 | #define ACTIVE_SRC_ID 0x800 | ||
467 | #define ACTIVE_SRC_ID__VALUE 0x00ff | ||
468 | |||
469 | #define PTN_INTR 0x810 | ||
470 | #define PTN_INTR__CONFIG_ERROR 0x0001 | ||
471 | #define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 | ||
472 | #define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 | ||
473 | #define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 | ||
474 | #define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 | ||
475 | #define PTN_INTR__REG_ACCESS_ERROR 0x0020 | ||
476 | |||
477 | #define PTN_INTR_EN 0x820 | ||
478 | #define PTN_INTR_EN__CONFIG_ERROR 0x0001 | ||
479 | #define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 | ||
480 | #define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 | ||
481 | #define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 | ||
482 | #define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 | ||
483 | #define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 | ||
484 | |||
485 | #define PERM_SRC_ID_0 0x830 | ||
486 | #define PERM_SRC_ID_0__SRCID 0x00ff | ||
487 | #define PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE 0x0800 | ||
488 | #define PERM_SRC_ID_0__WRITE_ACTIVE 0x2000 | ||
489 | #define PERM_SRC_ID_0__READ_ACTIVE 0x4000 | ||
490 | #define PERM_SRC_ID_0__PARTITION_VALID 0x8000 | ||
491 | |||
492 | #define MIN_BLK_ADDR_0 0x840 | ||
493 | #define MIN_BLK_ADDR_0__VALUE 0xffff | ||
494 | |||
495 | #define MAX_BLK_ADDR_0 0x850 | ||
496 | #define MAX_BLK_ADDR_0__VALUE 0xffff | ||
497 | |||
498 | #define MIN_MAX_BANK_0 0x860 | ||
499 | #define MIN_MAX_BANK_0__MIN_VALUE 0x0003 | ||
500 | #define MIN_MAX_BANK_0__MAX_VALUE 0x000c | ||
501 | |||
502 | #define PERM_SRC_ID_1 0x870 | ||
503 | #define PERM_SRC_ID_1__SRCID 0x00ff | ||
504 | #define PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE 0x0800 | ||
505 | #define PERM_SRC_ID_1__WRITE_ACTIVE 0x2000 | ||
506 | #define PERM_SRC_ID_1__READ_ACTIVE 0x4000 | ||
507 | #define PERM_SRC_ID_1__PARTITION_VALID 0x8000 | ||
508 | |||
509 | #define MIN_BLK_ADDR_1 0x880 | ||
510 | #define MIN_BLK_ADDR_1__VALUE 0xffff | ||
511 | |||
512 | #define MAX_BLK_ADDR_1 0x890 | ||
513 | #define MAX_BLK_ADDR_1__VALUE 0xffff | ||
514 | |||
515 | #define MIN_MAX_BANK_1 0x8a0 | ||
516 | #define MIN_MAX_BANK_1__MIN_VALUE 0x0003 | ||
517 | #define MIN_MAX_BANK_1__MAX_VALUE 0x000c | ||
518 | |||
519 | #define PERM_SRC_ID_2 0x8b0 | ||
520 | #define PERM_SRC_ID_2__SRCID 0x00ff | ||
521 | #define PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE 0x0800 | ||
522 | #define PERM_SRC_ID_2__WRITE_ACTIVE 0x2000 | ||
523 | #define PERM_SRC_ID_2__READ_ACTIVE 0x4000 | ||
524 | #define PERM_SRC_ID_2__PARTITION_VALID 0x8000 | ||
525 | |||
526 | #define MIN_BLK_ADDR_2 0x8c0 | ||
527 | #define MIN_BLK_ADDR_2__VALUE 0xffff | ||
528 | |||
529 | #define MAX_BLK_ADDR_2 0x8d0 | ||
530 | #define MAX_BLK_ADDR_2__VALUE 0xffff | ||
531 | |||
532 | #define MIN_MAX_BANK_2 0x8e0 | ||
533 | #define MIN_MAX_BANK_2__MIN_VALUE 0x0003 | ||
534 | #define MIN_MAX_BANK_2__MAX_VALUE 0x000c | ||
535 | |||
536 | #define PERM_SRC_ID_3 0x8f0 | ||
537 | #define PERM_SRC_ID_3__SRCID 0x00ff | ||
538 | #define PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE 0x0800 | ||
539 | #define PERM_SRC_ID_3__WRITE_ACTIVE 0x2000 | ||
540 | #define PERM_SRC_ID_3__READ_ACTIVE 0x4000 | ||
541 | #define PERM_SRC_ID_3__PARTITION_VALID 0x8000 | ||
542 | |||
543 | #define MIN_BLK_ADDR_3 0x900 | ||
544 | #define MIN_BLK_ADDR_3__VALUE 0xffff | ||
545 | |||
546 | #define MAX_BLK_ADDR_3 0x910 | ||
547 | #define MAX_BLK_ADDR_3__VALUE 0xffff | ||
548 | |||
549 | #define MIN_MAX_BANK_3 0x920 | ||
550 | #define MIN_MAX_BANK_3__MIN_VALUE 0x0003 | ||
551 | #define MIN_MAX_BANK_3__MAX_VALUE 0x000c | ||
552 | |||
553 | #define PERM_SRC_ID_4 0x930 | ||
554 | #define PERM_SRC_ID_4__SRCID 0x00ff | ||
555 | #define PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE 0x0800 | ||
556 | #define PERM_SRC_ID_4__WRITE_ACTIVE 0x2000 | ||
557 | #define PERM_SRC_ID_4__READ_ACTIVE 0x4000 | ||
558 | #define PERM_SRC_ID_4__PARTITION_VALID 0x8000 | ||
559 | |||
560 | #define MIN_BLK_ADDR_4 0x940 | ||
561 | #define MIN_BLK_ADDR_4__VALUE 0xffff | ||
562 | |||
563 | #define MAX_BLK_ADDR_4 0x950 | ||
564 | #define MAX_BLK_ADDR_4__VALUE 0xffff | ||
565 | |||
566 | #define MIN_MAX_BANK_4 0x960 | ||
567 | #define MIN_MAX_BANK_4__MIN_VALUE 0x0003 | ||
568 | #define MIN_MAX_BANK_4__MAX_VALUE 0x000c | ||
569 | |||
570 | #define PERM_SRC_ID_5 0x970 | ||
571 | #define PERM_SRC_ID_5__SRCID 0x00ff | ||
572 | #define PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE 0x0800 | ||
573 | #define PERM_SRC_ID_5__WRITE_ACTIVE 0x2000 | ||
574 | #define PERM_SRC_ID_5__READ_ACTIVE 0x4000 | ||
575 | #define PERM_SRC_ID_5__PARTITION_VALID 0x8000 | ||
576 | |||
577 | #define MIN_BLK_ADDR_5 0x980 | ||
578 | #define MIN_BLK_ADDR_5__VALUE 0xffff | ||
579 | |||
580 | #define MAX_BLK_ADDR_5 0x990 | ||
581 | #define MAX_BLK_ADDR_5__VALUE 0xffff | ||
582 | |||
583 | #define MIN_MAX_BANK_5 0x9a0 | ||
584 | #define MIN_MAX_BANK_5__MIN_VALUE 0x0003 | ||
585 | #define MIN_MAX_BANK_5__MAX_VALUE 0x000c | ||
586 | |||
587 | #define PERM_SRC_ID_6 0x9b0 | ||
588 | #define PERM_SRC_ID_6__SRCID 0x00ff | ||
589 | #define PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE 0x0800 | ||
590 | #define PERM_SRC_ID_6__WRITE_ACTIVE 0x2000 | ||
591 | #define PERM_SRC_ID_6__READ_ACTIVE 0x4000 | ||
592 | #define PERM_SRC_ID_6__PARTITION_VALID 0x8000 | ||
593 | |||
594 | #define MIN_BLK_ADDR_6 0x9c0 | ||
595 | #define MIN_BLK_ADDR_6__VALUE 0xffff | ||
596 | |||
597 | #define MAX_BLK_ADDR_6 0x9d0 | ||
598 | #define MAX_BLK_ADDR_6__VALUE 0xffff | ||
599 | |||
600 | #define MIN_MAX_BANK_6 0x9e0 | ||
601 | #define MIN_MAX_BANK_6__MIN_VALUE 0x0003 | ||
602 | #define MIN_MAX_BANK_6__MAX_VALUE 0x000c | ||
603 | |||
604 | #define PERM_SRC_ID_7 0x9f0 | ||
605 | #define PERM_SRC_ID_7__SRCID 0x00ff | ||
606 | #define PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE 0x0800 | ||
607 | #define PERM_SRC_ID_7__WRITE_ACTIVE 0x2000 | ||
608 | #define PERM_SRC_ID_7__READ_ACTIVE 0x4000 | ||
609 | #define PERM_SRC_ID_7__PARTITION_VALID 0x8000 | ||
610 | |||
611 | #define MIN_BLK_ADDR_7 0xa00 | ||
612 | #define MIN_BLK_ADDR_7__VALUE 0xffff | ||
613 | |||
614 | #define MAX_BLK_ADDR_7 0xa10 | ||
615 | #define MAX_BLK_ADDR_7__VALUE 0xffff | ||
616 | |||
617 | #define MIN_MAX_BANK_7 0xa20 | ||
618 | #define MIN_MAX_BANK_7__MIN_VALUE 0x0003 | ||
619 | #define MIN_MAX_BANK_7__MAX_VALUE 0x000c | ||