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-rw-r--r--drivers/staging/rtl8192su/Makefile2
-rw-r--r--drivers/staging/rtl8192su/r8192S_hw.h26
-rw-r--r--drivers/staging/rtl8192su/r8192S_phy.c5
-rw-r--r--drivers/staging/rtl8192su/r8192U.h6
-rw-r--r--drivers/staging/rtl8192su/r8192U_core.c197
5 files changed, 0 insertions, 236 deletions
diff --git a/drivers/staging/rtl8192su/Makefile b/drivers/staging/rtl8192su/Makefile
index 969ec438526..11cf9f182e0 100644
--- a/drivers/staging/rtl8192su/Makefile
+++ b/drivers/staging/rtl8192su/Makefile
@@ -12,8 +12,6 @@ EXTRA_CFLAGS += -DRTL8190_Download_Firmware_From_Header=1
12EXTRA_CFLAGS += -DRTL8192S_PREPARE_FOR_NORMAL_RELEASE 12EXTRA_CFLAGS += -DRTL8192S_PREPARE_FOR_NORMAL_RELEASE
13EXTRA_CFLAGS += -DRTL8192SU_DISABLE_IQK=1 13EXTRA_CFLAGS += -DRTL8192SU_DISABLE_IQK=1
14 14
15#EXTRA_CFLAGS += -DEEPROM_OLD_FORMAT_SUPPORT
16
17#EXTRA_CFLAGS += -DUSB_RX_AGGREGATION_SUPPORT=0 15#EXTRA_CFLAGS += -DUSB_RX_AGGREGATION_SUPPORT=0
18#EXTRA_CFLAGS += -DUSB_TX_DRIVER_AGGREGATION_ENABLE=0 16#EXTRA_CFLAGS += -DUSB_TX_DRIVER_AGGREGATION_ENABLE=0
19#EXTRA_CFLAGS += -DRTL8192SU_DISABLE_CCK_RATE=0 17#EXTRA_CFLAGS += -DRTL8192SU_DISABLE_CCK_RATE=0
diff --git a/drivers/staging/rtl8192su/r8192S_hw.h b/drivers/staging/rtl8192su/r8192S_hw.h
index 7a3d850de0b..1647550c3ac 100644
--- a/drivers/staging/rtl8192su/r8192S_hw.h
+++ b/drivers/staging/rtl8192su/r8192S_hw.h
@@ -1282,17 +1282,11 @@ Default: 00b.
1282#define EEPROM_Default_TxPower 0x1010 1282#define EEPROM_Default_TxPower 0x1010
1283#define EEPROM_Default_HT2T_TxPwr 0x10 1283#define EEPROM_Default_HT2T_TxPwr 0x10
1284 1284
1285#ifdef EEPROM_OLD_FORMAT_SUPPORT
1286#define EEPROM_Default_TxPowerBase 0x0
1287#define EEPROM_Default_ThermalMeter 0x12
1288#define EEPROM_Default_PwDiff 0x4
1289#else
1290#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 1285#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1291#define EEPROM_Default_ThermalMeter 0x12 1286#define EEPROM_Default_ThermalMeter 0x12
1292#define EEPROM_Default_AntTxPowerDiff 0x0 1287#define EEPROM_Default_AntTxPowerDiff 0x0
1293#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 1288#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
1294#define EEPROM_Default_TxPowerLevel 0x22 1289#define EEPROM_Default_TxPowerLevel 0x22
1295#endif
1296 1290
1297#define EEPROM_CHANNEL_PLAN_FCC 0x0 1291#define EEPROM_CHANNEL_PLAN_FCC 0x0
1298#define EEPROM_CHANNEL_PLAN_IC 0x1 1292#define EEPROM_CHANNEL_PLAN_IC 0x1
@@ -1330,25 +1324,6 @@ Default: 00b.
1330 1324
1331 1325
1332 // <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22. 1326 // <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22.
1333#ifdef EEPROM_OLD_FORMAT_SUPPORT
1334#define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM.
1335#define EEPROM_ThermalMeter 0x55 // Thermal meter default value.
1336#define EEPROM_Reserved 0x56 // Reserved.
1337#define EEPROM_CrystalCap 0x57 // Crystal Cap.
1338#define EEPROM_TxPowerBase 0x58 // Tx Power of serving station.
1339#define EEPROM_TxPwIndex_CCK_24G 0x59 // 0x59~0x66
1340#define EEPROM_TxPwIndex_OFDM_24G 0x67 // 0x67~0x74
1341#define EEPROM_TSSI_A 0x75 //TSSI value of path A.
1342#define EEPROM_TSSI_B 0x76 //TSSI value of path B.
1343#define EEPROM_TxPwTkMode 0x77 //Tx Power tracking mode.
1344#define EEPROM_HT2T_CH1_A 0x78 //HT 2T path A channel 1 Power Index.
1345#define EEPROM_HT2T_CH7_A 0x79 //HT 2T path A channel 7 Power Index.
1346#define EEPROM_HT2T_CH13_A 0x7a //HT 2T path A channel 13 Power Index.
1347#define EEPROM_HT2T_CH1_B 0x7b //HT 2T path B channel 1 Power Index.
1348#define EEPROM_HT2T_CH7_B 0x7c //HT 2T path B channel 7 Power Index.
1349#define EEPROM_HT2T_CH13_B 0x7d //HT 2T path B channel 13 Power Index.
1350#define EEPROM_BoardType 0x7e //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
1351#else
1352#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU 1327#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
1353#define EEPROM_TxPwIndex 0x55 //0x55-0x66, Tx Power index. 1328#define EEPROM_TxPwIndex 0x55 //0x55-0x66, Tx Power index.
1354#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM. 1329#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM.
@@ -1366,7 +1341,6 @@ Default: 00b.
1366#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference 1341#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference
1367#define EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel 1342#define EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel
1368#define TX_PWR_BAND_EDGE_CHK 0x79// Check if band-edge scheme is enabled 1343#define TX_PWR_BAND_EDGE_CHK 0x79// Check if band-edge scheme is enabled
1369#endif
1370#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 1344#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1371#define EEPROM_USB_Default_OPTIONAL_FUNC 0x8 1345#define EEPROM_USB_Default_OPTIONAL_FUNC 0x8
1372#define EEPROM_USB_Default_PHY_PARAM 0x0 1346#define EEPROM_USB_Default_PHY_PARAM 0x0
diff --git a/drivers/staging/rtl8192su/r8192S_phy.c b/drivers/staging/rtl8192su/r8192S_phy.c
index e2c9ed20287..36f5e247c91 100644
--- a/drivers/staging/rtl8192su/r8192S_phy.c
+++ b/drivers/staging/rtl8192su/r8192S_phy.c
@@ -2639,10 +2639,6 @@ PHY_GetTxPowerLevel8192S(
2639 // 2639 //
2640// if(priv->epromtype == EPROM_93c46) 2640// if(priv->epromtype == EPROM_93c46)
2641 { 2641 {
2642#ifdef EEPROM_OLD_FORMAT_SUPPORT
2643 powerlevel = priv->TxPowerLevelCCK[index];
2644 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[index];
2645#else
2646 // 2642 //
2647 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx 2643 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
2648 // Power must be calculated by the antenna diff. 2644 // Power must be calculated by the antenna diff.
@@ -2821,7 +2817,6 @@ PHY_GetTxPowerLevel8192S(
2821 2817
2822 // Notify Tx power difference for B/C/D to A!!! 2818 // Notify Tx power difference for B/C/D to A!!!
2823 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); 2819 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2824#endif
2825 } 2820 }
2826 2821
2827 // 2822 //
diff --git a/drivers/staging/rtl8192su/r8192U.h b/drivers/staging/rtl8192su/r8192U.h
index 0e1213f9de1..222b615499e 100644
--- a/drivers/staging/rtl8192su/r8192U.h
+++ b/drivers/staging/rtl8192su/r8192U.h
@@ -1662,11 +1662,6 @@ typedef struct r8192_priv
1662 bool bDmDisableProtect; 1662 bool bDmDisableProtect;
1663 bool bIgnoreDiffRateTxPowerOffset; 1663 bool bIgnoreDiffRateTxPowerOffset;
1664 1664
1665#ifdef EEPROM_OLD_FORMAT_SUPPORT
1666 u8 EEPROMTxPowerLevelCCK24G[14]; // CCK 2.4G channel 1~14
1667 //u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1668 //u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1669#else
1670 // For EEPROM TX Power Index like 8190 series 1665 // For EEPROM TX Power Index like 8190 series
1671 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7 1666 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1672 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 1667 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
@@ -1678,7 +1673,6 @@ typedef struct r8192_priv
1678 u8 RfCckChnlAreaTxPwr[2][3]; 1673 u8 RfCckChnlAreaTxPwr[2][3];
1679 u8 RfOfdmChnlAreaTxPwr1T[2][3]; 1674 u8 RfOfdmChnlAreaTxPwr1T[2][3];
1680 u8 RfOfdmChnlAreaTxPwr2T[2][3]; 1675 u8 RfOfdmChnlAreaTxPwr2T[2][3];
1681#endif
1682 1676
1683 // Add For EEPROM Efuse switch and Efuse Shadow map Setting 1677 // Add For EEPROM Efuse switch and Efuse Shadow map Setting
1684 bool EepromOrEfuse; 1678 bool EepromOrEfuse;
diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c
index 4793e654096..efcc5d1c5d4 100644
--- a/drivers/staging/rtl8192su/r8192U_core.c
+++ b/drivers/staging/rtl8192su/r8192U_core.c
@@ -5056,26 +5056,6 @@ rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
5056 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode; 5056 priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
5057 5057
5058 5058
5059#ifdef EEPROM_OLD_FORMAT_SUPPORT
5060 for(i=0; i<6; i++)
5061 {
5062 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5063 }
5064
5065 for(i=0; i<14; i++)
5066 {
5067 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5068 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5069 }
5070
5071 //
5072 // Update HAL variables.
5073 //
5074 memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
5075 memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
5076 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), priv->TxPowerLevelCCK, 14);
5077 //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), priv->TxPowerLevelOFDM24G, 14);
5078#else
5079 5059
5080 for (rf_path = 0; rf_path < 2; rf_path++) 5060 for (rf_path = 0; rf_path < 2; rf_path++)
5081 { 5061 {
@@ -5125,7 +5105,6 @@ rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
5125 //priv->RfTxPwrLevelOfdm1T[0][i] , 5105 //priv->RfTxPwrLevelOfdm1T[0][i] ,
5126 //priv->RfTxPwrLevelOfdm2T[0][i] ); 5106 //priv->RfTxPwrLevelOfdm2T[0][i] );
5127 } 5107 }
5128#endif
5129 5108
5130 // 5109 //
5131 // Update remained HAL variables. 5110 // Update remained HAL variables.
@@ -5349,50 +5328,8 @@ static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
5349 5328
5350 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType); 5329 RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
5351 5330
5352#ifdef EEPROM_OLD_FORMAT_SUPPORT
5353
5354 //
5355 // Buffer TxPwIdx(i.e., from offset 0x58~0x75, total 30Bytes)
5356 //
5357 if(bLoad_From_EEPOM)
5358 {
5359 for(i = 0; i < 30; i += 2)
5360 {
5361 tmpValue = eprom_read(dev, (u16) ((EEPROM_TxPowerBase+i)>>1));
5362 *((u16 *)(&tmpBuffer[i])) = tmpValue;
5363 }
5364 }
5365
5366 //
5367 // Update CCK, OFDM Tx Power Index from above buffer.
5368 //
5369 if(bLoad_From_EEPOM)
5370 {
5371 for(i=0; i<14; i++)
5372 {
5373 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)tmpBuffer[i+1];
5374 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)tmpBuffer[i+15];
5375 }
5376
5377 }
5378 else
5379 {
5380 for(i=0; i<14; i++)
5381 {
5382 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5383 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5384 }
5385 }
5386
5387 for(i=0; i<14; i++)
5388 {
5389 RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK24G[i]);
5390 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]);
5391 }
5392#else
5393 // Please add code in the section!!!! 5331 // Please add code in the section!!!!
5394 // And merge tx power difference section. 5332 // And merge tx power difference section.
5395#endif
5396 5333
5397 // 5334 //
5398 // Get TSSI value for each path. 5335 // Get TSSI value for each path.
@@ -5422,47 +5359,10 @@ static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
5422 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B); 5359 RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
5423 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode); 5360 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
5424 5361
5425#ifdef EEPROM_OLD_FORMAT_SUPPORT
5426 //
5427 // Get HT 2T Path A and B Power Index.
5428 //
5429 if(bLoad_From_EEPOM)
5430 {
5431 for(i = 0; i < 6; i += 2)
5432 {
5433 tmpValue = eprom_read(dev, (u16) ((EEPROM_HT2T_CH1_A+i)>>1));
5434 *((u16*)(&priv->EEPROMHT2T_TxPwr[i])) = tmpValue;
5435 }
5436 }
5437 else
5438 { // Default setting for Empty EEPROM
5439 for(i=0; i<6; i++)
5440 {
5441 priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
5442 }
5443 }
5444
5445 for(i=0; i<6; i++)
5446 {
5447 RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n", i, priv->EEPROMHT2T_TxPwr[i]);
5448 }
5449#else
5450 5362
5451#endif
5452 } 5363 }
5453 5364
5454#ifdef EEPROM_OLD_FORMAT_SUPPORT
5455 //
5456 // Update HAL variables.
5457 //
5458 for(i=0; i<14; i++)
5459 {
5460 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
5461 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
5462 }
5463#else
5464 5365
5465#endif
5466 priv->TxPowerDiff = priv->EEPROMPwDiff; 5366 priv->TxPowerDiff = priv->EEPROMPwDiff;
5467 // Antenna B gain offset to antenna A, bit0~3 5367 // Antenna B gain offset to antenna A, bit0~3
5468 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf); 5368 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
@@ -5750,47 +5650,8 @@ rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
5750 5650
5751 //if(pHalData->EEPROM_Def_Ver == 0) 5651 //if(pHalData->EEPROM_Def_Ver == 0)
5752 { 5652 {
5753#ifdef EEPROM_OLD_FORMAT_SUPPORT
5754 //
5755 // Get CCK Tx Power Index.
5756 //
5757 if(!priv->AutoloadFailFlag)
5758 {
5759 ReadEFuse(dev, EEPROM_TxPwIndex_CCK_24G, 14, (unsigned char*)CCKTxPwr);
5760 for(i=0; i<14; i++)
5761 {
5762 RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, CCKTxPwr[i]);
5763 priv->EEPROMTxPowerLevelCCK24G[i] = CCKTxPwr[i];
5764 }
5765 }
5766 else
5767 { // Default setting for Empty EEPROM
5768 for(i=0; i<14; i++)
5769 priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
5770 }
5771
5772 //
5773 // Get OFDM Tx Power Index.
5774 //
5775 if(!priv->AutoloadFailFlag)
5776 {
5777 ReadEFuse(dev, EEPROM_TxPwIndex_OFDM_24G, 14, (unsigned char*)OFDMTxPwr);
5778 for(i=0; i<14; i++)
5779 {
5780 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, OFDMTxPwr[i]);
5781 priv->EEPROMTxPowerLevelOFDM24G[i] = OFDMTxPwr[i];
5782 }
5783 }
5784 else
5785 { // Default setting for Empty EEPROM
5786 usValue = 0x10;
5787 for(i=0; i<14; i++)
5788 priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)usValue;
5789 }
5790#else
5791 // Please add code in the section!!!! 5653 // Please add code in the section!!!!
5792 // And merge tx power difference section. 5654 // And merge tx power difference section.
5793#endif
5794 5655
5795 // 5656 //
5796 // Get TSSI value for each path. 5657 // Get TSSI value for each path.
@@ -5853,18 +5714,7 @@ rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
5853 } 5714 }
5854 } 5715 }
5855 5716
5856#ifdef EEPROM_OLD_FORMAT_SUPPORT
5857 //
5858 // Update HAL variables.
5859 //
5860 for(i=0; i<14; i++)
5861 {
5862 priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
5863 priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
5864 }
5865#else
5866 5717
5867#endif
5868 priv->TxPowerDiff = priv->EEPROMPwDiff; 5718 priv->TxPowerDiff = priv->EEPROMPwDiff;
5869 // Antenna B gain offset to antenna A, bit0~3 5719 // Antenna B gain offset to antenna A, bit0~3
5870 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf); 5720 priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
@@ -6254,52 +6104,6 @@ rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
6254 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode); 6104 RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
6255 6105
6256 6106
6257#ifdef EEPROM_OLD_FORMAT_SUPPORT
6258
6259 //
6260 // <Roger_Notes> The following settings are EFUSE version dependence.
6261 // So we need to adjust reading offset.
6262 // 2008.11.22.
6263 //
6264 {
6265 //
6266 // Get HT 2T Path A and B Power Index.
6267 //
6268 //if(!priv->AutoloadFailFlag)
6269 {
6270 for(i=0; i<6; i++)
6271 {
6272 priv->EEPROMHT2T_TxPwr[i] = *(u8 *)&hwinfo[EEPROM_HT2T_CH1_A+i];
6273 }
6274 }
6275
6276 //RT_PRINT_DATA(COMP_EFUSE, "HT2T TxPwr: \n"), pHalData->EEPROMHT2T_TxPwr, 6);
6277
6278 //
6279 // Get CCK and OFDM Tx Power Index.
6280 //
6281 //if(!priv->AutoloadFailFlag)
6282 {
6283 for(i=0; i<14; i++)
6284 {
6285 priv->EEPROMTxPowerLevelCCK24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_CCK_24G+i];
6286 priv->EEPROMTxPowerLevelOFDM24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_OFDM_24G+i];
6287 }
6288 }
6289
6290 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("CCK 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelCCK24G, 14);
6291 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("OFDM 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelOFDM24G, 14);
6292
6293 //
6294 // Update HAL variables.
6295 //
6296 memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
6297 memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
6298 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), pHalData->TxPowerLevelCCK, 14);
6299 //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), pHalData->TxPowerLevelOFDM24G, 14);
6300
6301 }
6302#else // Support new version of EFUSE content, 2008.11.22.
6303 { 6107 {
6304 // 6108 //
6305 // Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes) 6109 // Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes)
@@ -6467,7 +6271,6 @@ rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
6467 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0], 6271 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0],
6468 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]); 6272 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]);
6469 RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag); 6273 RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag);
6470#endif
6471 6274
6472 // 6275 //
6473 // Update remained HAL variables. 6276 // Update remained HAL variables.
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 21:50:16 -0400